/*
* MIPS32 emulation for qemu: main translation routines.
- *
+ *
* Copyright (c) 2004-2005 Jocelyn Mayer
* Copyright (c) 2006 Marius Groeger (FPU operations)
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
OPC_SRA = 0x03 | OPC_SPECIAL,
OPC_SLLV = 0x04 | OPC_SPECIAL,
- OPC_SRLV = 0x06 | OPC_SPECIAL,
+ OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
OPC_SRAV = 0x07 | OPC_SPECIAL,
OPC_DSLLV = 0x14 | OPC_SPECIAL,
OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
};
+/* Multiplication variants of the vr54xx. */
+#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
+
+enum {
+ OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
+ OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
+ OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
+ OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
+ OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
+ OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
+ OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
+ OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
+ OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
+ OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
+ OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
+ OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
+ OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
+ OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
+};
+
/* REGIMM (rt field) opcodes */
#define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
OPC_DINSM = 0x05 | OPC_SPECIAL3,
OPC_DINSU = 0x06 | OPC_SPECIAL3,
OPC_DINS = 0x07 | OPC_SPECIAL3,
+ OPC_FORK = 0x08 | OPC_SPECIAL3,
+ OPC_YIELD = 0x09 | OPC_SPECIAL3,
OPC_BSHFL = 0x20 | OPC_SPECIAL3,
OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
OPC_RDHWR = 0x3B | OPC_SPECIAL3,
OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
OPC_MTC0 = (0x04 << 21) | OPC_CP0,
OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
+ OPC_MFTR = (0x08 << 21) | OPC_CP0,
OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
+ OPC_MTTR = (0x0C << 21) | OPC_CP0,
OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
OPC_C0 = (0x10 << 21) | OPC_CP0,
OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
enum {
+ OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
+ OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
+ OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
+ OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
};
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
}; \
-static inline void func(int n) \
+static always_inline void func(int n) \
{ \
NAME ## _table[n](); \
}
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
+/* Moves to/from shadow registers */
+GEN32(gen_op_load_srsgpr_T0, gen_op_load_srsgpr_T0_gpr);
+GEN32(gen_op_store_T0_srsgpr, gen_op_store_T0_srsgpr_gpr);
+
static const char *fregnames[] =
{ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
}; \
-static inline void func(int n) \
+static always_inline void func(int n) \
{ \
NAME ## _table[n](); \
}
FGEN32(gen_op_store_fpr_WTH2, gen_op_store_fpr_WTH2_fpr);
#define FOP_CONDS(type, fmt) \
-static GenOpFunc1 * cond ## type ## _ ## fmt ## _table[16] = { \
+static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
gen_op_cmp ## type ## _ ## fmt ## _f, \
gen_op_cmp ## type ## _ ## fmt ## _un, \
gen_op_cmp ## type ## _ ## fmt ## _eq, \
gen_op_cmp ## type ## _ ## fmt ## _le, \
gen_op_cmp ## type ## _ ## fmt ## _ngt, \
}; \
-static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
+static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
{ \
- cond ## type ## _ ## fmt ## _table[n](cc); \
+ gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
}
FOP_CONDS(, d)
struct TranslationBlock *tb;
target_ulong pc, saved_pc;
uint32_t opcode;
- uint32_t fp_status, saved_fp_status;
+ uint32_t fp_status;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
- uint32_t CP0_Status;
int bstate;
target_ulong btarget;
+ void *last_T0_store;
+ int last_T0_gpr;
} DisasContext;
enum {
ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
} while (0)
-#define GEN_LOAD_REG_TN(Tn, Rn) \
+#define GEN_LOAD_REG_T0(Rn) \
+do { \
+ if (Rn == 0) { \
+ gen_op_reset_T0(); \
+ } else { \
+ if (ctx->glue(last_T0, _store) != gen_opc_ptr \
+ || ctx->glue(last_T0, _gpr) != Rn) { \
+ gen_op_load_gpr_T0(Rn); \
+ } \
+ } \
+} while (0)
+
+#define GEN_LOAD_REG_T1(Rn) \
+do { \
+ if (Rn == 0) { \
+ gen_op_reset_T1(); \
+ } else { \
+ gen_op_load_gpr_T1(Rn); \
+ } \
+} while (0)
+
+#define GEN_LOAD_REG_T2(Rn) \
+do { \
+ if (Rn == 0) { \
+ gen_op_reset_T2(); \
+ } else { \
+ gen_op_load_gpr_T2(Rn); \
+ } \
+} while (0)
+
+#define GEN_LOAD_SRSREG_TN(Tn, Rn) \
do { \
if (Rn == 0) { \
glue(gen_op_reset_, Tn)(); \
} else { \
- glue(gen_op_load_gpr_, Tn)(Rn); \
+ glue(gen_op_load_srsgpr_, Tn)(Rn); \
} \
} while (0)
+#if defined(TARGET_MIPS64)
+#define GEN_LOAD_IMM_TN(Tn, Imm) \
+do { \
+ if (Imm == 0) { \
+ glue(gen_op_reset_, Tn)(); \
+ } else if ((int32_t)Imm == Imm) { \
+ glue(gen_op_set_, Tn)(Imm); \
+ } else { \
+ glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm); \
+ } \
+} while (0)
+#else
#define GEN_LOAD_IMM_TN(Tn, Imm) \
do { \
if (Imm == 0) { \
glue(gen_op_set_, Tn)(Imm); \
} \
} while (0)
+#endif
+
+#define GEN_STORE_T0_REG(Rn) \
+do { \
+ if (Rn != 0) { \
+ glue(gen_op_store_T0,_gpr)(Rn); \
+ ctx->glue(last_T0,_store) = gen_opc_ptr; \
+ ctx->glue(last_T0,_gpr) = Rn; \
+ } \
+} while (0)
+
+#define GEN_STORE_T1_REG(Rn) \
+do { \
+ if (Rn != 0) \
+ glue(gen_op_store_T1,_gpr)(Rn); \
+} while (0)
-#define GEN_STORE_TN_REG(Rn, Tn) \
+#define GEN_STORE_TN_SRSREG(Rn, Tn) \
do { \
if (Rn != 0) { \
- glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
+ glue(glue(gen_op_store_, Tn),_srsgpr)(Rn); \
} \
} while (0)
glue(gen_op_store_fpr_, FTn)(Fn); \
} while (0)
-static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
+static always_inline void gen_save_pc(target_ulong pc)
+{
+#if defined(TARGET_MIPS64)
+ if (pc == (int32_t)pc) {
+ gen_op_save_pc(pc);
+ } else {
+ gen_op_save_pc64(pc >> 32, (uint32_t)pc);
+ }
+#else
+ gen_op_save_pc(pc);
+#endif
+}
+
+static always_inline void gen_save_btarget(target_ulong btarget)
+{
+#if defined(TARGET_MIPS64)
+ if (btarget == (int32_t)btarget) {
+ gen_op_save_btarget(btarget);
+ } else {
+ gen_op_save_btarget64(btarget >> 32, (uint32_t)btarget);
+ }
+#else
+ gen_op_save_btarget(btarget);
+#endif
+}
+
+static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
{
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
}
#endif
if (do_save_pc && ctx->pc != ctx->saved_pc) {
- gen_op_save_pc(ctx->pc);
+ gen_save_pc(ctx->pc);
ctx->saved_pc = ctx->pc;
}
if (ctx->hflags != ctx->saved_hflags) {
/* bcond was already saved by the BL insn */
/* fall through */
case MIPS_HFLAG_B:
- gen_op_save_btarget(ctx->btarget);
+ gen_save_btarget(ctx->btarget);
break;
}
}
}
-static inline void save_fpu_state (DisasContext *ctx)
+static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
{
- if (ctx->fp_status != ctx->saved_fp_status) {
- gen_op_save_fp_status(ctx->fp_status);
- ctx->saved_fp_status = ctx->fp_status;
+ ctx->saved_hflags = ctx->hflags;
+ switch (ctx->hflags & MIPS_HFLAG_BMASK) {
+ case MIPS_HFLAG_BR:
+ gen_op_restore_breg_target();
+ break;
+ case MIPS_HFLAG_B:
+ ctx->btarget = env->btarget;
+ break;
+ case MIPS_HFLAG_BC:
+ case MIPS_HFLAG_BL:
+ ctx->btarget = env->btarget;
+ gen_op_restore_bcond();
+ break;
}
}
-static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
+static always_inline void generate_exception_err (DisasContext *ctx, int excp, int err)
{
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
ctx->bstate = BS_EXCP;
}
-static inline void generate_exception (DisasContext *ctx, int excp)
+static always_inline void generate_exception (DisasContext *ctx, int excp)
{
generate_exception_err (ctx, excp, 0);
}
+static always_inline void check_cp0_enabled(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
+ generate_exception_err(ctx, EXCP_CpU, 1);
+}
+
+static always_inline void check_cp1_enabled(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
+ generate_exception_err(ctx, EXCP_CpU, 1);
+}
+
+/* Verify that the processor is running with COP1X instructions enabled.
+ This is associated with the nabla symbol in the MIPS32 and MIPS64
+ opcode tables. */
+
+static always_inline void check_cop1x(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
+ generate_exception(ctx, EXCP_RI);
+}
+
+/* Verify that the processor is running with 64-bit floating-point
+ operations enabled. */
+
+static always_inline void check_cp1_64bitmode(DisasContext *ctx)
+{
+ if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
+ generate_exception(ctx, EXCP_RI);
+}
+
+/*
+ * Verify if floating point register is valid; an operation is not defined
+ * if bit 0 of any register specification is set and the FR bit in the
+ * Status register equals zero, since the register numbers specify an
+ * even-odd pair of adjacent coprocessor general registers. When the FR bit
+ * in the Status register equals one, both even and odd register numbers
+ * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
+ *
+ * Multiple 64 bit wide registers can be checked by calling
+ * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
+ */
+void check_cp1_registers(DisasContext *ctx, int regs)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
+ generate_exception(ctx, EXCP_RI);
+}
+
+/* This code generates a "reserved instruction" exception if the
+ CPU does not support the instruction set corresponding to flags. */
+static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
+{
+ if (unlikely(!(env->insn_flags & flags)))
+ generate_exception(ctx, EXCP_RI);
+}
+
+/* This code generates a "reserved instruction" exception if 64-bit
+ instructions are not enabled. */
+static always_inline void check_mips_64(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
+ generate_exception(ctx, EXCP_RI);
+}
+
#if defined(CONFIG_USER_ONLY)
#define op_ldst(name) gen_op_##name##_raw()
#define OP_LD_TABLE(width)
#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
#define OP_LD_TABLE(width) \
static GenOpFunc *gen_op_l##width[] = { \
- &gen_op_l##width##_user, \
&gen_op_l##width##_kernel, \
+ &gen_op_l##width##_super, \
+ &gen_op_l##width##_user, \
}
#define OP_ST_TABLE(width) \
static GenOpFunc *gen_op_s##width[] = { \
- &gen_op_s##width##_user, \
&gen_op_s##width##_kernel, \
+ &gen_op_s##width##_super, \
+ &gen_op_s##width##_user, \
}
#endif
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
OP_LD_TABLE(d);
OP_LD_TABLE(dl);
OP_LD_TABLE(dr);
OP_ST_TABLE(dr);
OP_LD_TABLE(ld);
OP_ST_TABLE(cd);
+OP_LD_TABLE(wu);
#endif
OP_LD_TABLE(w);
-OP_LD_TABLE(wu);
OP_LD_TABLE(wl);
OP_LD_TABLE(wr);
OP_ST_TABLE(w);
OP_ST_TABLE(wc1);
OP_LD_TABLE(dc1);
OP_ST_TABLE(dc1);
-OP_LD_TABLE(wxc1);
-OP_ST_TABLE(wxc1);
-OP_LD_TABLE(dxc1);
-OP_ST_TABLE(dxc1);
OP_LD_TABLE(uxc1);
OP_ST_TABLE(uxc1);
gen_op_addr_add();
}
/* Don't do NOP if destination is zero: we must perform the actual
- * memory access
- */
+ memory access. */
switch (opc) {
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
+ case OPC_LWU:
+ op_ldst(lwu);
+ GEN_STORE_T0_REG(rt);
+ opn = "lwu";
+ break;
case OPC_LD:
op_ldst(ld);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "ld";
break;
case OPC_LLD:
op_ldst(lld);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "lld";
break;
case OPC_SD:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(sd);
opn = "sd";
break;
case OPC_SCD:
save_cpu_state(ctx, 1);
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(scd);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "scd";
break;
case OPC_LDL:
+ GEN_LOAD_REG_T1(rt);
op_ldst(ldl);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T1_REG(rt);
opn = "ldl";
break;
case OPC_SDL:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(sdl);
opn = "sdl";
break;
case OPC_LDR:
+ GEN_LOAD_REG_T1(rt);
op_ldst(ldr);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T1_REG(rt);
opn = "ldr";
break;
case OPC_SDR:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(sdr);
opn = "sdr";
break;
#endif
case OPC_LW:
op_ldst(lw);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "lw";
break;
- case OPC_LWU:
- op_ldst(lwu);
- GEN_STORE_TN_REG(rt, T0);
- opn = "lwu";
- break;
case OPC_SW:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(sw);
opn = "sw";
break;
case OPC_LH:
op_ldst(lh);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "lh";
break;
case OPC_SH:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(sh);
opn = "sh";
break;
case OPC_LHU:
op_ldst(lhu);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "lhu";
break;
case OPC_LB:
op_ldst(lb);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "lb";
break;
case OPC_SB:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(sb);
opn = "sb";
break;
case OPC_LBU:
op_ldst(lbu);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "lbu";
break;
case OPC_LWL:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(lwl);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T1_REG(rt);
opn = "lwl";
break;
case OPC_SWL:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(swl);
opn = "swr";
break;
case OPC_LWR:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(lwr);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T1_REG(rt);
opn = "lwr";
break;
case OPC_SWR:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(swr);
opn = "swr";
break;
case OPC_LL:
op_ldst(ll);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "ll";
break;
case OPC_SC:
save_cpu_state(ctx, 1);
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
op_ldst(sc);
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "sc";
break;
default:
gen_op_addr_add();
}
/* Don't do NOP if destination is zero: we must perform the actual
- * memory access
- */
+ memory access. */
switch (opc) {
case OPC_LWC1:
op_ldst(lwc1);
}
/* Arithmetic with immediate operand */
-static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
- int rs, int16_t imm)
+static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
+ int rt, int rs, int16_t imm)
{
- uint32_t uimm;
+ target_ulong uimm;
const char *opn = "imm arith";
if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
- /* if no destination, treat it as a NOP
- * For addi, we must generate the overflow exception when needed.
- */
+ /* If no destination, treat it as a NOP.
+ For addi, we must generate the overflow exception when needed. */
MIPS_DEBUG("NOP");
return;
}
switch (opc) {
case OPC_ADDI:
case OPC_ADDIU:
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DADDI:
case OPC_DADDIU:
#endif
case OPC_SLTI:
case OPC_SLTIU:
- uimm = (int32_t)imm; /* Sign extend to 32 bits */
+ uimm = (target_long)imm; /* Sign extend to 32/64 bits */
/* Fall through. */
case OPC_ANDI:
case OPC_ORI:
case OPC_XORI:
- GEN_LOAD_REG_TN(T0, rs);
+ GEN_LOAD_REG_T0(rs);
GEN_LOAD_IMM_TN(T1, uimm);
break;
case OPC_LUI:
- GEN_LOAD_IMM_TN(T0, uimm << 16);
+ GEN_LOAD_IMM_TN(T0, imm << 16);
break;
case OPC_SLL:
case OPC_SRA:
case OPC_SRL:
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DSLL:
case OPC_DSRA:
case OPC_DSRL:
case OPC_DSRL32:
#endif
uimm &= 0x1f;
- GEN_LOAD_REG_TN(T0, rs);
+ GEN_LOAD_REG_T0(rs);
GEN_LOAD_IMM_TN(T1, uimm);
break;
}
gen_op_add();
opn = "addiu";
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DADDI:
save_cpu_state(ctx, 1);
gen_op_daddo();
opn = "srl";
break;
case 1:
- gen_op_rotr();
- opn = "rotr";
+ /* rotr is decoded as srl on non-R2 CPUs */
+ if (env->insn_flags & ISA_MIPS32R2) {
+ gen_op_rotr();
+ opn = "rotr";
+ } else {
+ gen_op_srl();
+ opn = "srl";
+ }
break;
default:
MIPS_INVAL("invalid srl flag");
break;
}
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DSLL:
gen_op_dsll();
opn = "dsll";
opn = "dsrl";
break;
case 1:
- gen_op_drotr();
- opn = "drotr";
+ /* drotr is decoded as dsrl on non-R2 CPUs */
+ if (env->insn_flags & ISA_MIPS32R2) {
+ gen_op_drotr();
+ opn = "drotr";
+ } else {
+ gen_op_dsrl();
+ opn = "dsrl";
+ }
break;
default:
MIPS_INVAL("invalid dsrl flag");
opn = "dsrl32";
break;
case 1:
- gen_op_drotr32();
- opn = "drotr32";
+ /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
+ if (env->insn_flags & ISA_MIPS32R2) {
+ gen_op_drotr32();
+ opn = "drotr32";
+ } else {
+ gen_op_dsrl32();
+ opn = "dsrl32";
+ }
break;
default:
MIPS_INVAL("invalid dsrl32 flag");
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_STORE_TN_REG(rt, T0);
- MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
+ GEN_STORE_T0_REG(rt);
+ MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
}
/* Arithmetic */
-static void gen_arith (DisasContext *ctx, uint32_t opc,
+static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "arith";
if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
&& opc != OPC_DADD && opc != OPC_DSUB) {
- /* if no destination, treat it as a NOP
- * For add & sub, we must generate the overflow exception when needed.
- */
+ /* If no destination, treat it as a NOP.
+ For add & sub, we must generate the overflow exception when needed. */
MIPS_DEBUG("NOP");
return;
}
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T0(rs);
+ /* Specialcase the conventional move operation. */
+ if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU
+ || opc == OPC_SUBU || opc == OPC_DSUBU)) {
+ GEN_STORE_T0_REG(rd);
+ return;
+ }
+ GEN_LOAD_REG_T1(rt);
switch (opc) {
case OPC_ADD:
save_cpu_state(ctx, 1);
gen_op_sub();
opn = "subu";
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DADD:
save_cpu_state(ctx, 1);
gen_op_daddo();
opn = "srlv";
break;
case 1:
- gen_op_rotrv();
- opn = "rotrv";
+ /* rotrv is decoded as srlv on non-R2 CPUs */
+ if (env->insn_flags & ISA_MIPS32R2) {
+ gen_op_rotrv();
+ opn = "rotrv";
+ } else {
+ gen_op_srlv();
+ opn = "srlv";
+ }
break;
default:
MIPS_INVAL("invalid srlv flag");
break;
}
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DSLLV:
gen_op_dsllv();
opn = "dsllv";
opn = "dsrlv";
break;
case 1:
- gen_op_drotrv();
- opn = "drotrv";
+ /* drotrv is decoded as dsrlv on non-R2 CPUs */
+ if (env->insn_flags & ISA_MIPS32R2) {
+ gen_op_drotrv();
+ opn = "drotrv";
+ } else {
+ gen_op_dsrlv();
+ opn = "dsrlv";
+ }
break;
default:
MIPS_INVAL("invalid dsrlv flag");
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_STORE_TN_REG(rd, T0);
+ GEN_STORE_T0_REG(rd);
print:
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
}
const char *opn = "hilo";
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
- /* Treat as a NOP */
+ /* Treat as NOP. */
MIPS_DEBUG("NOP");
return;
}
switch (opc) {
case OPC_MFHI:
- gen_op_load_HI();
- GEN_STORE_TN_REG(reg, T0);
+ gen_op_load_HI(0);
+ GEN_STORE_T0_REG(reg);
opn = "mfhi";
break;
case OPC_MFLO:
- gen_op_load_LO();
- GEN_STORE_TN_REG(reg, T0);
+ gen_op_load_LO(0);
+ GEN_STORE_T0_REG(reg);
opn = "mflo";
break;
case OPC_MTHI:
- GEN_LOAD_REG_TN(T0, reg);
- gen_op_store_HI();
+ GEN_LOAD_REG_T0(reg);
+ gen_op_store_HI(0);
opn = "mthi";
break;
case OPC_MTLO:
- GEN_LOAD_REG_TN(T0, reg);
- gen_op_store_LO();
+ GEN_LOAD_REG_T0(reg);
+ gen_op_store_LO(0);
opn = "mtlo";
break;
default:
{
const char *opn = "mul/div";
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T0(rs);
+ GEN_LOAD_REG_T1(rt);
switch (opc) {
case OPC_DIV:
gen_op_div();
gen_op_multu();
opn = "multu";
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DDIV:
gen_op_ddiv();
opn = "ddiv";
MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
}
+static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
+ int rd, int rs, int rt)
+{
+ const char *opn = "mul vr54xx";
+
+ GEN_LOAD_REG_T0(rs);
+ GEN_LOAD_REG_T1(rt);
+
+ switch (opc) {
+ case OPC_VR54XX_MULS:
+ gen_op_muls();
+ opn = "muls";
+ break;
+ case OPC_VR54XX_MULSU:
+ gen_op_mulsu();
+ opn = "mulsu";
+ break;
+ case OPC_VR54XX_MACC:
+ gen_op_macc();
+ opn = "macc";
+ break;
+ case OPC_VR54XX_MACCU:
+ gen_op_maccu();
+ opn = "maccu";
+ break;
+ case OPC_VR54XX_MSAC:
+ gen_op_msac();
+ opn = "msac";
+ break;
+ case OPC_VR54XX_MSACU:
+ gen_op_msacu();
+ opn = "msacu";
+ break;
+ case OPC_VR54XX_MULHI:
+ gen_op_mulhi();
+ opn = "mulhi";
+ break;
+ case OPC_VR54XX_MULHIU:
+ gen_op_mulhiu();
+ opn = "mulhiu";
+ break;
+ case OPC_VR54XX_MULSHI:
+ gen_op_mulshi();
+ opn = "mulshi";
+ break;
+ case OPC_VR54XX_MULSHIU:
+ gen_op_mulshiu();
+ opn = "mulshiu";
+ break;
+ case OPC_VR54XX_MACCHI:
+ gen_op_macchi();
+ opn = "macchi";
+ break;
+ case OPC_VR54XX_MACCHIU:
+ gen_op_macchiu();
+ opn = "macchiu";
+ break;
+ case OPC_VR54XX_MSACHI:
+ gen_op_msachi();
+ opn = "msachi";
+ break;
+ case OPC_VR54XX_MSACHIU:
+ gen_op_msachiu();
+ opn = "msachiu";
+ break;
+ default:
+ MIPS_INVAL("mul vr54xx");
+ generate_exception(ctx, EXCP_RI);
+ return;
+ }
+ GEN_STORE_T0_REG(rd);
+ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
+}
+
static void gen_cl (DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
const char *opn = "CLx";
if (rd == 0) {
- /* Treat as a NOP */
+ /* Treat as NOP. */
MIPS_DEBUG("NOP");
return;
}
- GEN_LOAD_REG_TN(T0, rs);
+ GEN_LOAD_REG_T0(rs);
switch (opc) {
case OPC_CLO:
gen_op_clo();
gen_op_clz();
opn = "clz";
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DCLO:
gen_op_dclo();
opn = "dclo";
case OPC_TNE:
/* Compare two registers */
if (rs != rt) {
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T0(rs);
+ GEN_LOAD_REG_T1(rt);
cond = 1;
}
break;
case OPC_TNEI:
/* Compare register to immediate */
if (rs != 0 || imm != 0) {
- GEN_LOAD_REG_TN(T0, rs);
+ GEN_LOAD_REG_T0(rs);
GEN_LOAD_IMM_TN(T1, (int32_t)imm);
cond = 1;
}
case OPC_TLTIU: /* r0 < 0 unsigned */
case OPC_TNE: /* rs != rs */
case OPC_TNEI: /* r0 != 0 */
- /* Never trap: treat as NOP */
+ /* Never trap: treat as NOP. */
return;
default:
MIPS_INVAL("trap");
ctx->bstate = BS_STOP;
}
-static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
TranslationBlock *tb;
tb = ctx->tb;
gen_op_goto_tb0(TBPARAM(tb));
else
gen_op_goto_tb1(TBPARAM(tb));
- gen_op_save_pc(dest);
+ gen_save_pc(dest);
gen_op_set_T0((long)tb + n);
} else {
- gen_op_save_pc(dest);
+ gen_save_pc(dest);
gen_op_reset_T0();
}
gen_op_exit_tb();
case OPC_BNEL:
/* Compare two registers */
if (rs != rt) {
- GEN_LOAD_REG_TN(T0, rs);
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T0(rs);
+ GEN_LOAD_REG_T1(rt);
bcond = 1;
}
btarget = ctx->pc + 4 + offset;
case OPC_J:
case OPC_JAL:
/* Jump to immediate */
- btarget = ((ctx->pc + 4) & (int32_t)0xF0000000) | offset;
+ btarget = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset;
break;
case OPC_JR:
case OPC_JALR:
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_LOAD_REG_TN(T2, rs);
+ GEN_LOAD_REG_T2(rs);
break;
default:
MIPS_INVAL("branch/jump");
case OPC_BNE: /* rx != rx */
case OPC_BGTZ: /* 0 > 0 */
case OPC_BLTZ: /* 0 < 0 */
- /* Treated as NOP */
+ /* Treat as NOP. */
MIPS_DEBUG("bnever (NOP)");
return;
case OPC_BLTZAL: /* 0 < 0 */
- gen_op_set_T0(ctx->pc + 8);
+ GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
gen_op_store_T0_gpr(31);
MIPS_DEBUG("bnever and link");
return;
case OPC_BLTZALL: /* 0 < 0 likely */
- gen_op_set_T0(ctx->pc + 8);
+ GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
gen_op_store_T0_gpr(31);
/* Skip the instruction in the delay slot */
MIPS_DEBUG("bnever, link and skip");
}
MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
blink, ctx->hflags, btarget);
+
ctx->btarget = btarget;
if (blink > 0) {
- gen_op_set_T0(ctx->pc + 8);
+ GEN_LOAD_IMM_TN(T0, ctx->pc + 8);
gen_op_store_T0_gpr(blink);
}
}
static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
int rs, int lsb, int msb)
{
- GEN_LOAD_REG_TN(T1, rs);
+ GEN_LOAD_REG_T1(rs);
switch (opc) {
case OPC_EXT:
if (lsb + msb > 31)
goto fail;
gen_op_ext(lsb, msb + 1);
break;
+#if defined(TARGET_MIPS64)
case OPC_DEXTM:
if (lsb + msb > 63)
goto fail;
- gen_op_ext(lsb, msb + 1 + 32);
+ gen_op_dext(lsb, msb + 1 + 32);
break;
case OPC_DEXTU:
if (lsb + msb > 63)
goto fail;
- gen_op_ext(lsb + 32, msb + 1);
+ gen_op_dext(lsb + 32, msb + 1);
break;
case OPC_DEXT:
- gen_op_ext(lsb, msb + 1);
+ if (lsb + msb > 63)
+ goto fail;
+ gen_op_dext(lsb, msb + 1);
break;
+#endif
case OPC_INS:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
+ GEN_LOAD_REG_T0(rt);
gen_op_ins(lsb, msb - lsb + 1);
break;
+#if defined(TARGET_MIPS64)
case OPC_DINSM:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb, msb - lsb + 1 + 32);
+ GEN_LOAD_REG_T0(rt);
+ gen_op_dins(lsb, msb - lsb + 1 + 32);
break;
case OPC_DINSU:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb + 32, msb - lsb + 1);
+ GEN_LOAD_REG_T0(rt);
+ gen_op_dins(lsb + 32, msb - lsb + 1);
break;
case OPC_DINS:
if (lsb > msb)
goto fail;
- GEN_LOAD_REG_TN(T0, rt);
- gen_op_ins(lsb, msb - lsb + 1);
+ GEN_LOAD_REG_T0(rt);
+ gen_op_dins(lsb, msb - lsb + 1);
break;
+#endif
default:
fail:
MIPS_INVAL("bitops");
generate_exception(ctx, EXCP_RI);
return;
}
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
}
/* CP0 (MMU and control) */
-static void gen_mfc0 (DisasContext *ctx, int reg, int sel)
+static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ if (sel != 0)
+ check_insn(env, ctx, ISA_MIPS32);
+
switch (reg) {
case 0:
switch (sel) {
rn = "Index";
break;
case 1:
-// gen_op_mfc0_mvpcontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_mvpcontrol();
rn = "MVPControl";
-// break;
+ break;
case 2:
-// gen_op_mfc0_mvpconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_mvpconf0();
rn = "MVPConf0";
-// break;
+ break;
case 3:
-// gen_op_mfc0_mvpconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_mvpconf1();
rn = "MVPConf1";
-// break;
+ break;
default:
goto die;
}
rn = "Random";
break;
case 1:
-// gen_op_mfc0_vpecontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpecontrol();
rn = "VPEControl";
-// break;
+ break;
case 2:
-// gen_op_mfc0_vpeconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeconf0();
rn = "VPEConf0";
-// break;
+ break;
case 3:
-// gen_op_mfc0_vpeconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeconf1();
rn = "VPEConf1";
-// break;
+ break;
case 4:
-// gen_op_mfc0_YQMask(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_yqmask();
rn = "YQMask";
-// break;
+ break;
case 5:
-// gen_op_mfc0_vpeschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeschedule();
rn = "VPESchedule";
-// break;
+ break;
case 6:
-// gen_op_mfc0_vpeschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeschefback();
rn = "VPEScheFBack";
-// break;
+ break;
case 7:
-// gen_op_mfc0_vpeopt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeopt();
rn = "VPEOpt";
-// break;
+ break;
default:
goto die;
}
rn = "EntryLo0";
break;
case 1:
-// gen_op_mfc0_tcstatus(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tcstatus();
rn = "TCStatus";
-// break;
+ break;
case 2:
-// gen_op_mfc0_tcbind(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tcbind();
rn = "TCBind";
-// break;
+ break;
case 3:
-// gen_op_mfc0_tcrestart(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tcrestart();
rn = "TCRestart";
-// break;
+ break;
case 4:
-// gen_op_mfc0_tchalt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tchalt();
rn = "TCHalt";
-// break;
+ break;
case 5:
-// gen_op_mfc0_tccontext(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tccontext();
rn = "TCContext";
-// break;
+ break;
case 6:
-// gen_op_mfc0_tcschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tcschedule();
rn = "TCSchedule";
-// break;
+ break;
case 7:
-// gen_op_mfc0_tcschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tcschefback();
rn = "TCScheFBack";
-// break;
+ break;
default:
goto die;
}
rn = "PageMask";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_pagegrain();
rn = "PageGrain";
break;
rn = "Wired";
break;
case 1:
-// gen_op_mfc0_srsconf0(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf0();
rn = "SRSConf0";
-// break;
+ break;
case 2:
-// gen_op_mfc0_srsconf1(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf1();
rn = "SRSConf1";
-// break;
+ break;
case 3:
-// gen_op_mfc0_srsconf2(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf2();
rn = "SRSConf2";
-// break;
+ break;
case 4:
-// gen_op_mfc0_srsconf3(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf3();
rn = "SRSConf3";
-// break;
+ break;
case 5:
-// gen_op_mfc0_srsconf4(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf4();
rn = "SRSConf4";
-// break;
+ break;
default:
goto die;
}
case 7:
switch (sel) {
case 0:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_hwrena();
rn = "HWREna";
break;
rn = "Status";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_intctl();
rn = "IntCtl";
break;
case 2:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_srsctl();
rn = "SRSCtl";
break;
case 3:
-// gen_op_mfc0_srsmap(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsmap();
rn = "SRSMap";
-// break;
+ break;
default:
goto die;
}
rn = "PRid";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_ebase();
rn = "EBase";
break;
break;
case 18:
switch (sel) {
- case 0:
- gen_op_mfc0_watchlo0();
+ case 0 ... 7:
+ gen_op_mfc0_watchlo(sel);
rn = "WatchLo";
break;
- case 1:
-// gen_op_mfc0_watchlo1();
- rn = "WatchLo1";
-// break;
- case 2:
-// gen_op_mfc0_watchlo2();
- rn = "WatchLo2";
-// break;
- case 3:
-// gen_op_mfc0_watchlo3();
- rn = "WatchLo3";
-// break;
- case 4:
-// gen_op_mfc0_watchlo4();
- rn = "WatchLo4";
-// break;
- case 5:
-// gen_op_mfc0_watchlo5();
- rn = "WatchLo5";
-// break;
- case 6:
-// gen_op_mfc0_watchlo6();
- rn = "WatchLo6";
-// break;
- case 7:
-// gen_op_mfc0_watchlo7();
- rn = "WatchLo7";
-// break;
default:
goto die;
}
break;
case 19:
switch (sel) {
- case 0:
- gen_op_mfc0_watchhi0();
+ case 0 ...7:
+ gen_op_mfc0_watchhi(sel);
rn = "WatchHi";
break;
- case 1:
-// gen_op_mfc0_watchhi1();
- rn = "WatchHi1";
-// break;
- case 2:
-// gen_op_mfc0_watchhi2();
- rn = "WatchHi2";
-// break;
- case 3:
-// gen_op_mfc0_watchhi3();
- rn = "WatchHi3";
-// break;
- case 4:
-// gen_op_mfc0_watchhi4();
- rn = "WatchHi4";
-// break;
- case 5:
-// gen_op_mfc0_watchhi5();
- rn = "WatchHi5";
-// break;
- case 6:
-// gen_op_mfc0_watchhi6();
- rn = "WatchHi6";
-// break;
- case 7:
-// gen_op_mfc0_watchhi7();
- rn = "WatchHi7";
-// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
+ check_insn(env, ctx, ISA_MIPS3);
gen_op_mfc0_xcontext();
rn = "XContext";
break;
generate_exception(ctx, EXCP_RI);
}
-static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
+static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ if (sel != 0)
+ check_insn(env, ctx, ISA_MIPS32);
+
switch (reg) {
case 0:
switch (sel) {
case 0:
- gen_op_mtc0_index();
+ gen_op_mtc0_index();
rn = "Index";
break;
case 1:
-// gen_op_mtc0_mvpcontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_mvpcontrol();
rn = "MVPControl";
-// break;
+ break;
case 2:
-// gen_op_mtc0_mvpconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ /* ignored */
rn = "MVPConf0";
-// break;
+ break;
case 3:
-// gen_op_mtc0_mvpconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ /* ignored */
rn = "MVPConf1";
-// break;
+ break;
default:
goto die;
}
rn = "Random";
break;
case 1:
-// gen_op_mtc0_vpecontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpecontrol();
rn = "VPEControl";
-// break;
+ break;
case 2:
-// gen_op_mtc0_vpeconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeconf0();
rn = "VPEConf0";
-// break;
+ break;
case 3:
-// gen_op_mtc0_vpeconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeconf1();
rn = "VPEConf1";
-// break;
+ break;
case 4:
-// gen_op_mtc0_YQMask(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_yqmask();
rn = "YQMask";
-// break;
+ break;
case 5:
-// gen_op_mtc0_vpeschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeschedule();
rn = "VPESchedule";
-// break;
+ break;
case 6:
-// gen_op_mtc0_vpeschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeschefback();
rn = "VPEScheFBack";
-// break;
+ break;
case 7:
-// gen_op_mtc0_vpeopt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeopt();
rn = "VPEOpt";
-// break;
+ break;
default:
goto die;
}
rn = "EntryLo0";
break;
case 1:
-// gen_op_mtc0_tcstatus(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcstatus();
rn = "TCStatus";
-// break;
+ break;
case 2:
-// gen_op_mtc0_tcbind(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcbind();
rn = "TCBind";
-// break;
+ break;
case 3:
-// gen_op_mtc0_tcrestart(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcrestart();
rn = "TCRestart";
-// break;
+ break;
case 4:
-// gen_op_mtc0_tchalt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tchalt();
rn = "TCHalt";
-// break;
+ break;
case 5:
-// gen_op_mtc0_tccontext(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tccontext();
rn = "TCContext";
-// break;
+ break;
case 6:
-// gen_op_mtc0_tcschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcschedule();
rn = "TCSchedule";
-// break;
+ break;
case 7:
-// gen_op_mtc0_tcschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcschefback();
rn = "TCScheFBack";
-// break;
+ break;
default:
goto die;
}
rn = "PageMask";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_pagegrain();
rn = "PageGrain";
break;
rn = "Wired";
break;
case 1:
-// gen_op_mtc0_srsconf0(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf0();
rn = "SRSConf0";
-// break;
+ break;
case 2:
-// gen_op_mtc0_srsconf1(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf1();
rn = "SRSConf1";
-// break;
+ break;
case 3:
-// gen_op_mtc0_srsconf2(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf2();
rn = "SRSConf2";
-// break;
+ break;
case 4:
-// gen_op_mtc0_srsconf3(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf3();
rn = "SRSConf3";
-// break;
+ break;
case 5:
-// gen_op_mtc0_srsconf4(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf4();
rn = "SRSConf4";
-// break;
+ break;
default:
goto die;
}
case 7:
switch (sel) {
case 0:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_hwrena();
rn = "HWREna";
break;
switch (sel) {
case 0:
gen_op_mtc0_status();
+ /* BS_STOP isn't good enough here, hflags may have changed. */
+ gen_save_pc(ctx->pc + 4);
+ ctx->bstate = BS_EXCP;
rn = "Status";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_intctl();
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_srsctl();
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "SRSCtl";
break;
case 3:
-// gen_op_mtc0_srsmap(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsmap();
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "SRSMap";
-// break;
+ break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
case 13:
switch (sel) {
rn = "PRid";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_ebase();
rn = "EBase";
break;
break;
case 18:
switch (sel) {
- case 0:
- gen_op_mtc0_watchlo0();
+ case 0 ... 7:
+ gen_op_mtc0_watchlo(sel);
rn = "WatchLo";
break;
- case 1:
-// gen_op_mtc0_watchlo1();
- rn = "WatchLo1";
-// break;
- case 2:
-// gen_op_mtc0_watchlo2();
- rn = "WatchLo2";
-// break;
- case 3:
-// gen_op_mtc0_watchlo3();
- rn = "WatchLo3";
-// break;
- case 4:
-// gen_op_mtc0_watchlo4();
- rn = "WatchLo4";
-// break;
- case 5:
-// gen_op_mtc0_watchlo5();
- rn = "WatchLo5";
-// break;
- case 6:
-// gen_op_mtc0_watchlo6();
- rn = "WatchLo6";
-// break;
- case 7:
-// gen_op_mtc0_watchlo7();
- rn = "WatchLo7";
-// break;
default:
goto die;
}
break;
case 19:
switch (sel) {
- case 0:
- gen_op_mtc0_watchhi0();
+ case 0 ... 7:
+ gen_op_mtc0_watchhi(sel);
rn = "WatchHi";
break;
- case 1:
-// gen_op_mtc0_watchhi1();
- rn = "WatchHi1";
-// break;
- case 2:
-// gen_op_mtc0_watchhi2();
- rn = "WatchHi2";
-// break;
- case 3:
-// gen_op_mtc0_watchhi3();
- rn = "WatchHi3";
-// break;
- case 4:
-// gen_op_mtc0_watchhi4();
- rn = "WatchHi4";
-// break;
- case 5:
-// gen_op_mtc0_watchhi5();
- rn = "WatchHi5";
-// break;
- case 6:
-// gen_op_mtc0_watchhi6();
- rn = "WatchHi6";
-// break;
- case 7:
-// gen_op_mtc0_watchhi7();
- rn = "WatchHi7";
-// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
-#ifdef TARGET_MIPS64
- /* Nothing writable in lower 32 bits */
+#if defined(TARGET_MIPS64)
+ check_insn(env, ctx, ISA_MIPS3);
+ gen_op_mtc0_xcontext();
rn = "XContext";
break;
#endif
switch (sel) {
case 0:
gen_op_mtc0_debug(); /* EJTAG support */
+ /* BS_STOP isn't good enough here, hflags may have changed. */
+ gen_save_pc(ctx->pc + 4);
+ ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
// gen_op_mtc0_tracecontrol(); /* PDtrace support */
rn = "TraceControl";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
// break;
case 2:
// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
rn = "TraceControl2";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
// break;
case 3:
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
// gen_op_mtc0_usertracedata(); /* PDtrace support */
rn = "UserTraceData";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
// break;
case 4:
// gen_op_mtc0_debug(); /* PDtrace support */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "TraceBPC";
// break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
case 24:
switch (sel) {
generate_exception(ctx, EXCP_RI);
}
-#ifdef TARGET_MIPS64
-static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
+#if defined(TARGET_MIPS64)
+static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ if (sel != 0)
+ check_insn(env, ctx, ISA_MIPS64);
+
switch (reg) {
case 0:
switch (sel) {
rn = "Index";
break;
case 1:
-// gen_op_dmfc0_mvpcontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_mvpcontrol();
rn = "MVPControl";
-// break;
+ break;
case 2:
-// gen_op_dmfc0_mvpconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_mvpconf0();
rn = "MVPConf0";
-// break;
+ break;
case 3:
-// gen_op_dmfc0_mvpconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_mvpconf1();
rn = "MVPConf1";
-// break;
+ break;
default:
goto die;
}
rn = "Random";
break;
case 1:
-// gen_op_dmfc0_vpecontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpecontrol();
rn = "VPEControl";
-// break;
+ break;
case 2:
-// gen_op_dmfc0_vpeconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeconf0();
rn = "VPEConf0";
-// break;
+ break;
case 3:
-// gen_op_dmfc0_vpeconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeconf1();
rn = "VPEConf1";
-// break;
+ break;
case 4:
-// gen_op_dmfc0_YQMask(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_yqmask();
rn = "YQMask";
-// break;
+ break;
case 5:
-// gen_op_dmfc0_vpeschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_vpeschedule();
rn = "VPESchedule";
-// break;
+ break;
case 6:
-// gen_op_dmfc0_vpeschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_vpeschefback();
rn = "VPEScheFBack";
-// break;
+ break;
case 7:
-// gen_op_dmfc0_vpeopt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_vpeopt();
rn = "VPEOpt";
-// break;
+ break;
default:
goto die;
}
rn = "EntryLo0";
break;
case 1:
-// gen_op_dmfc0_tcstatus(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tcstatus();
rn = "TCStatus";
-// break;
+ break;
case 2:
-// gen_op_dmfc0_tcbind(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mfc0_tcbind();
rn = "TCBind";
-// break;
+ break;
case 3:
-// gen_op_dmfc0_tcrestart(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_tcrestart();
rn = "TCRestart";
-// break;
+ break;
case 4:
-// gen_op_dmfc0_tchalt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_tchalt();
rn = "TCHalt";
-// break;
+ break;
case 5:
-// gen_op_dmfc0_tccontext(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_tccontext();
rn = "TCContext";
-// break;
+ break;
case 6:
-// gen_op_dmfc0_tcschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_tcschedule();
rn = "TCSchedule";
-// break;
+ break;
case 7:
-// gen_op_dmfc0_tcschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmfc0_tcschefback();
rn = "TCScheFBack";
-// break;
+ break;
default:
goto die;
}
rn = "PageMask";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_pagegrain();
rn = "PageGrain";
break;
rn = "Wired";
break;
case 1:
-// gen_op_dmfc0_srsconf0(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf0();
rn = "SRSConf0";
-// break;
+ break;
case 2:
-// gen_op_dmfc0_srsconf1(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf1();
rn = "SRSConf1";
-// break;
+ break;
case 3:
-// gen_op_dmfc0_srsconf2(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf2();
rn = "SRSConf2";
-// break;
+ break;
case 4:
-// gen_op_dmfc0_srsconf3(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf3();
rn = "SRSConf3";
-// break;
+ break;
case 5:
-// gen_op_dmfc0_srsconf4(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsconf4();
rn = "SRSConf4";
-// break;
+ break;
default:
goto die;
}
case 7:
switch (sel) {
case 0:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_hwrena();
rn = "HWREna";
break;
rn = "Status";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_intctl();
rn = "IntCtl";
break;
case 2:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_srsctl();
rn = "SRSCtl";
break;
case 3:
- gen_op_mfc0_srsmap(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mfc0_srsmap();
rn = "SRSMap";
break;
default:
rn = "PRid";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mfc0_ebase();
rn = "EBase";
break;
break;
case 18:
switch (sel) {
- case 0:
- gen_op_dmfc0_watchlo0();
+ case 0 ... 7:
+ gen_op_dmfc0_watchlo(sel);
rn = "WatchLo";
break;
- case 1:
-// gen_op_dmfc0_watchlo1();
- rn = "WatchLo1";
-// break;
- case 2:
-// gen_op_dmfc0_watchlo2();
- rn = "WatchLo2";
-// break;
- case 3:
-// gen_op_dmfc0_watchlo3();
- rn = "WatchLo3";
-// break;
- case 4:
-// gen_op_dmfc0_watchlo4();
- rn = "WatchLo4";
-// break;
- case 5:
-// gen_op_dmfc0_watchlo5();
- rn = "WatchLo5";
-// break;
- case 6:
-// gen_op_dmfc0_watchlo6();
- rn = "WatchLo6";
-// break;
- case 7:
-// gen_op_dmfc0_watchlo7();
- rn = "WatchLo7";
-// break;
default:
goto die;
}
break;
case 19:
switch (sel) {
- case 0:
- gen_op_mfc0_watchhi0();
+ case 0 ... 7:
+ gen_op_mfc0_watchhi(sel);
rn = "WatchHi";
break;
- case 1:
-// gen_op_mfc0_watchhi1();
- rn = "WatchHi1";
-// break;
- case 2:
-// gen_op_mfc0_watchhi2();
- rn = "WatchHi2";
-// break;
- case 3:
-// gen_op_mfc0_watchhi3();
- rn = "WatchHi3";
-// break;
- case 4:
-// gen_op_mfc0_watchhi4();
- rn = "WatchHi4";
-// break;
- case 5:
-// gen_op_mfc0_watchhi5();
- rn = "WatchHi5";
-// break;
- case 6:
-// gen_op_mfc0_watchhi6();
- rn = "WatchHi6";
-// break;
- case 7:
-// gen_op_mfc0_watchhi7();
- rn = "WatchHi7";
-// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
-#ifdef TARGET_MIPS64
+ check_insn(env, ctx, ISA_MIPS3);
gen_op_dmfc0_xcontext();
rn = "XContext";
break;
-#endif
default:
goto die;
}
generate_exception(ctx, EXCP_RI);
}
-static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
+static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
+ if (sel != 0)
+ check_insn(env, ctx, ISA_MIPS64);
+
switch (reg) {
case 0:
switch (sel) {
rn = "Index";
break;
case 1:
-// gen_op_dmtc0_mvpcontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_mvpcontrol();
rn = "MVPControl";
-// break;
+ break;
case 2:
-// gen_op_dmtc0_mvpconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ /* ignored */
rn = "MVPConf0";
-// break;
+ break;
case 3:
-// gen_op_dmtc0_mvpconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ /* ignored */
rn = "MVPConf1";
-// break;
+ break;
default:
goto die;
}
rn = "Random";
break;
case 1:
-// gen_op_dmtc0_vpecontrol(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpecontrol();
rn = "VPEControl";
-// break;
+ break;
case 2:
-// gen_op_dmtc0_vpeconf0(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeconf0();
rn = "VPEConf0";
-// break;
+ break;
case 3:
-// gen_op_dmtc0_vpeconf1(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeconf1();
rn = "VPEConf1";
-// break;
+ break;
case 4:
-// gen_op_dmtc0_YQMask(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_yqmask();
rn = "YQMask";
-// break;
+ break;
case 5:
-// gen_op_dmtc0_vpeschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeschedule();
rn = "VPESchedule";
-// break;
+ break;
case 6:
-// gen_op_dmtc0_vpeschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeschefback();
rn = "VPEScheFBack";
-// break;
+ break;
case 7:
-// gen_op_dmtc0_vpeopt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_vpeopt();
rn = "VPEOpt";
-// break;
+ break;
default:
goto die;
}
case 2:
switch (sel) {
case 0:
- gen_op_dmtc0_entrylo0();
+ gen_op_mtc0_entrylo0();
rn = "EntryLo0";
break;
case 1:
-// gen_op_dmtc0_tcstatus(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcstatus();
rn = "TCStatus";
-// break;
+ break;
case 2:
-// gen_op_dmtc0_tcbind(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcbind();
rn = "TCBind";
-// break;
+ break;
case 3:
-// gen_op_dmtc0_tcrestart(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcrestart();
rn = "TCRestart";
-// break;
+ break;
case 4:
-// gen_op_dmtc0_tchalt(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tchalt();
rn = "TCHalt";
-// break;
+ break;
case 5:
-// gen_op_dmtc0_tccontext(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tccontext();
rn = "TCContext";
-// break;
+ break;
case 6:
-// gen_op_dmtc0_tcschedule(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcschedule();
rn = "TCSchedule";
-// break;
+ break;
case 7:
-// gen_op_dmtc0_tcschefback(); /* MT ASE */
+ check_insn(env, ctx, ASE_MT);
+ gen_op_mtc0_tcschefback();
rn = "TCScheFBack";
-// break;
+ break;
default:
goto die;
}
case 3:
switch (sel) {
case 0:
- gen_op_dmtc0_entrylo1();
+ gen_op_mtc0_entrylo1();
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- gen_op_dmtc0_context();
+ gen_op_mtc0_context();
rn = "Context";
break;
case 1:
-// gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
+// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
rn = "PageMask";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_pagegrain();
rn = "PageGrain";
break;
rn = "Wired";
break;
case 1:
-// gen_op_dmtc0_srsconf0(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf0();
rn = "SRSConf0";
-// break;
+ break;
case 2:
-// gen_op_dmtc0_srsconf1(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf1();
rn = "SRSConf1";
-// break;
+ break;
case 3:
-// gen_op_dmtc0_srsconf2(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf2();
rn = "SRSConf2";
-// break;
+ break;
case 4:
-// gen_op_dmtc0_srsconf3(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf3();
rn = "SRSConf3";
-// break;
+ break;
case 5:
-// gen_op_dmtc0_srsconf4(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsconf4();
rn = "SRSConf4";
-// break;
+ break;
default:
goto die;
}
case 7:
switch (sel) {
case 0:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_hwrena();
rn = "HWREna";
break;
switch (sel) {
case 0:
gen_op_mtc0_status();
+ /* BS_STOP isn't good enough here, hflags may have changed. */
+ gen_save_pc(ctx->pc + 4);
+ ctx->bstate = BS_EXCP;
rn = "Status";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_intctl();
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_srsctl();
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "SRSCtl";
break;
case 3:
- gen_op_mtc0_srsmap(); /* shadow registers */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ gen_op_mtc0_srsmap();
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "SRSMap";
break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
case 13:
switch (sel) {
case 14:
switch (sel) {
case 0:
- gen_op_dmtc0_epc();
+ gen_op_mtc0_epc();
rn = "EPC";
break;
default:
rn = "PRid";
break;
case 1:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_op_mtc0_ebase();
rn = "EBase";
break;
break;
case 18:
switch (sel) {
- case 0:
- gen_op_dmtc0_watchlo0();
+ case 0 ... 7:
+ gen_op_mtc0_watchlo(sel);
rn = "WatchLo";
break;
- case 1:
-// gen_op_dmtc0_watchlo1();
- rn = "WatchLo1";
-// break;
- case 2:
-// gen_op_dmtc0_watchlo2();
- rn = "WatchLo2";
-// break;
- case 3:
-// gen_op_dmtc0_watchlo3();
- rn = "WatchLo3";
-// break;
- case 4:
-// gen_op_dmtc0_watchlo4();
- rn = "WatchLo4";
-// break;
- case 5:
-// gen_op_dmtc0_watchlo5();
- rn = "WatchLo5";
-// break;
- case 6:
-// gen_op_dmtc0_watchlo6();
- rn = "WatchLo6";
-// break;
- case 7:
-// gen_op_dmtc0_watchlo7();
- rn = "WatchLo7";
-// break;
default:
goto die;
}
break;
case 19:
switch (sel) {
- case 0:
- gen_op_mtc0_watchhi0();
+ case 0 ... 7:
+ gen_op_mtc0_watchhi(sel);
rn = "WatchHi";
break;
- case 1:
-// gen_op_dmtc0_watchhi1();
- rn = "WatchHi1";
-// break;
- case 2:
-// gen_op_dmtc0_watchhi2();
- rn = "WatchHi2";
-// break;
- case 3:
-// gen_op_dmtc0_watchhi3();
- rn = "WatchHi3";
-// break;
- case 4:
-// gen_op_dmtc0_watchhi4();
- rn = "WatchHi4";
-// break;
- case 5:
-// gen_op_dmtc0_watchhi5();
- rn = "WatchHi5";
-// break;
- case 6:
-// gen_op_dmtc0_watchhi6();
- rn = "WatchHi6";
-// break;
- case 7:
-// gen_op_dmtc0_watchhi7();
- rn = "WatchHi7";
-// break;
default:
goto die;
}
case 20:
switch (sel) {
case 0:
-#ifdef TARGET_MIPS64
- gen_op_dmtc0_xcontext();
+ check_insn(env, ctx, ISA_MIPS3);
+ gen_op_mtc0_xcontext();
rn = "XContext";
break;
-#endif
default:
goto die;
}
switch (sel) {
case 0:
gen_op_mtc0_debug(); /* EJTAG support */
+ /* BS_STOP isn't good enough here, hflags may have changed. */
+ gen_save_pc(ctx->pc + 4);
+ ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
-// gen_op_dmtc0_tracecontrol(); /* PDtrace support */
+// gen_op_mtc0_tracecontrol(); /* PDtrace support */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "TraceControl";
// break;
case 2:
-// gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
+// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "TraceControl2";
// break;
case 3:
-// gen_op_dmtc0_usertracedata(); /* PDtrace support */
+// gen_op_mtc0_usertracedata(); /* PDtrace support */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "UserTraceData";
// break;
case 4:
-// gen_op_dmtc0_debug(); /* PDtrace support */
+// gen_op_mtc0_debug(); /* PDtrace support */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
rn = "TraceBPC";
// break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
case 24:
switch (sel) {
case 0:
- gen_op_dmtc0_depc(); /* EJTAG support */
+ gen_op_mtc0_depc(); /* EJTAG support */
rn = "DEPC";
break;
default:
rn = "Performance0";
break;
case 1:
-// gen_op_dmtc0_performance1();
+// gen_op_mtc0_performance1();
rn = "Performance1";
// break;
case 2:
-// gen_op_dmtc0_performance2();
+// gen_op_mtc0_performance2();
rn = "Performance2";
// break;
case 3:
-// gen_op_dmtc0_performance3();
+// gen_op_mtc0_performance3();
rn = "Performance3";
// break;
case 4:
-// gen_op_dmtc0_performance4();
+// gen_op_mtc0_performance4();
rn = "Performance4";
// break;
case 5:
-// gen_op_dmtc0_performance5();
+// gen_op_mtc0_performance5();
rn = "Performance5";
// break;
case 6:
-// gen_op_dmtc0_performance6();
+// gen_op_mtc0_performance6();
rn = "Performance6";
// break;
case 7:
-// gen_op_dmtc0_performance7();
+// gen_op_mtc0_performance7();
rn = "Performance7";
// break;
default:
rn = "CacheErr";
break;
default:
- goto die;
+ goto die;
+ }
+ break;
+ case 28:
+ switch (sel) {
+ case 0:
+ case 2:
+ case 4:
+ case 6:
+ gen_op_mtc0_taglo();
+ rn = "TagLo";
+ break;
+ case 1:
+ case 3:
+ case 5:
+ case 7:
+ gen_op_mtc0_datalo();
+ rn = "DataLo";
+ break;
+ default:
+ goto die;
+ }
+ break;
+ case 29:
+ switch (sel) {
+ case 0:
+ case 2:
+ case 4:
+ case 6:
+ gen_op_mtc0_taghi();
+ rn = "TagHi";
+ break;
+ case 1:
+ case 3:
+ case 5:
+ case 7:
+ gen_op_mtc0_datahi();
+ rn = "DataHi";
+ break;
+ default:
+ rn = "invalid sel";
+ goto die;
+ }
+ break;
+ case 30:
+ switch (sel) {
+ case 0:
+ gen_op_mtc0_errorepc();
+ rn = "ErrorEPC";
+ break;
+ default:
+ goto die;
+ }
+ break;
+ case 31:
+ switch (sel) {
+ case 0:
+ gen_op_mtc0_desave(); /* EJTAG support */
+ rn = "DESAVE";
+ break;
+ default:
+ goto die;
+ }
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
+ break;
+ default:
+ goto die;
+ }
+#if defined MIPS_DEBUG_DISAS
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
+ fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
+ rn, reg, sel);
+ }
+#endif
+ return;
+
+die:
+#if defined MIPS_DEBUG_DISAS
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
+ fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
+ rn, reg, sel);
+ }
+#endif
+ generate_exception(ctx, EXCP_RI);
+}
+#endif /* TARGET_MIPS64 */
+
+static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
+ int u, int sel, int h)
+{
+ int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
+
+ if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
+ ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
+ (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
+ gen_op_set_T0(-1);
+ else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
+ (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ gen_op_set_T0(-1);
+ else if (u == 0) {
+ switch (rt) {
+ case 2:
+ switch (sel) {
+ case 1:
+ gen_op_mftc0_tcstatus();
+ break;
+ case 2:
+ gen_op_mftc0_tcbind();
+ break;
+ case 3:
+ gen_op_mftc0_tcrestart();
+ break;
+ case 4:
+ gen_op_mftc0_tchalt();
+ break;
+ case 5:
+ gen_op_mftc0_tccontext();
+ break;
+ case 6:
+ gen_op_mftc0_tcschedule();
+ break;
+ case 7:
+ gen_op_mftc0_tcschefback();
+ break;
+ default:
+ gen_mfc0(env, ctx, rt, sel);
+ break;
+ }
+ break;
+ case 10:
+ switch (sel) {
+ case 0:
+ gen_op_mftc0_entryhi();
+ break;
+ default:
+ gen_mfc0(env, ctx, rt, sel);
+ break;
+ }
+ case 12:
+ switch (sel) {
+ case 0:
+ gen_op_mftc0_status();
+ break;
+ default:
+ gen_mfc0(env, ctx, rt, sel);
+ break;
+ }
+ case 23:
+ switch (sel) {
+ case 0:
+ gen_op_mftc0_debug();
+ break;
+ default:
+ gen_mfc0(env, ctx, rt, sel);
+ break;
+ }
+ break;
+ default:
+ gen_mfc0(env, ctx, rt, sel);
+ }
+ } else switch (sel) {
+ /* GPR registers. */
+ case 0:
+ gen_op_mftgpr(rt);
+ break;
+ /* Auxiliary CPU registers */
+ case 1:
+ switch (rt) {
+ case 0:
+ gen_op_mftlo(0);
+ break;
+ case 1:
+ gen_op_mfthi(0);
+ break;
+ case 2:
+ gen_op_mftacx(0);
+ break;
+ case 4:
+ gen_op_mftlo(1);
+ break;
+ case 5:
+ gen_op_mfthi(1);
+ break;
+ case 6:
+ gen_op_mftacx(1);
+ break;
+ case 8:
+ gen_op_mftlo(2);
+ break;
+ case 9:
+ gen_op_mfthi(2);
+ break;
+ case 10:
+ gen_op_mftacx(2);
+ break;
+ case 12:
+ gen_op_mftlo(3);
+ break;
+ case 13:
+ gen_op_mfthi(3);
+ break;
+ case 14:
+ gen_op_mftacx(3);
+ break;
+ case 16:
+ gen_op_mftdsp();
+ break;
+ default:
+ goto die;
+ }
+ break;
+ /* Floating point (COP1). */
+ case 2:
+ /* XXX: For now we support only a single FPU context. */
+ if (h == 0) {
+ GEN_LOAD_FREG_FTN(WT0, rt);
+ gen_op_mfc1();
+ } else {
+ GEN_LOAD_FREG_FTN(WTH0, rt);
+ gen_op_mfhc1();
+ }
+ break;
+ case 3:
+ /* XXX: For now we support only a single FPU context. */
+ gen_op_cfc1(rt);
+ break;
+ /* COP2: Not implemented. */
+ case 4:
+ case 5:
+ /* fall through */
+ default:
+ goto die;
+ }
+#if defined MIPS_DEBUG_DISAS
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
+ fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
+ rt, u, sel, h);
+ }
+#endif
+ return;
+
+die:
+#if defined MIPS_DEBUG_DISAS
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
+ fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
+ rt, u, sel, h);
+ }
+#endif
+ generate_exception(ctx, EXCP_RI);
+}
+
+static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
+ int u, int sel, int h)
+{
+ int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
+
+ if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
+ ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) !=
+ (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE))))
+ /* NOP */ ;
+ else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
+ (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ /* NOP */ ;
+ else if (u == 0) {
+ switch (rd) {
+ case 2:
+ switch (sel) {
+ case 1:
+ gen_op_mttc0_tcstatus();
+ break;
+ case 2:
+ gen_op_mttc0_tcbind();
+ break;
+ case 3:
+ gen_op_mttc0_tcrestart();
+ break;
+ case 4:
+ gen_op_mttc0_tchalt();
+ break;
+ case 5:
+ gen_op_mttc0_tccontext();
+ break;
+ case 6:
+ gen_op_mttc0_tcschedule();
+ break;
+ case 7:
+ gen_op_mttc0_tcschefback();
+ break;
+ default:
+ gen_mtc0(env, ctx, rd, sel);
+ break;
+ }
+ break;
+ case 10:
+ switch (sel) {
+ case 0:
+ gen_op_mttc0_entryhi();
+ break;
+ default:
+ gen_mtc0(env, ctx, rd, sel);
+ break;
+ }
+ case 12:
+ switch (sel) {
+ case 0:
+ gen_op_mttc0_status();
+ break;
+ default:
+ gen_mtc0(env, ctx, rd, sel);
+ break;
+ }
+ case 23:
+ switch (sel) {
+ case 0:
+ gen_op_mttc0_debug();
+ break;
+ default:
+ gen_mtc0(env, ctx, rd, sel);
+ break;
+ }
+ break;
+ default:
+ gen_mtc0(env, ctx, rd, sel);
}
+ } else switch (sel) {
+ /* GPR registers. */
+ case 0:
+ gen_op_mttgpr(rd);
break;
- case 28:
- switch (sel) {
+ /* Auxiliary CPU registers */
+ case 1:
+ switch (rd) {
case 0:
- case 2:
- case 4:
- case 6:
- gen_op_mtc0_taglo();
- rn = "TagLo";
+ gen_op_mttlo(0);
break;
case 1:
- case 3:
- case 5:
- case 7:
- gen_op_mtc0_datalo();
- rn = "DataLo";
+ gen_op_mtthi(0);
break;
- default:
- goto die;
- }
- break;
- case 29:
- switch (sel) {
- case 0:
case 2:
+ gen_op_mttacx(0);
+ break;
case 4:
- case 6:
- gen_op_mtc0_taghi();
- rn = "TagHi";
+ gen_op_mttlo(1);
break;
- case 1:
- case 3:
case 5:
- case 7:
- gen_op_mtc0_datahi();
- rn = "DataHi";
+ gen_op_mtthi(1);
break;
- default:
- rn = "invalid sel";
- goto die;
- }
- break;
- case 30:
- switch (sel) {
- case 0:
- gen_op_dmtc0_errorepc();
- rn = "ErrorEPC";
+ case 6:
+ gen_op_mttacx(1);
+ break;
+ case 8:
+ gen_op_mttlo(2);
+ break;
+ case 9:
+ gen_op_mtthi(2);
+ break;
+ case 10:
+ gen_op_mttacx(2);
+ break;
+ case 12:
+ gen_op_mttlo(3);
+ break;
+ case 13:
+ gen_op_mtthi(3);
+ break;
+ case 14:
+ gen_op_mttacx(3);
+ break;
+ case 16:
+ gen_op_mttdsp();
break;
default:
goto die;
}
break;
- case 31:
- switch (sel) {
- case 0:
- gen_op_mtc0_desave(); /* EJTAG support */
- rn = "DESAVE";
- break;
- default:
- goto die;
+ /* Floating point (COP1). */
+ case 2:
+ /* XXX: For now we support only a single FPU context. */
+ if (h == 0) {
+ gen_op_mtc1();
+ GEN_STORE_FTN_FREG(rd, WT0);
+ } else {
+ gen_op_mthc1();
+ GEN_STORE_FTN_FREG(rd, WTH0);
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
+ case 3:
+ /* XXX: For now we support only a single FPU context. */
+ gen_op_ctc1(rd);
+ break;
+ /* COP2: Not implemented. */
+ case 4:
+ case 5:
+ /* fall through */
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
- fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
- rn, reg, sel);
+ fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
+ rd, u, sel, h);
}
#endif
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
- fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
- rn, reg, sel);
+ fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
+ rd, u, sel, h);
}
#endif
generate_exception(ctx, EXCP_RI);
}
-#endif /* TARGET_MIPS64 */
static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
{
switch (opc) {
case OPC_MFC0:
if (rt == 0) {
- /* Treat as NOP */
+ /* Treat as NOP. */
return;
}
- gen_mfc0(ctx, rd, ctx->opcode & 0x7);
+ gen_mfc0(env, ctx, rd, ctx->opcode & 0x7);
gen_op_store_T0_gpr(rt);
opn = "mfc0";
break;
case OPC_MTC0:
- GEN_LOAD_REG_TN(T0, rt);
- gen_mtc0(ctx, rd, ctx->opcode & 0x7);
+ GEN_LOAD_REG_T0(rt);
+ save_cpu_state(ctx, 1);
+ gen_mtc0(env, ctx, rd, ctx->opcode & 0x7);
opn = "mtc0";
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DMFC0:
+ check_insn(env, ctx, ISA_MIPS3);
if (rt == 0) {
- /* Treat as NOP */
+ /* Treat as NOP. */
return;
}
- gen_dmfc0(ctx, rd, ctx->opcode & 0x7);
+ gen_dmfc0(env, ctx, rd, ctx->opcode & 0x7);
gen_op_store_T0_gpr(rt);
opn = "dmfc0";
break;
case OPC_DMTC0:
- GEN_LOAD_REG_TN(T0, rt);
- gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
+ check_insn(env, ctx, ISA_MIPS3);
+ GEN_LOAD_REG_T0(rt);
+ save_cpu_state(ctx, 1);
+ gen_dmtc0(env, ctx, rd, ctx->opcode & 0x7);
opn = "dmtc0";
break;
#endif
+ case OPC_MFTR:
+ check_insn(env, ctx, ASE_MT);
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return;
+ }
+ gen_mftr(env, ctx, rt, (ctx->opcode >> 5) & 1,
+ ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
+ gen_op_store_T0_gpr(rd);
+ opn = "mftr";
+ break;
+ case OPC_MTTR:
+ check_insn(env, ctx, ASE_MT);
+ GEN_LOAD_REG_T0(rt);
+ gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1,
+ ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
+ opn = "mttr";
+ break;
case OPC_TLBWI:
opn = "tlbwi";
- if (!env->do_tlbwi)
+ if (!env->tlb->do_tlbwi)
goto die;
gen_op_tlbwi();
break;
case OPC_TLBWR:
opn = "tlbwr";
- if (!env->do_tlbwr)
+ if (!env->tlb->do_tlbwr)
goto die;
gen_op_tlbwr();
break;
case OPC_TLBP:
opn = "tlbp";
- if (!env->do_tlbp)
+ if (!env->tlb->do_tlbp)
goto die;
gen_op_tlbp();
break;
case OPC_TLBR:
opn = "tlbr";
- if (!env->do_tlbr)
+ if (!env->tlb->do_tlbr)
goto die;
gen_op_tlbr();
break;
case OPC_ERET:
opn = "eret";
- save_cpu_state(ctx, 0);
+ check_insn(env, ctx, ISA_MIPS2);
+ save_cpu_state(ctx, 1);
gen_op_eret();
ctx->bstate = BS_EXCP;
break;
case OPC_DERET:
opn = "deret";
+ check_insn(env, ctx, ISA_MIPS32);
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
} else {
- save_cpu_state(ctx, 0);
+ save_cpu_state(ctx, 1);
gen_op_deret();
ctx->bstate = BS_EXCP;
}
break;
case OPC_WAIT:
opn = "wait";
+ check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
/* If we get an exception, we want to restart at next instruction */
ctx->pc += 4;
save_cpu_state(ctx, 1);
}
/* CP1 Branches (before delay slot) */
-static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
+static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
int32_t cc, int32_t offset)
{
target_ulong btarget;
const char *opn = "cp1 cond branch";
+ if (cc != 0)
+ check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
+
btarget = ctx->pc + 4 + offset;
switch (op) {
gen_op_save_bcond();
break;
case OPC_BC1FANY2:
- gen_op_bc1fany2(cc);
- opn = "bc1fany2";
+ gen_op_bc1any2f(cc);
+ opn = "bc1any2f";
goto not_likely;
case OPC_BC1TANY2:
- gen_op_bc1tany2(cc);
- opn = "bc1tany2";
+ gen_op_bc1any2t(cc);
+ opn = "bc1any2t";
goto not_likely;
case OPC_BC1FANY4:
- gen_op_bc1fany4(cc);
- opn = "bc1fany4";
+ gen_op_bc1any4f(cc);
+ opn = "bc1any4f";
goto not_likely;
case OPC_BC1TANY4:
- gen_op_bc1tany4(cc);
- opn = "bc1tany4";
+ gen_op_bc1any4t(cc);
+ opn = "bc1any4t";
not_likely:
ctx->hflags |= MIPS_HFLAG_BC;
gen_op_set_bcond();
/* Coprocessor 1 (FPU) */
-/* verify if floating point register is valid; an operation is not defined
- * if bit 0 of any register specification is set and the FR bit in the
- * Status register equals zero, since the register numbers specify an
- * even-odd pair of adjacent coprocessor general registers. When the FR bit
- * in the Status register equals one, both even and odd register numbers
- * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
- *
- * Multiple 64 bit wide registers can be checked by calling
- * CHECK_FR(ctx, freg1 | freg2 | ... | fregN);
- *
- * FIXME: This is broken for R2, it needs to be checked at runtime, not
- * at translation time.
- */
-#define CHECK_FR(ctx, freg) do { \
- if (!((ctx)->CP0_Status & (1 << CP0St_FR)) && ((freg) & 1)) { \
- MIPS_INVAL("FPU mode"); \
- generate_exception (ctx, EXCP_RI); \
- return; \
- } \
- } while(0)
-
#define FOP(func, fmt) (((fmt) << 21) | (func))
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
case OPC_MFC1:
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_mfc1();
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "mfc1";
break;
case OPC_MTC1:
- GEN_LOAD_REG_TN(T0, rt);
+ GEN_LOAD_REG_T0(rt);
gen_op_mtc1();
GEN_STORE_FTN_FREG(fs, WT0);
opn = "mtc1";
break;
case OPC_CFC1:
- GEN_LOAD_IMM_TN(T1, fs);
- gen_op_cfc1();
- GEN_STORE_TN_REG(rt, T0);
+ gen_op_cfc1(fs);
+ GEN_STORE_T0_REG(rt);
opn = "cfc1";
break;
case OPC_CTC1:
- GEN_LOAD_IMM_TN(T1, fs);
- GEN_LOAD_REG_TN(T0, rt);
- gen_op_ctc1();
+ GEN_LOAD_REG_T0(rt);
+ gen_op_ctc1(fs);
opn = "ctc1";
break;
case OPC_DMFC1:
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_dmfc1();
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "dmfc1";
break;
case OPC_DMTC1:
- GEN_LOAD_REG_TN(T0, rt);
+ GEN_LOAD_REG_T0(rt);
gen_op_dmtc1();
GEN_STORE_FTN_FREG(fs, DT0);
opn = "dmtc1";
break;
case OPC_MFHC1:
- CHECK_FR(ctx, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_mfhc1();
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
opn = "mfhc1";
break;
case OPC_MTHC1:
- CHECK_FR(ctx, fs);
- GEN_LOAD_REG_TN(T0, rt);
+ GEN_LOAD_REG_T0(rt);
gen_op_mthc1();
GEN_STORE_FTN_FREG(fs, WTH0);
opn = "mthc1";
{
uint32_t ccbit;
- GEN_LOAD_REG_TN(T0, rd);
- GEN_LOAD_REG_TN(T1, rs);
- if (cc)
+ GEN_LOAD_REG_T0(rd);
+ GEN_LOAD_REG_T1(rs);
+ if (cc) {
ccbit = 1 << (24 + cc);
- else
+ } else
ccbit = 1 << 23;
if (!tf)
gen_op_movf(ccbit);
else
gen_op_movt(ccbit);
- GEN_STORE_TN_REG(rd, T0);
+ GEN_STORE_T0_REG(rd);
}
#define GEN_MOVCF(fmt) \
{ \
uint32_t ccbit; \
\
- if (cc) \
+ if (cc) { \
ccbit = 1 << (24 + cc); \
- else \
+ } else \
ccbit = 1 << 23; \
if (!tf) \
glue(gen_op_float_movf_, fmt)(ccbit); \
GEN_MOVCF(ps);
#undef GEN_MOVCF
-static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
- int fs, int fd, int cc)
+static void gen_farith (DisasContext *ctx, uint32_t op1,
+ int ft, int fs, int fd, int cc)
{
const char *opn = "farith";
const char *condnames[] = {
opn = "neg.s";
break;
case FOP(8, 16):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_roundl_s();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "round.l.s";
break;
case FOP(9, 16):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_truncl_s();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "trunc.l.s";
break;
case FOP(10, 16):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_ceill_s();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "ceil.l.s";
break;
case FOP(11, 16):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_floorl_s();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "floor.w.s";
break;
case FOP(17, 16):
- GEN_LOAD_REG_TN(T0, ft);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
gen_movcf_s(ctx, (ft >> 2) & 0x7, ft & 0x1);
opn = "movcf.s";
break;
case FOP(18, 16):
- GEN_LOAD_REG_TN(T0, ft);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
gen_op_float_movz_s();
opn = "movz.s";
break;
case FOP(19, 16):
- GEN_LOAD_REG_TN(T0, ft);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
gen_op_float_movn_s();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "movn.s";
break;
+ case FOP(21, 16):
+ check_cop1x(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_recip_s();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "recip.s";
+ break;
+ case FOP(22, 16):
+ check_cop1x(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_rsqrt_s();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "rsqrt.s";
+ break;
+ case FOP(28, 16):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ GEN_LOAD_FREG_FTN(WT2, fd);
+ gen_op_float_recip2_s();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "recip2.s";
+ break;
+ case FOP(29, 16):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_recip1_s();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "recip1.s";
+ break;
+ case FOP(30, 16):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_rsqrt1_s();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "rsqrt1.s";
+ break;
+ case FOP(31, 16):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ GEN_LOAD_FREG_FTN(WT2, ft);
+ gen_op_float_rsqrt2_s();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "rsqrt2.s";
+ break;
case FOP(33, 16):
- CHECK_FR(ctx, fd);
+ check_cp1_registers(ctx, fd);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_cvtd_s();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "cvt.w.s";
break;
case FOP(37, 16):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_cvtl_s();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "cvt.l.s";
break;
case FOP(38, 16):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT1, fs);
GEN_LOAD_FREG_FTN(WT0, ft);
gen_op_float_cvtps_s();
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
if (ctx->opcode & (1 << 6)) {
+ check_cop1x(ctx);
gen_cmpabs_s(func-48, cc);
opn = condnames_abs[func-48];
} else {
}
break;
case FOP(0, 17):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_registers(ctx, fs | ft | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
gen_op_float_add_d();
optype = BINOP;
break;
case FOP(1, 17):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_registers(ctx, fs | ft | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
gen_op_float_sub_d();
optype = BINOP;
break;
case FOP(2, 17):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_registers(ctx, fs | ft | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
gen_op_float_mul_d();
optype = BINOP;
break;
case FOP(3, 17):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_registers(ctx, fs | ft | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
gen_op_float_div_d();
optype = BINOP;
break;
case FOP(4, 17):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_registers(ctx, fs | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_sqrt_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "sqrt.d";
break;
case FOP(5, 17):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_registers(ctx, fs | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_abs_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "abs.d";
break;
case FOP(6, 17):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_registers(ctx, fs | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_mov_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "mov.d";
break;
case FOP(7, 17):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_registers(ctx, fs | fd);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_chs_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "neg.d";
break;
case FOP(8, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_roundl_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "round.l.d";
break;
case FOP(9, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_truncl_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "trunc.l.d";
break;
case FOP(10, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_ceill_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "ceil.l.d";
break;
case FOP(11, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_floorl_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "floor.l.d";
break;
case FOP(12, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_registers(ctx, fs);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_roundw_d();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "round.w.d";
break;
case FOP(13, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_registers(ctx, fs);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_truncw_d();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "trunc.w.d";
break;
case FOP(14, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_registers(ctx, fs);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_ceilw_d();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "ceil.w.d";
break;
case FOP(15, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_registers(ctx, fs);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_floorw_d();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "floor.w.d";
break;
case FOP(17, 17):
- GEN_LOAD_REG_TN(T0, ft);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT2, fd);
gen_movcf_d(ctx, (ft >> 2) & 0x7, ft & 0x1);
opn = "movcf.d";
break;
case FOP(18, 17):
- GEN_LOAD_REG_TN(T0, ft);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT2, fd);
gen_op_float_movz_d();
opn = "movz.d";
break;
case FOP(19, 17):
- GEN_LOAD_REG_TN(T0, ft);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT2, fd);
gen_op_float_movn_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "movn.d";
break;
+ case FOP(21, 17):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(DT0, fs);
+ gen_op_float_recip_d();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "recip.d";
+ break;
+ case FOP(22, 17):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(DT0, fs);
+ gen_op_float_rsqrt_d();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "rsqrt.d";
+ break;
+ case FOP(28, 17):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(DT0, fs);
+ GEN_LOAD_FREG_FTN(DT2, ft);
+ gen_op_float_recip2_d();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "recip2.d";
+ break;
+ case FOP(29, 17):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(DT0, fs);
+ gen_op_float_recip1_d();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "recip1.d";
+ break;
+ case FOP(30, 17):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(DT0, fs);
+ gen_op_float_rsqrt1_d();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "rsqrt1.d";
+ break;
+ case FOP(31, 17):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(DT0, fs);
+ GEN_LOAD_FREG_FTN(DT2, ft);
+ gen_op_float_rsqrt2_d();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "rsqrt2.d";
+ break;
case FOP(48, 17):
case FOP(49, 17):
case FOP(50, 17):
case FOP(61, 17):
case FOP(62, 17):
case FOP(63, 17):
- CHECK_FR(ctx, fs | ft);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
if (ctx->opcode & (1 << 6)) {
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fs | ft);
gen_cmpabs_d(func-48, cc);
opn = condnames_abs[func-48];
} else {
+ check_cp1_registers(ctx, fs | ft);
gen_cmp_d(func-48, cc);
opn = condnames[func-48];
}
break;
case FOP(32, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_registers(ctx, fs);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_cvts_d();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "cvt.s.d";
break;
case FOP(36, 17):
- CHECK_FR(ctx, fs);
+ check_cp1_registers(ctx, fs);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_cvtw_d();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "cvt.w.d";
break;
case FOP(37, 17):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_cvtl_d();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "cvt.s.w";
break;
case FOP(33, 20):
- CHECK_FR(ctx, fd);
+ check_cp1_registers(ctx, fd);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_cvtd_w();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "cvt.d.w";
break;
case FOP(32, 21):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_cvts_l();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "cvt.s.l";
break;
case FOP(33, 21):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(DT0, fs);
gen_op_float_cvtd_l();
GEN_STORE_FTN_FREG(fd, DT2);
opn = "cvt.d.l";
break;
case FOP(38, 20):
- case FOP(38, 21):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_float_cvtps_pw();
opn = "cvt.ps.pw";
break;
case FOP(0, 22):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "add.ps";
break;
case FOP(1, 22):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "sub.ps";
break;
case FOP(2, 22):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "mul.ps";
break;
case FOP(5, 22):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_float_abs_ps();
opn = "abs.ps";
break;
case FOP(6, 22):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_float_mov_ps();
opn = "mov.ps";
break;
case FOP(7, 22):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_float_chs_ps();
opn = "neg.ps";
break;
case FOP(17, 22):
- GEN_LOAD_REG_TN(T0, ft);
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
opn = "movcf.ps";
break;
case FOP(18, 22):
- GEN_LOAD_REG_TN(T0, ft);
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
opn = "movz.ps";
break;
case FOP(19, 22):
- GEN_LOAD_REG_TN(T0, ft);
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_REG_T0(ft);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT2, fd);
opn = "movn.ps";
break;
case FOP(24, 22):
- CHECK_FR(ctx, fs | fd | ft);
- GEN_LOAD_FREG_FTN(WT0, fs);
- GEN_LOAD_FREG_FTN(WTH0, fs);
- GEN_LOAD_FREG_FTN(WT1, ft);
- GEN_LOAD_FREG_FTN(WTH1, ft);
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, ft);
+ GEN_LOAD_FREG_FTN(WTH0, ft);
+ GEN_LOAD_FREG_FTN(WT1, fs);
+ GEN_LOAD_FREG_FTN(WTH1, fs);
gen_op_float_addr_ps();
GEN_STORE_FTN_FREG(fd, WT2);
GEN_STORE_FTN_FREG(fd, WTH2);
opn = "addr.ps";
break;
+ case FOP(26, 22):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, ft);
+ GEN_LOAD_FREG_FTN(WTH0, ft);
+ GEN_LOAD_FREG_FTN(WT1, fs);
+ GEN_LOAD_FREG_FTN(WTH1, fs);
+ gen_op_float_mulr_ps();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ GEN_STORE_FTN_FREG(fd, WTH2);
+ opn = "mulr.ps";
+ break;
+ case FOP(28, 22):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ GEN_LOAD_FREG_FTN(WTH0, fs);
+ GEN_LOAD_FREG_FTN(WT2, fd);
+ GEN_LOAD_FREG_FTN(WTH2, fd);
+ gen_op_float_recip2_ps();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ GEN_STORE_FTN_FREG(fd, WTH2);
+ opn = "recip2.ps";
+ break;
+ case FOP(29, 22):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ GEN_LOAD_FREG_FTN(WTH0, fs);
+ gen_op_float_recip1_ps();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ GEN_STORE_FTN_FREG(fd, WTH2);
+ opn = "recip1.ps";
+ break;
+ case FOP(30, 22):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ GEN_LOAD_FREG_FTN(WTH0, fs);
+ gen_op_float_rsqrt1_ps();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ GEN_STORE_FTN_FREG(fd, WTH2);
+ opn = "rsqrt1.ps";
+ break;
+ case FOP(31, 22):
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ GEN_LOAD_FREG_FTN(WTH0, fs);
+ GEN_LOAD_FREG_FTN(WT2, ft);
+ GEN_LOAD_FREG_FTN(WTH2, ft);
+ gen_op_float_rsqrt2_ps();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ GEN_STORE_FTN_FREG(fd, WTH2);
+ opn = "rsqrt2.ps";
+ break;
case FOP(32, 22):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_float_cvts_pu();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "cvt.s.pu";
break;
case FOP(36, 22):
- CHECK_FR(ctx, fs | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
gen_op_float_cvtpw_ps();
opn = "cvt.pw.ps";
break;
case FOP(40, 22):
- CHECK_FR(ctx, fs);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
gen_op_float_cvts_pl();
GEN_STORE_FTN_FREG(fd, WT2);
opn = "cvt.s.pl";
break;
case FOP(44, 22):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
gen_op_float_pll_ps();
opn = "pll.ps";
break;
case FOP(45, 22):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH1, ft);
gen_op_float_plu_ps();
opn = "plu.ps";
break;
case FOP(46, 22):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
gen_op_float_pul_ps();
opn = "pul.ps";
break;
case FOP(47, 22):
- CHECK_FR(ctx, fs | ft | fd);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WTH1, ft);
gen_op_float_puu_ps();
case FOP(61, 22):
case FOP(62, 22):
case FOP(63, 22):
- CHECK_FR(ctx, fs | ft);
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
}
/* Coprocessor 3 (FPU) */
-static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd,
- int base, int index)
+static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
+ int fd, int fs, int base, int index)
{
const char *opn = "extended float load/store";
+ int store = 0;
- GEN_LOAD_REG_TN(T0, base);
- GEN_LOAD_REG_TN(T1, index);
+ if (base == 0) {
+ if (index == 0)
+ gen_op_reset_T0();
+ else
+ GEN_LOAD_REG_T0(index);
+ } else if (index == 0) {
+ GEN_LOAD_REG_T0(base);
+ } else {
+ GEN_LOAD_REG_T0(base);
+ GEN_LOAD_REG_T1(index);
+ gen_op_addr_add();
+ }
/* Don't do NOP if destination is zero: we must perform the actual
- * memory access
- */
+ memory access. */
switch (opc) {
case OPC_LWXC1:
- op_ldst(lwxc1);
+ check_cop1x(ctx);
+ op_ldst(lwc1);
GEN_STORE_FTN_FREG(fd, WT0);
opn = "lwxc1";
break;
case OPC_LDXC1:
- op_ldst(ldxc1);
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd);
+ op_ldst(ldc1);
GEN_STORE_FTN_FREG(fd, DT0);
opn = "ldxc1";
break;
case OPC_LUXC1:
+ check_cp1_64bitmode(ctx);
op_ldst(luxc1);
GEN_STORE_FTN_FREG(fd, DT0);
opn = "luxc1";
break;
case OPC_SWXC1:
- GEN_LOAD_FREG_FTN(WT0, fd);
- op_ldst(swxc1);
+ check_cop1x(ctx);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ op_ldst(swc1);
opn = "swxc1";
+ store = 1;
break;
case OPC_SDXC1:
- GEN_LOAD_FREG_FTN(DT0, fd);
- op_ldst(sdxc1);
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fs);
+ GEN_LOAD_FREG_FTN(DT0, fs);
+ op_ldst(sdc1);
opn = "sdxc1";
+ store = 1;
break;
case OPC_SUXC1:
- GEN_LOAD_FREG_FTN(DT0, fd);
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_FREG_FTN(DT0, fs);
op_ldst(suxc1);
opn = "suxc1";
+ store = 1;
break;
default:
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
return;
}
- MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[fd],regnames[index], regnames[base]);
+ MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
+ regnames[index], regnames[base]);
}
-static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd,
- int fr, int fs, int ft)
+static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
+ int fd, int fr, int fs, int ft)
{
const char *opn = "flt3_arith";
- /* All of those work only on 64bit FPUs. */
- CHECK_FR(ctx, fd | fr | fs | ft);
switch (opc) {
case OPC_ALNV_PS:
- GEN_LOAD_REG_TN(T0, fr);
+ check_cp1_64bitmode(ctx);
+ GEN_LOAD_REG_T0(fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
gen_op_float_alnv_ps();
opn = "alnv.ps";
break;
case OPC_MADD_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "madd.s";
break;
case OPC_MADD_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "madd.d";
break;
case OPC_MADD_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "madd.ps";
break;
case OPC_MSUB_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "msub.s";
break;
case OPC_MSUB_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "msub.d";
break;
case OPC_MSUB_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "msub.ps";
break;
case OPC_NMADD_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "nmadd.s";
break;
case OPC_NMADD_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "nmadd.d";
break;
case OPC_NMADD_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
opn = "nmadd.ps";
break;
case OPC_NMSUB_S:
+ check_cop1x(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
GEN_LOAD_FREG_FTN(WT2, fr);
opn = "nmsub.s";
break;
case OPC_NMSUB_D:
+ check_cop1x(ctx);
+ check_cp1_registers(ctx, fd | fs | ft | fr);
GEN_LOAD_FREG_FTN(DT0, fs);
GEN_LOAD_FREG_FTN(DT1, ft);
GEN_LOAD_FREG_FTN(DT2, fr);
opn = "nmsub.d";
break;
case OPC_NMSUB_PS:
+ check_cp1_64bitmode(ctx);
GEN_LOAD_FREG_FTN(WT0, fs);
GEN_LOAD_FREG_FTN(WTH0, fs);
GEN_LOAD_FREG_FTN(WT1, ft);
/* MIPS16 extension to MIPS32 */
/* SmartMIPS extension to MIPS32 */
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
/* MDMX extension to MIPS64 */
-/* MIPS-3D extension to MIPS64 */
#endif
switch (op1) {
case OPC_SLL: /* Arithmetic with immediate */
case OPC_SRL ... OPC_SRA:
- gen_arith_imm(ctx, op1, rd, rt, sa);
+ gen_arith_imm(env, ctx, op1, rd, rt, sa);
break;
+ case OPC_MOVZ ... OPC_MOVN:
+ check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
case OPC_SLLV: /* Arithmetic */
case OPC_SRLV ... OPC_SRAV:
- case OPC_MOVZ ... OPC_MOVN:
case OPC_ADD ... OPC_NOR:
case OPC_SLT ... OPC_SLTU:
- gen_arith(ctx, op1, rd, rs, rt);
+ gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_MULT ... OPC_DIVU:
- gen_muldiv(ctx, op1, rs, rt);
+ if (sa) {
+ check_insn(env, ctx, INSN_VR54XX);
+ op1 = MASK_MUL_VR54XX(ctx->opcode);
+ gen_mul_vr54xx(ctx, op1, rd, rs, rt);
+ } else
+ gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_JR ... OPC_JALR:
gen_compute_branch(ctx, op1, rs, rd, sa);
#endif
break;
case OPC_SYNC:
- /* Treat as a noop. */
+ /* Treat as NOP. */
break;
case OPC_MOVCI:
+ check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
- gen_op_cp1_enabled();
+ check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
(ctx->opcode >> 16) & 1);
} else {
}
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
/* MIPS64 specific opcodes */
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
case OPC_DSLL32:
case OPC_DSRL32 ... OPC_DSRA32:
- gen_arith_imm(ctx, op1, rd, rt, sa);
+ check_insn(env, ctx, ISA_MIPS3);
+ check_mips_64(ctx);
+ gen_arith_imm(env, ctx, op1, rd, rt, sa);
break;
case OPC_DSLLV:
case OPC_DSRLV ... OPC_DSRAV:
case OPC_DADD ... OPC_DSUBU:
- gen_arith(ctx, op1, rd, rs, rt);
+ check_insn(env, ctx, ISA_MIPS3);
+ check_mips_64(ctx);
+ gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_DMULT ... OPC_DDIVU:
+ check_insn(env, ctx, ISA_MIPS3);
+ check_mips_64(ctx);
gen_muldiv(ctx, op1, rs, rt);
break;
#endif
switch (op1) {
case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
case OPC_MSUB ... OPC_MSUBU:
+ check_insn(env, ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_MUL:
- gen_arith(ctx, op1, rd, rs, rt);
+ gen_arith(env, ctx, op1, rd, rs, rt);
break;
case OPC_CLZ ... OPC_CLO:
+ check_insn(env, ctx, ISA_MIPS32);
gen_cl(ctx, op1, rd, rs);
break;
case OPC_SDBBP:
/* XXX: not clear which exception should be raised
* when in debug mode...
*/
+ check_insn(env, ctx, ISA_MIPS32);
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
generate_exception(ctx, EXCP_DBp);
} else {
generate_exception(ctx, EXCP_DBp);
}
- /* Treat as a noop */
+ /* Treat as NOP. */
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
case OPC_DCLZ ... OPC_DCLO:
+ check_insn(env, ctx, ISA_MIPS64);
+ check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
#endif
switch (op1) {
case OPC_EXT:
case OPC_INS:
+ check_insn(env, ctx, ISA_MIPS32R2);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_BSHFL:
+ check_insn(env, ctx, ISA_MIPS32R2);
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_WSBH:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
gen_op_wsbh();
break;
case OPC_SEB:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
gen_op_seb();
break;
case OPC_SEH:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
gen_op_seh();
break;
default: /* Invalid */
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rd, T0);
+ GEN_STORE_T0_REG(rd);
break;
case OPC_RDHWR:
+ check_insn(env, ctx, ISA_MIPS32R2);
switch (rd) {
case 0:
save_cpu_state(ctx, 1);
break;
case 29:
#if defined (CONFIG_USER_ONLY)
- gen_op_tls_value ();
+ gen_op_tls_value();
break;
#endif
default: /* Invalid */
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
+ break;
+ case OPC_FORK:
+ check_insn(env, ctx, ASE_MT);
+ GEN_LOAD_REG_T0(rt);
+ GEN_LOAD_REG_T1(rs);
+ gen_op_fork();
break;
-#ifdef TARGET_MIPS64
+ case OPC_YIELD:
+ check_insn(env, ctx, ASE_MT);
+ GEN_LOAD_REG_T0(rs);
+ gen_op_yield();
+ GEN_STORE_T0_REG(rd);
+ break;
+#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
+ check_insn(env, ctx, ISA_MIPS64R2);
+ check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_DBSHFL:
+ check_insn(env, ctx, ISA_MIPS64R2);
+ check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DSBH:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
gen_op_dsbh();
break;
case OPC_DSHD:
- GEN_LOAD_REG_TN(T1, rt);
+ GEN_LOAD_REG_T1(rt);
gen_op_dshd();
break;
default: /* Invalid */
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rd, T0);
+ GEN_STORE_T0_REG(rd);
+ break;
#endif
default: /* Invalid */
MIPS_INVAL("special3");
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SYNCI:
- /* treat as noop */
+ check_insn(env, ctx, ISA_MIPS32R2);
+ /* Treat as NOP. */
break;
default: /* Invalid */
MIPS_INVAL("regimm");
}
break;
case OPC_CP0:
- save_cpu_state(ctx, 1);
- gen_op_cp0_enabled();
+ check_cp0_enabled(ctx);
op1 = MASK_CP0(ctx->opcode);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
-#ifdef TARGET_MIPS64
+ case OPC_MFTR:
+ case OPC_MTTR:
+#if defined(TARGET_MIPS64)
case OPC_DMFC0:
case OPC_DMTC0:
#endif
case OPC_MFMC0:
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
+ case OPC_DMT:
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dmt();
+ break;
+ case OPC_EMT:
+ check_insn(env, ctx, ASE_MT);
+ gen_op_emt();
+ break;
+ case OPC_DVPE:
+ check_insn(env, ctx, ASE_MT);
+ gen_op_dvpe();
+ break;
+ case OPC_EVPE:
+ check_insn(env, ctx, ASE_MT);
+ gen_op_evpe();
+ break;
case OPC_DI:
+ check_insn(env, ctx, ISA_MIPS32R2);
+ save_cpu_state(ctx, 1);
gen_op_di();
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
break;
case OPC_EI:
+ check_insn(env, ctx, ISA_MIPS32R2);
+ save_cpu_state(ctx, 1);
gen_op_ei();
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
generate_exception(ctx, EXCP_RI);
break;
}
- GEN_STORE_TN_REG(rt, T0);
+ GEN_STORE_T0_REG(rt);
break;
case OPC_RDPGPR:
+ check_insn(env, ctx, ISA_MIPS32R2);
+ GEN_LOAD_SRSREG_TN(T0, rt);
+ GEN_STORE_T0_REG(rd);
+ break;
case OPC_WRPGPR:
- if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) {
- /* Shadow registers not implemented. */
- GEN_LOAD_REG_TN(T0, rt);
- GEN_STORE_TN_REG(rd, T0);
- } else {
- MIPS_INVAL("shadow register move");
- generate_exception(ctx, EXCP_RI);
- }
+ check_insn(env, ctx, ISA_MIPS32R2);
+ GEN_LOAD_REG_T0(rt);
+ GEN_STORE_TN_SRSREG(rd, T0);
break;
default:
MIPS_INVAL("cp0");
}
break;
case OPC_ADDI ... OPC_LUI: /* Arithmetic with immediate opcode */
- gen_arith_imm(ctx, op, rt, rs, imm);
+ gen_arith_imm(env, ctx, op, rt, rs, imm);
break;
case OPC_J ... OPC_JAL: /* Jump */
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_ldst(ctx, op, rt, rs, imm);
break;
case OPC_CACHE:
- /* Treat as a noop */
- break;
+ check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
+ /* Treat as NOP. */
+ break;
case OPC_PREF:
- /* Treat as a noop */
+ check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
+ /* Treat as NOP. */
break;
/* Floating point (COP1). */
case OPC_SDC1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
- gen_op_cp1_enabled();
+ check_cp1_enabled(ctx);
gen_flt_ldst(ctx, op, rt, rs, imm);
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
case OPC_CP1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
- gen_op_cp1_enabled();
+ check_cp1_enabled(ctx);
op1 = MASK_CP1(ctx->opcode);
switch (op1) {
+ case OPC_MFHC1:
+ case OPC_MTHC1:
+ check_insn(env, ctx, ISA_MIPS32R2);
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
case OPC_CTC1:
-#ifdef TARGET_MIPS64
+ gen_cp1(ctx, op1, rt, rd);
+ break;
+#if defined(TARGET_MIPS64)
case OPC_DMFC1:
case OPC_DMTC1:
-#endif
- case OPC_MFHC1:
- case OPC_MTHC1:
+ check_insn(env, ctx, ISA_MIPS3);
gen_cp1(ctx, op1, rt, rd);
break;
- case OPC_BC1:
+#endif
case OPC_BC1ANY2:
case OPC_BC1ANY4:
- gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
+ check_cop1x(ctx);
+ check_insn(env, ctx, ASE_MIPS3D);
+ /* fall through */
+ case OPC_BC1:
+ gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
return;
case OPC_S_FMT:
case OPC_CP3:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
save_cpu_state(ctx, 1);
- gen_op_cp1_enabled();
+ check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
switch (op1) {
case OPC_LWXC1:
case OPC_SWXC1:
case OPC_SDXC1:
case OPC_SUXC1:
- gen_flt3_ldst(ctx, op1, sa, rs, rt);
+ gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break;
case OPC_PREFX:
- /* treat as noop */
+ /* Treat as NOP. */
break;
case OPC_ALNV_PS:
case OPC_MADD_S:
}
break;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
case OPC_LD:
case OPC_SCD:
case OPC_SD:
+ check_insn(env, ctx, ISA_MIPS3);
+ check_mips_64(ctx);
gen_ldst(ctx, op, rt, rs, imm);
break;
case OPC_DADDI ... OPC_DADDIU:
- gen_arith_imm(ctx, op, rt, rs, imm);
+ check_insn(env, ctx, ISA_MIPS3);
+ check_mips_64(ctx);
+ gen_arith_imm(env, ctx, op, rt, rs, imm);
break;
#endif
-#ifdef MIPS_HAS_MIPS16
case OPC_JALX:
+ check_insn(env, ctx, ASE_MIPS16);
/* MIPS16: Not implemented. */
-#endif
-#ifdef MIPS_HAS_MDMX
case OPC_MDMX:
+ check_insn(env, ctx, ASE_MDMX);
/* MDMX: Not implemented. */
-#endif
default: /* Invalid */
MIPS_INVAL("major opcode");
generate_exception(ctx, EXCP_RI);
}
}
-static inline int
+static always_inline int
gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
int search_pc)
{
- DisasContext ctx, *ctxp = &ctx;
+ DisasContext ctx;
target_ulong pc_start;
uint16_t *gen_opc_end;
int j, lj = -1;
ctx.tb = tb;
ctx.bstate = BS_NONE;
/* Restore delay slot state from the tb context. */
- ctx.hflags = tb->flags;
- ctx.saved_hflags = ctx.hflags;
- switch (ctx.hflags & MIPS_HFLAG_BMASK) {
- case MIPS_HFLAG_BR:
- gen_op_restore_breg_target();
- break;
- case MIPS_HFLAG_B:
- ctx.btarget = env->btarget;
- break;
- case MIPS_HFLAG_BC:
- case MIPS_HFLAG_BL:
- ctx.btarget = env->btarget;
- gen_op_restore_bcond();
- break;
- }
+ ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
+ restore_cpu_state(env, &ctx);
#if defined(CONFIG_USER_ONLY)
- ctx.mem_idx = 0;
+ ctx.mem_idx = MIPS_HFLAG_UM;
#else
- ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
+ ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
#endif
- ctx.CP0_Status = env->CP0_Status;
#ifdef DEBUG_DISAS
if (loglevel & CPU_LOG_TB_CPU) {
fprintf(logfile, "------------------------------------------------\n");
#endif
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
- fprintf(logfile, "\ntb %p super %d cond %04x\n",
+ fprintf(logfile, "\ntb %p idx %d hflags %04x\n",
tb, ctx.mem_idx, ctx.hflags);
#endif
while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
if (env->nb_breakpoints > 0) {
for(j = 0; j < env->nb_breakpoints; j++) {
if (env->breakpoints[j] == ctx.pc) {
- save_cpu_state(ctxp, 1);
+ save_cpu_state(&ctx, 1);
ctx.bstate = BS_BRANCH;
gen_op_debug();
+ /* Include the breakpoint location or the tb won't
+ * be flushed when it must be. */
+ ctx.pc += 4;
goto done_generating;
}
}
#endif
}
if (env->singlestep_enabled) {
- save_cpu_state(ctxp, ctx.bstate == BS_NONE);
+ save_cpu_state(&ctx, ctx.bstate == BS_NONE);
gen_op_debug();
} else {
switch (ctx.bstate) {
case BS_STOP:
gen_op_interrupt_restart();
- /* Fall through. */
+ gen_goto_tb(&ctx, 0, ctx.pc);
+ break;
case BS_NONE:
- save_cpu_state(ctxp, 0);
+ save_cpu_state(&ctx, 0);
gen_goto_tb(&ctx, 0, ctx.pc);
break;
case BS_EXCP:
}
}
done_generating:
+ ctx.last_T0_store = NULL;
*gen_opc_ptr = INDEX_op_end;
if (search_pc) {
j = gen_opc_ptr - gen_opc_buf;
lj++;
while (lj <= j)
gen_opc_instr_start[lj++] = 0;
- tb->size = 0;
} else {
tb->size = ctx.pc - pc_start;
}
fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
}
#endif
-
+
return 0;
}
return gen_intermediate_code_internal(env, tb, 1);
}
-void fpu_dump_state(CPUState *env, FILE *f,
+void fpu_dump_state(CPUState *env, FILE *f,
int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
{
int i;
- int is_fpu64 = !!(env->CP0_Status & (1 << CP0St_FR));
+ int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
#define printfpr(fp) \
do { \
fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
- env->fcr0, env->fcr31, is_fpu64, env->fp_status, get_float_exception_flags(&env->fp_status));
- fpu_fprintf(f, "FT0: "); printfpr(&env->ft0);
- fpu_fprintf(f, "FT1: "); printfpr(&env->ft1);
- fpu_fprintf(f, "FT2: "); printfpr(&env->ft2);
+ env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,
+ get_float_exception_flags(&env->fpu->fp_status));
+ fpu_fprintf(f, "FT0: "); printfpr(&env->fpu->ft0);
+ fpu_fprintf(f, "FT1: "); printfpr(&env->fpu->ft1);
+ fpu_fprintf(f, "FT2: "); printfpr(&env->fpu->ft2);
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
fpu_fprintf(f, "%3s: ", fregnames[i]);
- printfpr(&env->fpr[i]);
+ printfpr(&env->fpu->fpr[i]);
}
#undef printfpr
void dump_fpu (CPUState *env)
{
- if (loglevel) {
+ if (loglevel) {
fprintf(logfile, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
- env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
+ env->PC[env->current_tc], env->HI[0][env->current_tc], env->LO[0][env->current_tc], env->hflags, env->btarget, env->bcond);
fpu_dump_state(env, logfile, fprintf, 0);
}
}
{
int i;
- if (!SIGN_EXT_P(env->PC))
- cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->PC);
- if (!SIGN_EXT_P(env->HI))
- cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI);
- if (!SIGN_EXT_P(env->LO))
- cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO);
+ if (!SIGN_EXT_P(env->PC[env->current_tc]))
+ cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->PC[env->current_tc]);
+ if (!SIGN_EXT_P(env->HI[0][env->current_tc]))
+ cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI[0][env->current_tc]);
+ if (!SIGN_EXT_P(env->LO[0][env->current_tc]))
+ cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO[0][env->current_tc]);
if (!SIGN_EXT_P(env->btarget))
cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget);
for (i = 0; i < 32; i++) {
- if (!SIGN_EXT_P(env->gpr[i]))
- cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[i]);
+ if (!SIGN_EXT_P(env->gpr[i][env->current_tc]))
+ cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[i][env->current_tc]);
}
if (!SIGN_EXT_P(env->CP0_EPC))
}
#endif
-void cpu_dump_state (CPUState *env, FILE *f,
+void cpu_dump_state (CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
{
- uint32_t c0_status;
int i;
-
+
cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
- env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
+ env->PC[env->current_tc], env->HI[env->current_tc], env->LO[env->current_tc], env->hflags, env->btarget, env->bcond);
for (i = 0; i < 32; i++) {
if ((i & 3) == 0)
cpu_fprintf(f, "GPR%02d:", i);
- cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]);
+ cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i][env->current_tc]);
if ((i & 3) == 3)
cpu_fprintf(f, "\n");
}
- c0_status = env->CP0_Status;
-
cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
- c0_status, env->CP0_Cause, env->CP0_EPC);
+ env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
- if (c0_status & (1 << CP0St_CU1))
+ if (env->hflags & MIPS_HFLAG_FPU)
fpu_dump_state(env, f, cpu_fprintf, flags);
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
#endif
}
-CPUMIPSState *cpu_mips_init (void)
+#include "translate_init.c"
+
+CPUMIPSState *cpu_mips_init (const char *cpu_model)
{
CPUMIPSState *env;
+ const mips_def_t *def;
+ def = cpu_mips_find_by_name(cpu_model);
+ if (!def)
+ return NULL;
env = qemu_mallocz(sizeof(CPUMIPSState));
if (!env)
return NULL;
+ env->cpu_model = def;
+
cpu_exec_init(env);
+ env->cpu_model_str = cpu_model;
cpu_reset(env);
return env;
}
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
* come back to the jump. */
- env->CP0_ErrorEPC = env->PC - 4;
- env->hflags &= ~MIPS_HFLAG_BMASK;
+ env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
} else {
- env->CP0_ErrorEPC = env->PC;
+ env->CP0_ErrorEPC = env->PC[env->current_tc];
}
- env->hflags = 0;
- env->PC = (int32_t)0xBFC00000;
+ env->PC[env->current_tc] = (int32_t)0xBFC00000;
env->CP0_Wired = 0;
/* SMP not implemented */
env->CP0_EBase = 0x80000000;
/* vectored interrupts not implemented, timer on int 7,
no performance counters. */
env->CP0_IntCtl = 0xe0000000;
- env->CP0_WatchLo = 0;
- env->CP0_WatchHi = 0;
+ {
+ int i;
+
+ for (i = 0; i < 7; i++) {
+ env->CP0_WatchLo[i] = 0;
+ env->CP0_WatchHi[i] = 0x80000000;
+ }
+ env->CP0_WatchLo[7] = 0;
+ env->CP0_WatchHi[7] = 0;
+ }
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
#endif
env->exception_index = EXCP_NONE;
#if defined(CONFIG_USER_ONLY)
- env->hflags |= MIPS_HFLAG_UM;
+ env->hflags = MIPS_HFLAG_UM;
env->user_mode_only = 1;
+#else
+ env->hflags = MIPS_HFLAG_CP0;
#endif
+ cpu_mips_register(env, env->cpu_model);
}
-
-#include "translate_init.c"
projects / qemu / blobdiff