* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include <math.h>
#include "exec.h"
#define MIPS_DEBUG_DISAS
+#define GETPC() (__builtin_return_address(0))
+
/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit(void)
longjmp(env->jmp_env, 1);
}
-__attribute__ (( regparm(2) ))
void do_raise_exception_err (uint32_t exception, int error_code)
{
#if 1
cpu_loop_exit();
}
-__attribute__ (( regparm(1) ))
void do_raise_exception (uint32_t exception)
{
do_raise_exception_err(exception, 0);
}
+void do_restore_state (void *pc_ptr)
+{
+ TranslationBlock *tb;
+ unsigned long pc = (unsigned long) pc_ptr;
+
+ tb = tb_find_pc (pc);
+ cpu_restore_state (tb, env, pc, NULL);
+}
+
+void do_raise_exception_direct (uint32_t exception)
+{
+ do_restore_state (GETPC ());
+ do_raise_exception_err (exception, 0);
+}
+
#define MEMSUFFIX _raw
#include "op_helper_mem.c"
#undef MEMSUFFIX
void do_mult (void)
{
- set_HILO((int64_t)T0 * (int64_t)T1);
+ set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
}
void do_multu (void)
{
int64_t tmp;
- tmp = ((int64_t)T0 * (int64_t)T1);
+ tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
set_HILO((int64_t)get_HILO() + tmp);
}
{
int64_t tmp;
- tmp = ((int64_t)T0 * (int64_t)T1);
+ tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
set_HILO((int64_t)get_HILO() - tmp);
}
}
#endif
+#if defined(CONFIG_USER_ONLY)
+void do_mfc0 (int reg, int sel)
+{
+ cpu_abort(env, "mfc0 reg=%d sel=%d\n", reg, sel);
+}
+void do_mtc0 (int reg, int sel)
+{
+ cpu_abort(env, "mtc0 reg=%d sel=%d\n", reg, sel);
+}
+
+void do_tlbwi (void)
+{
+ cpu_abort(env, "tlbwi\n");
+}
+
+void do_tlbwr (void)
+{
+ cpu_abort(env, "tlbwr\n");
+}
+
+void do_tlbp (void)
+{
+ cpu_abort(env, "tlbp\n");
+}
+
+void do_tlbr (void)
+{
+ cpu_abort(env, "tlbr\n");
+}
+#else
+
/* CP0 helpers */
-__attribute__ (( regparm(2) ))
void do_mfc0 (int reg, int sel)
{
const unsigned char *rn;
case 12:
T0 = env->CP0_Status;
if (env->hflags & MIPS_HFLAG_UM)
- T0 |= CP0St_UM;
+ T0 |= (1 << CP0St_UM);
if (env->hflags & MIPS_HFLAG_ERL)
- T0 |= CP0St_ERL;
+ T0 |= (1 << CP0St_ERL);
if (env->hflags & MIPS_HFLAG_EXL)
- T0 |= CP0St_EXL;
+ T0 |= (1 << CP0St_EXL);
rn = "Status";
break;
case 13:
return;
}
-__attribute__ (( regparm(2) ))
void do_mtc0 (int reg, int sel)
{
const unsigned char *rn;
uint32_t val, old, mask;
- int i, raise;
if (sel != 0 && reg != 16 && reg != 28) {
val = -1;
rn = "Index";
break;
case 2:
- val = T0 & 0x03FFFFFFF;
+ val = T0 & 0x3FFFFFFF;
old = env->CP0_EntryLo0;
env->CP0_EntryLo0 = val;
rn = "EntryLo0";
break;
case 3:
- val = T0 & 0x03FFFFFFF;
+ val = T0 & 0x3FFFFFFF;
old = env->CP0_EntryLo1;
env->CP0_EntryLo1 = val;
rn = "EntryLo1";
break;
case 4:
- val = (env->CP0_Context & 0xFF000000) | (T0 & 0x00FFFFF0);
+ val = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0);
old = env->CP0_Context;
env->CP0_Context = val;
rn = "Context";
rn = "Count";
break;
case 10:
- val = T0 & 0xFFFFF0FF;
+ val = T0 & 0xFFFFE0FF;
old = env->CP0_EntryHi;
env->CP0_EntryHi = val;
+ /* If the ASID changes, flush qemu's TLB. */
+ if ((old & 0xFF) != (val & 0xFF))
+ tlb_flush (env, 1);
rn = "EntryHi";
break;
case 11:
old = env->CP0_Status;
env->CP0_Status = val;
/* If we unmasked an asserted IRQ, raise it */
- mask = 0x0000FC00;
+ mask = 0x0000FF00;
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
old, val, env->CP0_Cause, old & mask, val & mask,
env->CP0_Cause & mask);
}
-#if 1
if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
!(env->hflags & MIPS_HFLAG_EXL) &&
!(env->hflags & MIPS_HFLAG_ERL) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- (env->CP0_Cause & mask)) {
+ !(env->hflags & MIPS_HFLAG_DM) &&
+ (env->CP0_Status & env->CP0_Cause & mask)) {
if (logfile)
fprintf(logfile, "Raise pending IRQs\n");
env->interrupt_request |= CPU_INTERRUPT_HARD;
- do_raise_exception(EXCP_EXT_INTERRUPT);
- } else if (!(val & 0x00000001) && (old & 0x00000001)) {
+ } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
}
-#endif
rn = "Status";
break;
case 13:
old = env->CP0_Cause;
env->CP0_Cause = val;
#if 0
- /* Check if we ever asserted a software IRQ */
- for (i = 0; i < 2; i++) {
- mask = 0x100 << i;
- if ((val & mask) & !(old & mask))
- mips_set_irq(i);
+ {
+ int i;
+ /* Check if we ever asserted a software IRQ */
+ for (i = 0; i < 2; i++) {
+ mask = 0x100 << i;
+ if ((val & mask) & !(old & mask))
+ mips_set_irq(i);
+ }
}
#endif
rn = "Cause";
/* TLB management */
#if defined(MIPS_USES_R4K_TLB)
-__attribute__ (( regparm(1) ))
-static void invalidate_tb (int idx)
+static void invalidate_tlb (int idx)
{
tlb_t *tlb;
- target_ulong addr, end;
+ target_ulong addr;
tlb = &env->tlb[idx];
- if (tlb->V[0]) {
- addr = tlb->PFN[0];
- end = addr + (tlb->end - tlb->VPN);
- tb_invalidate_page_range(addr, end);
+ if (tlb->V0) {
+ tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN);
+ addr = tlb->VPN;
+ while (addr < tlb->end) {
+ tlb_flush_page (env, addr);
+ addr += TARGET_PAGE_SIZE;
+ }
}
- if (tlb->V[1]) {
- addr = tlb->PFN[1];
- end = addr + (tlb->end - tlb->VPN);
- tb_invalidate_page_range(addr, end);
+ if (tlb->V1) {
+ tb_invalidate_page_range(tlb->PFN[1], tlb->end2 - tlb->end);
+ addr = tlb->end;
+ while (addr < tlb->end2) {
+ tlb_flush_page (env, addr);
+ addr += TARGET_PAGE_SIZE;
+ }
}
}
-__attribute__ (( regparm(1) ))
-static void fill_tb (int idx)
+static void fill_tlb (int idx)
{
tlb_t *tlb;
int size;
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
tlb = &env->tlb[idx];
tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
- tlb->ASID = env->CP0_EntryHi & 0x000000FF;
+ tlb->ASID = env->CP0_EntryHi & 0xFF;
size = env->CP0_PageMask >> 13;
size = 4 * (size + 1);
tlb->end = tlb->VPN + (1 << (8 + size));
+ tlb->end2 = tlb->end + (1 << (8 + size));
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
- tlb->V[0] = env->CP0_EntryLo0 & 2;
- tlb->D[0] = env->CP0_EntryLo0 & 4;
- tlb->C[0] = (env->CP0_EntryLo0 >> 3) & 0x7;
+ tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
+ tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
+ tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
- tlb->V[1] = env->CP0_EntryLo1 & 2;
- tlb->D[1] = env->CP0_EntryLo1 & 4;
- tlb->C[1] = (env->CP0_EntryLo1 >> 3) & 0x7;
+ tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
+ tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
+ tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
}
void do_tlbwi (void)
{
- invalidate_tb(env->CP0_index & 0xF);
- fill_tb(env->CP0_index & 0xF);
+ /* Wildly undefined effects for CP0_index containing a too high value and
+ MIPS_TLB_NB not being a power of two. But so does real silicon. */
+ invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
+ fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
}
void do_tlbwr (void)
{
int r = cpu_mips_get_random(env);
- invalidate_tb(r);
- fill_tb(r);
+ invalidate_tlb(r);
+ fill_tlb(r);
}
void do_tlbp (void)
uint8_t ASID;
int i;
- tag = (env->CP0_EntryHi & 0xFFFFE000);
- ASID = env->CP0_EntryHi & 0x000000FF;
- for (i = 0; i < 16; i++) {
+ tag = env->CP0_EntryHi & 0xFFFFE000;
+ ASID = env->CP0_EntryHi & 0xFF;
+ for (i = 0; i < MIPS_TLB_NB; i++) {
tlb = &env->tlb[i];
/* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
break;
}
}
- if (i == 16) {
+ if (i == MIPS_TLB_NB) {
env->CP0_index |= 0x80000000;
}
}
void do_tlbr (void)
{
tlb_t *tlb;
+ uint8_t ASID;
int size;
- tlb = &env->tlb[env->CP0_index & 0xF];
+ ASID = env->CP0_EntryHi & 0xFF;
+ tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
+
+ /* If this will change the current ASID, flush qemu's TLB. */
+ if (ASID != tlb->ASID && tlb->G != 1)
+ tlb_flush (env, 1);
+
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
size = (tlb->end - tlb->VPN) >> 12;
env->CP0_PageMask = (size - 1) << 13;
- env->CP0_EntryLo0 = tlb->V[0] | tlb->D[0] | (tlb->C[0] << 3) |
- (tlb->PFN[0] >> 6);
- env->CP0_EntryLo1 = tlb->V[1] | tlb->D[1] | (tlb->C[1] << 3) |
- (tlb->PFN[1] >> 6);
+ env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2)
+ | (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
+ env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2)
+ | (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
#endif
-__attribute__ (( regparm(1) ))
+#endif /* !CONFIG_USER_ONLY */
+
void op_dump_ldst (const unsigned char *func)
{
if (loglevel)
}
}
-__attribute__ (( regparm(1) ))
void do_pmon (int function)
{
function /= 2;
break;
}
}
+
+#if !defined(CONFIG_USER_ONLY)
+
+static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
+
+#define MMUSUFFIX _mmu
+#define ALIGNED_ONLY
+
+#define SHIFT 0
+#include "softmmu_template.h"
+
+#define SHIFT 1
+#include "softmmu_template.h"
+
+#define SHIFT 2
+#include "softmmu_template.h"
+
+#define SHIFT 3
+#include "softmmu_template.h"
+
+static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
+{
+ env->CP0_BadVAddr = addr;
+ do_restore_state (retaddr);
+ do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
+}
+
+void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
+{
+ TranslationBlock *tb;
+ CPUState *saved_env;
+ unsigned long pc;
+ int ret;
+
+ /* XXX: hack to restore env in all cases, even if not called from
+ generated code */
+ saved_env = env;
+ env = cpu_single_env;
+ ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
+ if (ret) {
+ if (retaddr) {
+ /* now we have a real cpu fault */
+ pc = (unsigned long)retaddr;
+ tb = tb_find_pc(pc);
+ if (tb) {
+ /* the PC is inside the translated code. It means that we have
+ a virtual CPU fault */
+ cpu_restore_state(tb, env, pc, NULL);
+ }
+ }
+ do_raise_exception_err(env->exception_index, env->error_code);
+ }
+ env = saved_env;
+}
+
+#endif
projects / qemu / blobdiff