* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#include <math.h>
#include "exec.h"
#define MIPS_DEBUG_DISAS
+#define GETPC() (__builtin_return_address(0))
+
/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit(void)
do_raise_exception_err(exception, 0);
}
+void do_restore_state (void *pc_ptr)
+{
+ TranslationBlock *tb;
+ unsigned long pc = (unsigned long) pc_ptr;
+
+ tb = tb_find_pc (pc);
+ cpu_restore_state (tb, env, pc, NULL);
+}
+
+void do_raise_exception_direct (uint32_t exception)
+{
+ do_restore_state (GETPC ());
+ do_raise_exception_err (exception, 0);
+}
+
#define MEMSUFFIX _raw
#include "op_helper_mem.c"
#undef MEMSUFFIX
void do_mult (void)
{
- set_HILO((int64_t)T0 * (int64_t)T1);
+ set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
}
void do_multu (void)
{
int64_t tmp;
- tmp = ((int64_t)T0 * (int64_t)T1);
+ tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
set_HILO((int64_t)get_HILO() + tmp);
}
{
int64_t tmp;
- tmp = ((int64_t)T0 * (int64_t)T1);
+ tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
set_HILO((int64_t)get_HILO() - tmp);
}
rn = "Index";
break;
case 2:
- val = T0 & 0x03FFFFFFF;
+ val = T0 & 0x3FFFFFFF;
old = env->CP0_EntryLo0;
env->CP0_EntryLo0 = val;
rn = "EntryLo0";
break;
case 3:
- val = T0 & 0x03FFFFFFF;
+ val = T0 & 0x3FFFFFFF;
old = env->CP0_EntryLo1;
env->CP0_EntryLo1 = val;
rn = "EntryLo1";
break;
case 4:
- val = (env->CP0_Context & 0xFF000000) | (T0 & 0x00FFFFF0);
+ val = (env->CP0_Context & 0xFF800000) | (T0 & 0x007FFFF0);
old = env->CP0_Context;
env->CP0_Context = val;
rn = "Context";
rn = "Count";
break;
case 10:
- val = T0 & 0xFFFFF0FF;
+ val = T0 & 0xFFFFE0FF;
old = env->CP0_EntryHi;
env->CP0_EntryHi = val;
+ /* If the ASID changes, flush qemu's TLB. */
+ if ((old & 0xFF) != (val & 0xFF))
+ tlb_flush (env, 1);
rn = "EntryHi";
break;
case 11:
old, val, env->CP0_Cause, old & mask, val & mask,
env->CP0_Cause & mask);
}
-#if 1
if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
!(env->hflags & MIPS_HFLAG_EXL) &&
!(env->hflags & MIPS_HFLAG_ERL) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
+ !(env->hflags & MIPS_HFLAG_DM) &&
(env->CP0_Status & env->CP0_Cause & mask)) {
if (logfile)
fprintf(logfile, "Raise pending IRQs\n");
env->interrupt_request |= CPU_INTERRUPT_HARD;
- do_raise_exception(EXCP_EXT_INTERRUPT);
- } else if (!(val & 0x00000001) && (old & 0x00000001)) {
+ } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
}
-#endif
rn = "Status";
break;
case 13:
/* TLB management */
#if defined(MIPS_USES_R4K_TLB)
-static void invalidate_tb (int idx)
+static void invalidate_tlb (int idx)
{
tlb_t *tlb;
- target_ulong addr, end;
+ target_ulong addr;
tlb = &env->tlb[idx];
- if (tlb->V[0]) {
- addr = tlb->PFN[0];
- end = addr + (tlb->end - tlb->VPN);
- tb_invalidate_page_range(addr, end);
+ if (tlb->V0) {
+ tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN);
+ addr = tlb->VPN;
+ while (addr < tlb->end) {
+ tlb_flush_page (env, addr);
+ addr += TARGET_PAGE_SIZE;
+ }
}
- if (tlb->V[1]) {
- addr = tlb->PFN[1];
- end = addr + (tlb->end - tlb->VPN);
- tb_invalidate_page_range(addr, end);
+ if (tlb->V1) {
+ tb_invalidate_page_range(tlb->PFN[1], tlb->end2 - tlb->end);
+ addr = tlb->end;
+ while (addr < tlb->end2) {
+ tlb_flush_page (env, addr);
+ addr += TARGET_PAGE_SIZE;
+ }
}
}
-static void fill_tb (int idx)
+static void fill_tlb (int idx)
{
tlb_t *tlb;
int size;
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
tlb = &env->tlb[idx];
tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
- tlb->ASID = env->CP0_EntryHi & 0x000000FF;
+ tlb->ASID = env->CP0_EntryHi & 0xFF;
size = env->CP0_PageMask >> 13;
size = 4 * (size + 1);
tlb->end = tlb->VPN + (1 << (8 + size));
+ tlb->end2 = tlb->end + (1 << (8 + size));
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
- tlb->V[0] = env->CP0_EntryLo0 & 2;
- tlb->D[0] = env->CP0_EntryLo0 & 4;
- tlb->C[0] = (env->CP0_EntryLo0 >> 3) & 0x7;
+ tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
+ tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
+ tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
- tlb->V[1] = env->CP0_EntryLo1 & 2;
- tlb->D[1] = env->CP0_EntryLo1 & 4;
- tlb->C[1] = (env->CP0_EntryLo1 >> 3) & 0x7;
+ tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
+ tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
+ tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
}
{
/* Wildly undefined effects for CP0_index containing a too high value and
MIPS_TLB_NB not being a power of two. But so does real silicon. */
- invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1));
- fill_tb(env->CP0_index & (MIPS_TLB_NB - 1));
+ invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
+ fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
}
void do_tlbwr (void)
{
int r = cpu_mips_get_random(env);
- invalidate_tb(r);
- fill_tb(r);
+ invalidate_tlb(r);
+ fill_tlb(r);
}
void do_tlbp (void)
uint8_t ASID;
int i;
- tag = (env->CP0_EntryHi & 0xFFFFE000);
- ASID = env->CP0_EntryHi & 0x000000FF;
- for (i = 0; i < MIPS_TLB_NB; i++) {
+ tag = env->CP0_EntryHi & 0xFFFFE000;
+ ASID = env->CP0_EntryHi & 0xFF;
+ for (i = 0; i < MIPS_TLB_NB; i++) {
tlb = &env->tlb[i];
/* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
void do_tlbr (void)
{
tlb_t *tlb;
+ uint8_t ASID;
int size;
+ ASID = env->CP0_EntryHi & 0xFF;
tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
+
+ /* If this will change the current ASID, flush qemu's TLB. */
+ if (ASID != tlb->ASID && tlb->G != 1)
+ tlb_flush (env, 1);
+
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
size = (tlb->end - tlb->VPN) >> 12;
env->CP0_PageMask = (size - 1) << 13;
- env->CP0_EntryLo0 = tlb->V[0] | tlb->D[0] | (tlb->C[0] << 3) |
- (tlb->PFN[0] >> 6);
- env->CP0_EntryLo1 = tlb->V[1] | tlb->D[1] | (tlb->C[1] << 3) |
- (tlb->PFN[1] >> 6);
+ env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2)
+ | (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
+ env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2)
+ | (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
#endif
#if !defined(CONFIG_USER_ONLY)
+static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
+
#define MMUSUFFIX _mmu
-#define GETPC() (__builtin_return_address(0))
+#define ALIGNED_ONLY
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"
+static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
+{
+ env->CP0_BadVAddr = addr;
+ do_restore_state (retaddr);
+ do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
+}
+
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
{
TranslationBlock *tb;
projects / qemu / blobdiff