close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC
+#define TARGET_HAS_ICE 1
+
#include "cpu-defs.h"
#include "softfloat.h"
#define MSR_IA32_SYSENTER_ESP 0x175
#define MSR_IA32_SYSENTER_EIP 0x176
+#define MSR_MCG_CAP 0x179
+#define MSR_MCG_STATUS 0x17a
+#define MSR_MCG_CTL 0x17b
+
+#define MSR_PAT 0x277
+
#define MSR_EFER 0xc0000080
#define MSR_EFER_SCE (1 << 0)
#define CPUID_PGE (1 << 13)
#define CPUID_MCA (1 << 14)
#define CPUID_CMOV (1 << 15)
+#define CPUID_PAT (1 << 16)
+#define CPUID_CLFLUSH (1 << 19)
/* ... */
#define CPUID_MMX (1 << 23)
#define CPUID_FXSR (1 << 24)
#define CPUID_EXT2_SYSCALL (1 << 11)
#define CPUID_EXT2_NX (1 << 20)
+#define CPUID_EXT2_FFXSR (1 << 25)
#define CPUID_EXT2_LM (1 << 29)
#define EXCP00_DIVZ 0
uint32_t sysenter_cs;
uint32_t sysenter_esp;
uint32_t sysenter_eip;
+ uint64_t efer;
+ uint64_t star;
#ifdef TARGET_X86_64
- target_ulong efer;
- target_ulong star;
target_ulong lstar;
target_ulong cstar;
target_ulong fmask;
target_ulong kernelgsbase;
#endif
+ uint64_t pat;
+
/* temporary data for USE_CODE_COPY mode */
#ifdef USE_CODE_COPY
uint32_t tmp0;
int singlestep_enabled;
/* processor features (e.g. for CPUID insn) */
+ uint32_t cpuid_level;
uint32_t cpuid_vendor1;
uint32_t cpuid_vendor2;
uint32_t cpuid_vendor3;
uint32_t cpuid_version;
uint32_t cpuid_features;
uint32_t cpuid_ext_features;
-
+ uint32_t cpuid_xlevel;
+ uint32_t cpuid_model[12];
+ uint32_t cpuid_ext2_features;
+
#ifdef USE_KQEMU
int kqemu_enabled;
#endif