added verr, verw, arpl - more precise segment rights checks

[qemu] / target-arm / translate.c

diff --git a/target-arm/translate.c b/target-arm/translate.c
index bffeefa..9447946 100644 (file)
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -516,9 +516,9 @@ static void disas_arm_insn(DisasContext *s)
                         gen_movl_T0_reg(s, rs);
                         gen_movl_T1_reg(s, rm);
                         if (insn & (1 << 22)) 
-                            gen_op_mull_T0_T1();
-                        else
                             gen_op_imull_T0_T1();
+                        else
+                            gen_op_mull_T0_T1();
                         if (insn & (1 << 21)) 
                             gen_op_addq_T0_T1(rn, rd);
                         if (insn & (1 << 20)) 
@@ -546,8 +546,7 @@ static void disas_arm_insn(DisasContext *s)
                 rn = (insn >> 16) & 0xf;
                 rd = (insn >> 12) & 0xf;
                 gen_movl_T1_reg(s, rn);
-                if (insn & (1 << 25))
-                    gen_add_datah_offset(s, insn);
+                gen_add_datah_offset(s, insn);
                 if (insn & (1 << 20)) {
                     /* load */
                     switch(sh) {
@@ -562,8 +561,10 @@ static void disas_arm_insn(DisasContext *s)
                         gen_op_ldsw_T0_T1();
                         break;
                     }
+                    gen_movl_reg_T0(s, rd);
                 } else {
                     /* store */
+                    gen_movl_T0_reg(s, rd);
                     gen_op_stw_T0_T1();
                 }
                 if (!(insn & (1 << 24))) {