switch(addr) {
case 0x0c:
val = s->sof_timing;
+ break;
default:
val = 0xff;
break;
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
/* start frame processing */
qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock));
+ s->status &= ~UHCI_STS_HCHALTED;
+ } else if (!(val & UHCI_CMD_RS)) {
+ s->status |= UHCI_STS_HCHALTED;
}
if (val & UHCI_CMD_GRESET) {
UHCIPort *port;
uhci_reset(s);
return;
}
- if (val & UHCI_CMD_GRESET) {
+ if (val & UHCI_CMD_HCRESET) {
uhci_reset(s);
return;
}
if (!(s->cmd & UHCI_CMD_RS)) {
qemu_del_timer(s->frame_timer);
+ /* set hchalted bit in status - UHCI11D 2.1.2 */
+ s->status |= UHCI_STS_HCHALTED;
return;
}
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
pci_conf[0x0b] = 0x0c;
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 4; // interrupt pin 3
+ pci_conf[0x60] = 0x10; // release number
for(i = 0; i < NB_PORTS; i++) {
port = &s->ports[i];
uhci_reset(s);
- pci_register_io_region(&s->dev, 0, 0x20,
+ /* Use region 4 for consistency with real hardware. BSD guests seem
+ to rely on this. */
+ pci_register_io_region(&s->dev, 4, 0x20,
PCI_ADDRESS_SPACE_IO, uhci_map);
}