*/
#ifdef DEBUG_DMA
-#define DPRINTF(fmt, args...) \
-do { printf("DMA: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...) \
+ do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define DPRINTF(fmt, args...)
+#define DPRINTF(fmt, ...)
#endif
#define DMA_REGS 4
#define DMA_SIZE (4 * sizeof(uint32_t))
-#define DMA_MAXADDR (DMA_SIZE - 1)
+/* We need the mask, because one instance of the device is not page
+ aligned (ledma, start address 0x0010) */
+#define DMA_MASK (DMA_SIZE - 1)
#define DMA_VER 0xa0000000
#define DMA_INTR 1
DMAState *s = opaque;
uint32_t saddr;
- saddr = (addr & DMA_MAXADDR) >> 2;
+ saddr = (addr & DMA_MASK) >> 2;
DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
s->dmaregs[saddr]);
DMAState *s = opaque;
uint32_t saddr;
- saddr = (addr & DMA_MAXADDR) >> 2;
+ saddr = (addr & DMA_MASK) >> 2;
DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
s->dmaregs[saddr], val);
switch (saddr) {
int dma_io_memory;
s = qemu_mallocz(sizeof(DMAState));
- if (!s)
- return NULL;
s->irq = parent_irq;
s->iommu = iommu;
cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
- qemu_register_reset(dma_reset, s);
+ qemu_register_reset(dma_reset, 0, s);
*dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
*reset = &s->dev_reset;