* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "vl.h"
-#include "m48t59.h"
+#include "hw.h"
+#include "ppc.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "nvram.h"
//#define PPC_DEBUG_IRQ
//#define PPC_DEBUG_TB
}
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
- fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
- __func__, env, n_IRQ, level,
+ fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08" PRIx32
+ "req %08x\n", __func__, env, n_IRQ, level,
env->pending_interrupts, env->interrupt_request);
}
#endif
case PPC6xx_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
-#if 0 // XXX: TOFIX
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: reset the CPU\n", __func__);
}
#endif
- cpu_reset(env);
+ env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ /* XXX: TOFIX */
+#if 0
+ cpu_ppc_reset(env);
+#else
+ qemu_system_reset_request();
#endif
}
break;
void ppc6xx_irq_init (CPUState *env)
{
- env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
+ env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
+ PPC6xx_INPUT_NB);
}
#if defined(TARGET_PPC64)
void ppc970_irq_init (CPUState *env)
{
- env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
+ env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
+ PPC970_INPUT_NB);
}
#endif /* defined(TARGET_PPC64) */
uint64_t decr_next; /* Tick for next decr interrupt */
uint32_t decr_freq; /* decrementer frequency */
struct QEMUTimer *decr_timer;
-#if defined(TARGET_PPC64H)
/* Hypervisor decrementer management */
uint64_t hdecr_next; /* Tick for next hdecr interrupt */
struct QEMUTimer *hdecr_timer;
uint64_t purr_load;
uint64_t purr_start;
-#endif
void *opaque;
};
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
- fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+ fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
- fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+ fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
- *tb_offsetp);
+ fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
+ __func__, value, *tb_offsetp);
}
#endif
}
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
- fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+ fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
- fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+ fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb, atb, vmclk;
-
+
/* If the time base is not frozen, do nothing */
if (tb_env->tb_freq == 0) {
vmclk = qemu_get_clock(vm_clock);
decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
- fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
+ fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr);
}
#endif
return _cpu_ppc_load_decr(env, &tb_env->decr_next);
}
-#if defined(TARGET_PPC64H)
uint32_t cpu_ppc_load_hdecr (CPUState *env)
{
ppc_tb_t *tb_env = env->tb_env;
return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
}
-#endif /* defined(TARGET_PPC64H) */
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
+ fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
+ decr, value);
}
#endif
now = qemu_get_clock(vm_clock);
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
-#if defined(TARGET_PPC64H)
static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
- __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
- &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
+ if (tb_env->hdecr_timer != NULL) {
+ __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
+ &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
+ }
}
void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
tb_env->purr_load = value;
tb_env->purr_start = qemu_get_clock(vm_clock);
}
-#endif /* defined(TARGET_PPC64H) */
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
{
* it's not ready to handle it...
*/
_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
-#if defined(TARGET_PPC64H)
_cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
cpu_ppc_store_purr(env, 0x0000000000000000ULL);
-#endif /* defined(TARGET_PPC64H) */
}
/* Set up (once) timebase frequency (in Hz) */
env->tb_env = tb_env;
/* Create new timer */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
-#if defined(TARGET_PPC64H)
- tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
-#endif /* defined(TARGET_PPC64H) */
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor decrementer
+ */
+ tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
+ } else {
+ tb_env->hdecr_timer = NULL;
+ }
cpu_ppc_set_tb_clk(env, freq);
return &cpu_ppc_set_tb_clk;
} else {
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s: start PIT 0x" REGX "\n",
+ fprintf(logfile, "%s: start PIT %016" PRIx64 "\n",
__func__, ppcemb_timer->pit_reload);
}
#endif
ppcemb_timer = tb_env->opaque;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
+ fprintf(logfile, "%s val" ADDRX "\n", __func__, val);
}
#endif
ppcemb_timer->pit_reload = val;
{
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
+ fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
}
#endif
env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
tb_env = env->tb_env;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
+ fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
}
#endif
env->spr[SPR_40x_TCR] = val & 0xFFC00000;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
+ fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__,
+ freq);
}
#endif
tb_env->tb_freq = freq;
tb_env->opaque = ppcemb_timer;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
- fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
- &ppc_emb_set_tb_clk);
+ fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq);
}
#endif
if (ppcemb_timer != NULL) {
fflush(stdout);
break;
case 2:
- printf("Set loglevel to %04x\n", val);
+ printf("Set loglevel to %04" PRIx32 "\n", val);
cpu_set_log(val | 0x100);
break;
}
/*****************************************************************************/
/* NVRAM helpers */
-void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
+static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
{
- m48t59_write(nvram, addr, value);
+ return (*nvram->read_fn)(nvram->opaque, addr);;
}
-uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
+static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
{
- return m48t59_read(nvram, addr);
+ (*nvram->write_fn)(nvram->opaque, addr, val);
}
-void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
+void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
{
- m48t59_write(nvram, addr, value >> 8);
- m48t59_write(nvram, addr + 1, value & 0xFF);
+ nvram_write(nvram, addr, value);
}
-uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
+uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr)
+{
+ return nvram_read(nvram, addr);
+}
+
+void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
+{
+ nvram_write(nvram, addr, value >> 8);
+ nvram_write(nvram, addr + 1, value & 0xFF);
+}
+
+uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr)
{
uint16_t tmp;
- tmp = m48t59_read(nvram, addr) << 8;
- tmp |= m48t59_read(nvram, addr + 1);
+ tmp = nvram_read(nvram, addr) << 8;
+ tmp |= nvram_read(nvram, addr + 1);
+
return tmp;
}
-void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
+void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
{
- m48t59_write(nvram, addr, value >> 24);
- m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
- m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
- m48t59_write(nvram, addr + 3, value & 0xFF);
+ nvram_write(nvram, addr, value >> 24);
+ nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
+ nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
+ nvram_write(nvram, addr + 3, value & 0xFF);
}
-uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
+uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
{
uint32_t tmp;
- tmp = m48t59_read(nvram, addr) << 24;
- tmp |= m48t59_read(nvram, addr + 1) << 16;
- tmp |= m48t59_read(nvram, addr + 2) << 8;
- tmp |= m48t59_read(nvram, addr + 3);
+ tmp = nvram_read(nvram, addr) << 24;
+ tmp |= nvram_read(nvram, addr + 1) << 16;
+ tmp |= nvram_read(nvram, addr + 2) << 8;
+ tmp |= nvram_read(nvram, addr + 3);
return tmp;
}
-void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
+void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
const unsigned char *str, uint32_t max)
{
int i;
for (i = 0; i < max && str[i] != '\0'; i++) {
- m48t59_write(nvram, addr + i, str[i]);
+ nvram_write(nvram, addr + i, str[i]);
}
- m48t59_write(nvram, addr + max - 1, '\0');
+ nvram_write(nvram, addr + i, str[i]);
+ nvram_write(nvram, addr + max - 1, '\0');
}
-int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
+int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
{
int i;
return tmp;
}
-uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
+uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
{
uint32_t i;
uint16_t crc = 0xFFFF;
#define CMDLINE_ADDR 0x017ff000
-int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
+int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
const unsigned char *arch,
uint32_t RAM_size, int boot_device,
uint32_t kernel_image, uint32_t kernel_size,
NVRAM_set_word(nvram, 0x56, height);
NVRAM_set_word(nvram, 0x58, depth);
crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
- NVRAM_set_word(nvram, 0xFC, crc);
+ NVRAM_set_word(nvram, 0xFC, crc);
return 0;
}
projects / qemu / blobdiff