* THE SOFTWARE.
*/
#include "vl.h"
+#include "m48t59.h"
/*****************************************************************************/
/* PPC time base and decrementer emulation */
decr = muldiv64(tb_env->decr_next - qemu_get_clock(vm_clock),
tb_env->tb_freq, ticks_per_sec);
-#ifdef DEBUG_TB
+#if defined(DEBUG_TB)
printf("%s: 0x%08x\n", __func__, decr);
#endif
}
#endif
-static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value)
+static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
cpu_outb(NULL, addr & 0xffff, value);
}
-static uint32_t PPC_io_readb (target_phys_addr_t addr)
+static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t ret = cpu_inb(NULL, addr & 0xffff);
return ret;
}
-static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
+static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
cpu_outw(NULL, addr & 0xffff, value);
}
-static uint32_t PPC_io_readw (target_phys_addr_t addr)
+static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t ret = cpu_inw(NULL, addr & 0xffff);
#ifdef TARGET_WORDS_BIGENDIAN
return ret;
}
-static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
+static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
cpu_outl(NULL, addr & 0xffff, value);
}
-static uint32_t PPC_io_readl (target_phys_addr_t addr)
+static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t ret = cpu_inl(NULL, addr & 0xffff);
/*****************************************************************************/
/* Debug port */
-void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val)
+void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
{
addr &= 0xF;
switch (addr) {
break;
case 2:
printf("Set loglevel to %04x\n", val);
- cpu_set_log(val);
+ cpu_set_log(val | 0x100);
break;
}
}
return crc;
}
+#define CMDLINE_ADDR 0x017ff000
+
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
const unsigned char *arch,
uint32_t RAM_size, int boot_device,
uint32_t kernel_image, uint32_t kernel_size,
- uint32_t cmdline, uint32_t cmdline_size,
+ const char *cmdline,
uint32_t initrd_image, uint32_t initrd_size,
- uint32_t NVRAM_image)
+ uint32_t NVRAM_image,
+ int width, int height, int depth)
{
uint16_t crc;
NVRAM_set_byte(nvram, 0x34, boot_device);
NVRAM_set_lword(nvram, 0x38, kernel_image);
NVRAM_set_lword(nvram, 0x3C, kernel_size);
- NVRAM_set_lword(nvram, 0x40, cmdline);
- NVRAM_set_lword(nvram, 0x44, cmdline_size);
+ if (cmdline) {
+ /* XXX: put the cmdline in NVRAM too ? */
+ strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
+ NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
+ NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
+ } else {
+ NVRAM_set_lword(nvram, 0x40, 0);
+ NVRAM_set_lword(nvram, 0x44, 0);
+ }
NVRAM_set_lword(nvram, 0x48, initrd_image);
NVRAM_set_lword(nvram, 0x4C, initrd_size);
NVRAM_set_lword(nvram, 0x50, NVRAM_image);
- crc = NVRAM_compute_crc(nvram, 0x00, 0x5C);
- NVRAM_set_word(nvram, 0x5C, crc);
- return 0;
- }
+ NVRAM_set_word(nvram, 0x54, width);
+ NVRAM_set_word(nvram, 0x56, height);
+ NVRAM_set_word(nvram, 0x58, depth);
+ crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
+ NVRAM_set_word(nvram, 0xFC, crc);
-/*****************************************************************************/
-void ppc_init (int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename, int snapshot,
- const char *kernel_filename, const char *kernel_cmdline,
- const char *initrd_filename)
-{
- if (prep_enabled) {
- ppc_prep_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
- snapshot, kernel_filename, kernel_cmdline,
- initrd_filename);
- } else {
- ppc_chrp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
- snapshot, kernel_filename, kernel_cmdline,
- initrd_filename);
- }
+ return 0;
}