* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
*/
-#include "vl.h"
+#include "sysbus.h"
+#include "pci.h"
+#include "net.h"
+#include "qemu-timer.h"
+#include "qemu_socket.h"
//#define PCNET_DEBUG
//#define PCNET_DEBUG_IO
#define PCNET_IOPORT_SIZE 0x20
#define PCNET_PNPMMIO_SIZE 0x20
+#define PCNET_LOOPTEST_CRC 1
+#define PCNET_LOOPTEST_NOCRC 2
+
typedef struct PCNetState_st PCNetState;
struct PCNetState_st {
- PCIDevice dev;
PCIDevice *pci_dev;
VLANClientState *vc;
- NICInfo *nd;
+ uint8_t macaddr[6];
QEMUTimer *poll_timer;
- int mmio_index, rap, isr, lnkst;
+ int rap, isr, lnkst;
uint32_t rdra, tdra;
uint8_t prom[16];
uint16_t csr[128];
uint16_t bcr[32];
uint64_t timer;
- int xmit_pos, recv_pos;
+ int mmio_index, xmit_pos, recv_pos;
uint8_t buffer[4096];
int tx_busy;
qemu_irq irq;
void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void *dma_opaque;
+ int looptest;
};
+typedef struct {
+ PCIDevice pci_dev;
+ PCNetState state;
+} PCIPCNetState;
+
+typedef struct {
+ SysBusDevice busdev;
+ PCNetState state;
+} SysBusPCNetState;
+
struct qemu_ether_header {
uint8_t ether_dhost[6];
uint8_t ether_shost[6];
#define CSR_DRX(S) !!(((S)->csr[15])&0x0001)
#define CSR_DTX(S) !!(((S)->csr[15])&0x0002)
#define CSR_LOOP(S) !!(((S)->csr[15])&0x0004)
+#define CSR_DXMTFCS(S) !!(((S)->csr[15])&0x0008)
#define CSR_DRCVPA(S) !!(((S)->csr[15])&0x2000)
#define CSR_DRCVBC(S) !!(((S)->csr[15])&0x4000)
#define CSR_PROM(S) !!(((S)->csr[15])&0x8000)
#define TMDS_LTINT_SH 12
#define TMDS_NOFCS_MASK 0x2000
#define TMDS_NOFCS_SH 13
+#define TMDS_ADDFCS_MASK TMDS_NOFCS_MASK
+#define TMDS_ADDFCS_SH TMDS_NOFCS_SH
#define TMDS_ERR_MASK 0x4000
#define TMDS_ERR_SH 14
#define TMDS_OWN_MASK 0x8000
} else {
s->phys_mem_read(s->dma_opaque, addr, (void *)tmd, sizeof(*tmd), 0);
le32_to_cpus(&tmd->tbadr);
- le16_to_cpus(&tmd->length);
- le16_to_cpus(&tmd->status);
+ le16_to_cpus((uint16_t *)&tmd->length);
+ le16_to_cpus((uint16_t *)&tmd->status);
le32_to_cpus(&tmd->misc);
le32_to_cpus(&tmd->res);
if (BCR_SWSTYLE(s) == 3) {
} else {
s->phys_mem_read(s->dma_opaque, addr, (void *)rmd, sizeof(*rmd), 0);
le32_to_cpus(&rmd->rbadr);
- le16_to_cpus(&rmd->buf_length);
- le16_to_cpus(&rmd->status);
+ le16_to_cpus((uint16_t *)&rmd->buf_length);
+ le16_to_cpus((uint16_t *)&rmd->status);
le32_to_cpus(&rmd->msg_length);
le32_to_cpus(&rmd->res);
if (BCR_SWSTYLE(s) == 3) {
s->rdra = 0;
s->tdra = 0;
s->rap = 0;
-
+
s->bcr[BCR_BSBC] &= ~0x0080;
s->csr[0] = 0x0004;
{
int isr = 0;
s->csr[0] &= ~0x0080;
-
+
#if 1
if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
(((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
(!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
#endif
{
-
+
isr = CSR_INEA(s);
s->csr[0] |= 0x0080;
}
-
+
if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
s->csr[4] &= ~0x0080;
s->csr[4] |= 0x0040;
#ifdef PCNET_DEBUG
printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
#endif
-
+
if (BCR_SSIZE32(s)) {
struct pcnet_initblk32 initblk;
s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
#endif
- s->csr[0] |= 0x0101;
+ s->csr[0] |= 0x0101;
s->csr[0] &= ~0x0004; /* clear STOP bit */
}
if (!CSR_DTX(s))
s->csr[0] |= 0x0010; /* set TXON */
-
+
if (!CSR_DRX(s))
s->csr[0] |= 0x0020; /* set RXON */
(BCR_SWSTYLE(s) ? 16 : 8 );
#endif
- CHECK_RMD(PHYSADDR(s,crda), bad);
+ CHECK_RMD(crda, bad);
if (!bad) {
- CHECK_RMD(PHYSADDR(s,nrda), bad);
+ CHECK_RMD(nrda, bad);
if (bad || (nrda == crda)) nrda = 0;
- CHECK_RMD(PHYSADDR(s,nnrd), bad);
+ CHECK_RMD(nnrd, bad);
if (bad || (nnrd == crda)) nnrd = 0;
s->csr[28] = crda & 0xffff;
s->csr[37] = nnrd >> 16;
#ifdef PCNET_DEBUG
if (bad) {
- printf("pcnet: BAD RMD RECORDS AFTER 0x%08x\n",
- PHYSADDR(s,crda));
+ printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
+ crda);
}
} else {
- printf("pcnet: BAD RMD RDA=0x%08x\n", PHYSADDR(s,crda));
+ printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n",
+ crda);
#endif
}
}
-
+
if (CSR_CRDA(s)) {
struct pcnet_RMD rmd;
RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
} else {
CSR_CRBC(s) = CSR_CRST(s) = 0;
}
-
+
if (CSR_NRDA(s)) {
struct pcnet_RMD rmd;
RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
(CSR_XMTRL(s) - CSR_XMTRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8);
int bad = 0;
- CHECK_TMD(PHYSADDR(s, cxda),bad);
+ CHECK_TMD(cxda, bad);
if (!bad) {
if (CSR_CXDA(s) != cxda) {
s->csr[60] = s->csr[34];
s->csr[34] = cxda & 0xffff;
s->csr[35] = cxda >> 16;
#ifdef PCNET_DEBUG_X
- printf("pcnet: BAD TMD XDA=0x%08x\n", PHYSADDR(s,cxda));
+ printf("pcnet: BAD TMD XDA=0x%08x\n", cxda);
#endif
}
}
if (CSR_CXDA(s)) {
struct pcnet_TMD tmd;
- TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
+ TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
CSR_CXST(s) = tmd.status;
} else {
CSR_CXBC(s) = CSR_CXST(s) = 0;
}
-
+
return !!(CSR_CXST(s) & 0x8000);
}
PCNetState *s = opaque;
if (CSR_STOP(s) || CSR_SPND(s))
return 0;
-
+
if (s->recv_pos > 0)
return 0;
PCNetState *s = opaque;
int is_padr = 0, is_bcast = 0, is_ladr = 0;
uint8_t buf1[60];
+ int remaining;
+ int crc_err = 0;
if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size)
return;
nrda = s->rdra +
(CSR_RCVRL(s) - rcvrc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
- RMDLOAD(&rmd, PHYSADDR(s,nrda));
+ RMDLOAD(&rmd, nrda);
if (GET_FIELD(rmd.status, RMDS, OWN)) {
#ifdef PCNET_DEBUG_RMD
printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
s->csr[0] |= 0x1000; /* Set MISS flag */
CSR_MISSC(s)++;
} else {
- uint8_t *src = &s->buffer[8];
+ uint8_t *src = s->buffer;
target_phys_addr_t crda = CSR_CRDA(s);
struct pcnet_RMD rmd;
int pktcount = 0;
- memcpy(src, buf, size);
-
-#if 1
- /* no need to compute the CRC */
- src[size] = 0;
- src[size + 1] = 0;
- src[size + 2] = 0;
- src[size + 3] = 0;
- size += 4;
-#else
- /* XXX: avoid CRC generation */
- if (!CSR_ASTRP_RCV(s)) {
+ if (!s->looptest) {
+ memcpy(src, buf, size);
+ /* no need to compute the CRC */
+ src[size] = 0;
+ src[size + 1] = 0;
+ src[size + 2] = 0;
+ src[size + 3] = 0;
+ size += 4;
+ } else if (s->looptest == PCNET_LOOPTEST_CRC ||
+ !CSR_DXMTFCS(s) || size < MIN_BUF_SIZE+4) {
uint32_t fcs = ~0;
uint8_t *p = src;
- while (size < 46) {
- src[size++] = 0;
- }
-
- while (p != &src[size]) {
+ while (p != &src[size])
CRC(fcs, *p++);
- }
- ((uint32_t *)&src[size])[0] = htonl(fcs);
- size += 4; /* FCS at end of packet */
- } else size += 4;
-#endif
+ *(uint32_t *)p = htonl(fcs);
+ size += 4;
+ } else {
+ uint32_t fcs = ~0;
+ uint8_t *p = src;
+
+ while (p != &src[size-4])
+ CRC(fcs, *p++);
+ crc_err = (*(uint32_t *)p != htonl(fcs));
+ }
#ifdef PCNET_DEBUG_MATCH
PRINT_PKTHDR(buf);
SET_FIELD(&rmd.status, RMDS, STP, 1);
#define PCNET_RECV_STORE() do { \
- int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),size); \
+ int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
- src += count; size -= count; \
- SET_FIELD(&rmd.msg_length, RMDM, MCNT, count); \
+ src += count; remaining -= count; \
SET_FIELD(&rmd.status, RMDS, OWN, 0); \
RMDSTORE(&rmd, PHYSADDR(s,crda)); \
pktcount++; \
} while (0)
+ remaining = size;
PCNET_RECV_STORE();
- if ((size > 0) && CSR_NRDA(s)) {
+ if ((remaining > 0) && CSR_NRDA(s)) {
target_phys_addr_t nrda = CSR_NRDA(s);
+#ifdef PCNET_DEBUG_RMD
+ PRINT_RMD(&rmd);
+#endif
RMDLOAD(&rmd, PHYSADDR(s,nrda));
if (GET_FIELD(rmd.status, RMDS, OWN)) {
crda = nrda;
PCNET_RECV_STORE();
- if ((size > 0) && (nrda=CSR_NNRD(s))) {
+#ifdef PCNET_DEBUG_RMD
+ PRINT_RMD(&rmd);
+#endif
+ if ((remaining > 0) && (nrda=CSR_NNRD(s))) {
RMDLOAD(&rmd, PHYSADDR(s,nrda));
if (GET_FIELD(rmd.status, RMDS, OWN)) {
crda = nrda;
PCNET_RECV_STORE();
}
}
- }
+ }
}
#undef PCNET_RECV_STORE
RMDLOAD(&rmd, PHYSADDR(s,crda));
- if (size == 0) {
+ if (remaining == 0) {
+ SET_FIELD(&rmd.msg_length, RMDM, MCNT, size);
SET_FIELD(&rmd.status, RMDS, ENP, 1);
SET_FIELD(&rmd.status, RMDS, PAM, !CSR_PROM(s) && is_padr);
SET_FIELD(&rmd.status, RMDS, LFAM, !CSR_PROM(s) && is_ladr);
SET_FIELD(&rmd.status, RMDS, BAM, !CSR_PROM(s) && is_bcast);
+ if (crc_err) {
+ SET_FIELD(&rmd.status, RMDS, CRC, 1);
+ SET_FIELD(&rmd.status, RMDS, ERR, 1);
+ }
} else {
SET_FIELD(&rmd.status, RMDS, OFLO, 1);
SET_FIELD(&rmd.status, RMDS, BUFF, 1);
#endif
#ifdef PCNET_DEBUG_RMD
PRINT_RMD(&rmd);
-#endif
+#endif
while (pktcount--) {
if (CSR_RCVRC(s) <= 1)
CSR_RCVRC(s) = CSR_RCVRL(s);
else
- CSR_RCVRC(s)--;
+ CSR_RCVRC(s)--;
}
-
+
pcnet_rdte_poll(s);
- }
+ }
}
pcnet_poll(s);
- pcnet_update_irq(s);
+ pcnet_update_irq(s);
}
static void pcnet_transmit(PCNetState *s)
{
target_phys_addr_t xmit_cxda = 0;
int count = CSR_XMTRL(s)-1;
+ int add_crc = 0;
+
s->xmit_pos = -1;
-
+
if (!CSR_TXON(s)) {
s->csr[0] &= ~0x0008;
return;
#endif
if (GET_FIELD(tmd.status, TMDS, STP)) {
s->xmit_pos = 0;
- if (!GET_FIELD(tmd.status, TMDS, ENP)) {
- int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
- s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
- s->buffer, bcnt, CSR_BSWP(s));
- s->xmit_pos += bcnt;
- }
xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
+ if (BCR_SWSTYLE(s) != 1)
+ add_crc = GET_FIELD(tmd.status, TMDS, ADDFCS);
}
- if (GET_FIELD(tmd.status, TMDS, ENP) && (s->xmit_pos >= 0)) {
+ if (!GET_FIELD(tmd.status, TMDS, ENP)) {
+ int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
+ s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
+ s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
+ s->xmit_pos += bcnt;
+ } else if (s->xmit_pos >= 0) {
int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
#ifdef PCNET_DEBUG
printf("pcnet_transmit size=%d\n", s->xmit_pos);
#endif
- if (CSR_LOOP(s))
+ if (CSR_LOOP(s)) {
+ if (BCR_SWSTYLE(s) == 1)
+ add_crc = !GET_FIELD(tmd.status, TMDS, NOFCS);
+ s->looptest = add_crc ? PCNET_LOOPTEST_CRC : PCNET_LOOPTEST_NOCRC;
pcnet_receive(s, s->buffer, s->xmit_pos);
- else
+ s->looptest = 0;
+ } else
if (s->vc)
qemu_send_packet(s->vc, s->buffer, s->xmit_pos);
} else
if (s->xmit_pos >= 0) {
struct pcnet_TMD tmd;
- TMDLOAD(&tmd, PHYSADDR(s,xmit_cxda));
+ TMDLOAD(&tmd, xmit_cxda);
SET_FIELD(&tmd.misc, TMDM, BUFF, 1);
SET_FIELD(&tmd.misc, TMDM, UFLO, 1);
SET_FIELD(&tmd.status, TMDS, ERR, 1);
SET_FIELD(&tmd.status, TMDS, OWN, 0);
- TMDSTORE(&tmd, PHYSADDR(s,xmit_cxda));
+ TMDSTORE(&tmd, xmit_cxda);
s->csr[0] |= 0x0200; /* set TINT */
if (!CSR_DXSUFLO(s)) {
s->csr[0] &= ~0x0010;
pcnet_transmit(s);
}
- pcnet_update_irq(s);
+ pcnet_update_irq(s);
if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
uint64_t now = qemu_get_clock(vm_clock) * 33;
/* Initialize the PROM */
- if (s->nd)
- memcpy(s->prom, s->nd->macaddr, 6);
+ memcpy(s->prom, s->macaddr, 6);
s->prom[12] = s->prom[13] = 0x00;
s->prom[14] = s->prom[15] = 0x57;
PCNetState *s = opaque;
#ifdef PCNET_DEBUG
printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
-#endif
+#endif
/* Check APROMWE bit to enable write access */
if (pcnet_bcr_readw(s,2) & 0x80)
s->prom[addr & 15] = val;
-}
+}
static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
{
pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
#ifdef PCNET_DEBUG_IO
printf("device switched into dword i/o mode\n");
-#endif
+#endif
}
pcnet_update_irq(s);
}
PCNetState *s = opaque;
uint32_t val = -1;
pcnet_poll_timer(s);
- if (BCR_DWIO(s)) {
+ if (BCR_DWIO(s)) {
switch (addr & 0x0f) {
case 0x00: /* RDP */
val = pcnet_csr_readw(s, s->rap);
static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
- PCNetState *d = (PCNetState *)pci_dev;
+ PCNetState *d = &((PCIPCNetState *)pci_dev)->state;
#ifdef PCNET_DEBUG_IO
printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);
register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
-
+
register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_writeb addr=0x%08x val=0x%02x\n", addr, val);
+ printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
+ val);
#endif
if (!(addr & 0x10))
pcnet_aprom_writeb(d, addr & 0x0f, val);
if (!(addr & 0x10))
val = pcnet_aprom_readb(d, addr & 0x0f);
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_readb addr=0x%08x val=0x%02x\n", addr, val & 0xff);
+ printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
+ val & 0xff);
#endif
return val;
}
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_writew addr=0x%08x val=0x%04x\n", addr, val);
+ printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
+ val);
#endif
if (addr & 0x10)
pcnet_ioport_writew(d, addr & 0x0f, val);
val |= pcnet_aprom_readb(d, addr);
}
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_readw addr=0x%08x val = 0x%04x\n", addr, val & 0xffff);
+ printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
+ val & 0xffff);
#endif
return val;
}
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_writel addr=0x%08x val=0x%08x\n", addr, val);
+ printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
+ val);
#endif
if (addr & 0x10)
pcnet_ioport_writel(d, addr & 0x0f, val);
val |= pcnet_aprom_readb(d, addr);
}
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_readl addr=0x%08x val=0x%08x\n", addr, val);
+ printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
+ val);
#endif
return val;
}
if (s->pci_dev)
pci_device_save(s->pci_dev, f);
- qemu_put_be32s(f, &s->rap);
- qemu_put_be32s(f, &s->isr);
- qemu_put_be32s(f, &s->lnkst);
+ qemu_put_sbe32(f, s->rap);
+ qemu_put_sbe32(f, s->isr);
+ qemu_put_sbe32(f, s->lnkst);
qemu_put_be32s(f, &s->rdra);
qemu_put_be32s(f, &s->tdra);
qemu_put_buffer(f, s->prom, 16);
for (i = 0; i < 32; i++)
qemu_put_be16s(f, &s->bcr[i]);
qemu_put_be64s(f, &s->timer);
- qemu_put_be32s(f, &s->xmit_pos);
- qemu_put_be32s(f, &s->recv_pos);
+ qemu_put_sbe32(f, s->xmit_pos);
+ qemu_put_sbe32(f, s->recv_pos);
qemu_put_buffer(f, s->buffer, 4096);
- qemu_put_be32s(f, &s->tx_busy);
+ qemu_put_sbe32(f, s->tx_busy);
qemu_put_timer(f, s->poll_timer);
}
return ret;
}
- qemu_get_be32s(f, &s->rap);
- qemu_get_be32s(f, &s->isr);
- qemu_get_be32s(f, &s->lnkst);
+ qemu_get_sbe32s(f, &s->rap);
+ qemu_get_sbe32s(f, &s->isr);
+ qemu_get_sbe32s(f, &s->lnkst);
qemu_get_be32s(f, &s->rdra);
qemu_get_be32s(f, &s->tdra);
qemu_get_buffer(f, s->prom, 16);
for (i = 0; i < 32; i++)
qemu_get_be16s(f, &s->bcr[i]);
qemu_get_be64s(f, &s->timer);
- qemu_get_be32s(f, &s->xmit_pos);
- qemu_get_be32s(f, &s->recv_pos);
+ qemu_get_sbe32s(f, &s->xmit_pos);
+ qemu_get_sbe32s(f, &s->recv_pos);
qemu_get_buffer(f, s->buffer, 4096);
- qemu_get_be32s(f, &s->tx_busy);
+ qemu_get_sbe32s(f, &s->tx_busy);
qemu_get_timer(f, s->poll_timer);
return 0;
}
-static void pcnet_common_init(PCNetState *d, NICInfo *nd, const char *info_str)
+static void pcnet_common_cleanup(PCNetState *d)
{
- d->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, d);
-
- d->nd = nd;
-
- if (nd && nd->vlan) {
- d->vc = qemu_new_vlan_client(nd->vlan, pcnet_receive,
- pcnet_can_receive, d);
-
- snprintf(d->vc->info_str, sizeof(d->vc->info_str),
- "pcnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
- d->nd->macaddr[0],
- d->nd->macaddr[1],
- d->nd->macaddr[2],
- d->nd->macaddr[3],
- d->nd->macaddr[4],
- d->nd->macaddr[5]);
- } else {
- d->vc = NULL;
- }
- pcnet_h_reset(d);
- register_savevm("pcnet", 0, 2, pcnet_save, pcnet_load, d);
+ unregister_savevm("pcnet", d);
+
+ qemu_del_timer(d->poll_timer);
+ qemu_free_timer(d->poll_timer);
+}
+
+static void pcnet_common_init(DeviceState *dev, PCNetState *s,
+ NetCleanup *cleanup)
+{
+ s->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, s);
+
+ qdev_get_macaddr(dev, s->macaddr);
+ s->vc = qdev_get_vlan_client(dev,
+ pcnet_receive, pcnet_can_receive,
+ cleanup, s);
+ pcnet_h_reset(s);
+ register_savevm("pcnet", -1, 2, pcnet_save, pcnet_load, s);
}
/* PCI interface */
static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
- PCNetState *d = (PCNetState *)pci_dev;
+ PCIPCNetState *d = (PCIPCNetState *)pci_dev;
#ifdef PCNET_DEBUG_IO
- printf("pcnet_ioport_map addr=0x%08x 0x%08x\n", addr, size);
+ printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size);
#endif
- cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->mmio_index);
+ cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index);
}
static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
cpu_physical_memory_read(addr, buf, len);
}
-void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
+static void pci_pcnet_cleanup(VLANClientState *vc)
+{
+ PCNetState *d = vc->opaque;
+
+ pcnet_common_cleanup(d);
+}
+
+static int pci_pcnet_uninit(PCIDevice *dev)
{
- PCNetState *d;
+ PCIPCNetState *d = (PCIPCNetState *)dev;
+
+ cpu_unregister_io_memory(d->state.mmio_index);
+
+ return 0;
+}
+
+static void pci_pcnet_init(PCIDevice *pci_dev)
+{
+ PCIPCNetState *d = (PCIPCNetState *)pci_dev;
+ PCNetState *s = &d->state;
uint8_t *pci_conf;
#if 0
sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
#endif
- d = (PCNetState *)pci_register_device(bus, "PCNet", sizeof(PCNetState),
- devfn, NULL, NULL);
-
- pci_conf = d->dev.config;
-
- *(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
- *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
+ pci_dev->unregister = pci_pcnet_uninit;
+
+ pci_conf = pci_dev->config;
+
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
*(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
*(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
pci_conf[0x08] = 0x10;
pci_conf[0x09] = 0x00;
- pci_conf[0x0a] = 0x00; // ethernet network controller
- pci_conf[0x0b] = 0x02;
- pci_conf[0x0e] = 0x00; // header_type
-
+ pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
+ pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
*(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
*(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
-
+
pci_conf[0x3d] = 1; // interrupt pin 0
pci_conf[0x3e] = 0x06;
pci_conf[0x3f] = 0xff;
/* Handler for memory-mapped I/O */
- d->mmio_index =
- cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, d);
+ s->mmio_index =
+ cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, &d->state);
pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
-
+
pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
-
- d->irq = d->dev.irq[0];
- d->phys_mem_read = pci_physical_memory_read;
- d->phys_mem_write = pci_physical_memory_write;
- d->pci_dev = &d->dev;
- pcnet_common_init(d, nd, "pcnet");
+ s->irq = pci_dev->irq[0];
+ s->phys_mem_read = pci_physical_memory_read;
+ s->phys_mem_write = pci_physical_memory_write;
+ s->pci_dev = pci_dev;
+
+ pcnet_common_init(&pci_dev->qdev, s, pci_pcnet_cleanup);
}
/* SPARC32 interface */
#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure
+#include "sun4m.h"
static void parent_lance_reset(void *opaque, int irq, int level)
{
+ SysBusPCNetState *d = opaque;
if (level)
- pcnet_h_reset(opaque);
+ pcnet_h_reset(&d->state);
}
static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
+ SysBusPCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
val & 0xffff);
#endif
- pcnet_ioport_writew(opaque, addr & 7, val & 0xffff);
+ pcnet_ioport_writew(&d->state, addr, val & 0xffff);
}
static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
{
+ SysBusPCNetState *d = opaque;
uint32_t val;
- val = pcnet_ioport_readw(opaque, addr & 7);
+ val = pcnet_ioport_readw(&d->state, addr);
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
+ printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
val & 0xffff);
#endif
}
static CPUReadMemoryFunc *lance_mem_read[3] = {
+ NULL,
lance_mem_readw,
- lance_mem_readw,
- lance_mem_readw,
+ NULL,
};
static CPUWriteMemoryFunc *lance_mem_write[3] = {
+ NULL,
lance_mem_writew,
- lance_mem_writew,
- lance_mem_writew,
+ NULL,
};
-void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
- qemu_irq irq, qemu_irq *reset)
+static void lance_cleanup(VLANClientState *vc)
{
- PCNetState *d;
- int lance_io_memory;
+ PCNetState *d = vc->opaque;
- d = qemu_mallocz(sizeof(PCNetState));
- if (!d)
- return;
+ pcnet_common_cleanup(d);
+}
- lance_io_memory =
+static void lance_init(SysBusDevice *dev)
+{
+ SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
+ PCNetState *s = &d->state;
+
+ s->mmio_index =
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
- d->dma_opaque = dma_opaque;
+ s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma");
+
+ qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
- *reset = *qemu_allocate_irqs(parent_lance_reset, d, 1);
+ sysbus_init_mmio(dev, 4, s->mmio_index);
- cpu_register_physical_memory(leaddr, 4, lance_io_memory);
+ sysbus_init_irq(dev, &s->irq);
- d->irq = irq;
- d->phys_mem_read = ledma_memory_read;
- d->phys_mem_write = ledma_memory_write;
+ s->phys_mem_read = ledma_memory_read;
+ s->phys_mem_write = ledma_memory_write;
- pcnet_common_init(d, nd, "lance");
+ pcnet_common_init(&dev->qdev, s, lance_cleanup);
}
#endif /* TARGET_SPARC */
+
+static void pcnet_register_devices(void)
+{
+ pci_qdev_register("pcnet", sizeof(PCIPCNetState), pci_pcnet_init);
+#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64)
+ sysbus_register_dev("lance", sizeof(SysBusPCNetState), lance_init);
+#endif
+}
+
+device_init(pcnet_register_devices)
projects / qemu / blobdiff