#include "vl.h"
-#define DEBUG_IRQ_COUNT
-
#define BIOS_FILENAME "mips_bios.bin"
//#define BIOS_FILENAME "system.bin"
#define KERNEL_LOAD_ADDR 0x80010000
#define INITRD_LOAD_ADDR 0x80800000
-/* MIPS R4K IRQ controler */
-#if defined(DEBUG_IRQ_COUNT)
-static uint64_t irq_count[16];
-#endif
+#define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
extern FILE *logfile;
-void mips_set_irq (int n_IRQ, int level)
-{
- uint32_t mask;
-
- if (n_IRQ < 0 || n_IRQ >= 8)
- return;
- mask = 0x100 << n_IRQ;
- if (level != 0) {
-#if 1
- if (logfile) {
- fprintf(logfile, "%s n %d l %d mask %08x %08x\n",
- __func__, n_IRQ, level, mask, cpu_single_env->CP0_Status);
- }
-#endif
- cpu_single_env->CP0_Cause |= mask;
- if ((cpu_single_env->CP0_Status & 0x00000001) &&
- (cpu_single_env->CP0_Status & mask)) {
-#if defined(DEBUG_IRQ_COUNT)
- irq_count[n_IRQ]++;
-#endif
-#if 1
- if (logfile)
- fprintf(logfile, "%s raise IRQ\n", __func__);
-#endif
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
- }
- } else {
- cpu_single_env->CP0_Cause &= ~mask;
- }
-}
-
-void pic_set_irq (int n_IRQ, int level)
-{
- mips_set_irq(n_IRQ + 2, level);
-}
-
-void pic_info (void)
-{
- term_printf("IRQ asserted: %02x mask: %02x\n",
- (cpu_single_env->CP0_Cause >> 8) & 0xFF,
- (cpu_single_env->CP0_Status >> 8) & 0xFF);
-}
+static PITState *pit;
-void irq_info (void)
+static void pic_irq_request(void *opaque, int level)
{
-#if !defined(DEBUG_IRQ_COUNT)
- term_printf("irq statistic code not compiled.\n");
-#else
- int i;
- int64_t count;
-
- term_printf("IRQ statistics:\n");
- for (i = 0; i < 8; i++) {
- count = irq_count[i];
- if (count > 0)
- term_printf("%2d: %lld\n", i, count);
+ CPUState *env = first_cpu;
+ if (level) {
+ env->CP0_Cause |= 0x00000400;
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ } else {
+ env->CP0_Cause &= ~0x00000400;
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
-#endif
}
void cpu_mips_irqctrl_init (void)
{
}
-/* MIPS R4K timer */
+/* XXX: do not use a global */
uint32_t cpu_mips_get_random (CPUState *env)
{
- uint64_t now = qemu_get_clock(vm_clock);
-
- return (uint32_t)now & 0x0000000F;
+ static uint32_t seed = 0;
+ uint32_t idx;
+ seed = seed * 314159 + 1;
+ idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
+ return idx;
}
+/* MIPS R4K timer */
uint32_t cpu_mips_get_count (CPUState *env)
{
return env->CP0_Count +
next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
if (next == now)
next++;
-#if 1
+#if 0
if (logfile) {
fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",
__func__, now, count, compare, next - now);
void cpu_mips_store_compare (CPUState *env, uint32_t value)
{
cpu_mips_update_count(env, cpu_mips_get_count(env), value);
- pic_set_irq(5, 0);
+ env->CP0_Cause &= ~0x00008000;
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
static void mips_timer_cb (void *opaque)
CPUState *env;
env = opaque;
-#if 1
+#if 0
if (logfile) {
fprintf(logfile, "%s\n", __func__);
}
#endif
cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
- pic_set_irq(5, 1);
+ env->CP0_Cause |= 0x00008000;
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
void cpu_mips_clock_init (CPUState *env)
cpu_mips_update_count(env, 1, 0);
}
+
static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
+#if 0
if (logfile)
fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
+#endif
cpu_outb(NULL, addr & 0xffff, value);
}
static uint32_t io_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t ret = cpu_inb(NULL, addr & 0xffff);
+#if 0
if (logfile)
fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
+#endif
return ret;
}
static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
+#if 0
if (logfile)
fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
+#endif
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap16(ret);
#endif
+#if 0
if (logfile)
fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
+#endif
return ret;
}
static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
+#if 0
if (logfile)
fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
+#endif
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap32(ret);
#endif
+#if 0
if (logfile)
fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
+#endif
return ret;
}
const char *initrd_filename)
{
char buf[1024];
- target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
+ int64_t entry = 0;
unsigned long bios_offset;
int io_memory;
- int linux_boot;
int ret;
+ CPUState *env;
+ long kernel_size;
+
+ env = cpu_init();
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
- printf("%s: start\n", __func__);
- linux_boot = (kernel_filename != NULL);
/* allocate RAM */
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
+
+ /* Try to load a BIOS image. If this fails, we continue regardless,
+ but initialize the hardware ourselves. When a kernel gets
+ preloaded we also initialize the hardware, since the BIOS wasn't
+ run. */
bios_offset = ram_size + vga_ram_size;
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
- printf("%s: load BIOS '%s' size %d\n", __func__, buf, BIOS_SIZE);
ret = load_image(buf, phys_ram_base + bios_offset);
- if (ret != BIOS_SIZE) {
- fprintf(stderr, "qemu: could not load MIPS bios '%s'\n", buf);
- exit(1);
+ if (ret == BIOS_SIZE) {
+ cpu_register_physical_memory((uint32_t)(0x1fc00000),
+ BIOS_SIZE, bios_offset | IO_MEM_ROM);
+ } else {
+ /* not fatal */
+ fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
+ buf);
}
- cpu_register_physical_memory((uint32_t)(0x1fc00000),
- BIOS_SIZE, bios_offset | IO_MEM_ROM);
-#if 0
- memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);
- cpu_single_env->PC = 0x80010004;
-#else
- cpu_single_env->PC = 0xBFC00004;
-#endif
- if (linux_boot) {
- kernel_base = KERNEL_LOAD_ADDR;
- /* now we can load the kernel */
- kernel_size = load_image(kernel_filename,
- phys_ram_base + (kernel_base - 0x80000000));
- if (kernel_size == (target_ulong) -1) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
- kernel_filename);
- exit(1);
- }
+
+ kernel_size = 0;
+ if (kernel_filename) {
+ kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
+ if (kernel_size >= 0)
+ env->PC = entry;
+ else {
+ kernel_size = load_image(kernel_filename,
+ phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
+ if (kernel_size < 0) {
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ kernel_filename);
+ exit(1);
+ }
+ env->PC = KERNEL_LOAD_ADDR;
+ }
+
/* load initrd */
if (initrd_filename) {
- initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image(initrd_filename,
- phys_ram_base + initrd_base);
- if (initrd_size == (target_ulong) -1) {
+ if (load_image(initrd_filename,
+ phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND)
+ == (target_ulong) -1) {
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
- } else {
- initrd_base = 0;
- initrd_size = 0;
}
- cpu_single_env->PC = KERNEL_LOAD_ADDR;
- } else {
- kernel_base = 0;
- kernel_size = 0;
- initrd_base = 0;
- initrd_size = 0;
- }
- /* XXX: should not be ! */
- printf("%s: init VGA\n", __func__);
- vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
- vga_ram_size);
+ /* Store command line. */
+ strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
+ /* FIXME: little endian support */
+ *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
+ *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
+ }
/* Init internal devices */
- cpu_mips_clock_init(cpu_single_env);
+ cpu_mips_clock_init(env);
cpu_mips_irqctrl_init();
- isa_mem_base = 0x78000000;
- /* Register 64 KB of ISA IO space at random address */
+ /* Register 64 KB of ISA IO space at 0x14000000 */
io_memory = cpu_register_io_memory(0, io_read, io_write, NULL);
- cpu_register_physical_memory(0x70000000, 0x00010000, io_memory);
- serial_init(0x3f8, 4, serial_hds[0]);
- printf("%s: done\n", __func__);
+ cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
+ isa_mem_base = 0x10000000;
+
+ isa_pic = pic_init(pic_irq_request, env);
+ pit = pit_init(0x40, 0);
+ serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
+ vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
+ vga_ram_size, 0, 0);
+
+ if (nd_table[0].vlan) {
+ if (nd_table[0].model == NULL
+ || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
+ isa_ne2000_init(0x300, 9, &nd_table[0]);
+ } else {
+ fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
+ exit (1);
+ }
+ }
}
QEMUMachine mips_machine = {