update

[qemu] / cpu-i386.h

diff --git a/cpu-i386.h b/cpu-i386.h
index abbb037..e6318fb 100644 (file)
--- a/cpu-i386.h
+++ b/cpu-i386.h
@@ -125,6 +125,15 @@
 #define PG_ERROR_U_MASK    0x04
 #define PG_ERROR_RSVD_MASK 0x08
 
+#define MSR_IA32_APICBASE               0x1b
+#define MSR_IA32_APICBASE_BSP           (1<<8)
+#define MSR_IA32_APICBASE_ENABLE        (1<<11)
+#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
+
+#define MSR_IA32_SYSENTER_CS            0x174
+#define MSR_IA32_SYSENTER_ESP           0x175
+#define MSR_IA32_SYSENTER_EIP           0x176
+
 #define EXCP00_DIVZ    0
 #define EXCP01_SSTP    1
 #define EXCP02_NMI     2
@@ -244,6 +253,11 @@ typedef struct CPUX86State {
     SegmentCache tr;
     SegmentCache gdt; /* only base and limit are used */
     SegmentCache idt; /* only base and limit are used */
+
+    /* sysenter registers */
+    uint32_t sysenter_cs;
+    uint32_t sysenter_esp;
+    uint32_t sysenter_eip;
     
     /* exception/interrupt handling */
     jmp_buf jmp_env;
@@ -251,15 +265,12 @@ typedef struct CPUX86State {
     int error_code;
     int exception_is_int;
     int exception_next_eip;
-
+    struct TranslationBlock *current_tb; /* currently executing TB */
     uint32_t cr[5]; /* NOTE: cr1 is unused */
     uint32_t dr[8]; /* debug registers */
-    int interrupt_request; /* if true, will exit from cpu_exec() ASAP */
-    /* if true, will call cpu_x86_get_pic_interrupt() ASAP to get the
-       request interrupt number */
-    int hard_interrupt_request; 
+    int interrupt_request; 
     int user_mode_only; /* user mode only simulation */
-
+    
     /* user data */
     void *opaque;
 } CPUX86State;
@@ -275,7 +286,6 @@ int cpu_x86_inl(CPUX86State *env, int addr);
 
 CPUX86State *cpu_x86_init(void);
 int cpu_x86_exec(CPUX86State *s);
-void cpu_x86_interrupt(CPUX86State *s);
 void cpu_x86_close(CPUX86State *s);
 int cpu_x86_get_pic_interrupt(CPUX86State *s);
 
@@ -295,7 +305,6 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
 
 /* MMU defines */
 void cpu_x86_init_mmu(CPUX86State *env);
-extern CPUX86State *global_env;
 extern int phys_ram_size;
 extern int phys_ram_fd;
 extern uint8_t *phys_ram_base;