/*
* i386 emulator main execution loop
*
- * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2003-2005 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
longjmp(env->jmp_env, 1);
}
#endif
+#ifndef TARGET_SPARC
+#define reg_T2
+#endif
/* exit the current TB from a signal handler. The host registers are
restored in a state compatible with the CPU emulator
int cpu_exec(CPUState *env1)
{
- int saved_T0, saved_T1, saved_T2;
+ int saved_T0, saved_T1;
+#if defined(reg_T2)
+ int saved_T2;
+#endif
CPUState *saved_env;
+#if defined(TARGET_I386)
#ifdef reg_EAX
int saved_EAX;
#endif
#ifdef reg_EDI
int saved_EDI;
#endif
+#elif defined(TARGET_SPARC)
+#if defined(reg_REGWPTR)
+ uint32_t *saved_regwptr;
+#endif
+#endif
#ifdef __sparc__
int saved_i7, tmp_T0;
#endif
env = env1;
saved_T0 = T0;
saved_T1 = T1;
+#if defined(reg_T2)
saved_T2 = T2;
+#endif
#ifdef __sparc__
/* we also save i7 because longjmp may not restore it */
asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
env->cpsr = psr & ~CACHED_CPSR_BITS;
}
#elif defined(TARGET_SPARC)
+#if defined(reg_REGWPTR)
+ saved_regwptr = REGWPTR;
+#endif
#elif defined(TARGET_PPC)
+#elif defined(TARGET_MIPS)
#else
#error unsupported target CPU
#endif
env->exception_next_eip, 0);
#elif defined(TARGET_PPC)
do_interrupt(env);
+#elif defined(TARGET_MIPS)
+ do_interrupt(env);
#elif defined(TARGET_SPARC)
- do_interrupt(env->exception_index,
- env->error_code);
+ do_interrupt(env->exception_index);
#endif
}
env->exception_index = -1;
env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
}
-#elif defined(TARGET_SPARC)
- if (interrupt_request & CPU_INTERRUPT_HARD) {
- do_interrupt(env->interrupt_index, 0);
+#elif defined(TARGET_MIPS)
+ if ((interrupt_request & CPU_INTERRUPT_HARD) &&
+ (env->CP0_Status & (1 << CP0St_IE)) &&
+ (env->CP0_Cause & 0x0000FF00) &&
+ !(env->hflags & MIPS_HFLAG_EXL) &&
+ !(env->hflags & MIPS_HFLAG_ERL) &&
+ !(env->hflags & MIPS_HFLAG_DM)) {
+ /* Raise it */
+ env->exception_index = EXCP_EXT_INTERRUPT;
+ env->error_code = 0;
+ do_interrupt(env);
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ }
+#elif defined(TARGET_SPARC)
+ if ((interrupt_request & CPU_INTERRUPT_HARD) &&
+ (env->psret != 0)) {
+ int pil = env->interrupt_index & 15;
+ int type = env->interrupt_index & 0xf0;
+
+ if (((type == TT_EXTINT) &&
+ (pil == 15 || pil > env->psrpil)) ||
+ type != TT_EXTINT) {
+ env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ do_interrupt(env->interrupt_index);
+ env->interrupt_index = 0;
+ }
} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
//do_interrupt(0, 0, 0, 0, 0);
env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
if ((loglevel & CPU_LOG_EXEC)) {
#if defined(TARGET_I386)
/* restore flags in standard format */
+#ifdef reg_EAX
env->regs[R_EAX] = EAX;
+#endif
+#ifdef reg_EBX
env->regs[R_EBX] = EBX;
+#endif
+#ifdef reg_ECX
env->regs[R_ECX] = ECX;
+#endif
+#ifdef reg_EDX
env->regs[R_EDX] = EDX;
+#endif
+#ifdef reg_ESI
env->regs[R_ESI] = ESI;
+#endif
+#ifdef reg_EDI
env->regs[R_EDI] = EDI;
+#endif
+#ifdef reg_EBP
env->regs[R_EBP] = EBP;
+#endif
+#ifdef reg_ESP
env->regs[R_ESP] = ESP;
+#endif
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
cpu_dump_state(env, logfile, fprintf, 0);
env->cpsr &= ~CACHED_CPSR_BITS;
#elif defined(TARGET_SPARC)
- cpu_dump_state (env, logfile, fprintf, 0);
+ REGWPTR = env->regbase + (env->cwp * 16);
+ env->regwptr = REGWPTR;
+ cpu_dump_state(env, logfile, fprintf, 0);
#elif defined(TARGET_PPC)
cpu_dump_state(env, logfile, fprintf, 0);
+#elif defined(TARGET_MIPS)
+ cpu_dump_state(env, logfile, fprintf, 0);
#else
#error unsupported target CPU
#endif
cs_base = env->segs[R_CS].base;
pc = cs_base + env->eip;
#elif defined(TARGET_ARM)
- flags = env->thumb;
+ flags = env->thumb | (env->vfp.vec_len << 1)
+ | (env->vfp.vec_stride << 4);
cs_base = 0;
pc = env->regs[15];
#elif defined(TARGET_SPARC)
- flags = 0;
+#ifdef TARGET_SPARC64
+ flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
+#else
+ flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
+#endif
cs_base = env->npc;
pc = env->pc;
#elif defined(TARGET_PPC)
- flags = 0;
+ flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
+ (msr_se << MSR_SE) | (msr_le << MSR_LE);
cs_base = 0;
pc = env->nip;
+#elif defined(TARGET_MIPS)
+ flags = env->hflags & MIPS_HFLAGS_TMASK;
+ cs_base = NULL;
+ pc = env->PC;
#else
#error unsupported CPU
#endif
);
}
}
+#elif defined(__ia64)
+ struct fptr {
+ void *ip;
+ void *gp;
+ } fp;
+
+ fp.ip = tc_ptr;
+ fp.gp = code_gen_buffer + 2 * (1 << 20);
+ (*(void (*)(void)) &fp)();
#else
gen_func();
#endif
#endif
#elif defined(TARGET_ARM)
env->cpsr = compute_cpsr();
+ /* XXX: Save/restore host fpu exception state?. */
#elif defined(TARGET_SPARC)
+#if defined(reg_REGWPTR)
+ REGWPTR = saved_regwptr;
+#endif
#elif defined(TARGET_PPC)
+#elif defined(TARGET_MIPS)
#else
#error unsupported target CPU
#endif
#endif
T0 = saved_T0;
T1 = saved_T1;
+#if defined(reg_T2)
T2 = saved_T2;
+#endif
env = saved_env;
return ret;
}
/* never comes here */
return 1;
}
+
+#elif defined (TARGET_MIPS)
+static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
+ int is_write, sigset_t *old_set,
+ void *puc)
+{
+ TranslationBlock *tb;
+ int ret;
+
+ if (cpu_single_env)
+ env = cpu_single_env; /* XXX: find a correct solution for multithread */
+#if defined(DEBUG_SIGNAL)
+ printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
+ pc, address, is_write, *(unsigned long *)old_set);
+#endif
+ /* XXX: locking issue */
+ if (is_write && page_unprotect(address, pc, puc)) {
+ return 1;
+ }
+
+ /* see if it is an MMU fault */
+ ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
+ if (ret < 0)
+ return 0; /* not an MMU fault */
+ if (ret == 0)
+ return 1; /* the MMU fault was handled without causing real CPU fault */
+
+ /* now we have a real cpu fault */
+ tb = tb_find_pc(pc);
+ if (tb) {
+ /* the PC is inside the translated code. It means that we have
+ a virtual CPU fault */
+ cpu_restore_state(tb, env, pc, puc);
+ }
+ if (ret == 1) {
+#if 0
+ printf("PF exception: NIP=0x%08x error=0x%x %p\n",
+ env->nip, env->error_code, tb);
+#endif
+ /* we restore the process signal mask as the sigreturn should
+ do it (XXX: use sigsetjmp) */
+ sigprocmask(SIG_SETMASK, old_set, NULL);
+ do_raise_exception_err(env->exception_index, env->error_code);
+ } else {
+ /* activate soft MMU for this block */
+ cpu_resume_from_signal(env, puc);
+ }
+ /* never comes here */
+ return 1;
+}
+
#else
#error unsupported target CPU
#endif
&uc->uc_sigmask, puc);
}
+#elif defined(__ia64)
+
+#ifndef __ISR_VALID
+ /* This ought to be in <bits/siginfo.h>... */
+# define __ISR_VALID 1
+# define si_flags _sifields._sigfault._si_pad0
+#endif
+
+int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
+{
+ struct ucontext *uc = puc;
+ unsigned long ip;
+ int is_write = 0;
+
+ ip = uc->uc_mcontext.sc_ip;
+ switch (host_signum) {
+ case SIGILL:
+ case SIGFPE:
+ case SIGSEGV:
+ case SIGBUS:
+ case SIGTRAP:
+ if (info->si_code && (info->si_flags & __ISR_VALID))
+ /* ISR.W (write-access) is bit 33: */
+ is_write = (info->si_isr >> 33) & 1;
+ break;
+
+ default:
+ break;
+ }
+ return handle_cpu_signal(ip, (unsigned long)info->si_addr,
+ is_write,
+ &uc->uc_sigmask, puc);
+}
+
#else
#error host CPU specific signal handler needed
projects / qemu / blobdiff