/* cannot fail at this point */
tb = tb_alloc(pc);
/* don't forget to invalidate previous TB info */
- T0 = 0;
+ tb_invalidated_flag = 1;
}
tc_ptr = code_gen_ptr;
tb->tc_ptr = tc_ptr;
tb_link_phys(tb, phys_pc, phys_page2);
found:
- if (tb_invalidated_flag) {
- /* as some TB could have been invalidated because
- of memory exceptions while generating the code, we
- must recompute the hash index here */
- T0 = 0;
- }
/* we add the TB in the virtual pc hash table */
env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
spin_unlock(&tb_lock);
pc = cs_base + env->eip;
#elif defined(TARGET_ARM)
flags = env->thumb | (env->vfp.vec_len << 1)
- | (env->vfp.vec_stride << 4);
+ | (env->vfp.vec_stride << 4);
+ if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
+ flags |= (1 << 6);
+ if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
+ flags |= (1 << 7);
cs_base = 0;
pc = env->regs[15];
#elif defined(TARGET_SPARC)
cs_base = 0;
pc = env->nip;
#elif defined(TARGET_MIPS)
- flags = env->hflags & MIPS_HFLAGS_TMASK;
- cs_base = NULL;
+ flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
+ cs_base = 0;
pc = env->PC;
#else
#error unsupported CPU
if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
tb->flags != flags, 0)) {
tb = tb_find_slow(pc, cs_base, flags);
+ /* Note: we do it here to avoid a gcc bug on Mac OS X when
+ doing it in tb_find_slow */
+ if (tb_invalidated_flag) {
+ /* as some TB could have been invalidated because
+ of memory exceptions while generating the code, we
+ must recompute the hash index here */
+ T0 = 0;
+ }
}
return tb;
}
TranslationBlock *tb;
uint8_t *tc_ptr;
+#if defined(TARGET_I386)
+ /* handle exit of HALTED state */
+ if (env1->hflags & HF_HALTED_MASK) {
+ /* disable halt condition */
+ if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (env1->eflags & IF_MASK)) {
+ env1->hflags &= ~HF_HALTED_MASK;
+ } else {
+ return EXCP_HALTED;
+ }
+ }
+#elif defined(TARGET_PPC)
+ if (env1->halted) {
+ if (env1->msr[MSR_EE] &&
+ (env1->interrupt_request &
+ (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
+ env1->halted = 0;
+ } else {
+ return EXCP_HALTED;
+ }
+ }
+#elif defined(TARGET_SPARC)
+ if (env1->halted) {
+ if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (env1->psret != 0)) {
+ env1->halted = 0;
+ } else {
+ return EXCP_HALTED;
+ }
+ }
+#elif defined(TARGET_ARM)
+ if (env1->halted) {
+ /* An interrupt wakes the CPU even if the I and F CPSR bits are
+ set. */
+ if (env1->interrupt_request
+ & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
+ env1->halted = 0;
+ } else {
+ return EXCP_HALTED;
+ }
+ }
+#elif defined(TARGET_MIPS)
+ if (env1->halted) {
+ if (env1->interrupt_request &
+ (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
+ env1->halted = 0;
+ } else {
+ return EXCP_HALTED;
+ }
+ }
+#endif
+
cpu_single_env = env1;
/* first we save global registers */
CC_OP = CC_OP_EFLAGS;
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
- {
- unsigned int psr;
- psr = env->cpsr;
- env->CF = (psr >> 29) & 1;
- env->NZF = (psr & 0xc0000000) ^ 0x40000000;
- env->VF = (psr << 3) & 0x80000000;
- env->QF = (psr >> 27) & 1;
- env->cpsr = psr & ~CACHED_CPSR_BITS;
- }
#elif defined(TARGET_SPARC)
#if defined(reg_REGWPTR)
saved_regwptr = REGWPTR;
do_interrupt(env);
#elif defined(TARGET_SPARC)
do_interrupt(env->exception_index);
+#elif defined(TARGET_ARM)
+ do_interrupt(env);
#endif
}
env->exception_index = -1;
} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
//do_interrupt(0, 0, 0, 0, 0);
env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
- }
+ } else if (interrupt_request & CPU_INTERRUPT_HALT) {
+ env1->halted = 1;
+ return EXCP_HALTED;
+ }
+#elif defined(TARGET_ARM)
+ if (interrupt_request & CPU_INTERRUPT_FIQ
+ && !(env->uncached_cpsr & CPSR_F)) {
+ env->exception_index = EXCP_FIQ;
+ do_interrupt(env);
+ }
+ if (interrupt_request & CPU_INTERRUPT_HARD
+ && !(env->uncached_cpsr & CPSR_I)) {
+ env->exception_index = EXCP_IRQ;
+ do_interrupt(env);
+ }
#endif
- if (interrupt_request & CPU_INTERRUPT_EXITTB) {
+ if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
/* ensure that no TB jump will be modified as
the program flow was changed */
}
}
#ifdef DEBUG_EXEC
- if ((loglevel & CPU_LOG_EXEC)) {
+ if ((loglevel & CPU_LOG_TB_CPU)) {
#if defined(TARGET_I386)
/* restore flags in standard format */
#ifdef reg_EAX
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
#elif defined(TARGET_ARM)
- env->cpsr = compute_cpsr();
cpu_dump_state(env, logfile, fprintf, 0);
- env->cpsr &= ~CACHED_CPSR_BITS;
#elif defined(TARGET_SPARC)
REGWPTR = env->regbase + (env->cwp * 16);
env->regwptr = REGWPTR;
jump. */
{
if (T0 != 0 &&
+#if USE_KQEMU
+ (env->kqemu_enabled != 2) &&
+#endif
tb->page_addr[1] == -1
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
&& (tb->cflags & CF_CODE_COPY) ==
T0 = 0;
}
#endif
+#if defined(USE_KQEMU)
+#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
+ if (kqemu_is_ok(env) &&
+ (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
+ cpu_loop_exit();
+ }
+#endif
}
} else {
env_to_regs();
EDI = saved_EDI;
#endif
#elif defined(TARGET_ARM)
- env->cpsr = compute_cpsr();
/* XXX: Save/restore host fpu exception state?. */
#elif defined(TARGET_SPARC)
#if defined(reg_REGWPTR)
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
- raise_exception_err(EXCP0E_PAGE, env->error_code);
+ raise_exception_err(env->exception_index, env->error_code);
} else {
/* activate soft MMU for this block */
env->hflags |= HF_SOFTMMU_MASK;
}
/* see if it is an MMU fault */
- ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
+ ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
if (ret < 0)
return 0; /* not an MMU fault */
if (ret == 0)