#ifndef CPU_ALL_H
#define CPU_ALL_H
+#if defined(__arm__) || defined(__sparc__)
+#define WORDS_ALIGNED
+#endif
+
+/* some important defines:
+ *
+ * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
+ * memory accesses.
+ *
+ * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
+ * otherwise little endian.
+ *
+ * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
+ *
+ * TARGET_WORDS_BIGENDIAN : same for target cpu
+ */
+
+/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
+typedef union {
+ double d;
+#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
+ struct {
+ uint32_t lower;
+ uint32_t upper;
+ } l;
+#else
+ struct {
+ uint32_t upper;
+ uint32_t lower;
+ } l;
+#endif
+ uint64_t ll;
+} CPU_DoubleU;
+
/* CPU memory access without any memory or io remapping */
+/*
+ * the generic syntax for the memory accesses is:
+ *
+ * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
+ *
+ * store: st{type}{size}{endian}_{access_type}(ptr, val)
+ *
+ * type is:
+ * (empty): integer access
+ * f : float access
+ *
+ * sign is:
+ * (empty): for floats or 32 bit size
+ * u : unsigned
+ * s : signed
+ *
+ * size is:
+ * b: 8 bits
+ * w: 16 bits
+ * l: 32 bits
+ * q: 64 bits
+ *
+ * endian is:
+ * (empty): target cpu endianness or 8 bit access
+ * r : reversed target cpu endianness (not implemented yet)
+ * be : big endian (not implemented yet)
+ * le : little endian (not implemented yet)
+ *
+ * access_type is:
+ * raw : host memory access
+ * user : user mode access using soft MMU
+ * kernel : kernel mode access using soft MMU
+ */
static inline int ldub_raw(void *ptr)
{
return *(uint8_t *)ptr;
/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
kernel handles unaligned load/stores may give better results, but
it is a system wide setting : bad */
-#if defined(WORDS_BIGENDIAN) || defined(__arm__)
+#if !defined(TARGET_WORDS_BIGENDIAN) && (defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
/* conservative code for little endian unaligned accesses */
static inline int lduw_raw(void *ptr)
stl_raw(ptr, u.i);
}
-
-#if defined(__arm__) && !defined(WORDS_BIGENDIAN)
-
-/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
-static inline double ldfq_raw(void *ptr)
-{
- union {
- double d;
- uint32_t tab[2];
- } u;
- u.tab[1] = ldl_raw(ptr);
- u.tab[0] = ldl_raw(ptr + 4);
- return u.d;
-}
-
-static inline void stfq_raw(void *ptr, double v)
-{
- union {
- double d;
- uint32_t tab[2];
- } u;
- u.d = v;
- stl_raw(ptr, u.tab[1]);
- stl_raw(ptr + 4, u.tab[0]);
-}
-
-#else
static inline double ldfq_raw(void *ptr)
{
- union {
- double d;
- uint64_t i;
- } u;
- u.i = ldq_raw(ptr);
+ CPU_DoubleU u;
+ u.l.lower = ldl_raw(ptr);
+ u.l.upper = ldl_raw(ptr + 4);
return u.d;
}
static inline void stfq_raw(void *ptr, double v)
{
- union {
- double d;
- uint64_t i;
- } u;
+ CPU_DoubleU u;
u.d = v;
- stq_raw(ptr, u.i);
+ stl_raw(ptr, u.l.lower);
+ stl_raw(ptr + 4, u.l.upper);
}
-#endif
-#elif defined(TARGET_WORDS_BIGENDIAN) && !defined(WORDS_BIGENDIAN)
+#elif defined(TARGET_WORDS_BIGENDIAN) && (!defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
static inline int lduw_raw(void *ptr)
{
+#if defined(__i386__)
+ int val;
+ asm volatile ("movzwl %1, %0\n"
+ "xchgb %b0, %h0\n"
+ : "=q" (val)
+ : "m" (*(uint16_t *)ptr));
+ return val;
+#else
uint8_t *b = (uint8_t *) ptr;
- return (b[0]<<8|b[1]);
+ return ((b[0] << 8) | b[1]);
+#endif
}
static inline int ldsw_raw(void *ptr)
{
- int8_t *b = (int8_t *) ptr;
- return (b[0]<<8|b[1]);
+#if defined(__i386__)
+ int val;
+ asm volatile ("movzwl %1, %0\n"
+ "xchgb %b0, %h0\n"
+ : "=q" (val)
+ : "m" (*(uint16_t *)ptr));
+ return (int16_t)val;
+#else
+ uint8_t *b = (uint8_t *) ptr;
+ return (int16_t)((b[0] << 8) | b[1]);
+#endif
}
static inline int ldl_raw(void *ptr)
{
+#if defined(__i386__)
+ int val;
+ asm volatile ("movl %1, %0\n"
+ "bswap %0\n"
+ : "=r" (val)
+ : "m" (*(uint32_t *)ptr));
+ return val;
+#else
uint8_t *b = (uint8_t *) ptr;
- return (b[0]<<24|b[1]<<16|b[2]<<8|b[3]);
+ return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
+#endif
}
static inline uint64_t ldq_raw(void *ptr)
static inline void stw_raw(void *ptr, int v)
{
+#if defined(__i386__)
+ asm volatile ("xchgb %b0, %h0\n"
+ "movw %w0, %1\n"
+ : "=q" (v)
+ : "m" (*(uint16_t *)ptr), "0" (v));
+#else
uint8_t *d = (uint8_t *) ptr;
d[0] = v >> 8;
d[1] = v;
+#endif
}
static inline void stl_raw(void *ptr, int v)
{
+#if defined(__i386__)
+ asm volatile ("bswap %0\n"
+ "movl %0, %1\n"
+ : "=r" (v)
+ : "m" (*(uint32_t *)ptr), "0" (v));
+#else
uint8_t *d = (uint8_t *) ptr;
d[0] = v >> 24;
d[1] = v >> 16;
d[2] = v >> 8;
d[3] = v;
+#endif
}
static inline void stq_raw(void *ptr, uint64_t v)
{
- stl_raw(ptr, v);
- stl_raw(ptr+4, v >> 32);
+ stl_raw(ptr, v >> 32);
+ stl_raw(ptr + 4, v);
+}
+
+/* float access */
+
+static inline float ldfl_raw(void *ptr)
+{
+ union {
+ float f;
+ uint32_t i;
+ } u;
+ u.i = ldl_raw(ptr);
+ return u.f;
+}
+
+static inline void stfl_raw(void *ptr, float v)
+{
+ union {
+ float f;
+ uint32_t i;
+ } u;
+ u.f = v;
+ stl_raw(ptr, u.i);
+}
+
+static inline double ldfq_raw(void *ptr)
+{
+ CPU_DoubleU u;
+ u.l.upper = ldl_raw(ptr);
+ u.l.lower = ldl_raw(ptr + 4);
+ return u.d;
+}
+
+static inline void stfq_raw(void *ptr, double v)
+{
+ CPU_DoubleU u;
+ u.d = v;
+ stl_raw(ptr, u.l.upper);
+ stl_raw(ptr + 4, u.l.lower);
}
#else
#define lduw_kernel(p) lduw_raw(p)
#define ldsw_kernel(p) ldsw_raw(p)
#define ldl_kernel(p) ldl_raw(p)
+#define ldfl_kernel(p) ldfl_raw(p)
+#define ldfq_kernel(p) ldfq_raw(p)
#define stb_kernel(p, v) stb_raw(p, v)
#define stw_kernel(p, v) stw_raw(p, v)
#define stl_kernel(p, v) stl_raw(p, v)
#define stq_kernel(p, v) stq_raw(p, v)
+#define stfl_kernel(p, v) stfl_raw(p, v)
+#define stfq_kernel(p, vt) stfq_raw(p, v)
#endif /* defined(CONFIG_USER_ONLY) */
#define cpu_gen_code cpu_x86_gen_code
#define cpu_interrupt cpu_x86_interrupt
#define cpu_signal_handler cpu_x86_signal_handler
+#define cpu_dump_state cpu_x86_dump_state
#elif defined(TARGET_ARM)
#define cpu_gen_code cpu_arm_gen_code
#define cpu_interrupt cpu_arm_interrupt
#define cpu_signal_handler cpu_arm_signal_handler
+#define cpu_dump_state cpu_arm_dump_state
#elif defined(TARGET_SPARC)
#define cpu_gen_code cpu_sparc_gen_code
#define cpu_interrupt cpu_sparc_interrupt
#define cpu_signal_handler cpu_sparc_signal_handler
+#define cpu_dump_state cpu_sparc_dump_state
#elif defined(TARGET_PPC)
#define cpu_gen_code cpu_ppc_gen_code
#define cpu_interrupt cpu_ppc_interrupt
#define cpu_signal_handler cpu_ppc_signal_handler
+#define cpu_dump_state cpu_ppc_dump_state
#else
void cpu_abort(CPUState *env, const char *fmt, ...);
extern CPUState *cpu_single_env;
+extern int code_copy_enabled;
-#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
-#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
+#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
+#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
+#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
void cpu_interrupt(CPUState *s, int mask);
int cpu_breakpoint_insert(CPUState *env, uint32_t pc);
int cpu_breakpoint_remove(CPUState *env, uint32_t pc);
void cpu_single_step(CPUState *env, int enabled);
+/* Return the physical page corresponding to a virtual one. Use it
+ only for debugging because no protection checks are done. Return -1
+ if no page found. */
+target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
+
#define CPU_LOG_ALL 1
void cpu_set_log(int log_flags);
void cpu_set_log_filename(const char *filename);
+/* IO ports API */
+
+/* NOTE: as these functions may be even used when there is an isa
+ brige on non x86 targets, we always defined them */
+#ifndef NO_CPU_IO_DEFS
+void cpu_outb(CPUState *env, int addr, int val);
+void cpu_outw(CPUState *env, int addr, int val);
+void cpu_outl(CPUState *env, int addr, int val);
+int cpu_inb(CPUState *env, int addr);
+int cpu_inw(CPUState *env, int addr);
+int cpu_inl(CPUState *env, int addr);
+#endif
+
/* memory API */
-typedef void CPUWriteMemoryFunc(uint32_t addr, uint32_t value);
+extern int phys_ram_size;
+extern int phys_ram_fd;
+extern uint8_t *phys_ram_base;
+extern uint8_t *phys_ram_dirty;
+
+/* physical memory access */
+#define IO_MEM_NB_ENTRIES 256
+#define TLB_INVALID_MASK (1 << 3)
+#define IO_MEM_SHIFT 4
+
+#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
+#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
+#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
+#define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */
+#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
+
+/* NOTE: vaddr is only used internally. Never use it except if you know what you do */
+typedef void CPUWriteMemoryFunc(uint32_t addr, uint32_t value, uint32_t vaddr);
typedef uint32_t CPUReadMemoryFunc(uint32_t addr);
void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write);
+void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
+ int len, int is_write);
+static inline void cpu_physical_memory_read(target_ulong addr, uint8_t *buf,
+ int len)
+{
+ cpu_physical_memory_rw(addr, buf, len, 0);
+}
+static inline void cpu_physical_memory_write(target_ulong addr, const uint8_t *buf,
+ int len)
+{
+ cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
+}
+
+int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
+ uint8_t *buf, int len, int is_write);
+
+/* read dirty bit (return 0 or 1) */
+static inline int cpu_physical_memory_is_dirty(target_ulong addr)
+{
+ return phys_ram_dirty[addr >> TARGET_PAGE_BITS];
+}
+
+static inline void cpu_physical_memory_set_dirty(target_ulong addr)
+{
+ phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 1;
+}
+
+void cpu_physical_memory_reset_dirty(target_ulong start, target_ulong end);
+
/* gdb stub API */
extern int gdbstub_fd;
CPUState *cpu_gdbstub_get_env(void *opaque);