+
+#elif defined(TARGET_MIPS)
+void cpu_save(QEMUFile *f, void *opaque)
+{
+}
+
+int cpu_load(QEMUFile *f, void *opaque, int version_id)
+{
+ return 0;
+}
+
+#elif defined(TARGET_SPARC)
+void cpu_save(QEMUFile *f, void *opaque)
+{
+ CPUState *env = opaque;
+ int i;
+ uint32_t tmp;
+
+ for(i = 0; i < 8; i++)
+ qemu_put_betls(f, &env->gregs[i]);
+ for(i = 0; i < NWINDOWS * 16; i++)
+ qemu_put_betls(f, &env->regbase[i]);
+
+ /* FPU */
+ for(i = 0; i < TARGET_FPREGS; i++) {
+ union {
+ TARGET_FPREG_T f;
+ target_ulong i;
+ } u;
+ u.f = env->fpr[i];
+ qemu_put_betl(f, u.i);
+ }
+
+ qemu_put_betls(f, &env->pc);
+ qemu_put_betls(f, &env->npc);
+ qemu_put_betls(f, &env->y);
+ tmp = GET_PSR(env);
+ qemu_put_be32(f, tmp);
+ qemu_put_betls(f, &env->fsr);
+ qemu_put_betls(f, &env->tbr);
+#ifndef TARGET_SPARC64
+ qemu_put_be32s(f, &env->wim);
+ /* MMU */
+ for(i = 0; i < 16; i++)
+ qemu_put_be32s(f, &env->mmuregs[i]);
+#endif
+}
+
+int cpu_load(QEMUFile *f, void *opaque, int version_id)
+{
+ CPUState *env = opaque;
+ int i;
+ uint32_t tmp;
+
+ for(i = 0; i < 8; i++)
+ qemu_get_betls(f, &env->gregs[i]);
+ for(i = 0; i < NWINDOWS * 16; i++)
+ qemu_get_betls(f, &env->regbase[i]);
+
+ /* FPU */
+ for(i = 0; i < TARGET_FPREGS; i++) {
+ union {
+ TARGET_FPREG_T f;
+ target_ulong i;
+ } u;
+ u.i = qemu_get_betl(f);
+ env->fpr[i] = u.f;
+ }
+
+ qemu_get_betls(f, &env->pc);
+ qemu_get_betls(f, &env->npc);
+ qemu_get_betls(f, &env->y);
+ tmp = qemu_get_be32(f);
+ env->cwp = 0; /* needed to ensure that the wrapping registers are
+ correctly updated */
+ PUT_PSR(env, tmp);
+ qemu_get_betls(f, &env->fsr);
+ qemu_get_betls(f, &env->tbr);
+#ifndef TARGET_SPARC64
+ qemu_get_be32s(f, &env->wim);
+ /* MMU */
+ for(i = 0; i < 16; i++)
+ qemu_get_be32s(f, &env->mmuregs[i]);
+#endif
+ tlb_flush(env, 1);
+ return 0;
+}