2 * QEMU based User Mode Linux
4 * This file is part of proprietary software - it is published here
5 * only for demonstration and information purposes.
7 * Copyright (c) 2003 Fabrice Bellard
28 #define DEBUG_LOGFILE "/tmp/vl.log"
29 //#define DEBUG_UNUSED_IOPORT
31 #define PHYS_RAM_BASE 0xa8000000
32 #define KERNEL_LOAD_ADDR 0x00100000
33 #define INITRD_LOAD_ADDR 0x00400000
34 #define KERNEL_PARAMS_ADDR 0x00090000
36 /* from plex86 (BSD license) */
37 struct __attribute__ ((packed)) linux_params {
38 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
39 // I just padded out the VESA parts, rather than define them.
41 /* 0x000 */ uint8_t orig_x;
42 /* 0x001 */ uint8_t orig_y;
43 /* 0x002 */ uint16_t ext_mem_k;
44 /* 0x004 */ uint16_t orig_video_page;
45 /* 0x006 */ uint8_t orig_video_mode;
46 /* 0x007 */ uint8_t orig_video_cols;
47 /* 0x008 */ uint16_t unused1;
48 /* 0x00a */ uint16_t orig_video_ega_bx;
49 /* 0x00c */ uint16_t unused2;
50 /* 0x00e */ uint8_t orig_video_lines;
51 /* 0x00f */ uint8_t orig_video_isVGA;
52 /* 0x010 */ uint16_t orig_video_points;
53 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
54 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
55 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
56 // is calculated as 0x90000 + cl_offset, bu
57 // only if cl_magic == 0xA33F.
58 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
60 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
61 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
63 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
64 // Might be truncated?
65 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
66 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
68 // System description table truncated to 16 bytes
69 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
70 /* 0x0a0 */ uint16_t sys_description_len;
71 /* 0x0a2 */ uint8_t sys_description_table[14];
73 // [1] machine submodel id
77 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
78 /* 0x1e0 */ uint32_t alt_mem_k;
79 /* 0x1e4 */ uint8_t pad4[4];
80 /* 0x1e8 */ uint8_t e820map_entries;
81 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
82 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
83 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
84 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
85 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
86 // (b)zImage-file (in 16 byte units, rounded up)
87 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
88 /* 0x1f8 */ uint16_t ramdisk_flags;
89 /* 0x1fa */ uint16_t vga_mode; // (old one)
90 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
91 /* 0x1fe */ uint8_t pad6[1];
92 /* 0x1ff */ uint8_t aux_device_info;
93 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
94 // aka "reserved" field.
95 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
96 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
97 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
98 // boot loaders, look there.
99 /* 0x210 */ uint8_t loader_type;
104 // T=2: bootsect-loader
108 /* 0x211 */ uint8_t loadflags;
109 // bit0 = 1: kernel is loaded high (bzImage)
110 // bit7 = 1: Heap and pointer (see below) set by boot
112 /* 0x212 */ uint16_t setup_S_temp1;
113 /* 0x214 */ uint32_t kernel_start;
114 /* 0x218 */ uint32_t initrd_start;
115 /* 0x21c */ uint32_t initrd_size;
116 /* 0x220 */ uint8_t setup_S_temp2[4];
117 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
118 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
120 /* 0x2d0 : Int 15, ax=e820 memory map. */
121 // (linux/include/asm-i386/e820.h, 'struct e820entry')
124 #define E820_RESERVED 2
125 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
133 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
135 // BIOS Enhanced Disk Drive Services.
136 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
137 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
138 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
140 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
141 /* 0x800 */ uint8_t commandline[0x800];
144 uint64_t gdt_table[256];
145 uint64_t idt_table[48];
148 #define KERNEL_CS 0x10
149 #define KERNEL_DS 0x18
151 typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data);
152 typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
154 #define MAX_IOPORTS 1024
156 char phys_ram_file[1024];
157 CPUX86State *global_env;
158 FILE *logfile = NULL;
160 IOPortReadFunc *ioport_readb_table[MAX_IOPORTS];
161 IOPortWriteFunc *ioport_writeb_table[MAX_IOPORTS];
162 IOPortReadFunc *ioport_readw_table[MAX_IOPORTS];
163 IOPortWriteFunc *ioport_writew_table[MAX_IOPORTS];
165 /***********************************************************/
168 uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
170 #ifdef DEBUG_UNUSED_IOPORT
171 fprintf(stderr, "inb: port=0x%04x\n", address);
176 void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
178 #ifdef DEBUG_UNUSED_IOPORT
179 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
183 /* default is to make two byte accesses */
184 uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
187 data = ioport_readb_table[address](env, address);
188 data |= ioport_readb_table[address + 1](env, address + 1) << 8;
192 void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
194 ioport_writeb_table[address](env, address, data & 0xff);
195 ioport_writeb_table[address + 1](env, address + 1, (data >> 8) & 0xff);
198 void init_ioports(void)
202 for(i = 0; i < MAX_IOPORTS; i++) {
203 ioport_readb_table[i] = default_ioport_readb;
204 ioport_writeb_table[i] = default_ioport_writeb;
205 ioport_readw_table[i] = default_ioport_readw;
206 ioport_writew_table[i] = default_ioport_writew;
210 int register_ioport_readb(int start, int length, IOPortReadFunc *func)
214 for(i = start; i < start + length; i++)
215 ioport_readb_table[i] = func;
219 int register_ioport_writeb(int start, int length, IOPortWriteFunc *func)
223 for(i = start; i < start + length; i++)
224 ioport_writeb_table[i] = func;
228 void pstrcpy(char *buf, int buf_size, const char *str)
238 if (c == 0 || q >= buf + buf_size - 1)
245 /* strcat and truncate. */
246 char *pstrcat(char *buf, int buf_size, const char *s)
251 pstrcpy(buf + len, buf_size - len, s);
255 int load_kernel(const char *filename, uint8_t *addr)
257 int fd, size, setup_sects;
258 uint8_t bootsect[512];
260 fd = open(filename, O_RDONLY);
263 if (read(fd, bootsect, 512) != 512)
265 setup_sects = bootsect[0x1F1];
268 /* skip 16 bit setup code */
269 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
270 size = read(fd, addr, 16 * 1024 * 1024);
280 /* return the size or -1 if error */
281 int load_image(const char *filename, uint8_t *addr)
284 fd = open(filename, O_RDONLY);
287 size = lseek(fd, 0, SEEK_END);
288 lseek(fd, 0, SEEK_SET);
289 if (read(fd, addr, size) != size) {
297 void cpu_x86_outb(CPUX86State *env, int addr, int val)
299 ioport_writeb_table[addr & (MAX_IOPORTS - 1)](env, addr, val);
302 void cpu_x86_outw(CPUX86State *env, int addr, int val)
304 ioport_writew_table[addr & (MAX_IOPORTS - 1)](env, addr, val);
307 void cpu_x86_outl(CPUX86State *env, int addr, int val)
309 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
312 int cpu_x86_inb(CPUX86State *env, int addr)
314 return ioport_readb_table[addr & (MAX_IOPORTS - 1)](env, addr);
317 int cpu_x86_inw(CPUX86State *env, int addr)
319 return ioport_readw_table[addr & (MAX_IOPORTS - 1)](env, addr);
322 int cpu_x86_inl(CPUX86State *env, int addr)
324 fprintf(stderr, "inl: port=0x%04x\n", addr);
328 /***********************************************************/
329 void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
333 void hw_error(const char *fmt, ...)
338 fprintf(stderr, "qemu: hardware error: ");
339 vfprintf(stderr, fmt, ap);
340 fprintf(stderr, "\n");
342 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
348 /***********************************************************/
350 static uint8_t vga_index;
351 static uint8_t vga_regs[256];
352 static int last_cursor_pos;
354 void update_console_messages(void)
356 int c, i, cursor_pos, eol;
358 cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8);
360 for(i = last_cursor_pos; i < cursor_pos; i++) {
361 c = phys_ram_base[0xb8000 + (i) * 2];
372 last_cursor_pos = cursor_pos;
375 /* just to see first Linux console messages, we intercept cursor position */
376 void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
383 vga_regs[vga_index] = data;
384 if (vga_index == 0x0f)
385 update_console_messages();
391 /***********************************************************/
394 #define RTC_SECONDS 0
395 #define RTC_SECONDS_ALARM 1
396 #define RTC_MINUTES 2
397 #define RTC_MINUTES_ALARM 3
399 #define RTC_HOURS_ALARM 5
400 #define RTC_ALARM_DONT_CARE 0xC0
402 #define RTC_DAY_OF_WEEK 6
403 #define RTC_DAY_OF_MONTH 7
412 /* PC cmos mappings */
413 #define REG_EQUIPMENT_BYTE 0x14
415 uint8_t cmos_data[128];
418 void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
421 cmos_index = data & 0x7f;
425 uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
432 /* toggle update-in-progress bit for Linux (same hack as
434 ret = cmos_data[cmos_index];
435 if (cmos_index == RTC_REG_A)
436 cmos_data[RTC_REG_A] ^= 0x80;
437 else if (cmos_index == RTC_REG_C)
438 cmos_data[RTC_REG_C] = 0x00;
444 static inline int to_bcd(int a)
446 return ((a / 10) << 4) | (a % 10);
456 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
457 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
458 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
459 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
460 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
461 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon);
462 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
464 cmos_data[RTC_REG_A] = 0x26;
465 cmos_data[RTC_REG_B] = 0x02;
466 cmos_data[RTC_REG_C] = 0x00;
467 cmos_data[RTC_REG_D] = 0x80;
469 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
471 register_ioport_writeb(0x70, 2, cmos_ioport_write);
472 register_ioport_readb(0x70, 2, cmos_ioport_read);
475 /***********************************************************/
476 /* 8259 pic emulation */
478 typedef struct PicState {
479 uint8_t last_irr; /* edge detection */
480 uint8_t irr; /* interrupt request register */
481 uint8_t imr; /* interrupt mask register */
482 uint8_t isr; /* interrupt service register */
483 uint8_t priority_add; /* used to compute irq priority */
485 uint8_t read_reg_select;
486 uint8_t special_mask;
489 uint8_t rotate_on_autoeoi;
490 uint8_t init4; /* true if 4 byte init */
493 /* 0 is master pic, 1 is slave pic */
495 int pic_irq_requested;
497 /* set irq level. If an edge is detected, then the IRR is set to 1 */
498 static inline void pic_set_irq1(PicState *s, int irq, int level)
503 if ((s->last_irr & mask) == 0)
507 s->last_irr &= ~mask;
511 static inline int get_priority(PicState *s, int mask)
517 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
522 /* return the pic wanted interrupt. return -1 if none */
523 static int pic_get_irq(PicState *s)
525 int mask, cur_priority, priority;
527 mask = s->irr & ~s->imr;
528 priority = get_priority(s, mask);
531 /* compute current priority */
532 cur_priority = get_priority(s, s->isr);
533 if (priority > cur_priority) {
534 /* higher priority found: an irq should be generated */
541 void pic_set_irq(int irq, int level)
543 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
546 /* can be called at any time outside cpu_exec() to raise irqs if
548 void pic_handle_irq(void)
552 /* first look at slave pic */
553 irq2 = pic_get_irq(&pics[1]);
555 /* if irq request by slave pic, signal master PIC */
556 pic_set_irq1(&pics[0], 2, 1);
557 pic_set_irq1(&pics[0], 2, 0);
559 /* look at requested irq */
560 irq = pic_get_irq(&pics[0]);
564 pic_irq_requested = 8 + irq2;
566 /* from master pic */
567 pic_irq_requested = irq;
569 global_env->hard_interrupt_request = 1;
573 int cpu_x86_get_pic_interrupt(CPUX86State *env)
575 int irq, irq2, intno;
577 /* signal the pic that the irq was acked by the CPU */
578 irq = pic_irq_requested;
581 pics[1].isr |= (1 << irq2);
582 pics[1].irr &= ~(1 << irq2);
584 intno = pics[1].irq_base + irq2;
586 intno = pics[0].irq_base + irq;
588 pics[0].isr |= (1 << irq);
589 pics[0].irr &= ~(1 << irq);
593 void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
598 s = &pics[addr >> 7];
603 memset(s, 0, sizeof(PicState));
607 hw_error("single mode not supported");
609 hw_error("level sensitive irq not supported");
610 } else if (val & 0x08) {
612 s->read_reg_select = val & 1;
614 s->special_mask = (val >> 5) & 1;
619 s->rotate_on_autoeoi = val >> 7;
621 case 0x20: /* end of interrupt */
623 priority = get_priority(s, s->isr);
625 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
628 s->priority_add = (s->priority_add + 1) & 7;
632 s->isr &= ~(1 << priority);
635 s->priority_add = (val + 1) & 7;
639 s->isr &= ~(1 << priority);
640 s->priority_add = (priority + 1) & 7;
645 switch(s->init_state) {
651 s->irq_base = val & 0xf8;
662 s->auto_eoi = (val >> 1) & 1;
669 uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr)
672 s = &pics[addr >> 7];
675 if (s->read_reg_select)
686 register_ioport_writeb(0x20, 2, pic_ioport_write);
687 register_ioport_readb(0x20, 2, pic_ioport_read);
688 register_ioport_writeb(0xa0, 2, pic_ioport_write);
689 register_ioport_readb(0xa0, 2, pic_ioport_read);
692 /***********************************************************/
693 /* 8253 PIT emulation */
695 #define PIT_FREQ 1193182
697 #define RW_STATE_LSB 0
698 #define RW_STATE_MSB 1
699 #define RW_STATE_WORD0 2
700 #define RW_STATE_WORD1 3
701 #define RW_STATE_LATCHED_WORD0 4
702 #define RW_STATE_LATCHED_WORD1 5
704 typedef struct PITChannelState {
706 uint16_t latched_count;
709 uint8_t bcd; /* not supported */
710 uint8_t gate; /* timer start */
711 int64_t count_load_time;
714 PITChannelState pit_channels[3];
717 int64_t ticks_per_sec;
719 int64_t get_clock(void)
722 gettimeofday(&tv, NULL);
723 return tv.tv_sec * 1000000LL + tv.tv_usec;
726 int64_t cpu_get_ticks(void)
729 asm("rdtsc" : "=A" (val));
733 void cpu_calibrate_ticks(void)
738 ticks = cpu_get_ticks();
740 usec = get_clock() - usec;
741 ticks = cpu_get_ticks() - ticks;
742 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
745 static int pit_get_count(PITChannelState *s)
750 d = ((cpu_get_ticks() - s->count_load_time) * PIT_FREQ) /
757 counter = (s->count - d) & 0xffff;
760 counter = s->count - (d % s->count);
766 /* get pit output bit */
767 static int pit_get_out(PITChannelState *s)
772 d = ((cpu_get_ticks() - s->count_load_time) * PIT_FREQ) /
777 out = (d >= s->count);
780 out = (d < s->count);
783 if ((d % s->count) == 0 && d != 0)
789 out = (d % s->count) < (s->count >> 1);
793 out = (d == s->count);
799 void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
809 s = &pit_channels[channel];
810 access = (val >> 4) & 3;
813 s->latched_count = pit_get_count(s);
814 s->rw_state = RW_STATE_LATCHED_WORD0;
817 s->rw_state = access - 1 + RW_STATE_LSB;
820 s->mode = (val >> 1) & 7;
823 s = &pit_channels[addr];
824 switch(s->rw_state) {
826 s->count_load_time = cpu_get_ticks();
830 s->count_load_time = cpu_get_ticks();
831 s->count = (val << 8);
835 if (s->rw_state & 1) {
836 s->count_load_time = cpu_get_ticks();
837 s->count = (s->latched_count & 0xff) | (val << 8);
839 s->latched_count = val;
847 uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
853 s = &pit_channels[addr];
854 switch(s->rw_state) {
859 count = pit_get_count(s);
861 ret = (count >> 8) & 0xff;
868 case RW_STATE_LATCHED_WORD0:
869 case RW_STATE_LATCHED_WORD1:
871 ret = s->latched_count >> 8;
873 ret = s->latched_count & 0xff;
880 void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
882 speaker_data_on = (val >> 1) & 1;
883 pit_channels[2].gate = val & 1;
886 uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
889 out = pit_get_out(&pit_channels[2]);
890 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5);
895 pit_channels[0].gate = 1;
896 pit_channels[1].gate = 1;
897 pit_channels[2].gate = 0;
899 register_ioport_writeb(0x40, 4, pit_ioport_write);
900 register_ioport_readb(0x40, 3, pit_ioport_read);
902 register_ioport_readb(0x61, 1, speaker_ioport_read);
903 register_ioport_writeb(0x61, 1, speaker_ioport_write);
904 cpu_calibrate_ticks();
907 /***********************************************************/
908 /* serial port emulation */
912 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
914 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
915 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
916 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
917 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
919 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
920 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
922 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
923 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
924 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
925 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
927 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
928 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
929 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
930 #define UART_LSR_FE 0x08 /* Frame error indicator */
931 #define UART_LSR_PE 0x04 /* Parity error indicator */
932 #define UART_LSR_OE 0x02 /* Overrun error indicator */
933 #define UART_LSR_DR 0x01 /* Receiver data ready */
935 typedef struct SerialState {
937 uint8_t rbr; /* receive register */
939 uint8_t iir; /* read only */
942 uint8_t lsr; /* read only */
947 SerialState serial_ports[1];
949 void serial_update_irq(void)
951 SerialState *s = &serial_ports[0];
953 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
954 s->iir = UART_IIR_RDI;
955 } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
956 s->iir = UART_IIR_THRI;
958 s->iir = UART_IIR_NO_INT;
960 if (s->iir != UART_IIR_NO_INT) {
961 pic_set_irq(UART_IRQ, 1);
963 pic_set_irq(UART_IRQ, 0);
967 void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
969 SerialState *s = &serial_ports[0];
977 if (s->lcr & UART_LCR_DLAB) {
978 s->divider = (s->divider & 0xff00) | val;
980 s->lsr &= ~UART_LSR_THRE;
985 ret = write(1, &ch, 1);
987 s->lsr |= UART_LSR_THRE;
988 s->lsr |= UART_LSR_TEMT;
993 if (s->lcr & UART_LCR_DLAB) {
994 s->divider = (s->divider & 0x00ff) | (val << 8);
1019 uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1021 SerialState *s = &serial_ports[0];
1028 if (s->lcr & UART_LCR_DLAB) {
1029 ret = s->divider & 0xff;
1032 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1033 serial_update_irq();
1037 if (s->lcr & UART_LCR_DLAB) {
1038 ret = (s->divider >> 8) & 0xff;
1065 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1066 static int term_got_escape;
1068 void term_print_help(void)
1071 "C-a h print this help\n"
1072 "C-a x exit emulatior\n"
1073 "C-a b send break (magic sysrq)\n"
1074 "C-a C-a send C-a\n"
1078 /* called when a char is received */
1079 void serial_received_byte(SerialState *s, int ch)
1081 if (term_got_escape) {
1082 term_got_escape = 0;
1093 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1094 serial_update_irq();
1099 } else if (ch == TERM_ESCAPE) {
1100 term_got_escape = 1;
1104 s->lsr |= UART_LSR_DR;
1105 serial_update_irq();
1109 /* init terminal so that we can grab keys */
1110 static struct termios oldtty;
1112 static void term_exit(void)
1114 tcsetattr (0, TCSANOW, &oldtty);
1117 static void term_init(void)
1121 tcgetattr (0, &tty);
1124 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
1125 |INLCR|IGNCR|ICRNL|IXON);
1126 tty.c_oflag |= OPOST;
1127 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
1128 tty.c_cflag &= ~(CSIZE|PARENB);
1131 tty.c_cc[VTIME] = 0;
1133 tcsetattr (0, TCSANOW, &tty);
1137 fcntl(0, F_SETFL, O_NONBLOCK);
1140 void serial_init(void)
1142 SerialState *s = &serial_ports[0];
1144 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1146 register_ioport_writeb(0x3f8, 8, serial_ioport_write);
1147 register_ioport_readb(0x3f8, 8, serial_ioport_read);
1152 /* cpu signal handler */
1153 static void host_segv_handler(int host_signum, siginfo_t *info,
1156 if (cpu_signal_handler(host_signum, info, puc))
1162 static int timer_irq_pending;
1164 static void host_alarm_handler(int host_signum, siginfo_t *info,
1167 /* just exit from the cpu to have a change to handle timers */
1168 cpu_x86_interrupt(global_env);
1169 timer_irq_pending = 1;
1174 printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
1175 "usage: vl [-h] bzImage initrd [kernel parameters...]\n"
1177 "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
1178 "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
1179 "'initrd' is an initrd image\n"
1180 "-m megs set virtual RAM size to megs MB\n"
1181 "-d output log in /tmp/vl.log\n"
1183 "During emulation, use C-a h to get terminal commands:\n"
1189 int main(int argc, char **argv)
1191 int c, ret, initrd_size, i;
1192 struct linux_params *params;
1193 struct sigaction act;
1194 struct itimerval itv;
1197 /* we never want that malloc() uses mmap() */
1198 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
1200 phys_ram_size = 32 * 1024 * 1024;
1202 c = getopt(argc, argv, "hm:d");
1210 phys_ram_size = atoi(optarg) * 1024 * 1024;
1211 if (phys_ram_size <= 0)
1219 if (optind + 1 >= argc)
1224 logfile = fopen(DEBUG_LOGFILE, "w");
1226 perror(DEBUG_LOGFILE);
1229 setvbuf(logfile, NULL, _IOLBF, 0);
1232 /* init the memory */
1233 strcpy(phys_ram_file, "/tmp/vlXXXXXX");
1234 if (mkstemp(phys_ram_file) < 0) {
1235 fprintf(stderr, "Could not create temporary memory file\n");
1238 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
1239 if (phys_ram_fd < 0) {
1240 fprintf(stderr, "Could not open temporary memory file\n");
1243 ftruncate(phys_ram_fd, phys_ram_size);
1244 unlink(phys_ram_file);
1245 phys_ram_base = mmap((void *)PHYS_RAM_BASE, phys_ram_size,
1246 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
1248 if (phys_ram_base == MAP_FAILED) {
1249 fprintf(stderr, "Could not map physical memory\n");
1253 /* now we can load the kernel */
1254 ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
1256 fprintf(stderr, "%s: could not load kernel\n", argv[optind]);
1261 initrd_size = load_image(argv[optind + 1], phys_ram_base + INITRD_LOAD_ADDR);
1262 if (initrd_size < 0) {
1263 fprintf(stderr, "%s: could not load initrd\n", argv[optind + 1]);
1267 /* init kernel params */
1268 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
1269 memset(params, 0, sizeof(struct linux_params));
1270 params->mount_root_rdonly = 0;
1271 params->cl_magic = 0xA33F;
1272 params->cl_offset = params->commandline - (uint8_t *)params;
1273 params->ext_mem_k = (phys_ram_size / 1024) - 1024;
1274 for(i = optind + 2; i < argc; i++) {
1275 if (i != optind + 2)
1276 pstrcat(params->commandline, sizeof(params->commandline), " ");
1277 pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
1279 params->loader_type = 0x01;
1280 if (initrd_size > 0) {
1281 params->initrd_start = INITRD_LOAD_ADDR;
1282 params->initrd_size = initrd_size;
1284 params->orig_video_lines = 25;
1285 params->orig_video_cols = 80;
1287 /* init basic PC hardware */
1289 register_ioport_writeb(0x80, 1, ioport80_write);
1291 register_ioport_writeb(0x3d4, 2, vga_ioport_write);
1298 /* setup cpu signal handlers for MMU / self modifying code handling */
1299 sigfillset(&act.sa_mask);
1300 act.sa_flags = SA_SIGINFO;
1301 act.sa_sigaction = host_segv_handler;
1302 sigaction(SIGSEGV, &act, NULL);
1303 sigaction(SIGBUS, &act, NULL);
1305 act.sa_sigaction = host_alarm_handler;
1306 sigaction(SIGALRM, &act, NULL);
1308 /* init CPU state */
1312 /* setup basic memory access */
1313 env->cr[0] = 0x00000033;
1314 cpu_x86_init_mmu(env);
1316 memset(params->idt_table, 0, sizeof(params->idt_table));
1318 params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
1319 params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
1321 env->idt.base = (void *)params->idt_table;
1322 env->idt.limit = sizeof(params->idt_table) - 1;
1323 env->gdt.base = (void *)params->gdt_table;
1324 env->gdt.limit = sizeof(params->gdt_table) - 1;
1326 cpu_x86_load_seg(env, R_CS, KERNEL_CS);
1327 cpu_x86_load_seg(env, R_DS, KERNEL_DS);
1328 cpu_x86_load_seg(env, R_ES, KERNEL_DS);
1329 cpu_x86_load_seg(env, R_SS, KERNEL_DS);
1330 cpu_x86_load_seg(env, R_FS, KERNEL_DS);
1331 cpu_x86_load_seg(env, R_GS, KERNEL_DS);
1333 env->eip = KERNEL_LOAD_ADDR;
1334 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
1337 itv.it_interval.tv_sec = 0;
1338 itv.it_interval.tv_usec = 10 * 1000;
1339 itv.it_value.tv_sec = 0;
1340 itv.it_value.tv_usec = 10 * 1000;
1341 setitimer(ITIMER_REAL, &itv, NULL);
1344 struct pollfd ufds[1], *pf;
1345 int ret, n, timeout;
1348 ret = cpu_x86_exec(env);
1350 /* if hlt instruction, we wait until the next IRQ */
1351 if (ret == EXCP_HLT)
1355 /* poll any events */
1357 if (!(serial_ports[0].lsr & UART_LSR_DR)) {
1359 pf->events = POLLIN;
1362 ret = poll(ufds, pf - ufds, timeout);
1364 if (ufds[0].revents & POLLIN) {
1365 n = read(0, &ch, 1);
1367 serial_received_byte(&serial_ports[0], ch);
1372 /* just for testing */
1373 if (timer_irq_pending) {
1376 timer_irq_pending = 0;