2 * QEMU PC System Emulator
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
45 #include <linux/if_tun.h>
53 #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup"
54 #define BIOS_FILENAME "bios.bin"
55 #define VGABIOS_FILENAME "vgabios.bin"
57 //#define DEBUG_UNUSED_IOPORT
59 //#define DEBUG_IRQ_LATENCY
61 /* output Bochs bios info messages */
67 /* debug NE2000 card */
68 //#define DEBUG_NE2000
70 /* debug PC keyboard */
73 /* debug PC keyboard : only mouse */
76 #define PHYS_RAM_BASE 0xac000000
77 #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
79 #define KERNEL_LOAD_ADDR 0x00100000
80 #define INITRD_LOAD_ADDR 0x00400000
81 #define KERNEL_PARAMS_ADDR 0x00090000
83 #define GUI_REFRESH_INTERVAL 30
85 /* from plex86 (BSD license) */
86 struct __attribute__ ((packed)) linux_params {
87 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
88 // I just padded out the VESA parts, rather than define them.
90 /* 0x000 */ uint8_t orig_x;
91 /* 0x001 */ uint8_t orig_y;
92 /* 0x002 */ uint16_t ext_mem_k;
93 /* 0x004 */ uint16_t orig_video_page;
94 /* 0x006 */ uint8_t orig_video_mode;
95 /* 0x007 */ uint8_t orig_video_cols;
96 /* 0x008 */ uint16_t unused1;
97 /* 0x00a */ uint16_t orig_video_ega_bx;
98 /* 0x00c */ uint16_t unused2;
99 /* 0x00e */ uint8_t orig_video_lines;
100 /* 0x00f */ uint8_t orig_video_isVGA;
101 /* 0x010 */ uint16_t orig_video_points;
102 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
103 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
104 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
105 // is calculated as 0x90000 + cl_offset, bu
106 // only if cl_magic == 0xA33F.
107 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
109 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
110 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
112 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
113 // Might be truncated?
114 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
115 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
117 // System description table truncated to 16 bytes
118 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
119 /* 0x0a0 */ uint16_t sys_description_len;
120 /* 0x0a2 */ uint8_t sys_description_table[14];
122 // [1] machine submodel id
126 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
127 /* 0x1e0 */ uint32_t alt_mem_k;
128 /* 0x1e4 */ uint8_t pad4[4];
129 /* 0x1e8 */ uint8_t e820map_entries;
130 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
131 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
132 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
133 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
134 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
135 // (b)zImage-file (in 16 byte units, rounded up)
136 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
137 /* 0x1f8 */ uint16_t ramdisk_flags;
138 /* 0x1fa */ uint16_t vga_mode; // (old one)
139 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
140 /* 0x1fe */ uint8_t pad6[1];
141 /* 0x1ff */ uint8_t aux_device_info;
142 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
143 // aka "reserved" field.
144 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
145 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
146 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
147 // boot loaders, look there.
148 /* 0x210 */ uint8_t loader_type;
153 // T=2: bootsect-loader
157 /* 0x211 */ uint8_t loadflags;
158 // bit0 = 1: kernel is loaded high (bzImage)
159 // bit7 = 1: Heap and pointer (see below) set by boot
161 /* 0x212 */ uint16_t setup_S_temp1;
162 /* 0x214 */ uint32_t kernel_start;
163 /* 0x218 */ uint32_t initrd_start;
164 /* 0x21c */ uint32_t initrd_size;
165 /* 0x220 */ uint8_t setup_S_temp2[4];
166 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
167 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
169 /* 0x2d0 : Int 15, ax=e820 memory map. */
170 // (linux/include/asm-i386/e820.h, 'struct e820entry')
173 #define E820_RESERVED 2
174 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
182 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
184 // BIOS Enhanced Disk Drive Services.
185 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
186 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
187 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
189 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
190 /* 0x800 */ uint8_t commandline[0x800];
193 uint64_t gdt_table[256];
194 uint64_t idt_table[48];
197 #define KERNEL_CS 0x10
198 #define KERNEL_DS 0x18
200 #define MAX_IOPORTS 4096
202 static const char *bios_dir = CONFIG_QEMU_SHAREDIR;
203 char phys_ram_file[1024];
204 CPUX86State *global_env;
205 CPUX86State *cpu_single_env;
206 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
207 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
208 BlockDriverState *bs_table[MAX_DISKS];
210 static DisplayState display_state;
213 int64_t ticks_per_sec;
214 int boot_device = 'c';
216 /***********************************************************/
219 uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
221 #ifdef DEBUG_UNUSED_IOPORT
222 fprintf(stderr, "inb: port=0x%04x\n", address);
227 void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
229 #ifdef DEBUG_UNUSED_IOPORT
230 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
234 /* default is to make two byte accesses */
235 uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
238 data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
239 data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
243 void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
245 ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
246 ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
249 uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
251 #ifdef DEBUG_UNUSED_IOPORT
252 fprintf(stderr, "inl: port=0x%04x\n", address);
257 void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
259 #ifdef DEBUG_UNUSED_IOPORT
260 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
264 void init_ioports(void)
268 for(i = 0; i < MAX_IOPORTS; i++) {
269 ioport_read_table[0][i] = default_ioport_readb;
270 ioport_write_table[0][i] = default_ioport_writeb;
271 ioport_read_table[1][i] = default_ioport_readw;
272 ioport_write_table[1][i] = default_ioport_writew;
273 ioport_read_table[2][i] = default_ioport_readl;
274 ioport_write_table[2][i] = default_ioport_writel;
278 /* size is the word size in byte */
279 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
291 for(i = start; i < start + length; i += size)
292 ioport_read_table[bsize][i] = func;
296 /* size is the word size in byte */
297 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
309 for(i = start; i < start + length; i += size)
310 ioport_write_table[bsize][i] = func;
314 void pstrcpy(char *buf, int buf_size, const char *str)
324 if (c == 0 || q >= buf + buf_size - 1)
331 /* strcat and truncate. */
332 char *pstrcat(char *buf, int buf_size, const char *s)
337 pstrcpy(buf + len, buf_size - len, s);
341 int load_kernel(const char *filename, uint8_t *addr)
343 int fd, size, setup_sects;
344 uint8_t bootsect[512];
346 fd = open(filename, O_RDONLY);
349 if (read(fd, bootsect, 512) != 512)
351 setup_sects = bootsect[0x1F1];
354 /* skip 16 bit setup code */
355 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
356 size = read(fd, addr, 16 * 1024 * 1024);
366 /* return the size or -1 if error */
367 int load_image(const char *filename, uint8_t *addr)
370 fd = open(filename, O_RDONLY);
373 size = lseek(fd, 0, SEEK_END);
374 lseek(fd, 0, SEEK_SET);
375 if (read(fd, addr, size) != size) {
383 void cpu_x86_outb(CPUX86State *env, int addr, int val)
385 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
388 void cpu_x86_outw(CPUX86State *env, int addr, int val)
390 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
393 void cpu_x86_outl(CPUX86State *env, int addr, int val)
395 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
398 int cpu_x86_inb(CPUX86State *env, int addr)
400 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
403 int cpu_x86_inw(CPUX86State *env, int addr)
405 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
408 int cpu_x86_inl(CPUX86State *env, int addr)
410 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
413 /***********************************************************/
414 void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
418 void hw_error(const char *fmt, ...)
423 fprintf(stderr, "qemu: hardware error: ");
424 vfprintf(stderr, fmt, ap);
425 fprintf(stderr, "\n");
427 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
433 /***********************************************************/
436 #define RTC_SECONDS 0
437 #define RTC_SECONDS_ALARM 1
438 #define RTC_MINUTES 2
439 #define RTC_MINUTES_ALARM 3
441 #define RTC_HOURS_ALARM 5
442 #define RTC_ALARM_DONT_CARE 0xC0
444 #define RTC_DAY_OF_WEEK 6
445 #define RTC_DAY_OF_MONTH 7
454 /* PC cmos mappings */
455 #define REG_EQUIPMENT_BYTE 0x14
457 uint8_t cmos_data[128];
460 void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
463 cmos_index = data & 0x7f;
467 uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
474 /* toggle update-in-progress bit for Linux (same hack as
476 ret = cmos_data[cmos_index];
477 if (cmos_index == RTC_REG_A)
478 cmos_data[RTC_REG_A] ^= 0x80;
479 else if (cmos_index == RTC_REG_C)
480 cmos_data[RTC_REG_C] = 0x00;
486 static inline int to_bcd(int a)
488 return ((a / 10) << 4) | (a % 10);
499 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
500 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
501 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
502 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
503 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
504 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
505 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
507 cmos_data[RTC_REG_A] = 0x26;
508 cmos_data[RTC_REG_B] = 0x02;
509 cmos_data[RTC_REG_C] = 0x00;
510 cmos_data[RTC_REG_D] = 0x80;
512 /* various important CMOS locations needed by PC/Bochs bios */
514 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
515 cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
518 val = (phys_ram_size / 1024) - 1024;
521 cmos_data[0x17] = val;
522 cmos_data[0x18] = val >> 8;
523 cmos_data[0x30] = val;
524 cmos_data[0x31] = val >> 8;
526 val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
529 cmos_data[0x34] = val;
530 cmos_data[0x35] = val >> 8;
532 switch(boot_device) {
534 cmos_data[0x3d] = 0x01; /* floppy boot */
538 cmos_data[0x3d] = 0x02; /* hard drive boot */
541 cmos_data[0x3d] = 0x03; /* CD-ROM boot */
545 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
546 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
549 /***********************************************************/
550 /* 8259 pic emulation */
552 typedef struct PicState {
553 uint8_t last_irr; /* edge detection */
554 uint8_t irr; /* interrupt request register */
555 uint8_t imr; /* interrupt mask register */
556 uint8_t isr; /* interrupt service register */
557 uint8_t priority_add; /* used to compute irq priority */
559 uint8_t read_reg_select;
560 uint8_t special_mask;
563 uint8_t rotate_on_autoeoi;
564 uint8_t init4; /* true if 4 byte init */
567 /* 0 is master pic, 1 is slave pic */
569 int pic_irq_requested;
571 /* set irq level. If an edge is detected, then the IRR is set to 1 */
572 static inline void pic_set_irq1(PicState *s, int irq, int level)
577 if ((s->last_irr & mask) == 0)
581 s->last_irr &= ~mask;
585 static inline int get_priority(PicState *s, int mask)
591 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
596 /* return the pic wanted interrupt. return -1 if none */
597 static int pic_get_irq(PicState *s)
599 int mask, cur_priority, priority;
601 mask = s->irr & ~s->imr;
602 priority = get_priority(s, mask);
605 /* compute current priority */
606 cur_priority = get_priority(s, s->isr);
607 if (priority > cur_priority) {
608 /* higher priority found: an irq should be generated */
615 /* raise irq to CPU if necessary. must be called every time the active
617 static void pic_update_irq(void)
621 /* first look at slave pic */
622 irq2 = pic_get_irq(&pics[1]);
624 /* if irq request by slave pic, signal master PIC */
625 pic_set_irq1(&pics[0], 2, 1);
626 pic_set_irq1(&pics[0], 2, 0);
628 /* look at requested irq */
629 irq = pic_get_irq(&pics[0]);
633 pic_irq_requested = 8 + irq2;
635 /* from master pic */
636 pic_irq_requested = irq;
638 cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD);
642 #ifdef DEBUG_IRQ_LATENCY
643 int64_t irq_time[16];
644 int64_t cpu_get_ticks(void);
646 #if defined(DEBUG_PIC)
650 void pic_set_irq(int irq, int level)
652 #if defined(DEBUG_PIC)
653 if (level != irq_level[irq]) {
654 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
655 irq_level[irq] = level;
658 #ifdef DEBUG_IRQ_LATENCY
660 irq_time[irq] = cpu_get_ticks();
663 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
667 int cpu_x86_get_pic_interrupt(CPUX86State *env)
669 int irq, irq2, intno;
671 /* signal the pic that the irq was acked by the CPU */
672 irq = pic_irq_requested;
673 #ifdef DEBUG_IRQ_LATENCY
674 printf("IRQ%d latency=%0.3fus\n",
676 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
679 printf("pic_interrupt: irq=%d\n", irq);
684 pics[1].isr |= (1 << irq2);
685 pics[1].irr &= ~(1 << irq2);
687 intno = pics[1].irq_base + irq2;
689 intno = pics[0].irq_base + irq;
691 pics[0].isr |= (1 << irq);
692 pics[0].irr &= ~(1 << irq);
696 void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
702 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
704 s = &pics[addr >> 7];
709 memset(s, 0, sizeof(PicState));
713 hw_error("single mode not supported");
715 hw_error("level sensitive irq not supported");
716 } else if (val & 0x08) {
718 s->read_reg_select = val & 1;
720 s->special_mask = (val >> 5) & 1;
725 s->rotate_on_autoeoi = val >> 7;
727 case 0x20: /* end of interrupt */
729 priority = get_priority(s, s->isr);
731 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
734 s->priority_add = (s->priority_add + 1) & 7;
739 s->isr &= ~(1 << priority);
743 s->priority_add = (val + 1) & 7;
748 s->isr &= ~(1 << priority);
749 s->priority_add = (priority + 1) & 7;
755 switch(s->init_state) {
762 s->irq_base = val & 0xf8;
773 s->auto_eoi = (val >> 1) & 1;
780 uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1)
787 s = &pics[addr >> 7];
790 if (s->read_reg_select)
798 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
805 register_ioport_write(0x20, 2, pic_ioport_write, 1);
806 register_ioport_read(0x20, 2, pic_ioport_read, 1);
807 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
808 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
811 /***********************************************************/
812 /* 8253 PIT emulation */
814 #define PIT_FREQ 1193182
816 #define RW_STATE_LSB 0
817 #define RW_STATE_MSB 1
818 #define RW_STATE_WORD0 2
819 #define RW_STATE_WORD1 3
820 #define RW_STATE_LATCHED_WORD0 4
821 #define RW_STATE_LATCHED_WORD1 5
823 typedef struct PITChannelState {
824 int count; /* can be 65536 */
825 uint16_t latched_count;
828 uint8_t bcd; /* not supported */
829 uint8_t gate; /* timer start */
830 int64_t count_load_time;
831 int64_t count_last_edge_check_time;
834 PITChannelState pit_channels[3];
836 int dummy_refresh_clock;
837 int pit_min_timer_count = 0;
840 #if defined(__powerpc__)
842 static inline uint32_t get_tbl(void)
845 asm volatile("mftb %0" : "=r" (tbl));
849 static inline uint32_t get_tbu(void)
852 asm volatile("mftbu %0" : "=r" (tbl));
856 int64_t cpu_get_real_ticks(void)
859 /* NOTE: we test if wrapping has occurred */
865 return ((int64_t)h << 32) | l;
868 #elif defined(__i386__)
870 int64_t cpu_get_real_ticks(void)
873 asm("rdtsc" : "=A" (val));
878 #error unsupported CPU
881 static int64_t cpu_ticks_offset;
882 static int64_t cpu_ticks_last;
884 int64_t cpu_get_ticks(void)
886 return cpu_get_real_ticks() + cpu_ticks_offset;
889 /* enable cpu_get_ticks() */
890 void cpu_enable_ticks(void)
892 cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks();
895 /* disable cpu_get_ticks() : the clock is stopped. You must not call
896 cpu_get_ticks() after that. */
897 void cpu_disable_ticks(void)
899 cpu_ticks_last = cpu_get_ticks();
902 int64_t get_clock(void)
905 gettimeofday(&tv, NULL);
906 return tv.tv_sec * 1000000LL + tv.tv_usec;
909 void cpu_calibrate_ticks(void)
914 ticks = cpu_get_ticks();
916 usec = get_clock() - usec;
917 ticks = cpu_get_ticks() - ticks;
918 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
921 /* compute with 96 bit intermediate result: (a*b)/c */
922 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
927 #ifdef WORDS_BIGENDIAN
937 rl = (uint64_t)u.l.low * (uint64_t)b;
938 rh = (uint64_t)u.l.high * (uint64_t)b;
941 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
945 static int pit_get_count(PITChannelState *s)
950 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
956 counter = (s->count - d) & 0xffff;
959 counter = s->count - (d % s->count);
965 /* get pit output bit */
966 static int pit_get_out(PITChannelState *s)
971 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
975 out = (d >= s->count);
978 out = (d < s->count);
981 if ((d % s->count) == 0 && d != 0)
987 out = (d % s->count) < (s->count >> 1);
991 out = (d == s->count);
997 /* get the number of 0 to 1 transitions we had since we call this
999 /* XXX: maybe better to use ticks precision to avoid getting edges
1000 twice if checks are done at very small intervals */
1001 static int pit_get_out_edges(PITChannelState *s)
1007 ticks = cpu_get_ticks();
1008 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
1009 PIT_FREQ, ticks_per_sec);
1010 d2 = muldiv64(ticks - s->count_load_time,
1011 PIT_FREQ, ticks_per_sec);
1012 s->count_last_edge_check_time = ticks;
1016 if (d1 < s->count && d2 >= s->count)
1030 v = s->count - (s->count >> 1);
1031 d1 = (d1 + v) / s->count;
1032 d2 = (d2 + v) / s->count;
1037 if (d1 < s->count && d2 >= s->count)
1046 static inline void pit_load_count(PITChannelState *s, int val)
1050 s->count_load_time = cpu_get_ticks();
1051 s->count_last_edge_check_time = s->count_load_time;
1053 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
1055 "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
1056 PIT_FREQ / pit_min_timer_count);
1060 void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1062 int channel, access;
1070 s = &pit_channels[channel];
1071 access = (val >> 4) & 3;
1074 s->latched_count = pit_get_count(s);
1075 s->rw_state = RW_STATE_LATCHED_WORD0;
1078 s->mode = (val >> 1) & 7;
1080 s->rw_state = access - 1 + RW_STATE_LSB;
1084 s = &pit_channels[addr];
1085 switch(s->rw_state) {
1087 pit_load_count(s, val);
1090 pit_load_count(s, val << 8);
1092 case RW_STATE_WORD0:
1093 case RW_STATE_WORD1:
1094 if (s->rw_state & 1) {
1095 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
1097 s->latched_count = val;
1105 uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
1111 s = &pit_channels[addr];
1112 switch(s->rw_state) {
1115 case RW_STATE_WORD0:
1116 case RW_STATE_WORD1:
1117 count = pit_get_count(s);
1118 if (s->rw_state & 1)
1119 ret = (count >> 8) & 0xff;
1122 if (s->rw_state & 2)
1126 case RW_STATE_LATCHED_WORD0:
1127 case RW_STATE_LATCHED_WORD1:
1128 if (s->rw_state & 1)
1129 ret = s->latched_count >> 8;
1131 ret = s->latched_count & 0xff;
1138 void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1140 speaker_data_on = (val >> 1) & 1;
1141 pit_channels[2].gate = val & 1;
1144 uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
1147 out = pit_get_out(&pit_channels[2]);
1148 dummy_refresh_clock ^= 1;
1149 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
1150 (dummy_refresh_clock << 4);
1158 cpu_calibrate_ticks();
1160 for(i = 0;i < 3; i++) {
1161 s = &pit_channels[i];
1164 pit_load_count(s, 0);
1167 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1168 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1170 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1171 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1174 /***********************************************************/
1175 /* serial port emulation */
1179 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1181 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1182 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1183 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1184 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1186 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1187 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1189 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1190 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1191 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1192 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1194 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1195 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1196 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1197 #define UART_LSR_FE 0x08 /* Frame error indicator */
1198 #define UART_LSR_PE 0x04 /* Parity error indicator */
1199 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1200 #define UART_LSR_DR 0x01 /* Receiver data ready */
1202 typedef struct SerialState {
1204 uint8_t rbr; /* receive register */
1206 uint8_t iir; /* read only */
1209 uint8_t lsr; /* read only */
1214 SerialState serial_ports[1];
1216 void serial_update_irq(void)
1218 SerialState *s = &serial_ports[0];
1220 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1221 s->iir = UART_IIR_RDI;
1222 } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
1223 s->iir = UART_IIR_THRI;
1225 s->iir = UART_IIR_NO_INT;
1227 if (s->iir != UART_IIR_NO_INT) {
1228 pic_set_irq(UART_IRQ, 1);
1230 pic_set_irq(UART_IRQ, 0);
1234 void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1236 SerialState *s = &serial_ports[0];
1244 if (s->lcr & UART_LCR_DLAB) {
1245 s->divider = (s->divider & 0xff00) | val;
1247 s->lsr &= ~UART_LSR_THRE;
1248 serial_update_irq();
1252 ret = write(1, &ch, 1);
1254 s->lsr |= UART_LSR_THRE;
1255 s->lsr |= UART_LSR_TEMT;
1256 serial_update_irq();
1260 if (s->lcr & UART_LCR_DLAB) {
1261 s->divider = (s->divider & 0x00ff) | (val << 8);
1264 serial_update_irq();
1286 uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1288 SerialState *s = &serial_ports[0];
1295 if (s->lcr & UART_LCR_DLAB) {
1296 ret = s->divider & 0xff;
1299 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1300 serial_update_irq();
1304 if (s->lcr & UART_LCR_DLAB) {
1305 ret = (s->divider >> 8) & 0xff;
1332 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1333 static int term_got_escape;
1335 void term_print_help(void)
1338 "C-a h print this help\n"
1339 "C-a x exit emulatior\n"
1340 "C-a s save disk data back to file (if -snapshot)\n"
1341 "C-a b send break (magic sysrq)\n"
1342 "C-a C-a send C-a\n"
1346 /* called when a char is received */
1347 void serial_received_byte(SerialState *s, int ch)
1349 if (term_got_escape) {
1350 term_got_escape = 0;
1361 for (i = 0; i < MAX_DISKS; i++) {
1363 bdrv_commit(bs_table[i]);
1370 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1371 serial_update_irq();
1376 } else if (ch == TERM_ESCAPE) {
1377 term_got_escape = 1;
1381 s->lsr |= UART_LSR_DR;
1382 serial_update_irq();
1386 void serial_init(void)
1388 SerialState *s = &serial_ports[0];
1390 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1392 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1393 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1396 /***********************************************************/
1397 /* ne2000 emulation */
1399 #define NE2000_IOPORT 0x300
1400 #define NE2000_IRQ 9
1402 #define MAX_ETH_FRAME_SIZE 1514
1404 #define E8390_CMD 0x00 /* The command register (for all pages) */
1405 /* Page 0 register offsets. */
1406 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1407 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1408 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1409 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1410 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1411 #define EN0_TSR 0x04 /* Transmit status reg RD */
1412 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1413 #define EN0_NCR 0x05 /* Number of collision reg RD */
1414 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1415 #define EN0_FIFO 0x06 /* FIFO RD */
1416 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1417 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1418 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1419 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1420 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1421 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1422 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1423 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1424 #define EN0_RSR 0x0c /* rx status reg RD */
1425 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1426 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1427 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1428 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1429 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1430 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1431 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1433 #define EN1_PHYS 0x11
1434 #define EN1_CURPAG 0x17
1435 #define EN1_MULT 0x18
1437 /* Register accessed at EN_CMD, the 8390 base addr. */
1438 #define E8390_STOP 0x01 /* Stop and reset the chip */
1439 #define E8390_START 0x02 /* Start the chip, clear reset */
1440 #define E8390_TRANS 0x04 /* Transmit a frame */
1441 #define E8390_RREAD 0x08 /* Remote read */
1442 #define E8390_RWRITE 0x10 /* Remote write */
1443 #define E8390_NODMA 0x20 /* Remote DMA */
1444 #define E8390_PAGE0 0x00 /* Select page chip registers */
1445 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1446 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1448 /* Bits in EN0_ISR - Interrupt status register */
1449 #define ENISR_RX 0x01 /* Receiver, no error */
1450 #define ENISR_TX 0x02 /* Transmitter, no error */
1451 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1452 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1453 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1454 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1455 #define ENISR_RDC 0x40 /* remote dma complete */
1456 #define ENISR_RESET 0x80 /* Reset completed */
1457 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1459 /* Bits in received packet status byte and EN0_RSR*/
1460 #define ENRSR_RXOK 0x01 /* Received a good packet */
1461 #define ENRSR_CRC 0x02 /* CRC error */
1462 #define ENRSR_FAE 0x04 /* frame alignment error */
1463 #define ENRSR_FO 0x08 /* FIFO overrun */
1464 #define ENRSR_MPA 0x10 /* missed pkt */
1465 #define ENRSR_PHY 0x20 /* physical/multicast address */
1466 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1467 #define ENRSR_DEF 0x80 /* deferring */
1469 /* Transmitted packet status, EN0_TSR. */
1470 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1471 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1472 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1473 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1474 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1475 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1476 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1477 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1479 #define NE2000_MEM_SIZE 32768
1481 typedef struct NE2000State {
1494 uint8_t phys[6]; /* mac address */
1496 uint8_t mult[8]; /* multicast mask array */
1497 uint8_t mem[NE2000_MEM_SIZE];
1500 NE2000State ne2000_state;
1502 char network_script[1024];
1504 void ne2000_reset(void)
1506 NE2000State *s = &ne2000_state;
1509 s->isr = ENISR_RESET;
1519 /* duplicate prom data */
1520 for(i = 15;i >= 0; i--) {
1521 s->mem[2 * i] = s->mem[i];
1522 s->mem[2 * i + 1] = s->mem[i];
1526 void ne2000_update_irq(NE2000State *s)
1529 isr = s->isr & s->imr;
1531 pic_set_irq(NE2000_IRQ, 1);
1533 pic_set_irq(NE2000_IRQ, 0);
1539 int fd, ret, pid, status;
1541 fd = open("/dev/net/tun", O_RDWR);
1543 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1546 memset(&ifr, 0, sizeof(ifr));
1547 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1548 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1549 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1551 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1555 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1556 fcntl(fd, F_SETFL, O_NONBLOCK);
1559 /* try to launch network init script */
1563 execl(network_script, network_script, ifr.ifr_name, NULL);
1566 while (waitpid(pid, &status, 0) != pid);
1567 if (!WIFEXITED(status) ||
1568 WEXITSTATUS(status) != 0) {
1569 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1570 network_script, ifr.ifr_name);
1576 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1579 printf("NE2000: sending packet size=%d\n", size);
1581 write(net_fd, buf, size);
1584 /* return true if the NE2000 can receive more data */
1585 int ne2000_can_receive(NE2000State *s)
1587 int avail, index, boundary;
1589 if (s->cmd & E8390_STOP)
1591 index = s->curpag << 8;
1592 boundary = s->boundary << 8;
1593 if (index < boundary)
1594 avail = boundary - index;
1596 avail = (s->stop - s->start) - (index - boundary);
1597 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1602 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1605 int total_len, next, avail, len, index;
1607 #if defined(DEBUG_NE2000)
1608 printf("NE2000: received len=%d\n", size);
1611 index = s->curpag << 8;
1612 /* 4 bytes for header */
1613 total_len = size + 4;
1614 /* address for next packet (4 bytes for CRC) */
1615 next = index + ((total_len + 4 + 255) & ~0xff);
1616 if (next >= s->stop)
1617 next -= (s->stop - s->start);
1618 /* prepare packet header */
1620 p[0] = ENRSR_RXOK; /* receive status */
1623 p[3] = total_len >> 8;
1626 /* write packet data */
1628 avail = s->stop - index;
1632 memcpy(s->mem + index, buf, len);
1635 if (index == s->stop)
1639 s->curpag = next >> 8;
1641 /* now we can signal we have receive something */
1643 ne2000_update_irq(s);
1646 void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1648 NE2000State *s = &ne2000_state;
1653 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
1655 if (addr == E8390_CMD) {
1656 /* control register */
1658 if (val & E8390_START) {
1659 /* test specific case: zero length transfert */
1660 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
1662 s->isr |= ENISR_RDC;
1663 ne2000_update_irq(s);
1665 if (val & E8390_TRANS) {
1666 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
1667 /* signal end of transfert */
1670 ne2000_update_irq(s);
1675 offset = addr | (page << 4);
1678 s->start = val << 8;
1688 ne2000_update_irq(s);
1694 s->tcnt = (s->tcnt & 0xff00) | val;
1697 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
1700 s->rsar = (s->rsar & 0xff00) | val;
1703 s->rsar = (s->rsar & 0x00ff) | (val << 8);
1706 s->rcnt = (s->rcnt & 0xff00) | val;
1709 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
1716 ne2000_update_irq(s);
1718 case EN1_PHYS ... EN1_PHYS + 5:
1719 s->phys[offset - EN1_PHYS] = val;
1724 case EN1_MULT ... EN1_MULT + 7:
1725 s->mult[offset - EN1_MULT] = val;
1731 uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr)
1733 NE2000State *s = &ne2000_state;
1734 int offset, page, ret;
1737 if (addr == E8390_CMD) {
1741 offset = addr | (page << 4);
1752 case EN1_PHYS ... EN1_PHYS + 5:
1753 ret = s->phys[offset - EN1_PHYS];
1758 case EN1_MULT ... EN1_MULT + 7:
1759 ret = s->mult[offset - EN1_MULT];
1767 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
1772 void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1774 NE2000State *s = &ne2000_state;
1778 printf("NE2000: asic write val=0x%04x\n", val);
1780 p = s->mem + s->rsar;
1781 if (s->dcfg & 0x01) {
1794 if (s->rsar == s->stop)
1797 /* signal end of transfert */
1798 s->isr |= ENISR_RDC;
1799 ne2000_update_irq(s);
1803 uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr)
1805 NE2000State *s = &ne2000_state;
1809 p = s->mem + s->rsar;
1810 if (s->dcfg & 0x01) {
1812 ret = p[0] | (p[1] << 8);
1822 if (s->rsar == s->stop)
1825 /* signal end of transfert */
1826 s->isr |= ENISR_RDC;
1827 ne2000_update_irq(s);
1830 printf("NE2000: asic read val=0x%04x\n", ret);
1835 void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1837 /* nothing to do (end of reset pulse) */
1840 uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr)
1846 void ne2000_init(void)
1848 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
1849 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
1851 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
1852 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
1853 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
1854 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
1856 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
1857 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
1861 /***********************************************************/
1862 /* keyboard emulation */
1864 /* Keyboard Controller Commands */
1865 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
1866 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
1867 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
1868 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
1869 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
1870 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
1871 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
1872 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
1873 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
1874 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
1875 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
1876 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
1877 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
1878 #define KBD_CCMD_WRITE_OBUF 0xD2
1879 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
1880 initiated by the auxiliary device */
1881 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
1882 #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
1883 #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
1884 #define KBD_CCMD_RESET 0xFE
1886 /* Keyboard Commands */
1887 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
1888 #define KBD_CMD_ECHO 0xEE
1889 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
1890 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
1891 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
1892 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
1893 #define KBD_CMD_RESET 0xFF /* Reset */
1895 /* Keyboard Replies */
1896 #define KBD_REPLY_POR 0xAA /* Power on reset */
1897 #define KBD_REPLY_ACK 0xFA /* Command ACK */
1898 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
1900 /* Status Register Bits */
1901 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
1902 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
1903 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
1904 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
1905 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
1906 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
1907 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
1908 #define KBD_STAT_PERR 0x80 /* Parity error */
1910 /* Controller Mode Register Bits */
1911 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
1912 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
1913 #define KBD_MODE_SYS 0x04 /* The system flag (?) */
1914 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
1915 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
1916 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
1917 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
1918 #define KBD_MODE_RFU 0x80
1920 /* Mouse Commands */
1921 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
1922 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
1923 #define AUX_SET_RES 0xE8 /* Set resolution */
1924 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
1925 #define AUX_SET_STREAM 0xEA /* Set stream mode */
1926 #define AUX_POLL 0xEB /* Poll */
1927 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
1928 #define AUX_SET_WRAP 0xEE /* Set wrap mode */
1929 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
1930 #define AUX_GET_TYPE 0xF2 /* Get type */
1931 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
1932 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
1933 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
1934 #define AUX_SET_DEFAULT 0xF6
1935 #define AUX_RESET 0xFF /* Reset aux device */
1936 #define AUX_ACK 0xFA /* Command byte ACK. */
1938 #define MOUSE_STATUS_REMOTE 0x40
1939 #define MOUSE_STATUS_ENABLED 0x20
1940 #define MOUSE_STATUS_SCALE21 0x10
1942 #define KBD_QUEUE_SIZE 256
1945 uint8_t data[KBD_QUEUE_SIZE];
1946 int rptr, wptr, count;
1949 typedef struct KBDState {
1951 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
1954 /* keyboard state */
1958 int mouse_write_cmd;
1959 uint8_t mouse_status;
1960 uint8_t mouse_resolution;
1961 uint8_t mouse_sample_rate;
1963 uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
1964 uint8_t mouse_detect_state;
1965 int mouse_dx; /* current values, needed for 'poll' mode */
1968 uint8_t mouse_buttons;
1972 int reset_requested;
1974 /* update irq and KBD_STAT_[MOUSE_]OBF */
1975 static void kbd_update_irq(KBDState *s)
1977 int irq12_level, irq1_level;
1981 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
1982 if (s->queues[0].count != 0 ||
1983 s->queues[1].count != 0) {
1984 s->status |= KBD_STAT_OBF;
1985 if (s->queues[1].count != 0) {
1986 s->status |= KBD_STAT_MOUSE_OBF;
1987 if (s->mode & KBD_MODE_MOUSE_INT)
1990 if (s->mode & KBD_MODE_KBD_INT)
1994 pic_set_irq(1, irq1_level);
1995 pic_set_irq(12, irq12_level);
1998 static void kbd_queue(KBDState *s, int b, int aux)
2000 KBDQueue *q = &kbd_state.queues[aux];
2002 #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
2004 printf("mouse event: 0x%02x\n", b);
2007 printf("kbd event: 0x%02x\n", b);
2010 if (q->count >= KBD_QUEUE_SIZE)
2012 q->data[q->wptr] = b;
2013 if (++q->wptr == KBD_QUEUE_SIZE)
2019 void kbd_put_keycode(int keycode)
2021 KBDState *s = &kbd_state;
2022 kbd_queue(s, keycode, 0);
2025 uint32_t kbd_read_status(CPUX86State *env, uint32_t addr)
2027 KBDState *s = &kbd_state;
2030 #if defined(DEBUG_KBD) && 0
2031 printf("kbd: read status=0x%02x\n", val);
2036 void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
2038 KBDState *s = &kbd_state;
2041 printf("kbd: write cmd=0x%02x\n", val);
2044 case KBD_CCMD_READ_MODE:
2045 kbd_queue(s, s->mode, 0);
2047 case KBD_CCMD_WRITE_MODE:
2048 case KBD_CCMD_WRITE_OBUF:
2049 case KBD_CCMD_WRITE_AUX_OBUF:
2050 case KBD_CCMD_WRITE_MOUSE:
2051 case KBD_CCMD_WRITE_OUTPORT:
2054 case KBD_CCMD_MOUSE_DISABLE:
2055 s->mode |= KBD_MODE_DISABLE_MOUSE;
2057 case KBD_CCMD_MOUSE_ENABLE:
2058 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
2060 case KBD_CCMD_TEST_MOUSE:
2061 kbd_queue(s, 0x00, 0);
2063 case KBD_CCMD_SELF_TEST:
2064 s->status |= KBD_STAT_SELFTEST;
2065 kbd_queue(s, 0x55, 0);
2067 case KBD_CCMD_KBD_TEST:
2068 kbd_queue(s, 0x00, 0);
2070 case KBD_CCMD_KBD_DISABLE:
2071 s->mode |= KBD_MODE_DISABLE_KBD;
2073 case KBD_CCMD_KBD_ENABLE:
2074 s->mode &= ~KBD_MODE_DISABLE_KBD;
2076 case KBD_CCMD_READ_INPORT:
2077 kbd_queue(s, 0x00, 0);
2079 case KBD_CCMD_READ_OUTPORT:
2080 /* XXX: check that */
2081 val = 0x01 | (a20_enabled << 1);
2082 if (s->status & KBD_STAT_OBF)
2084 if (s->status & KBD_STAT_MOUSE_OBF)
2086 kbd_queue(s, val, 0);
2088 case KBD_CCMD_ENABLE_A20:
2089 cpu_x86_set_a20(env, 1);
2091 case KBD_CCMD_DISABLE_A20:
2092 cpu_x86_set_a20(env, 0);
2094 case KBD_CCMD_RESET:
2095 reset_requested = 1;
2096 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2099 fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
2104 uint32_t kbd_read_data(CPUX86State *env, uint32_t addr)
2106 KBDState *s = &kbd_state;
2110 q = &s->queues[0]; /* first check KBD data */
2112 q = &s->queues[1]; /* then check AUX data */
2113 if (q->count == 0) {
2114 /* XXX: return something else ? */
2117 val = q->data[q->rptr];
2118 if (++q->rptr == KBD_QUEUE_SIZE)
2121 /* reading deasserts IRQ */
2122 if (q == &s->queues[0])
2127 /* reassert IRQs if data left */
2130 printf("kbd: read data=0x%02x\n", val);
2135 static void kbd_reset_keyboard(KBDState *s)
2137 s->scan_enabled = 1;
2140 static void kbd_write_keyboard(KBDState *s, int val)
2142 switch(s->kbd_write_cmd) {
2147 kbd_queue(s, KBD_REPLY_ACK, 0);
2150 kbd_queue(s, KBD_REPLY_RESEND, 0);
2153 kbd_queue(s, KBD_CMD_ECHO, 0);
2155 case KBD_CMD_ENABLE:
2156 s->scan_enabled = 1;
2157 kbd_queue(s, KBD_REPLY_ACK, 0);
2159 case KBD_CMD_SET_LEDS:
2160 case KBD_CMD_SET_RATE:
2161 s->kbd_write_cmd = val;
2162 kbd_queue(s, KBD_REPLY_ACK, 0);
2164 case KBD_CMD_RESET_DISABLE:
2165 kbd_reset_keyboard(s);
2166 s->scan_enabled = 0;
2167 kbd_queue(s, KBD_REPLY_ACK, 0);
2169 case KBD_CMD_RESET_ENABLE:
2170 kbd_reset_keyboard(s);
2171 s->scan_enabled = 1;
2172 kbd_queue(s, KBD_REPLY_ACK, 0);
2175 kbd_reset_keyboard(s);
2176 kbd_queue(s, KBD_REPLY_ACK, 0);
2177 kbd_queue(s, KBD_REPLY_POR, 0);
2180 kbd_queue(s, KBD_REPLY_ACK, 0);
2184 case KBD_CMD_SET_LEDS:
2185 kbd_queue(s, KBD_REPLY_ACK, 0);
2186 s->kbd_write_cmd = -1;
2188 case KBD_CMD_SET_RATE:
2189 kbd_queue(s, KBD_REPLY_ACK, 0);
2190 s->kbd_write_cmd = -1;
2195 static void kbd_mouse_send_packet(KBDState *s)
2203 /* XXX: increase range to 8 bits ? */
2206 else if (dx1 < -127)
2210 else if (dy1 < -127)
2212 b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
2214 kbd_queue(s, dx1 & 0xff, 1);
2215 kbd_queue(s, dy1 & 0xff, 1);
2216 /* extra byte for IMPS/2 or IMEX */
2217 switch(s->mouse_type) {
2223 else if (dz1 < -127)
2225 kbd_queue(s, dz1 & 0xff, 1);
2232 b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
2243 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
2245 KBDState *s = &kbd_state;
2247 /* check if deltas are recorded when disabled */
2248 if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
2254 s->mouse_buttons = buttons_state;
2256 if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
2257 (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) {
2259 /* if not remote, send event. Multiple events are sent if
2261 kbd_mouse_send_packet(s);
2262 if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0)
2268 static void kbd_write_mouse(KBDState *s, int val)
2271 printf("kbd: write mouse 0x%02x\n", val);
2273 switch(s->mouse_write_cmd) {
2277 if (s->mouse_wrap) {
2278 if (val == AUX_RESET_WRAP) {
2280 kbd_queue(s, AUX_ACK, 1);
2282 } else if (val != AUX_RESET) {
2283 kbd_queue(s, val, 1);
2288 case AUX_SET_SCALE11:
2289 s->mouse_status &= ~MOUSE_STATUS_SCALE21;
2290 kbd_queue(s, AUX_ACK, 1);
2292 case AUX_SET_SCALE21:
2293 s->mouse_status |= MOUSE_STATUS_SCALE21;
2294 kbd_queue(s, AUX_ACK, 1);
2296 case AUX_SET_STREAM:
2297 s->mouse_status &= ~MOUSE_STATUS_REMOTE;
2298 kbd_queue(s, AUX_ACK, 1);
2302 kbd_queue(s, AUX_ACK, 1);
2304 case AUX_SET_REMOTE:
2305 s->mouse_status |= MOUSE_STATUS_REMOTE;
2306 kbd_queue(s, AUX_ACK, 1);
2309 kbd_queue(s, AUX_ACK, 1);
2310 kbd_queue(s, s->mouse_type, 1);
2313 case AUX_SET_SAMPLE:
2314 s->mouse_write_cmd = val;
2315 kbd_queue(s, AUX_ACK, 1);
2318 kbd_queue(s, AUX_ACK, 1);
2319 kbd_queue(s, s->mouse_status, 1);
2320 kbd_queue(s, s->mouse_resolution, 1);
2321 kbd_queue(s, s->mouse_sample_rate, 1);
2324 kbd_queue(s, AUX_ACK, 1);
2325 kbd_mouse_send_packet(s);
2327 case AUX_ENABLE_DEV:
2328 s->mouse_status |= MOUSE_STATUS_ENABLED;
2329 kbd_queue(s, AUX_ACK, 1);
2331 case AUX_DISABLE_DEV:
2332 s->mouse_status &= ~MOUSE_STATUS_ENABLED;
2333 kbd_queue(s, AUX_ACK, 1);
2335 case AUX_SET_DEFAULT:
2336 s->mouse_sample_rate = 100;
2337 s->mouse_resolution = 2;
2338 s->mouse_status = 0;
2339 kbd_queue(s, AUX_ACK, 1);
2342 s->mouse_sample_rate = 100;
2343 s->mouse_resolution = 2;
2344 s->mouse_status = 0;
2345 kbd_queue(s, AUX_ACK, 1);
2346 kbd_queue(s, 0xaa, 1);
2347 kbd_queue(s, s->mouse_type, 1);
2353 case AUX_SET_SAMPLE:
2354 s->mouse_sample_rate = val;
2356 /* detect IMPS/2 or IMEX */
2357 switch(s->mouse_detect_state) {
2361 s->mouse_detect_state = 1;
2365 s->mouse_detect_state = 2;
2366 else if (val == 200)
2367 s->mouse_detect_state = 3;
2369 s->mouse_detect_state = 0;
2373 s->mouse_type = 3; /* IMPS/2 */
2374 s->mouse_detect_state = 0;
2378 s->mouse_type = 4; /* IMEX */
2379 s->mouse_detect_state = 0;
2383 kbd_queue(s, AUX_ACK, 1);
2384 s->mouse_write_cmd = -1;
2387 s->mouse_resolution = val;
2388 kbd_queue(s, AUX_ACK, 1);
2389 s->mouse_write_cmd = -1;
2394 void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val)
2396 KBDState *s = &kbd_state;
2399 printf("kbd: write data=0x%02x\n", val);
2402 switch(s->write_cmd) {
2404 kbd_write_keyboard(s, val);
2406 case KBD_CCMD_WRITE_MODE:
2410 case KBD_CCMD_WRITE_OBUF:
2411 kbd_queue(s, val, 0);
2413 case KBD_CCMD_WRITE_AUX_OBUF:
2414 kbd_queue(s, val, 1);
2416 case KBD_CCMD_WRITE_OUTPORT:
2417 cpu_x86_set_a20(env, (val >> 1) & 1);
2419 reset_requested = 1;
2420 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2423 case KBD_CCMD_WRITE_MOUSE:
2424 kbd_write_mouse(s, val);
2432 void kbd_reset(KBDState *s)
2437 s->kbd_write_cmd = -1;
2438 s->mouse_write_cmd = -1;
2439 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
2440 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
2441 for(i = 0; i < 2; i++) {
2451 kbd_reset(&kbd_state);
2452 register_ioport_read(0x60, 1, kbd_read_data, 1);
2453 register_ioport_write(0x60, 1, kbd_write_data, 1);
2454 register_ioport_read(0x64, 1, kbd_read_status, 1);
2455 register_ioport_write(0x64, 1, kbd_write_command, 1);
2458 /***********************************************************/
2459 /* Bochs BIOS debug ports */
2461 void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
2464 /* Bochs BIOS messages */
2467 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
2472 fprintf(stderr, "%c", val);
2476 /* LGPL'ed VGA BIOS messages */
2479 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
2484 fprintf(stderr, "%c", val);
2490 void bochs_bios_init(void)
2492 register_ioport_write(0x400, 1, bochs_bios_write, 2);
2493 register_ioport_write(0x401, 1, bochs_bios_write, 2);
2494 register_ioport_write(0x402, 1, bochs_bios_write, 1);
2495 register_ioport_write(0x403, 1, bochs_bios_write, 1);
2497 register_ioport_write(0x501, 1, bochs_bios_write, 2);
2498 register_ioport_write(0x502, 1, bochs_bios_write, 2);
2499 register_ioport_write(0x500, 1, bochs_bios_write, 1);
2500 register_ioport_write(0x503, 1, bochs_bios_write, 1);
2503 /***********************************************************/
2506 /* init terminal so that we can grab keys */
2507 static struct termios oldtty;
2509 static void term_exit(void)
2511 tcsetattr (0, TCSANOW, &oldtty);
2514 static void term_init(void)
2518 tcgetattr (0, &tty);
2521 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
2522 |INLCR|IGNCR|ICRNL|IXON);
2523 tty.c_oflag |= OPOST;
2524 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN);
2525 /* if graphical mode, we allow Ctrl-C handling */
2527 tty.c_lflag &= ~ISIG;
2528 tty.c_cflag &= ~(CSIZE|PARENB);
2531 tty.c_cc[VTIME] = 0;
2533 tcsetattr (0, TCSANOW, &tty);
2537 fcntl(0, F_SETFL, O_NONBLOCK);
2540 static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
2544 static void dumb_resize(DisplayState *ds, int w, int h)
2548 static void dumb_refresh(DisplayState *ds)
2550 vga_update_display();
2553 void dumb_display_init(DisplayState *ds)
2558 ds->dpy_update = dumb_update;
2559 ds->dpy_resize = dumb_resize;
2560 ds->dpy_refresh = dumb_refresh;
2563 #if !defined(CONFIG_SOFTMMU)
2564 /***********************************************************/
2565 /* cpu signal handler */
2566 static void host_segv_handler(int host_signum, siginfo_t *info,
2569 if (cpu_signal_handler(host_signum, info, puc))
2576 static int timer_irq_pending;
2577 static int timer_irq_count;
2579 static int timer_ms;
2580 static int gui_refresh_pending, gui_refresh_count;
2582 static void host_alarm_handler(int host_signum, siginfo_t *info,
2585 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2586 some drift between cpu_get_ticks() and the interrupt time. So
2587 we queue some interrupts to avoid missing some */
2588 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
2589 if (timer_irq_count) {
2590 if (timer_irq_count > 2)
2591 timer_irq_count = 2;
2593 timer_irq_pending = 1;
2595 gui_refresh_count += timer_ms;
2596 if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
2597 gui_refresh_count = 0;
2598 gui_refresh_pending = 1;
2601 if (gui_refresh_pending || timer_irq_pending) {
2602 /* just exit from the cpu to have a chance to handle timers */
2603 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2607 #ifdef CONFIG_SOFTMMU
2608 void *get_mmap_addr(unsigned long size)
2613 unsigned long mmap_addr = PHYS_RAM_BASE;
2615 void *get_mmap_addr(unsigned long size)
2619 mmap_addr += ((size + 4095) & ~4095) + 4096;
2620 return (void *)addr;
2624 /* main execution loop */
2626 CPUState *cpu_gdbstub_get_env(void *opaque)
2631 int main_loop(void *opaque)
2633 struct pollfd ufds[3], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
2634 int ret, n, timeout, serial_ok;
2636 CPUState *env = global_env;
2639 /* initialize terminal only there so that the user has a
2640 chance to stop QEMU with Ctrl-C before the gdb connection
2649 ret = cpu_x86_exec(env);
2650 if (reset_requested) {
2651 ret = EXCP_INTERRUPT;
2654 if (ret == EXCP_DEBUG) {
2658 /* if hlt instruction, we wait until the next IRQ */
2659 if (ret == EXCP_HLT)
2663 /* poll any events */
2666 if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) {
2669 pf->events = POLLIN;
2673 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
2676 pf->events = POLLIN;
2680 if (gdbstub_fd > 0) {
2682 pf->fd = gdbstub_fd;
2683 pf->events = POLLIN;
2687 ret = poll(ufds, pf - ufds, timeout);
2689 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
2690 n = read(0, &ch, 1);
2692 serial_received_byte(&serial_ports[0], ch);
2694 /* Closed, stop polling. */
2698 if (net_ufd && (net_ufd->revents & POLLIN)) {
2699 uint8_t buf[MAX_ETH_FRAME_SIZE];
2701 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
2704 memset(buf + n, 0, 60 - n);
2707 ne2000_receive(&ne2000_state, buf, n);
2710 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
2712 /* stop emulation if requested by gdb */
2713 n = read(gdbstub_fd, buf, 1);
2715 ret = EXCP_INTERRUPT;
2722 if (timer_irq_pending) {
2725 timer_irq_pending = 0;
2729 if (gui_refresh_pending) {
2730 display_state.dpy_refresh(&display_state);
2731 gui_refresh_pending = 0;
2734 cpu_disable_ticks();
2740 printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
2741 "usage: %s [options] [disk_image]\n"
2743 "'disk_image' is a raw hard image image for IDE hard disk 0\n"
2745 "Standard options:\n"
2746 "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n"
2747 "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n"
2748 "-cdrom file use 'file' as IDE cdrom 2 image\n"
2749 "-boot [c|d] boot on hard disk or CD-ROM\n"
2750 "-snapshot write to temporary files instead of disk image files\n"
2751 "-m megs set virtual RAM size to megs MB\n"
2752 "-n script set network init script [default=%s]\n"
2753 "-tun-fd fd this fd talks to tap/tun, use it.\n"
2754 "-nographic disable graphical output\n"
2756 "Linux boot specific (does not require PC BIOS):\n"
2757 "-kernel bzImage use 'bzImage' as kernel image\n"
2758 "-append cmdline use 'cmdline' as kernel command line\n"
2759 "-initrd file use 'file' as initial ram disk\n"
2761 "Debug/Expert options:\n"
2762 "-s wait gdb connection to port %d\n"
2763 "-p port change gdb connection port\n"
2764 "-d output log in /tmp/vl.log\n"
2765 "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
2766 "-L path set the directory for the BIOS and VGA BIOS\n"
2768 "During emulation, use C-a h to get terminal commands:\n",
2769 #ifdef CONFIG_SOFTMMU
2774 DEFAULT_NETWORK_SCRIPT,
2775 DEFAULT_GDBSTUB_PORT);
2777 #ifndef CONFIG_SOFTMMU
2779 "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
2780 "work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
2786 struct option long_options[] = {
2787 { "initrd", 1, NULL, 0, },
2788 { "hda", 1, NULL, 0, },
2789 { "hdb", 1, NULL, 0, },
2790 { "snapshot", 0, NULL, 0, },
2791 { "hdachs", 1, NULL, 0, },
2792 { "nographic", 0, NULL, 0, },
2793 { "kernel", 1, NULL, 0, },
2794 { "append", 1, NULL, 0, },
2795 { "tun-fd", 1, NULL, 0, },
2796 { "hdc", 1, NULL, 0, },
2797 { "hdd", 1, NULL, 0, },
2798 { "cdrom", 1, NULL, 0, },
2799 { "boot", 1, NULL, 0, },
2800 { NULL, 0, NULL, 0 },
2804 /* SDL use the pthreads and they modify sigaction. We don't
2806 #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)
2807 extern void __libc_sigaction();
2808 #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
2810 extern void __sigaction();
2811 #define sigaction(sig, act, oact) __sigaction(sig, act, oact)
2813 #endif /* CONFIG_SDL */
2815 int main(int argc, char **argv)
2817 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
2818 int snapshot, linux_boot, total_ram_size;
2819 struct linux_params *params;
2820 struct sigaction act;
2821 struct itimerval itv;
2823 const char *initrd_filename;
2824 const char *hd_filename[MAX_DISKS];
2825 const char *kernel_filename, *kernel_cmdline;
2826 DisplayState *ds = &display_state;
2828 /* we never want that malloc() uses mmap() */
2829 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
2830 initrd_filename = NULL;
2831 for(i = 0; i < MAX_DISKS; i++)
2832 hd_filename[i] = NULL;
2833 phys_ram_size = 32 * 1024 * 1024;
2834 vga_ram_size = VGA_RAM_SIZE;
2835 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
2837 gdbstub_port = DEFAULT_GDBSTUB_PORT;
2840 kernel_filename = NULL;
2841 kernel_cmdline = "";
2843 c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
2848 switch(long_index) {
2850 initrd_filename = optarg;
2853 hd_filename[0] = optarg;
2856 hd_filename[1] = optarg;
2863 int cyls, heads, secs;
2866 cyls = strtol(p, (char **)&p, 0);
2870 heads = strtol(p, (char **)&p, 0);
2874 secs = strtol(p, (char **)&p, 0);
2877 ide_set_geometry(0, cyls, heads, secs);
2885 kernel_filename = optarg;
2888 kernel_cmdline = optarg;
2891 net_fd = atoi(optarg);
2894 hd_filename[2] = optarg;
2897 hd_filename[3] = optarg;
2900 hd_filename[2] = optarg;
2901 ide_set_cdrom(2, 1);
2904 boot_device = optarg[0];
2905 if (boot_device != 'c' && boot_device != 'd') {
2906 fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device);
2916 phys_ram_size = atoi(optarg) * 1024 * 1024;
2917 if (phys_ram_size <= 0)
2919 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
2920 fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
2921 PHYS_RAM_MAX_SIZE / (1024 * 1024));
2926 cpu_set_log(CPU_LOG_ALL);
2929 pstrcpy(network_script, sizeof(network_script), optarg);
2935 gdbstub_port = atoi(optarg);
2943 if (optind < argc) {
2944 hd_filename[0] = argv[optind++];
2947 linux_boot = (kernel_filename != NULL);
2949 if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0')
2953 setvbuf(stdout, NULL, _IOLBF, 0);
2955 /* init network tun interface */
2959 /* init the memory */
2960 total_ram_size = phys_ram_size + vga_ram_size;
2962 #ifdef CONFIG_SOFTMMU
2963 phys_ram_base = malloc(total_ram_size);
2964 if (!phys_ram_base) {
2965 fprintf(stderr, "Could not allocate physical memory\n");
2969 /* as we must map the same page at several addresses, we must use
2974 tmpdir = getenv("QEMU_TMPDIR");
2977 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
2978 if (mkstemp(phys_ram_file) < 0) {
2979 fprintf(stderr, "Could not create temporary memory file '%s'\n",
2983 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
2984 if (phys_ram_fd < 0) {
2985 fprintf(stderr, "Could not open temporary memory file '%s'\n",
2989 ftruncate(phys_ram_fd, total_ram_size);
2990 unlink(phys_ram_file);
2991 phys_ram_base = mmap(get_mmap_addr(total_ram_size),
2993 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
2995 if (phys_ram_base == MAP_FAILED) {
2996 fprintf(stderr, "Could not map physical memory\n");
3002 /* open the virtual block devices */
3003 for(i = 0; i < MAX_DISKS; i++) {
3004 if (hd_filename[i]) {
3005 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
3007 fprintf(stderr, "qemu: could not open hard disk image '%s\n",
3014 /* init CPU state */
3017 cpu_single_env = env;
3022 cpu_register_physical_memory(0, phys_ram_size, 0);
3025 /* now we can load the kernel */
3026 ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
3028 fprintf(stderr, "qemu: could not load kernel '%s'\n",
3035 if (initrd_filename) {
3036 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
3037 if (initrd_size < 0) {
3038 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3044 /* init kernel params */
3045 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
3046 memset(params, 0, sizeof(struct linux_params));
3047 params->mount_root_rdonly = 0;
3048 stw_raw(¶ms->cl_magic, 0xA33F);
3049 stw_raw(¶ms->cl_offset, params->commandline - (uint8_t *)params);
3050 stl_raw(¶ms->alt_mem_k, (phys_ram_size / 1024) - 1024);
3051 pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline);
3052 params->loader_type = 0x01;
3053 if (initrd_size > 0) {
3054 stl_raw(¶ms->initrd_start, INITRD_LOAD_ADDR);
3055 stl_raw(¶ms->initrd_size, initrd_size);
3057 params->orig_video_lines = 25;
3058 params->orig_video_cols = 80;
3060 /* setup basic memory access */
3061 env->cr[0] = 0x00000033;
3062 cpu_x86_init_mmu(env);
3064 memset(params->idt_table, 0, sizeof(params->idt_table));
3066 stq_raw(¶ms->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3067 stq_raw(¶ms->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */
3068 /* for newer kernels (2.6.0) CS/DS are at different addresses */
3069 stq_raw(¶ms->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3070 stq_raw(¶ms->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */
3072 env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base);
3073 env->idt.limit = sizeof(params->idt_table) - 1;
3074 env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base);
3075 env->gdt.limit = sizeof(params->gdt_table) - 1;
3077 cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00);
3078 cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3079 cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3080 cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3081 cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3082 cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3084 env->eip = KERNEL_LOAD_ADDR;
3085 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
3094 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
3095 ret = load_image(buf, phys_ram_base + 0x000f0000);
3096 if (ret != 0x10000) {
3097 fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
3102 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
3103 ret = load_image(buf, phys_ram_base + 0x000c0000);
3105 /* setup basic memory access */
3106 env->cr[0] = 0x60000010;
3107 cpu_x86_init_mmu(env);
3109 env->idt.limit = 0xffff;
3110 env->gdt.limit = 0xffff;
3111 env->ldt.limit = 0xffff;
3113 /* not correct (CS base=0xffff0000) */
3114 cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
3115 cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
3116 cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
3117 cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
3118 cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
3119 cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
3122 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
3131 dumb_display_init(ds);
3134 sdl_display_init(ds);
3136 dumb_display_init(ds);
3139 /* init basic PC hardware */
3140 register_ioport_write(0x80, 1, ioport80_write, 1);
3142 vga_init(ds, phys_ram_base + phys_ram_size, phys_ram_size,
3152 /* setup cpu signal handlers for MMU / self modifying code handling */
3153 sigfillset(&act.sa_mask);
3154 act.sa_flags = SA_SIGINFO;
3155 #if !defined(CONFIG_SOFTMMU)
3156 act.sa_sigaction = host_segv_handler;
3157 sigaction(SIGSEGV, &act, NULL);
3158 sigaction(SIGBUS, &act, NULL);
3161 act.sa_sigaction = host_alarm_handler;
3162 sigaction(SIGALRM, &act, NULL);
3164 itv.it_interval.tv_sec = 0;
3165 itv.it_interval.tv_usec = 1000;
3166 itv.it_value.tv_sec = 0;
3167 itv.it_value.tv_usec = 10 * 1000;
3168 setitimer(ITIMER_REAL, &itv, NULL);
3169 /* we probe the tick duration of the kernel to inform the user if
3170 the emulated kernel requested a too high timer frequency */
3171 getitimer(ITIMER_REAL, &itv);
3172 timer_ms = itv.it_interval.tv_usec / 1000;
3173 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
3177 cpu_gdbstub(NULL, main_loop, gdbstub_port);