2 * QEMU PC System Emulator
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
43 #include <sys/ioctl.h>
44 #include <sys/socket.h>
46 #include <linux/if_tun.h>
54 #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup"
55 #define BIOS_FILENAME "bios.bin"
56 #define VGABIOS_FILENAME "vgabios.bin"
58 //#define DEBUG_UNUSED_IOPORT
60 //#define DEBUG_IRQ_LATENCY
62 /* output Bochs bios info messages */
70 /* debug NE2000 card */
71 //#define DEBUG_NE2000
73 /* debug PC keyboard */
76 /* debug PC keyboard : only mouse */
79 //#define DEBUG_SERIAL
81 #define PHYS_RAM_BASE 0xac000000
82 #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
84 #if defined (TARGET_I386)
85 #define KERNEL_LOAD_ADDR 0x00100000
86 #elif defined (TARGET_PPC)
87 //#define USE_OPEN_FIRMWARE
88 #if !defined (USE_OPEN_FIRMWARE)
89 #define KERNEL_LOAD_ADDR 0x01000000
90 #define KERNEL_STACK_ADDR 0x01200000
92 #define KERNEL_LOAD_ADDR 0x00000000
93 #define KERNEL_STACK_ADDR 0x00400000
96 #define INITRD_LOAD_ADDR 0x00400000
97 #define KERNEL_PARAMS_ADDR 0x00090000
99 #define GUI_REFRESH_INTERVAL 30
101 /* from plex86 (BSD license) */
102 struct __attribute__ ((packed)) linux_params {
103 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
104 // I just padded out the VESA parts, rather than define them.
106 /* 0x000 */ uint8_t orig_x;
107 /* 0x001 */ uint8_t orig_y;
108 /* 0x002 */ uint16_t ext_mem_k;
109 /* 0x004 */ uint16_t orig_video_page;
110 /* 0x006 */ uint8_t orig_video_mode;
111 /* 0x007 */ uint8_t orig_video_cols;
112 /* 0x008 */ uint16_t unused1;
113 /* 0x00a */ uint16_t orig_video_ega_bx;
114 /* 0x00c */ uint16_t unused2;
115 /* 0x00e */ uint8_t orig_video_lines;
116 /* 0x00f */ uint8_t orig_video_isVGA;
117 /* 0x010 */ uint16_t orig_video_points;
118 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
119 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
120 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
121 // is calculated as 0x90000 + cl_offset, bu
122 // only if cl_magic == 0xA33F.
123 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
125 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
126 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
128 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
129 // Might be truncated?
130 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
131 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
133 // System description table truncated to 16 bytes
134 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
135 /* 0x0a0 */ uint16_t sys_description_len;
136 /* 0x0a2 */ uint8_t sys_description_table[14];
138 // [1] machine submodel id
142 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
143 /* 0x1e0 */ uint32_t alt_mem_k;
144 /* 0x1e4 */ uint8_t pad4[4];
145 /* 0x1e8 */ uint8_t e820map_entries;
146 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
147 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
148 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
149 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
150 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
151 // (b)zImage-file (in 16 byte units, rounded up)
152 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
153 /* 0x1f8 */ uint16_t ramdisk_flags;
154 /* 0x1fa */ uint16_t vga_mode; // (old one)
155 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
156 /* 0x1fe */ uint8_t pad6[1];
157 /* 0x1ff */ uint8_t aux_device_info;
158 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
159 // aka "reserved" field.
160 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
161 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
162 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
163 // boot loaders, look there.
164 /* 0x210 */ uint8_t loader_type;
169 // T=2: bootsect-loader
173 /* 0x211 */ uint8_t loadflags;
174 // bit0 = 1: kernel is loaded high (bzImage)
175 // bit7 = 1: Heap and pointer (see below) set by boot
177 /* 0x212 */ uint16_t setup_S_temp1;
178 /* 0x214 */ uint32_t kernel_start;
179 /* 0x218 */ uint32_t initrd_start;
180 /* 0x21c */ uint32_t initrd_size;
181 /* 0x220 */ uint8_t setup_S_temp2[4];
182 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
183 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
185 /* 0x2d0 : Int 15, ax=e820 memory map. */
186 // (linux/include/asm-i386/e820.h, 'struct e820entry')
189 #define E820_RESERVED 2
190 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
198 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
200 // BIOS Enhanced Disk Drive Services.
201 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
202 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
203 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
205 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
206 /* 0x800 */ uint8_t commandline[0x800];
209 uint64_t gdt_table[256];
210 uint64_t idt_table[48];
213 #define KERNEL_CS 0x10
214 #define KERNEL_DS 0x18
216 /* XXX: use a two level table to limit memory usage */
217 #define MAX_IOPORTS 65536
219 static const char *bios_dir = CONFIG_QEMU_SHAREDIR;
220 char phys_ram_file[1024];
221 CPUState *global_env;
222 CPUState *cpu_single_env;
223 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
224 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
225 BlockDriverState *bs_table[MAX_DISKS], *fd_table[MAX_FD];
227 static DisplayState display_state;
230 int64_t ticks_per_sec;
231 int boot_device = 'c';
233 /***********************************************************/
236 uint32_t default_ioport_readb(CPUState *env, uint32_t address)
238 #ifdef DEBUG_UNUSED_IOPORT
239 fprintf(stderr, "inb: port=0x%04x\n", address);
244 void default_ioport_writeb(CPUState *env, uint32_t address, uint32_t data)
246 #ifdef DEBUG_UNUSED_IOPORT
247 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
251 /* default is to make two byte accesses */
252 uint32_t default_ioport_readw(CPUState *env, uint32_t address)
255 data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
256 data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
260 void default_ioport_writew(CPUState *env, uint32_t address, uint32_t data)
262 ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
263 ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
266 uint32_t default_ioport_readl(CPUState *env, uint32_t address)
268 #ifdef DEBUG_UNUSED_IOPORT
269 fprintf(stderr, "inl: port=0x%04x\n", address);
274 void default_ioport_writel(CPUState *env, uint32_t address, uint32_t data)
276 #ifdef DEBUG_UNUSED_IOPORT
277 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
281 void init_ioports(void)
285 for(i = 0; i < MAX_IOPORTS; i++) {
286 ioport_read_table[0][i] = default_ioport_readb;
287 ioport_write_table[0][i] = default_ioport_writeb;
288 ioport_read_table[1][i] = default_ioport_readw;
289 ioport_write_table[1][i] = default_ioport_writew;
290 ioport_read_table[2][i] = default_ioport_readl;
291 ioport_write_table[2][i] = default_ioport_writel;
295 /* size is the word size in byte */
296 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
308 for(i = start; i < start + length; i += size)
309 ioport_read_table[bsize][i] = func;
313 /* size is the word size in byte */
314 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
326 for(i = start; i < start + length; i += size)
327 ioport_write_table[bsize][i] = func;
331 void pstrcpy(char *buf, int buf_size, const char *str)
341 if (c == 0 || q >= buf + buf_size - 1)
348 /* strcat and truncate. */
349 char *pstrcat(char *buf, int buf_size, const char *s)
354 pstrcpy(buf + len, buf_size - len, s);
358 int load_kernel(const char *filename, uint8_t *addr)
361 #if defined (TARGET_I386)
363 uint8_t bootsect[512];
366 printf("Load kernel at %p (0x%08x)\n", addr,
367 (uint32_t)addr - (uint32_t)phys_ram_base);
368 fd = open(filename, O_RDONLY);
371 #if defined (TARGET_I386)
372 if (read(fd, bootsect, 512) != 512)
374 setup_sects = bootsect[0x1F1];
377 /* skip 16 bit setup code */
378 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
380 size = read(fd, addr, 16 * 1024 * 1024);
390 /* return the size or -1 if error */
391 int load_image(const char *filename, uint8_t *addr)
394 fd = open(filename, O_RDONLY);
397 size = lseek(fd, 0, SEEK_END);
398 lseek(fd, 0, SEEK_SET);
399 if (read(fd, addr, size) != size) {
407 void cpu_outb(CPUState *env, int addr, int val)
409 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
412 void cpu_outw(CPUState *env, int addr, int val)
414 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
417 void cpu_outl(CPUState *env, int addr, int val)
419 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
422 int cpu_inb(CPUState *env, int addr)
424 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
427 int cpu_inw(CPUState *env, int addr)
429 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
432 int cpu_inl(CPUState *env, int addr)
434 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
437 /***********************************************************/
438 void ioport80_write(CPUState *env, uint32_t addr, uint32_t data)
442 void hw_error(const char *fmt, ...)
447 fprintf(stderr, "qemu: hardware error: ");
448 vfprintf(stderr, fmt, ap);
449 fprintf(stderr, "\n");
451 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
453 cpu_dump_state(global_env, stderr, 0);
459 /***********************************************************/
462 #if defined (TARGET_I386)
463 #define RTC_SECONDS 0
464 #define RTC_SECONDS_ALARM 1
465 #define RTC_MINUTES 2
466 #define RTC_MINUTES_ALARM 3
468 #define RTC_HOURS_ALARM 5
469 #define RTC_ALARM_DONT_CARE 0xC0
471 #define RTC_DAY_OF_WEEK 6
472 #define RTC_DAY_OF_MONTH 7
481 /* PC cmos mappings */
482 #define REG_EQUIPMENT_BYTE 0x14
483 #define REG_IBM_CENTURY_BYTE 0x32
485 uint8_t cmos_data[128];
488 void cmos_ioport_write(CPUState *env, uint32_t addr, uint32_t data)
491 cmos_index = data & 0x7f;
494 printf("cmos: write index=0x%02x val=0x%02x\n",
498 case RTC_SECONDS_ALARM:
499 case RTC_MINUTES_ALARM:
500 case RTC_HOURS_ALARM:
501 /* XXX: not supported */
502 cmos_data[cmos_index] = data;
507 case RTC_DAY_OF_WEEK:
508 case RTC_DAY_OF_MONTH:
511 cmos_data[cmos_index] = data;
515 cmos_data[cmos_index] = data;
519 /* cannot write to them */
522 cmos_data[cmos_index] = data;
528 static inline int to_bcd(int a)
530 return ((a / 10) << 4) | (a % 10);
533 static void cmos_update_time(void)
540 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
541 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
542 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
543 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
544 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
545 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
546 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
547 cmos_data[REG_IBM_CENTURY_BYTE] = to_bcd((tm->tm_year / 100) + 19);
550 uint32_t cmos_ioport_read(CPUState *env, uint32_t addr)
561 case RTC_DAY_OF_WEEK:
562 case RTC_DAY_OF_MONTH:
565 case REG_IBM_CENTURY_BYTE:
567 ret = cmos_data[cmos_index];
570 ret = cmos_data[cmos_index];
571 /* toggle update-in-progress bit for Linux (same hack as
573 cmos_data[RTC_REG_A] ^= 0x80;
576 ret = cmos_data[cmos_index];
578 cmos_data[RTC_REG_C] = 0x00;
581 ret = cmos_data[cmos_index];
585 printf("cmos: read index=0x%02x val=0x%02x\n",
598 cmos_data[RTC_REG_A] = 0x26;
599 cmos_data[RTC_REG_B] = 0x02;
600 cmos_data[RTC_REG_C] = 0x00;
601 cmos_data[RTC_REG_D] = 0x80;
603 /* various important CMOS locations needed by PC/Bochs bios */
605 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
606 cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
609 val = (phys_ram_size / 1024) - 1024;
612 cmos_data[0x17] = val;
613 cmos_data[0x18] = val >> 8;
614 cmos_data[0x30] = val;
615 cmos_data[0x31] = val >> 8;
617 val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
620 cmos_data[0x34] = val;
621 cmos_data[0x35] = val >> 8;
623 switch(boot_device) {
626 cmos_data[0x3d] = 0x01; /* floppy boot */
630 cmos_data[0x3d] = 0x02; /* hard drive boot */
633 cmos_data[0x3d] = 0x03; /* CD-ROM boot */
637 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
638 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
641 void cmos_register_fd (uint8_t fd0, uint8_t fd1)
648 /* 1.44 Mb 3"5 drive */
649 cmos_data[0x10] |= 0x40;
652 /* 2.88 Mb 3"5 drive */
653 cmos_data[0x10] |= 0x60;
656 /* 1.2 Mb 5"5 drive */
657 cmos_data[0x10] |= 0x20;
662 /* 1.44 Mb 3"5 drive */
663 cmos_data[0x10] |= 0x04;
666 /* 2.88 Mb 3"5 drive */
667 cmos_data[0x10] |= 0x06;
670 /* 1.2 Mb 5"5 drive */
671 cmos_data[0x10] |= 0x02;
682 cmos_data[REG_EQUIPMENT_BYTE] |= 0x01; /* 1 drive, ready for boot */
685 cmos_data[REG_EQUIPMENT_BYTE] |= 0x41; /* 2 drives, ready for boot */
689 #endif /* TARGET_I386 */
691 /***********************************************************/
692 /* 8259 pic emulation */
694 typedef struct PicState {
695 uint8_t last_irr; /* edge detection */
696 uint8_t irr; /* interrupt request register */
697 uint8_t imr; /* interrupt mask register */
698 uint8_t isr; /* interrupt service register */
699 uint8_t priority_add; /* highest irq priority */
701 uint8_t read_reg_select;
703 uint8_t special_mask;
706 uint8_t rotate_on_auto_eoi;
707 uint8_t special_fully_nested_mode;
708 uint8_t init4; /* true if 4 byte init */
711 /* 0 is master pic, 1 is slave pic */
713 int pic_irq_requested;
715 /* set irq level. If an edge is detected, then the IRR is set to 1 */
716 static inline void pic_set_irq1(PicState *s, int irq, int level)
721 if ((s->last_irr & mask) == 0)
725 s->last_irr &= ~mask;
729 /* return the highest priority found in mask (highest = smallest
730 number). Return 8 if no irq */
731 static inline int get_priority(PicState *s, int mask)
737 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
742 /* return the pic wanted interrupt. return -1 if none */
743 static int pic_get_irq(PicState *s)
745 int mask, cur_priority, priority;
747 mask = s->irr & ~s->imr;
748 priority = get_priority(s, mask);
751 /* compute current priority. If special fully nested mode on the
752 master, the IRQ coming from the slave is not taken into account
753 for the priority computation. */
755 if (s->special_fully_nested_mode && s == &pics[0])
757 cur_priority = get_priority(s, mask);
758 if (priority < cur_priority) {
759 /* higher priority found: an irq should be generated */
760 return (priority + s->priority_add) & 7;
766 /* raise irq to CPU if necessary. must be called every time the active
768 void pic_update_irq(void)
772 /* first look at slave pic */
773 irq2 = pic_get_irq(&pics[1]);
775 /* if irq request by slave pic, signal master PIC */
776 pic_set_irq1(&pics[0], 2, 1);
777 pic_set_irq1(&pics[0], 2, 0);
779 /* look at requested irq */
780 irq = pic_get_irq(&pics[0]);
784 pic_irq_requested = 8 + irq2;
786 /* from master pic */
787 pic_irq_requested = irq;
789 #if defined(DEBUG_PIC)
792 for(i = 0; i < 2; i++) {
793 printf("pic%d: imr=%x irr=%x padd=%d\n",
794 i, pics[i].imr, pics[i].irr, pics[i].priority_add);
798 printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
800 cpu_interrupt(global_env, CPU_INTERRUPT_HARD);
804 #ifdef DEBUG_IRQ_LATENCY
805 int64_t irq_time[16];
806 int64_t cpu_get_ticks(void);
808 #if defined(DEBUG_PIC)
812 void pic_set_irq(int irq, int level)
814 #if defined(DEBUG_PIC)
815 if (level != irq_level[irq]) {
816 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
817 irq_level[irq] = level;
820 #ifdef DEBUG_IRQ_LATENCY
822 irq_time[irq] = cpu_get_ticks();
825 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
829 /* acknowledge interrupt 'irq' */
830 static inline void pic_intack(PicState *s, int irq)
833 if (s->rotate_on_auto_eoi)
834 s->priority_add = (irq + 1) & 7;
836 s->isr |= (1 << irq);
838 s->irr &= ~(1 << irq);
841 int cpu_x86_get_pic_interrupt(CPUState *env)
843 int irq, irq2, intno;
845 /* signal the pic that the irq was acked by the CPU */
846 irq = pic_irq_requested;
847 #ifdef DEBUG_IRQ_LATENCY
848 printf("IRQ%d latency=%0.3fus\n",
850 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
852 #if defined(DEBUG_PIC)
853 printf("pic_interrupt: irq=%d\n", irq);
858 pic_intack(&pics[1], irq2);
860 intno = pics[1].irq_base + irq2;
862 intno = pics[0].irq_base + irq;
864 pic_intack(&pics[0], irq);
868 void pic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
871 int priority, cmd, irq;
874 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
876 s = &pics[addr >> 7];
881 memset(s, 0, sizeof(PicState));
885 hw_error("single mode not supported");
887 hw_error("level sensitive irq not supported");
888 } else if (val & 0x08) {
892 s->read_reg_select = val & 1;
894 s->special_mask = (val >> 5) & 1;
900 s->rotate_on_auto_eoi = cmd >> 2;
902 case 1: /* end of interrupt */
904 priority = get_priority(s, s->isr);
906 irq = (priority + s->priority_add) & 7;
907 s->isr &= ~(1 << irq);
909 s->priority_add = (irq + 1) & 7;
915 s->isr &= ~(1 << irq);
919 s->priority_add = (val + 1) & 7;
924 s->isr &= ~(1 << irq);
925 s->priority_add = (irq + 1) & 7;
934 switch(s->init_state) {
941 s->irq_base = val & 0xf8;
952 s->special_fully_nested_mode = (val >> 4) & 1;
953 s->auto_eoi = (val >> 1) & 1;
960 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
964 ret = pic_get_irq(s);
967 pics[0].isr &= ~(1 << 2);
968 pics[0].irr &= ~(1 << 2);
970 s->irr &= ~(1 << ret);
971 s->isr &= ~(1 << ret);
972 if (addr1 >> 7 || ret != 2)
982 uint32_t pic_ioport_read(CPUState *env, uint32_t addr1)
989 s = &pics[addr >> 7];
992 ret = pic_poll_read(s, addr1);
996 if (s->read_reg_select)
1005 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
1010 /* memory mapped interrupt status */
1011 uint32_t pic_intack_read(CPUState *env)
1015 ret = pic_poll_read(&pics[0], 0x00);
1017 ret = pic_poll_read(&pics[1], 0x80) + 8;
1018 /* Prepare for ISR read */
1019 pics[0].read_reg_select = 1;
1026 #if defined (TARGET_I386) || defined (TARGET_PPC)
1027 register_ioport_write(0x20, 2, pic_ioport_write, 1);
1028 register_ioport_read(0x20, 2, pic_ioport_read, 1);
1029 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
1030 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
1034 /***********************************************************/
1035 /* 8253 PIT emulation */
1037 #define PIT_FREQ 1193182
1039 #define RW_STATE_LSB 0
1040 #define RW_STATE_MSB 1
1041 #define RW_STATE_WORD0 2
1042 #define RW_STATE_WORD1 3
1043 #define RW_STATE_LATCHED_WORD0 4
1044 #define RW_STATE_LATCHED_WORD1 5
1046 typedef struct PITChannelState {
1047 int count; /* can be 65536 */
1048 uint16_t latched_count;
1051 uint8_t bcd; /* not supported */
1052 uint8_t gate; /* timer start */
1053 int64_t count_load_time;
1054 int64_t count_last_edge_check_time;
1057 PITChannelState pit_channels[3];
1058 int speaker_data_on;
1059 int dummy_refresh_clock;
1060 int pit_min_timer_count = 0;
1063 #if defined(__powerpc__)
1065 static inline uint32_t get_tbl(void)
1068 asm volatile("mftb %0" : "=r" (tbl));
1072 static inline uint32_t get_tbu(void)
1075 asm volatile("mftbu %0" : "=r" (tbl));
1079 int64_t cpu_get_real_ticks(void)
1082 /* NOTE: we test if wrapping has occurred */
1088 return ((int64_t)h << 32) | l;
1091 #elif defined(__i386__)
1093 int64_t cpu_get_real_ticks(void)
1096 asm("rdtsc" : "=A" (val));
1101 #error unsupported CPU
1104 static int64_t cpu_ticks_offset;
1105 static int64_t cpu_ticks_last;
1107 int64_t cpu_get_ticks(void)
1109 return cpu_get_real_ticks() + cpu_ticks_offset;
1112 /* enable cpu_get_ticks() */
1113 void cpu_enable_ticks(void)
1115 cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks();
1118 /* disable cpu_get_ticks() : the clock is stopped. You must not call
1119 cpu_get_ticks() after that. */
1120 void cpu_disable_ticks(void)
1122 cpu_ticks_last = cpu_get_ticks();
1125 int64_t get_clock(void)
1128 gettimeofday(&tv, NULL);
1129 return tv.tv_sec * 1000000LL + tv.tv_usec;
1132 void cpu_calibrate_ticks(void)
1134 int64_t usec, ticks;
1137 ticks = cpu_get_ticks();
1139 usec = get_clock() - usec;
1140 ticks = cpu_get_ticks() - ticks;
1141 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
1144 /* compute with 96 bit intermediate result: (a*b)/c */
1145 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
1150 #ifdef WORDS_BIGENDIAN
1160 rl = (uint64_t)u.l.low * (uint64_t)b;
1161 rh = (uint64_t)u.l.high * (uint64_t)b;
1163 res.l.high = rh / c;
1164 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
1168 static int pit_get_count(PITChannelState *s)
1173 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
1179 counter = (s->count - d) & 0xffff;
1182 /* XXX: may be incorrect for odd counts */
1183 counter = s->count - ((2 * d) % s->count);
1186 counter = s->count - (d % s->count);
1192 /* get pit output bit */
1193 static int pit_get_out(PITChannelState *s)
1198 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
1202 out = (d >= s->count);
1205 out = (d < s->count);
1208 if ((d % s->count) == 0 && d != 0)
1214 out = (d % s->count) < ((s->count + 1) >> 1);
1218 out = (d == s->count);
1224 /* get the number of 0 to 1 transitions we had since we call this
1226 /* XXX: maybe better to use ticks precision to avoid getting edges
1227 twice if checks are done at very small intervals */
1228 static int pit_get_out_edges(PITChannelState *s)
1234 ticks = cpu_get_ticks();
1235 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
1236 PIT_FREQ, ticks_per_sec);
1237 d2 = muldiv64(ticks - s->count_load_time,
1238 PIT_FREQ, ticks_per_sec);
1239 s->count_last_edge_check_time = ticks;
1243 if (d1 < s->count && d2 >= s->count)
1257 v = s->count - ((s->count + 1) >> 1);
1258 d1 = (d1 + v) / s->count;
1259 d2 = (d2 + v) / s->count;
1264 if (d1 < s->count && d2 >= s->count)
1273 /* val must be 0 or 1 */
1274 static inline void pit_set_gate(PITChannelState *s, int val)
1280 /* XXX: just disable/enable counting */
1284 if (s->gate < val) {
1285 /* restart counting on rising edge */
1286 s->count_load_time = cpu_get_ticks();
1287 s->count_last_edge_check_time = s->count_load_time;
1292 if (s->gate < val) {
1293 /* restart counting on rising edge */
1294 s->count_load_time = cpu_get_ticks();
1295 s->count_last_edge_check_time = s->count_load_time;
1297 /* XXX: disable/enable counting */
1303 static inline void pit_load_count(PITChannelState *s, int val)
1307 s->count_load_time = cpu_get_ticks();
1308 s->count_last_edge_check_time = s->count_load_time;
1310 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
1312 "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
1313 PIT_FREQ / pit_min_timer_count);
1317 void pit_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
1319 int channel, access;
1327 s = &pit_channels[channel];
1328 access = (val >> 4) & 3;
1331 s->latched_count = pit_get_count(s);
1332 s->rw_state = RW_STATE_LATCHED_WORD0;
1335 s->mode = (val >> 1) & 7;
1337 s->rw_state = access - 1 + RW_STATE_LSB;
1341 s = &pit_channels[addr];
1342 switch(s->rw_state) {
1344 pit_load_count(s, val);
1347 pit_load_count(s, val << 8);
1349 case RW_STATE_WORD0:
1350 case RW_STATE_WORD1:
1351 if (s->rw_state & 1) {
1352 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
1354 s->latched_count = val;
1362 uint32_t pit_ioport_read(CPUState *env, uint32_t addr)
1368 s = &pit_channels[addr];
1369 switch(s->rw_state) {
1372 case RW_STATE_WORD0:
1373 case RW_STATE_WORD1:
1374 count = pit_get_count(s);
1375 if (s->rw_state & 1)
1376 ret = (count >> 8) & 0xff;
1379 if (s->rw_state & 2)
1383 case RW_STATE_LATCHED_WORD0:
1384 case RW_STATE_LATCHED_WORD1:
1385 if (s->rw_state & 1)
1386 ret = s->latched_count >> 8;
1388 ret = s->latched_count & 0xff;
1395 #if defined (TARGET_I386)
1396 void speaker_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
1398 speaker_data_on = (val >> 1) & 1;
1399 pit_set_gate(&pit_channels[2], val & 1);
1402 uint32_t speaker_ioport_read(CPUState *env, uint32_t addr)
1405 out = pit_get_out(&pit_channels[2]);
1406 dummy_refresh_clock ^= 1;
1407 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
1408 (dummy_refresh_clock << 4);
1417 cpu_calibrate_ticks();
1419 for(i = 0;i < 3; i++) {
1420 s = &pit_channels[i];
1423 pit_load_count(s, 0);
1426 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1427 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1429 #if defined (TARGET_I386)
1430 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1431 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1435 /***********************************************************/
1436 /* serial port emulation */
1440 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1442 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1443 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1444 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1445 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1447 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1448 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1450 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1451 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1452 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1453 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1456 * These are the definitions for the Modem Control Register
1458 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1459 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1460 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1461 #define UART_MCR_RTS 0x02 /* RTS complement */
1462 #define UART_MCR_DTR 0x01 /* DTR complement */
1465 * These are the definitions for the Modem Status Register
1467 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1468 #define UART_MSR_RI 0x40 /* Ring Indicator */
1469 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1470 #define UART_MSR_CTS 0x10 /* Clear to Send */
1471 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1472 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1473 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1474 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1475 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1477 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1478 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1479 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1480 #define UART_LSR_FE 0x08 /* Frame error indicator */
1481 #define UART_LSR_PE 0x04 /* Parity error indicator */
1482 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1483 #define UART_LSR_DR 0x01 /* Receiver data ready */
1485 typedef struct SerialState {
1487 uint8_t rbr; /* receive register */
1489 uint8_t iir; /* read only */
1492 uint8_t lsr; /* read only */
1495 /* NOTE: this hidden state is necessary for tx irq generation as
1496 it can be reset while reading iir */
1500 SerialState serial_ports[1];
1502 void serial_update_irq(void)
1504 SerialState *s = &serial_ports[0];
1506 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1507 s->iir = UART_IIR_RDI;
1508 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
1509 s->iir = UART_IIR_THRI;
1511 s->iir = UART_IIR_NO_INT;
1513 if (s->iir != UART_IIR_NO_INT) {
1514 pic_set_irq(UART_IRQ, 1);
1516 pic_set_irq(UART_IRQ, 0);
1520 void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
1522 SerialState *s = &serial_ports[0];
1528 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
1533 if (s->lcr & UART_LCR_DLAB) {
1534 s->divider = (s->divider & 0xff00) | val;
1536 s->thr_ipending = 0;
1537 s->lsr &= ~UART_LSR_THRE;
1538 serial_update_irq();
1542 ret = write(1, &ch, 1);
1544 s->thr_ipending = 1;
1545 s->lsr |= UART_LSR_THRE;
1546 s->lsr |= UART_LSR_TEMT;
1547 serial_update_irq();
1551 if (s->lcr & UART_LCR_DLAB) {
1552 s->divider = (s->divider & 0x00ff) | (val << 8);
1555 serial_update_irq();
1577 uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
1579 SerialState *s = &serial_ports[0];
1586 if (s->lcr & UART_LCR_DLAB) {
1587 ret = s->divider & 0xff;
1590 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1591 serial_update_irq();
1595 if (s->lcr & UART_LCR_DLAB) {
1596 ret = (s->divider >> 8) & 0xff;
1603 /* reset THR pending bit */
1604 if ((ret & 0x7) == UART_IIR_THRI)
1605 s->thr_ipending = 0;
1606 serial_update_irq();
1618 if (s->mcr & UART_MCR_LOOP) {
1619 /* in loopback, the modem output pins are connected to the
1621 ret = (s->mcr & 0x0c) << 4;
1622 ret |= (s->mcr & 0x02) << 3;
1623 ret |= (s->mcr & 0x01) << 5;
1633 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
1638 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1639 static int term_got_escape, term_command;
1640 static unsigned char term_cmd_buf[128];
1642 typedef struct term_cmd_t {
1643 const unsigned char *name;
1644 void (*handler)(unsigned char *params);
1647 static void do_change_cdrom (unsigned char *params);
1648 static void do_change_fd0 (unsigned char *params);
1649 static void do_change_fd1 (unsigned char *params);
1651 static term_cmd_t term_cmds[] = {
1652 { "changecd", &do_change_cdrom, },
1653 { "changefd0", &do_change_fd0, },
1654 { "changefd1", &do_change_fd1, },
1658 void term_print_help(void)
1661 "C-a h print this help\n"
1662 "C-a x exit emulatior\n"
1663 "C-a d switch on/off debug log\n"
1664 "C-a s save disk data back to file (if -snapshot)\n"
1665 "C-a b send break (magic sysrq)\n"
1666 "C-a c send qemu internal command\n"
1667 "C-a C-a send C-a\n"
1671 static void do_change_cdrom (unsigned char *params)
1673 /* Dunno how to do it... */
1676 static void do_change_fd (int fd, unsigned char *params)
1678 unsigned char *name_start, *name_end, *ros;
1681 for (name_start = params;
1682 isspace(*name_start); name_start++)
1684 if (*name_start == '\0')
1686 for (name_end = name_start;
1687 !isspace(*name_end) && *name_end != '\0'; name_end++)
1689 for (ros = name_end + 1; isspace(*ros); ros++)
1691 if (ros[0] == 'r' && ros[1] == 'o')
1696 printf("Change fd %d to %s (%s)\n", fd, name_start, params);
1697 fdctrl_disk_change(fd, name_start, ro);
1700 static void do_change_fd0 (unsigned char *params)
1702 do_change_fd(0, params);
1705 static void do_change_fd1 (unsigned char *params)
1707 do_change_fd(1, params);
1710 static void serial_treat_command ()
1712 unsigned char *cmd_start, *cmd_end;
1715 for (cmd_start = term_cmd_buf; isspace(*cmd_start); cmd_start++)
1717 for (cmd_end = cmd_start;
1718 !isspace(*cmd_end) && *cmd_end != '\0'; cmd_end++)
1720 for (i = 0; term_cmds[i].name != NULL; i++) {
1721 if (strlen(term_cmds[i].name) == (cmd_end - cmd_start) &&
1722 memcmp(term_cmds[i].name, cmd_start, cmd_end - cmd_start) == 0) {
1723 (*term_cmds[i].handler)(cmd_end + 1);
1728 printf("Unknown term command: %s\n", cmd_start);
1731 extern FILE *logfile;
1733 /* called when a char is received */
1734 void serial_received_byte(SerialState *s, int ch)
1737 if (ch == '\n' || ch == '\r' || term_command == 127) {
1739 serial_treat_command();
1742 if (ch == 0x7F || ch == 0x08) {
1743 if (term_command > 1) {
1744 term_cmd_buf[--term_command - 1] = '\0';
1747 printf("\r> %s", term_cmd_buf);
1749 } else if (ch > 0x1f) {
1750 term_cmd_buf[term_command++ - 1] = ch;
1751 term_cmd_buf[term_command - 1] = '\0';
1752 printf("\r> %s", term_cmd_buf);
1756 } else if (term_got_escape) {
1757 term_got_escape = 0;
1768 for (i = 0; i < MAX_DISKS; i++) {
1770 bdrv_commit(bs_table[i]);
1777 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1778 serial_update_irq();
1786 cpu_set_log(CPU_LOG_ALL);
1791 } else if (ch == TERM_ESCAPE) {
1792 term_got_escape = 1;
1796 s->lsr |= UART_LSR_DR;
1797 serial_update_irq();
1801 void serial_init(void)
1803 SerialState *s = &serial_ports[0];
1805 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1806 s->iir = UART_IIR_NO_INT;
1808 #if defined(TARGET_I386) || defined (TARGET_PPC)
1809 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1810 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1814 /***********************************************************/
1815 /* ne2000 emulation */
1817 #if defined (TARGET_I386)
1818 #define NE2000_IOPORT 0x300
1819 #define NE2000_IRQ 9
1821 #define MAX_ETH_FRAME_SIZE 1514
1823 #define E8390_CMD 0x00 /* The command register (for all pages) */
1824 /* Page 0 register offsets. */
1825 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1826 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1827 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1828 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1829 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1830 #define EN0_TSR 0x04 /* Transmit status reg RD */
1831 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1832 #define EN0_NCR 0x05 /* Number of collision reg RD */
1833 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1834 #define EN0_FIFO 0x06 /* FIFO RD */
1835 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1836 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1837 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1838 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1839 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1840 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1841 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1842 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1843 #define EN0_RSR 0x0c /* rx status reg RD */
1844 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1845 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1846 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1847 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1848 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1849 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1850 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1852 #define EN1_PHYS 0x11
1853 #define EN1_CURPAG 0x17
1854 #define EN1_MULT 0x18
1856 /* Register accessed at EN_CMD, the 8390 base addr. */
1857 #define E8390_STOP 0x01 /* Stop and reset the chip */
1858 #define E8390_START 0x02 /* Start the chip, clear reset */
1859 #define E8390_TRANS 0x04 /* Transmit a frame */
1860 #define E8390_RREAD 0x08 /* Remote read */
1861 #define E8390_RWRITE 0x10 /* Remote write */
1862 #define E8390_NODMA 0x20 /* Remote DMA */
1863 #define E8390_PAGE0 0x00 /* Select page chip registers */
1864 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1865 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1867 /* Bits in EN0_ISR - Interrupt status register */
1868 #define ENISR_RX 0x01 /* Receiver, no error */
1869 #define ENISR_TX 0x02 /* Transmitter, no error */
1870 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1871 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1872 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1873 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1874 #define ENISR_RDC 0x40 /* remote dma complete */
1875 #define ENISR_RESET 0x80 /* Reset completed */
1876 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1878 /* Bits in received packet status byte and EN0_RSR*/
1879 #define ENRSR_RXOK 0x01 /* Received a good packet */
1880 #define ENRSR_CRC 0x02 /* CRC error */
1881 #define ENRSR_FAE 0x04 /* frame alignment error */
1882 #define ENRSR_FO 0x08 /* FIFO overrun */
1883 #define ENRSR_MPA 0x10 /* missed pkt */
1884 #define ENRSR_PHY 0x20 /* physical/multicast address */
1885 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1886 #define ENRSR_DEF 0x80 /* deferring */
1888 /* Transmitted packet status, EN0_TSR. */
1889 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1890 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1891 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1892 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1893 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1894 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1895 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1896 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1898 #define NE2000_MEM_SIZE 32768
1900 typedef struct NE2000State {
1913 uint8_t phys[6]; /* mac address */
1915 uint8_t mult[8]; /* multicast mask array */
1916 uint8_t mem[NE2000_MEM_SIZE];
1919 NE2000State ne2000_state;
1921 char network_script[1024];
1923 void ne2000_reset(void)
1925 NE2000State *s = &ne2000_state;
1928 s->isr = ENISR_RESET;
1938 /* duplicate prom data */
1939 for(i = 15;i >= 0; i--) {
1940 s->mem[2 * i] = s->mem[i];
1941 s->mem[2 * i + 1] = s->mem[i];
1945 void ne2000_update_irq(NE2000State *s)
1948 isr = s->isr & s->imr;
1950 pic_set_irq(NE2000_IRQ, 1);
1952 pic_set_irq(NE2000_IRQ, 0);
1958 int fd, ret, pid, status;
1960 fd = open("/dev/net/tun", O_RDWR);
1962 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1965 memset(&ifr, 0, sizeof(ifr));
1966 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1967 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1968 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1970 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1974 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1975 fcntl(fd, F_SETFL, O_NONBLOCK);
1978 /* try to launch network init script */
1982 execl(network_script, network_script, ifr.ifr_name, NULL);
1985 while (waitpid(pid, &status, 0) != pid);
1986 if (!WIFEXITED(status) ||
1987 WEXITSTATUS(status) != 0) {
1988 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1989 network_script, ifr.ifr_name);
1995 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1998 printf("NE2000: sending packet size=%d\n", size);
2000 write(net_fd, buf, size);
2003 /* return true if the NE2000 can receive more data */
2004 int ne2000_can_receive(NE2000State *s)
2006 int avail, index, boundary;
2008 if (s->cmd & E8390_STOP)
2010 index = s->curpag << 8;
2011 boundary = s->boundary << 8;
2012 if (index < boundary)
2013 avail = boundary - index;
2015 avail = (s->stop - s->start) - (index - boundary);
2016 if (avail < (MAX_ETH_FRAME_SIZE + 4))
2021 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
2024 int total_len, next, avail, len, index;
2026 #if defined(DEBUG_NE2000)
2027 printf("NE2000: received len=%d\n", size);
2030 index = s->curpag << 8;
2031 /* 4 bytes for header */
2032 total_len = size + 4;
2033 /* address for next packet (4 bytes for CRC) */
2034 next = index + ((total_len + 4 + 255) & ~0xff);
2035 if (next >= s->stop)
2036 next -= (s->stop - s->start);
2037 /* prepare packet header */
2039 p[0] = ENRSR_RXOK; /* receive status */
2042 p[3] = total_len >> 8;
2045 /* write packet data */
2047 avail = s->stop - index;
2051 memcpy(s->mem + index, buf, len);
2054 if (index == s->stop)
2058 s->curpag = next >> 8;
2060 /* now we can signal we have receive something */
2062 ne2000_update_irq(s);
2065 void ne2000_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
2067 NE2000State *s = &ne2000_state;
2072 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
2074 if (addr == E8390_CMD) {
2075 /* control register */
2077 if (val & E8390_START) {
2078 /* test specific case: zero length transfert */
2079 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
2081 s->isr |= ENISR_RDC;
2082 ne2000_update_irq(s);
2084 if (val & E8390_TRANS) {
2085 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
2086 /* signal end of transfert */
2089 ne2000_update_irq(s);
2094 offset = addr | (page << 4);
2097 s->start = val << 8;
2107 ne2000_update_irq(s);
2113 s->tcnt = (s->tcnt & 0xff00) | val;
2116 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
2119 s->rsar = (s->rsar & 0xff00) | val;
2122 s->rsar = (s->rsar & 0x00ff) | (val << 8);
2125 s->rcnt = (s->rcnt & 0xff00) | val;
2128 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
2135 ne2000_update_irq(s);
2137 case EN1_PHYS ... EN1_PHYS + 5:
2138 s->phys[offset - EN1_PHYS] = val;
2143 case EN1_MULT ... EN1_MULT + 7:
2144 s->mult[offset - EN1_MULT] = val;
2150 uint32_t ne2000_ioport_read(CPUState *env, uint32_t addr)
2152 NE2000State *s = &ne2000_state;
2153 int offset, page, ret;
2156 if (addr == E8390_CMD) {
2160 offset = addr | (page << 4);
2171 case EN1_PHYS ... EN1_PHYS + 5:
2172 ret = s->phys[offset - EN1_PHYS];
2177 case EN1_MULT ... EN1_MULT + 7:
2178 ret = s->mult[offset - EN1_MULT];
2186 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
2191 void ne2000_asic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
2193 NE2000State *s = &ne2000_state;
2197 printf("NE2000: asic write val=0x%04x\n", val);
2199 p = s->mem + s->rsar;
2200 if (s->dcfg & 0x01) {
2213 if (s->rsar == s->stop)
2216 /* signal end of transfert */
2217 s->isr |= ENISR_RDC;
2218 ne2000_update_irq(s);
2222 uint32_t ne2000_asic_ioport_read(CPUState *env, uint32_t addr)
2224 NE2000State *s = &ne2000_state;
2228 p = s->mem + s->rsar;
2229 if (s->dcfg & 0x01) {
2231 ret = p[0] | (p[1] << 8);
2241 if (s->rsar == s->stop)
2244 /* signal end of transfert */
2245 s->isr |= ENISR_RDC;
2246 ne2000_update_irq(s);
2249 printf("NE2000: asic read val=0x%04x\n", ret);
2254 void ne2000_reset_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
2256 /* nothing to do (end of reset pulse) */
2259 uint32_t ne2000_reset_ioport_read(CPUState *env, uint32_t addr)
2265 void ne2000_init(void)
2267 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
2268 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
2270 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
2271 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
2272 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
2273 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
2275 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
2276 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
2281 /***********************************************************/
2282 /* PC floppy disk controler emulation glue */
2283 #define PC_FDC_DMA 0x2
2284 #define PC_FDC_IRQ 0x6
2285 #define PC_FDC_BASE 0x3F0
2287 static void fdctrl_register (unsigned char **disknames, int ro,
2292 fdctrl_init(PC_FDC_IRQ, PC_FDC_DMA, 0, PC_FDC_BASE, boot_device);
2293 for (i = 0; i < MAX_FD; i++) {
2294 if (disknames[i] != NULL)
2295 fdctrl_disk_change(i, disknames[i], ro);
2299 /***********************************************************/
2300 /* keyboard emulation */
2302 /* Keyboard Controller Commands */
2303 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
2304 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
2305 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
2306 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
2307 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
2308 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
2309 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
2310 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
2311 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
2312 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
2313 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
2314 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
2315 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
2316 #define KBD_CCMD_WRITE_OBUF 0xD2
2317 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
2318 initiated by the auxiliary device */
2319 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
2320 #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
2321 #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
2322 #define KBD_CCMD_RESET 0xFE
2324 /* Keyboard Commands */
2325 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
2326 #define KBD_CMD_ECHO 0xEE
2327 #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
2328 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
2329 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
2330 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
2331 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
2332 #define KBD_CMD_RESET 0xFF /* Reset */
2334 /* Keyboard Replies */
2335 #define KBD_REPLY_POR 0xAA /* Power on reset */
2336 #define KBD_REPLY_ACK 0xFA /* Command ACK */
2337 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
2339 /* Status Register Bits */
2340 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
2341 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
2342 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
2343 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
2344 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
2345 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
2346 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
2347 #define KBD_STAT_PERR 0x80 /* Parity error */
2349 /* Controller Mode Register Bits */
2350 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
2351 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
2352 #define KBD_MODE_SYS 0x04 /* The system flag (?) */
2353 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
2354 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
2355 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
2356 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
2357 #define KBD_MODE_RFU 0x80
2359 /* Mouse Commands */
2360 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
2361 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
2362 #define AUX_SET_RES 0xE8 /* Set resolution */
2363 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
2364 #define AUX_SET_STREAM 0xEA /* Set stream mode */
2365 #define AUX_POLL 0xEB /* Poll */
2366 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
2367 #define AUX_SET_WRAP 0xEE /* Set wrap mode */
2368 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
2369 #define AUX_GET_TYPE 0xF2 /* Get type */
2370 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
2371 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
2372 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
2373 #define AUX_SET_DEFAULT 0xF6
2374 #define AUX_RESET 0xFF /* Reset aux device */
2375 #define AUX_ACK 0xFA /* Command byte ACK. */
2377 #define MOUSE_STATUS_REMOTE 0x40
2378 #define MOUSE_STATUS_ENABLED 0x20
2379 #define MOUSE_STATUS_SCALE21 0x10
2381 #define KBD_QUEUE_SIZE 256
2384 uint8_t data[KBD_QUEUE_SIZE];
2385 int rptr, wptr, count;
2388 typedef struct KBDState {
2390 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
2393 /* keyboard state */
2397 int mouse_write_cmd;
2398 uint8_t mouse_status;
2399 uint8_t mouse_resolution;
2400 uint8_t mouse_sample_rate;
2402 uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
2403 uint8_t mouse_detect_state;
2404 int mouse_dx; /* current values, needed for 'poll' mode */
2407 uint8_t mouse_buttons;
2411 int reset_requested;
2413 /* update irq and KBD_STAT_[MOUSE_]OBF */
2414 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
2415 incorrect, but it avoids having to simulate exact delays */
2416 static void kbd_update_irq(KBDState *s)
2418 int irq12_level, irq1_level;
2422 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
2423 if (s->queues[0].count != 0 ||
2424 s->queues[1].count != 0) {
2425 s->status |= KBD_STAT_OBF;
2426 if (s->queues[1].count != 0) {
2427 s->status |= KBD_STAT_MOUSE_OBF;
2428 if (s->mode & KBD_MODE_MOUSE_INT)
2431 if ((s->mode & KBD_MODE_KBD_INT) &&
2432 !(s->mode & KBD_MODE_DISABLE_KBD))
2436 pic_set_irq(1, irq1_level);
2437 pic_set_irq(12, irq12_level);
2440 static void kbd_queue(KBDState *s, int b, int aux)
2442 KBDQueue *q = &kbd_state.queues[aux];
2444 #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
2446 printf("mouse event: 0x%02x\n", b);
2449 printf("kbd event: 0x%02x\n", b);
2452 if (q->count >= KBD_QUEUE_SIZE)
2454 q->data[q->wptr] = b;
2455 if (++q->wptr == KBD_QUEUE_SIZE)
2461 void kbd_put_keycode(int keycode)
2463 KBDState *s = &kbd_state;
2464 kbd_queue(s, keycode, 0);
2467 uint32_t kbd_read_status(CPUState *env, uint32_t addr)
2469 KBDState *s = &kbd_state;
2472 #if defined(DEBUG_KBD)
2473 printf("kbd: read status=0x%02x\n", val);
2478 void kbd_write_command(CPUState *env, uint32_t addr, uint32_t val)
2480 KBDState *s = &kbd_state;
2483 printf("kbd: write cmd=0x%02x\n", val);
2486 case KBD_CCMD_READ_MODE:
2487 kbd_queue(s, s->mode, 0);
2489 case KBD_CCMD_WRITE_MODE:
2490 case KBD_CCMD_WRITE_OBUF:
2491 case KBD_CCMD_WRITE_AUX_OBUF:
2492 case KBD_CCMD_WRITE_MOUSE:
2493 case KBD_CCMD_WRITE_OUTPORT:
2496 case KBD_CCMD_MOUSE_DISABLE:
2497 s->mode |= KBD_MODE_DISABLE_MOUSE;
2499 case KBD_CCMD_MOUSE_ENABLE:
2500 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
2502 case KBD_CCMD_TEST_MOUSE:
2503 kbd_queue(s, 0x00, 0);
2505 case KBD_CCMD_SELF_TEST:
2506 s->status |= KBD_STAT_SELFTEST;
2507 kbd_queue(s, 0x55, 0);
2509 case KBD_CCMD_KBD_TEST:
2510 kbd_queue(s, 0x00, 0);
2512 case KBD_CCMD_KBD_DISABLE:
2513 s->mode |= KBD_MODE_DISABLE_KBD;
2516 case KBD_CCMD_KBD_ENABLE:
2517 s->mode &= ~KBD_MODE_DISABLE_KBD;
2520 case KBD_CCMD_READ_INPORT:
2521 kbd_queue(s, 0x00, 0);
2523 case KBD_CCMD_READ_OUTPORT:
2524 /* XXX: check that */
2526 val = 0x01 | (a20_enabled << 1);
2530 if (s->status & KBD_STAT_OBF)
2532 if (s->status & KBD_STAT_MOUSE_OBF)
2534 kbd_queue(s, val, 0);
2537 case KBD_CCMD_ENABLE_A20:
2538 cpu_x86_set_a20(env, 1);
2540 case KBD_CCMD_DISABLE_A20:
2541 cpu_x86_set_a20(env, 0);
2544 case KBD_CCMD_RESET:
2545 reset_requested = 1;
2546 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
2549 /* ignore that - I don't know what is its use */
2552 fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
2557 uint32_t kbd_read_data(CPUState *env, uint32_t addr)
2559 KBDState *s = &kbd_state;
2563 q = &s->queues[0]; /* first check KBD data */
2565 q = &s->queues[1]; /* then check AUX data */
2566 if (q->count == 0) {
2567 /* NOTE: if no data left, we return the last keyboard one
2568 (needed for EMM386) */
2569 /* XXX: need a timer to do things correctly */
2571 index = q->rptr - 1;
2573 index = KBD_QUEUE_SIZE - 1;
2574 val = q->data[index];
2576 val = q->data[q->rptr];
2577 if (++q->rptr == KBD_QUEUE_SIZE)
2580 /* reading deasserts IRQ */
2581 if (q == &s->queues[0])
2586 /* reassert IRQs if data left */
2589 printf("kbd: read data=0x%02x\n", val);
2594 static void kbd_reset_keyboard(KBDState *s)
2596 s->scan_enabled = 1;
2599 static void kbd_write_keyboard(KBDState *s, int val)
2601 switch(s->kbd_write_cmd) {
2606 kbd_queue(s, KBD_REPLY_ACK, 0);
2609 kbd_queue(s, KBD_REPLY_RESEND, 0);
2611 case KBD_CMD_GET_ID:
2612 kbd_queue(s, KBD_REPLY_ACK, 0);
2613 kbd_queue(s, 0xab, 0);
2614 kbd_queue(s, 0x83, 0);
2617 kbd_queue(s, KBD_CMD_ECHO, 0);
2619 case KBD_CMD_ENABLE:
2620 s->scan_enabled = 1;
2621 kbd_queue(s, KBD_REPLY_ACK, 0);
2623 case KBD_CMD_SET_LEDS:
2624 case KBD_CMD_SET_RATE:
2625 s->kbd_write_cmd = val;
2626 kbd_queue(s, KBD_REPLY_ACK, 0);
2628 case KBD_CMD_RESET_DISABLE:
2629 kbd_reset_keyboard(s);
2630 s->scan_enabled = 0;
2631 kbd_queue(s, KBD_REPLY_ACK, 0);
2633 case KBD_CMD_RESET_ENABLE:
2634 kbd_reset_keyboard(s);
2635 s->scan_enabled = 1;
2636 kbd_queue(s, KBD_REPLY_ACK, 0);
2639 kbd_reset_keyboard(s);
2640 kbd_queue(s, KBD_REPLY_ACK, 0);
2641 kbd_queue(s, KBD_REPLY_POR, 0);
2644 kbd_queue(s, KBD_REPLY_ACK, 0);
2648 case KBD_CMD_SET_LEDS:
2649 kbd_queue(s, KBD_REPLY_ACK, 0);
2650 s->kbd_write_cmd = -1;
2652 case KBD_CMD_SET_RATE:
2653 kbd_queue(s, KBD_REPLY_ACK, 0);
2654 s->kbd_write_cmd = -1;
2659 static void kbd_mouse_send_packet(KBDState *s)
2667 /* XXX: increase range to 8 bits ? */
2670 else if (dx1 < -127)
2674 else if (dy1 < -127)
2676 b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
2678 kbd_queue(s, dx1 & 0xff, 1);
2679 kbd_queue(s, dy1 & 0xff, 1);
2680 /* extra byte for IMPS/2 or IMEX */
2681 switch(s->mouse_type) {
2687 else if (dz1 < -127)
2689 kbd_queue(s, dz1 & 0xff, 1);
2696 b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
2707 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
2709 KBDState *s = &kbd_state;
2711 /* check if deltas are recorded when disabled */
2712 if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
2718 s->mouse_buttons = buttons_state;
2720 if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
2721 (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) {
2723 /* if not remote, send event. Multiple events are sent if
2725 kbd_mouse_send_packet(s);
2726 if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0)
2732 static void kbd_write_mouse(KBDState *s, int val)
2735 printf("kbd: write mouse 0x%02x\n", val);
2737 switch(s->mouse_write_cmd) {
2741 if (s->mouse_wrap) {
2742 if (val == AUX_RESET_WRAP) {
2744 kbd_queue(s, AUX_ACK, 1);
2746 } else if (val != AUX_RESET) {
2747 kbd_queue(s, val, 1);
2752 case AUX_SET_SCALE11:
2753 s->mouse_status &= ~MOUSE_STATUS_SCALE21;
2754 kbd_queue(s, AUX_ACK, 1);
2756 case AUX_SET_SCALE21:
2757 s->mouse_status |= MOUSE_STATUS_SCALE21;
2758 kbd_queue(s, AUX_ACK, 1);
2760 case AUX_SET_STREAM:
2761 s->mouse_status &= ~MOUSE_STATUS_REMOTE;
2762 kbd_queue(s, AUX_ACK, 1);
2766 kbd_queue(s, AUX_ACK, 1);
2768 case AUX_SET_REMOTE:
2769 s->mouse_status |= MOUSE_STATUS_REMOTE;
2770 kbd_queue(s, AUX_ACK, 1);
2773 kbd_queue(s, AUX_ACK, 1);
2774 kbd_queue(s, s->mouse_type, 1);
2777 case AUX_SET_SAMPLE:
2778 s->mouse_write_cmd = val;
2779 kbd_queue(s, AUX_ACK, 1);
2782 kbd_queue(s, AUX_ACK, 1);
2783 kbd_queue(s, s->mouse_status, 1);
2784 kbd_queue(s, s->mouse_resolution, 1);
2785 kbd_queue(s, s->mouse_sample_rate, 1);
2788 kbd_queue(s, AUX_ACK, 1);
2789 kbd_mouse_send_packet(s);
2791 case AUX_ENABLE_DEV:
2792 s->mouse_status |= MOUSE_STATUS_ENABLED;
2793 kbd_queue(s, AUX_ACK, 1);
2795 case AUX_DISABLE_DEV:
2796 s->mouse_status &= ~MOUSE_STATUS_ENABLED;
2797 kbd_queue(s, AUX_ACK, 1);
2799 case AUX_SET_DEFAULT:
2800 s->mouse_sample_rate = 100;
2801 s->mouse_resolution = 2;
2802 s->mouse_status = 0;
2803 kbd_queue(s, AUX_ACK, 1);
2806 s->mouse_sample_rate = 100;
2807 s->mouse_resolution = 2;
2808 s->mouse_status = 0;
2809 kbd_queue(s, AUX_ACK, 1);
2810 kbd_queue(s, 0xaa, 1);
2811 kbd_queue(s, s->mouse_type, 1);
2817 case AUX_SET_SAMPLE:
2818 s->mouse_sample_rate = val;
2820 /* detect IMPS/2 or IMEX */
2821 switch(s->mouse_detect_state) {
2825 s->mouse_detect_state = 1;
2829 s->mouse_detect_state = 2;
2830 else if (val == 200)
2831 s->mouse_detect_state = 3;
2833 s->mouse_detect_state = 0;
2837 s->mouse_type = 3; /* IMPS/2 */
2838 s->mouse_detect_state = 0;
2842 s->mouse_type = 4; /* IMEX */
2843 s->mouse_detect_state = 0;
2847 kbd_queue(s, AUX_ACK, 1);
2848 s->mouse_write_cmd = -1;
2851 s->mouse_resolution = val;
2852 kbd_queue(s, AUX_ACK, 1);
2853 s->mouse_write_cmd = -1;
2858 void kbd_write_data(CPUState *env, uint32_t addr, uint32_t val)
2860 KBDState *s = &kbd_state;
2863 printf("kbd: write data=0x%02x\n", val);
2866 switch(s->write_cmd) {
2868 kbd_write_keyboard(s, val);
2870 case KBD_CCMD_WRITE_MODE:
2874 case KBD_CCMD_WRITE_OBUF:
2875 kbd_queue(s, val, 0);
2877 case KBD_CCMD_WRITE_AUX_OBUF:
2878 kbd_queue(s, val, 1);
2880 case KBD_CCMD_WRITE_OUTPORT:
2882 cpu_x86_set_a20(env, (val >> 1) & 1);
2885 reset_requested = 1;
2886 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
2889 case KBD_CCMD_WRITE_MOUSE:
2890 kbd_write_mouse(s, val);
2898 void kbd_reset(KBDState *s)
2903 s->kbd_write_cmd = -1;
2904 s->mouse_write_cmd = -1;
2905 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
2906 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
2907 for(i = 0; i < 2; i++) {
2917 kbd_reset(&kbd_state);
2918 #if defined (TARGET_I386) || defined (TARGET_PPC)
2919 register_ioport_read(0x60, 1, kbd_read_data, 1);
2920 register_ioport_write(0x60, 1, kbd_write_data, 1);
2921 register_ioport_read(0x64, 1, kbd_read_status, 1);
2922 register_ioport_write(0x64, 1, kbd_write_command, 1);
2926 /***********************************************************/
2927 /* Bochs BIOS debug ports */
2929 void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
2932 /* Bochs BIOS messages */
2935 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
2940 fprintf(stderr, "%c", val);
2944 /* LGPL'ed VGA BIOS messages */
2947 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
2952 fprintf(stderr, "%c", val);
2958 void bochs_bios_init(void)
2960 register_ioport_write(0x400, 1, bochs_bios_write, 2);
2961 register_ioport_write(0x401, 1, bochs_bios_write, 2);
2962 register_ioport_write(0x402, 1, bochs_bios_write, 1);
2963 register_ioport_write(0x403, 1, bochs_bios_write, 1);
2965 register_ioport_write(0x501, 1, bochs_bios_write, 2);
2966 register_ioport_write(0x502, 1, bochs_bios_write, 2);
2967 register_ioport_write(0x500, 1, bochs_bios_write, 1);
2968 register_ioport_write(0x503, 1, bochs_bios_write, 1);
2972 /***********************************************************/
2975 /* init terminal so that we can grab keys */
2976 static struct termios oldtty;
2978 static void term_exit(void)
2980 tcsetattr (0, TCSANOW, &oldtty);
2983 static void term_init(void)
2987 tcgetattr (0, &tty);
2990 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
2991 |INLCR|IGNCR|ICRNL|IXON);
2992 tty.c_oflag |= OPOST;
2993 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN);
2994 /* if graphical mode, we allow Ctrl-C handling */
2996 tty.c_lflag &= ~ISIG;
2997 tty.c_cflag &= ~(CSIZE|PARENB);
3000 tty.c_cc[VTIME] = 0;
3002 tcsetattr (0, TCSANOW, &tty);
3006 fcntl(0, F_SETFL, O_NONBLOCK);
3009 static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
3013 static void dumb_resize(DisplayState *ds, int w, int h)
3017 static void dumb_refresh(DisplayState *ds)
3019 vga_update_display();
3022 void dumb_display_init(DisplayState *ds)
3027 ds->dpy_update = dumb_update;
3028 ds->dpy_resize = dumb_resize;
3029 ds->dpy_refresh = dumb_refresh;
3032 #if !defined(CONFIG_SOFTMMU)
3033 /***********************************************************/
3034 /* cpu signal handler */
3035 static void host_segv_handler(int host_signum, siginfo_t *info,
3038 if (cpu_signal_handler(host_signum, info, puc))
3045 static int timer_irq_pending;
3046 static int timer_irq_count;
3048 static int timer_ms;
3049 static int gui_refresh_pending, gui_refresh_count;
3051 static void host_alarm_handler(int host_signum, siginfo_t *info,
3054 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
3055 some drift between cpu_get_ticks() and the interrupt time. So
3056 we queue some interrupts to avoid missing some */
3057 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
3058 if (timer_irq_count) {
3059 if (timer_irq_count > 2)
3060 timer_irq_count = 2;
3062 timer_irq_pending = 1;
3064 gui_refresh_count += timer_ms;
3065 if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
3066 gui_refresh_count = 0;
3067 gui_refresh_pending = 1;
3070 /* XXX: seems dangerous to run that here. */
3074 if (gui_refresh_pending || timer_irq_pending) {
3075 /* just exit from the cpu to have a chance to handle timers */
3076 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
3080 #ifdef CONFIG_SOFTMMU
3081 void *get_mmap_addr(unsigned long size)
3086 unsigned long mmap_addr = PHYS_RAM_BASE;
3088 void *get_mmap_addr(unsigned long size)
3092 mmap_addr += ((size + 4095) & ~4095) + 4096;
3093 return (void *)addr;
3097 /* main execution loop */
3099 CPUState *cpu_gdbstub_get_env(void *opaque)
3104 int main_loop(void *opaque)
3106 struct pollfd ufds[3], *pf, *serial_ufd, *gdb_ufd;
3107 #if defined (TARGET_I386)
3108 struct pollfd *net_ufd;
3110 int ret, n, timeout, serial_ok;
3112 CPUState *env = global_env;
3115 /* initialize terminal only there so that the user has a
3116 chance to stop QEMU with Ctrl-C before the gdb connection
3125 #if defined (DO_TB_FLUSH)
3128 ret = cpu_exec(env);
3129 if (reset_requested) {
3130 ret = EXCP_INTERRUPT;
3133 if (ret == EXCP_DEBUG) {
3137 /* if hlt instruction, we wait until the next IRQ */
3138 if (ret == EXCP_HLT)
3142 /* poll any events */
3145 if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) {
3148 pf->events = POLLIN;
3151 #if defined (TARGET_I386)
3153 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
3156 pf->events = POLLIN;
3161 if (gdbstub_fd > 0) {
3163 pf->fd = gdbstub_fd;
3164 pf->events = POLLIN;
3168 ret = poll(ufds, pf - ufds, timeout);
3170 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
3171 n = read(0, &ch, 1);
3173 serial_received_byte(&serial_ports[0], ch);
3175 /* Closed, stop polling. */
3179 #if defined (TARGET_I386)
3180 if (net_ufd && (net_ufd->revents & POLLIN)) {
3181 uint8_t buf[MAX_ETH_FRAME_SIZE];
3183 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
3186 memset(buf + n, 0, 60 - n);
3189 ne2000_receive(&ne2000_state, buf, n);
3193 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
3195 /* stop emulation if requested by gdb */
3196 n = read(gdbstub_fd, buf, 1);
3198 ret = EXCP_INTERRUPT;
3205 if (timer_irq_pending) {
3206 #if defined (TARGET_I386)
3209 timer_irq_pending = 0;
3211 if (cmos_data[RTC_REG_B] & 0x50) {
3218 if (gui_refresh_pending) {
3219 display_state.dpy_refresh(&display_state);
3220 gui_refresh_pending = 0;
3223 cpu_disable_ticks();
3229 printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
3230 "usage: %s [options] [disk_image]\n"
3232 "'disk_image' is a raw hard image image for IDE hard disk 0\n"
3234 "Standard options:\n"
3235 "-fda/-fdb file use 'file' as floppy disk 0/1 image\n"
3236 "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n"
3237 "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n"
3238 "-cdrom file use 'file' as IDE cdrom 2 image\n"
3239 "-boot [a|b|c|d] boot on floppy (a, b), hard disk (c) or CD-ROM (d)\n"
3240 "-snapshot write to temporary files instead of disk image files\n"
3241 "-m megs set virtual RAM size to megs MB\n"
3242 "-n script set network init script [default=%s]\n"
3243 "-tun-fd fd this fd talks to tap/tun, use it.\n"
3244 "-nographic disable graphical output\n"
3246 "Linux boot specific (does not require PC BIOS):\n"
3247 "-kernel bzImage use 'bzImage' as kernel image\n"
3248 "-append cmdline use 'cmdline' as kernel command line\n"
3249 "-initrd file use 'file' as initial ram disk\n"
3251 "Debug/Expert options:\n"
3252 "-s wait gdb connection to port %d\n"
3253 "-p port change gdb connection port\n"
3254 "-d output log to %s\n"
3255 "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
3256 "-L path set the directory for the BIOS and VGA BIOS\n"
3258 "During emulation, use C-a h to get terminal commands:\n",
3259 #ifdef CONFIG_SOFTMMU
3264 DEFAULT_NETWORK_SCRIPT,
3265 DEFAULT_GDBSTUB_PORT,
3268 #ifndef CONFIG_SOFTMMU
3270 "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
3271 "work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
3277 struct option long_options[] = {
3278 { "initrd", 1, NULL, 0, },
3279 { "hda", 1, NULL, 0, },
3280 { "hdb", 1, NULL, 0, },
3281 { "snapshot", 0, NULL, 0, },
3282 { "hdachs", 1, NULL, 0, },
3283 { "nographic", 0, NULL, 0, },
3284 { "kernel", 1, NULL, 0, },
3285 { "append", 1, NULL, 0, },
3286 { "tun-fd", 1, NULL, 0, },
3287 { "hdc", 1, NULL, 0, },
3288 { "hdd", 1, NULL, 0, },
3289 { "cdrom", 1, NULL, 0, },
3290 { "boot", 1, NULL, 0, },
3291 { "fda", 1, NULL, 0, },
3292 { "fdb", 1, NULL, 0, },
3293 { NULL, 0, NULL, 0 },
3297 /* SDL use the pthreads and they modify sigaction. We don't
3299 #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2)
3300 extern void __libc_sigaction();
3301 #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
3303 extern void __sigaction();
3304 #define sigaction(sig, act, oact) __sigaction(sig, act, oact)
3306 #endif /* CONFIG_SDL */
3308 int main(int argc, char **argv)
3310 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
3311 int snapshot, linux_boot, total_ram_size;
3312 #if defined (TARGET_I386)
3313 struct linux_params *params;
3315 struct sigaction act;
3316 struct itimerval itv;
3318 const char *initrd_filename;
3319 const char *hd_filename[MAX_DISKS], *fd_filename[MAX_FD];
3320 const char *kernel_filename, *kernel_cmdline;
3321 DisplayState *ds = &display_state;
3323 /* we never want that malloc() uses mmap() */
3324 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
3325 initrd_filename = NULL;
3326 for(i = 0; i < MAX_FD; i++)
3327 fd_filename[i] = NULL;
3328 for(i = 0; i < MAX_DISKS; i++)
3329 hd_filename[i] = NULL;
3330 phys_ram_size = 32 * 1024 * 1024;
3331 vga_ram_size = VGA_RAM_SIZE;
3332 #if defined (TARGET_I386)
3333 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
3336 gdbstub_port = DEFAULT_GDBSTUB_PORT;
3339 kernel_filename = NULL;
3340 kernel_cmdline = "";
3342 c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
3347 switch(long_index) {
3349 initrd_filename = optarg;
3352 hd_filename[0] = optarg;
3355 hd_filename[1] = optarg;
3362 int cyls, heads, secs;
3365 cyls = strtol(p, (char **)&p, 0);
3369 heads = strtol(p, (char **)&p, 0);
3373 secs = strtol(p, (char **)&p, 0);
3376 ide_set_geometry(0, cyls, heads, secs);
3384 kernel_filename = optarg;
3387 kernel_cmdline = optarg;
3389 #if defined (TARGET_I386)
3391 net_fd = atoi(optarg);
3395 hd_filename[2] = optarg;
3398 hd_filename[3] = optarg;
3401 hd_filename[2] = optarg;
3402 ide_set_cdrom(2, 1);
3405 boot_device = optarg[0];
3406 if (boot_device != 'a' && boot_device != 'b' &&
3407 boot_device != 'c' && boot_device != 'd') {
3408 fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device);
3413 fd_filename[0] = optarg;
3416 fd_filename[1] = optarg;
3424 phys_ram_size = atoi(optarg) * 1024 * 1024;
3425 if (phys_ram_size <= 0)
3427 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
3428 fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
3429 PHYS_RAM_MAX_SIZE / (1024 * 1024));
3434 cpu_set_log(CPU_LOG_ALL);
3436 #if defined (TARGET_I386)
3438 pstrcpy(network_script, sizeof(network_script), optarg);
3445 gdbstub_port = atoi(optarg);
3453 if (optind < argc) {
3454 hd_filename[0] = argv[optind++];
3457 linux_boot = (kernel_filename != NULL);
3459 if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0' &&
3460 fd_filename[0] == '\0')
3463 /* boot to cd by default if no hard disk */
3464 if (hd_filename[0] == '\0' && boot_device == 'c') {
3465 if (fd_filename[0] != '\0')
3471 #if !defined(CONFIG_SOFTMMU)
3472 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
3474 static uint8_t stdout_buf[4096];
3475 setvbuf(stdout, stdout_buf, _IOLBF, sizeof(stdout_buf));
3478 setvbuf(stdout, NULL, _IOLBF, 0);
3481 /* init network tun interface */
3482 #if defined (TARGET_I386)
3487 /* init the memory */
3488 total_ram_size = phys_ram_size + vga_ram_size;
3490 #ifdef CONFIG_SOFTMMU
3491 phys_ram_base = malloc(total_ram_size);
3492 if (!phys_ram_base) {
3493 fprintf(stderr, "Could not allocate physical memory\n");
3497 /* as we must map the same page at several addresses, we must use
3502 tmpdir = getenv("QEMU_TMPDIR");
3505 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
3506 if (mkstemp(phys_ram_file) < 0) {
3507 fprintf(stderr, "Could not create temporary memory file '%s'\n",
3511 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
3512 if (phys_ram_fd < 0) {
3513 fprintf(stderr, "Could not open temporary memory file '%s'\n",
3517 ftruncate(phys_ram_fd, total_ram_size);
3518 unlink(phys_ram_file);
3519 phys_ram_base = mmap(get_mmap_addr(total_ram_size),
3521 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
3523 if (phys_ram_base == MAP_FAILED) {
3524 fprintf(stderr, "Could not map physical memory\n");
3530 /* open the virtual block devices */
3531 for(i = 0; i < MAX_DISKS; i++) {
3532 if (hd_filename[i]) {
3533 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
3535 fprintf(stderr, "qemu: could not open hard disk image '%s\n",
3542 /* init CPU state */
3545 cpu_single_env = env;
3550 cpu_register_physical_memory(0, phys_ram_size, 0);
3553 /* now we can load the kernel */
3554 ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
3556 fprintf(stderr, "qemu: could not load kernel '%s'\n",
3563 if (initrd_filename) {
3564 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
3565 if (initrd_size < 0) {
3566 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3572 /* init kernel params */
3574 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
3575 memset(params, 0, sizeof(struct linux_params));
3576 params->mount_root_rdonly = 0;
3577 stw_raw(¶ms->cl_magic, 0xA33F);
3578 stw_raw(¶ms->cl_offset, params->commandline - (uint8_t *)params);
3579 stl_raw(¶ms->alt_mem_k, (phys_ram_size / 1024) - 1024);
3580 pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline);
3581 params->loader_type = 0x01;
3582 if (initrd_size > 0) {
3583 stl_raw(¶ms->initrd_start, INITRD_LOAD_ADDR);
3584 stl_raw(¶ms->initrd_size, initrd_size);
3586 params->orig_video_lines = 25;
3587 params->orig_video_cols = 80;
3589 /* setup basic memory access */
3590 env->cr[0] = 0x00000033;
3591 env->hflags |= HF_PE_MASK;
3592 cpu_x86_init_mmu(env);
3594 memset(params->idt_table, 0, sizeof(params->idt_table));
3596 stq_raw(¶ms->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3597 stq_raw(¶ms->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */
3598 /* for newer kernels (2.6.0) CS/DS are at different addresses */
3599 stq_raw(¶ms->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3600 stq_raw(¶ms->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */
3602 env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base);
3603 env->idt.limit = sizeof(params->idt_table) - 1;
3604 env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base);
3605 env->gdt.limit = sizeof(params->gdt_table) - 1;
3607 cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00);
3608 cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3609 cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3610 cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3611 cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3612 cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3614 env->eip = KERNEL_LOAD_ADDR;
3615 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
3617 #elif defined (TARGET_PPC)
3618 cpu_x86_init_mmu(env);
3619 PPC_init_hw(env, phys_ram_size, KERNEL_LOAD_ADDR, ret,
3620 KERNEL_STACK_ADDR, boot_device);
3626 #if defined(TARGET_I386)
3628 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
3629 ret = load_image(buf, phys_ram_base + 0x000f0000);
3630 if (ret != 0x10000) {
3631 fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
3636 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
3637 ret = load_image(buf, phys_ram_base + 0x000c0000);
3639 /* setup basic memory access */
3640 env->cr[0] = 0x60000010;
3641 cpu_x86_init_mmu(env);
3643 cpu_register_physical_memory(0xc0000, 0x10000, 0xc0000 | IO_MEM_ROM);
3644 cpu_register_physical_memory(0xf0000, 0x10000, 0xf0000 | IO_MEM_ROM);
3646 env->idt.limit = 0xffff;
3647 env->gdt.limit = 0xffff;
3648 env->ldt.limit = 0xffff;
3649 env->ldt.flags = DESC_P_MASK;
3650 env->tr.limit = 0xffff;
3651 env->tr.flags = DESC_P_MASK;
3653 /* not correct (CS base=0xffff0000) */
3654 cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
3655 cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
3656 cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
3657 cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
3658 cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
3659 cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
3662 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
3667 #elif defined(TARGET_PPC)
3668 cpu_x86_init_mmu(env);
3670 // snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
3671 snprintf(buf, sizeof(buf), "%s", BIOS_FILENAME);
3672 printf("load BIOS at %p\n", phys_ram_base + 0x000f0000);
3673 ret = load_image(buf, phys_ram_base + 0x000f0000);
3674 if (ret != 0x10000) {
3675 fprintf(stderr, "qemu: could not load PPC bios '%s' (%d)\n%m\n",
3684 dumb_display_init(ds);
3687 sdl_display_init(ds);
3689 dumb_display_init(ds);
3692 /* init basic PC hardware */
3693 register_ioport_write(0x80, 1, ioport80_write, 1);
3695 vga_initialize(ds, phys_ram_base + phys_ram_size, phys_ram_size,
3697 #if defined (TARGET_I386)
3703 #if defined (TARGET_I386)
3710 #if defined (TARGET_I386)
3713 #if defined (TARGET_PPC)
3716 fdctrl_register((unsigned char **)fd_filename, snapshot, boot_device);
3717 /* setup cpu signal handlers for MMU / self modifying code handling */
3718 sigfillset(&act.sa_mask);
3719 act.sa_flags = SA_SIGINFO;
3720 #if !defined(CONFIG_SOFTMMU)
3721 act.sa_sigaction = host_segv_handler;
3722 sigaction(SIGSEGV, &act, NULL);
3723 sigaction(SIGBUS, &act, NULL);
3726 act.sa_sigaction = host_alarm_handler;
3727 sigaction(SIGALRM, &act, NULL);
3729 itv.it_interval.tv_sec = 0;
3730 itv.it_interval.tv_usec = 1000;
3731 itv.it_value.tv_sec = 0;
3732 itv.it_value.tv_usec = 10 * 1000;
3733 setitimer(ITIMER_REAL, &itv, NULL);
3734 /* we probe the tick duration of the kernel to inform the user if
3735 the emulated kernel requested a too high timer frequency */
3736 getitimer(ITIMER_REAL, &itv);
3737 timer_ms = itv.it_interval.tv_usec / 1000;
3738 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
3742 cpu_gdbstub(NULL, main_loop, gdbstub_port);