2 * QEMU PC System Emulator
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
45 #include <linux/if_tun.h>
53 #define DEBUG_LOGFILE "/tmp/vl.log"
54 #define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup"
56 //#define DEBUG_UNUSED_IOPORT
58 #define PHYS_RAM_BASE 0xa8000000
59 #define KERNEL_LOAD_ADDR 0x00100000
60 #define INITRD_LOAD_ADDR 0x00400000
61 #define KERNEL_PARAMS_ADDR 0x00090000
63 /* from plex86 (BSD license) */
64 struct __attribute__ ((packed)) linux_params {
65 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
66 // I just padded out the VESA parts, rather than define them.
68 /* 0x000 */ uint8_t orig_x;
69 /* 0x001 */ uint8_t orig_y;
70 /* 0x002 */ uint16_t ext_mem_k;
71 /* 0x004 */ uint16_t orig_video_page;
72 /* 0x006 */ uint8_t orig_video_mode;
73 /* 0x007 */ uint8_t orig_video_cols;
74 /* 0x008 */ uint16_t unused1;
75 /* 0x00a */ uint16_t orig_video_ega_bx;
76 /* 0x00c */ uint16_t unused2;
77 /* 0x00e */ uint8_t orig_video_lines;
78 /* 0x00f */ uint8_t orig_video_isVGA;
79 /* 0x010 */ uint16_t orig_video_points;
80 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
81 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
82 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
83 // is calculated as 0x90000 + cl_offset, bu
84 // only if cl_magic == 0xA33F.
85 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
87 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
88 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
90 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
91 // Might be truncated?
92 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
93 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
95 // System description table truncated to 16 bytes
96 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
97 /* 0x0a0 */ uint16_t sys_description_len;
98 /* 0x0a2 */ uint8_t sys_description_table[14];
100 // [1] machine submodel id
104 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
105 /* 0x1e0 */ uint32_t alt_mem_k;
106 /* 0x1e4 */ uint8_t pad4[4];
107 /* 0x1e8 */ uint8_t e820map_entries;
108 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
109 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
110 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
111 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
112 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
113 // (b)zImage-file (in 16 byte units, rounded up)
114 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
115 /* 0x1f8 */ uint16_t ramdisk_flags;
116 /* 0x1fa */ uint16_t vga_mode; // (old one)
117 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
118 /* 0x1fe */ uint8_t pad6[1];
119 /* 0x1ff */ uint8_t aux_device_info;
120 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
121 // aka "reserved" field.
122 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
123 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
124 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
125 // boot loaders, look there.
126 /* 0x210 */ uint8_t loader_type;
131 // T=2: bootsect-loader
135 /* 0x211 */ uint8_t loadflags;
136 // bit0 = 1: kernel is loaded high (bzImage)
137 // bit7 = 1: Heap and pointer (see below) set by boot
139 /* 0x212 */ uint16_t setup_S_temp1;
140 /* 0x214 */ uint32_t kernel_start;
141 /* 0x218 */ uint32_t initrd_start;
142 /* 0x21c */ uint32_t initrd_size;
143 /* 0x220 */ uint8_t setup_S_temp2[4];
144 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
145 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
147 /* 0x2d0 : Int 15, ax=e820 memory map. */
148 // (linux/include/asm-i386/e820.h, 'struct e820entry')
151 #define E820_RESERVED 2
152 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
160 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
162 // BIOS Enhanced Disk Drive Services.
163 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
164 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
165 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
167 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
168 /* 0x800 */ uint8_t commandline[0x800];
171 uint64_t gdt_table[256];
172 uint64_t idt_table[48];
175 #define KERNEL_CS 0x10
176 #define KERNEL_DS 0x18
178 typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data);
179 typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
181 #define MAX_IOPORTS 4096
183 char phys_ram_file[1024];
184 CPUX86State *global_env;
185 CPUX86State *cpu_single_env;
186 FILE *logfile = NULL;
188 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
189 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
191 /***********************************************************/
194 uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
196 #ifdef DEBUG_UNUSED_IOPORT
197 fprintf(stderr, "inb: port=0x%04x\n", address);
202 void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
204 #ifdef DEBUG_UNUSED_IOPORT
205 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
209 /* default is to make two byte accesses */
210 uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
213 data = ioport_read_table[0][address](env, address);
214 data |= ioport_read_table[0][address + 1](env, address + 1) << 8;
218 void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
220 ioport_write_table[0][address](env, address, data & 0xff);
221 ioport_write_table[0][address + 1](env, address + 1, (data >> 8) & 0xff);
224 uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
226 #ifdef DEBUG_UNUSED_IOPORT
227 fprintf(stderr, "inl: port=0x%04x\n", address);
232 void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
234 #ifdef DEBUG_UNUSED_IOPORT
235 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
239 void init_ioports(void)
243 for(i = 0; i < MAX_IOPORTS; i++) {
244 ioport_read_table[0][i] = default_ioport_readb;
245 ioport_write_table[0][i] = default_ioport_writeb;
246 ioport_read_table[1][i] = default_ioport_readw;
247 ioport_write_table[1][i] = default_ioport_writew;
248 ioport_read_table[2][i] = default_ioport_readl;
249 ioport_write_table[2][i] = default_ioport_writel;
253 /* size is the word size in byte */
254 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
266 for(i = start; i < start + length; i += size)
267 ioport_read_table[bsize][i] = func;
271 /* size is the word size in byte */
272 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
284 for(i = start; i < start + length; i += size)
285 ioport_write_table[bsize][i] = func;
289 void pstrcpy(char *buf, int buf_size, const char *str)
299 if (c == 0 || q >= buf + buf_size - 1)
306 /* strcat and truncate. */
307 char *pstrcat(char *buf, int buf_size, const char *s)
312 pstrcpy(buf + len, buf_size - len, s);
316 int load_kernel(const char *filename, uint8_t *addr)
318 int fd, size, setup_sects;
319 uint8_t bootsect[512];
321 fd = open(filename, O_RDONLY);
324 if (read(fd, bootsect, 512) != 512)
326 setup_sects = bootsect[0x1F1];
329 /* skip 16 bit setup code */
330 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
331 size = read(fd, addr, 16 * 1024 * 1024);
341 /* return the size or -1 if error */
342 int load_image(const char *filename, uint8_t *addr)
345 fd = open(filename, O_RDONLY);
348 size = lseek(fd, 0, SEEK_END);
349 lseek(fd, 0, SEEK_SET);
350 if (read(fd, addr, size) != size) {
358 void cpu_x86_outb(CPUX86State *env, int addr, int val)
360 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
363 void cpu_x86_outw(CPUX86State *env, int addr, int val)
365 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
368 void cpu_x86_outl(CPUX86State *env, int addr, int val)
370 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
373 int cpu_x86_inb(CPUX86State *env, int addr)
375 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
378 int cpu_x86_inw(CPUX86State *env, int addr)
380 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
383 int cpu_x86_inl(CPUX86State *env, int addr)
385 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
388 /***********************************************************/
389 void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
393 void hw_error(const char *fmt, ...)
398 fprintf(stderr, "qemu: hardware error: ");
399 vfprintf(stderr, fmt, ap);
400 fprintf(stderr, "\n");
402 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
408 /***********************************************************/
410 static uint8_t vga_index;
411 static uint8_t vga_regs[256];
412 static int last_cursor_pos;
414 void update_console_messages(void)
416 int c, i, cursor_pos, eol;
418 cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8);
420 for(i = last_cursor_pos; i < cursor_pos; i++) {
421 c = phys_ram_base[0xb8000 + (i) * 2];
432 last_cursor_pos = cursor_pos;
435 /* just to see first Linux console messages, we intercept cursor position */
436 void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
443 vga_regs[vga_index] = data;
444 if (vga_index == 0x0f)
445 update_console_messages();
451 /***********************************************************/
454 #define RTC_SECONDS 0
455 #define RTC_SECONDS_ALARM 1
456 #define RTC_MINUTES 2
457 #define RTC_MINUTES_ALARM 3
459 #define RTC_HOURS_ALARM 5
460 #define RTC_ALARM_DONT_CARE 0xC0
462 #define RTC_DAY_OF_WEEK 6
463 #define RTC_DAY_OF_MONTH 7
472 /* PC cmos mappings */
473 #define REG_EQUIPMENT_BYTE 0x14
475 uint8_t cmos_data[128];
478 void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
481 cmos_index = data & 0x7f;
485 uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
492 /* toggle update-in-progress bit for Linux (same hack as
494 ret = cmos_data[cmos_index];
495 if (cmos_index == RTC_REG_A)
496 cmos_data[RTC_REG_A] ^= 0x80;
497 else if (cmos_index == RTC_REG_C)
498 cmos_data[RTC_REG_C] = 0x00;
504 static inline int to_bcd(int a)
506 return ((a / 10) << 4) | (a % 10);
516 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
517 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
518 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
519 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
520 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
521 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon);
522 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
524 cmos_data[RTC_REG_A] = 0x26;
525 cmos_data[RTC_REG_B] = 0x02;
526 cmos_data[RTC_REG_C] = 0x00;
527 cmos_data[RTC_REG_D] = 0x80;
529 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
531 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
532 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
535 /***********************************************************/
536 /* 8259 pic emulation */
538 typedef struct PicState {
539 uint8_t last_irr; /* edge detection */
540 uint8_t irr; /* interrupt request register */
541 uint8_t imr; /* interrupt mask register */
542 uint8_t isr; /* interrupt service register */
543 uint8_t priority_add; /* used to compute irq priority */
545 uint8_t read_reg_select;
546 uint8_t special_mask;
549 uint8_t rotate_on_autoeoi;
550 uint8_t init4; /* true if 4 byte init */
553 /* 0 is master pic, 1 is slave pic */
555 int pic_irq_requested;
557 /* set irq level. If an edge is detected, then the IRR is set to 1 */
558 static inline void pic_set_irq1(PicState *s, int irq, int level)
563 if ((s->last_irr & mask) == 0)
567 s->last_irr &= ~mask;
571 static inline int get_priority(PicState *s, int mask)
577 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
582 /* return the pic wanted interrupt. return -1 if none */
583 static int pic_get_irq(PicState *s)
585 int mask, cur_priority, priority;
587 mask = s->irr & ~s->imr;
588 priority = get_priority(s, mask);
591 /* compute current priority */
592 cur_priority = get_priority(s, s->isr);
593 if (priority > cur_priority) {
594 /* higher priority found: an irq should be generated */
601 void pic_set_irq(int irq, int level)
603 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
606 /* can be called at any time outside cpu_exec() to raise irqs if
608 void pic_handle_irq(void)
612 /* first look at slave pic */
613 irq2 = pic_get_irq(&pics[1]);
615 /* if irq request by slave pic, signal master PIC */
616 pic_set_irq1(&pics[0], 2, 1);
617 pic_set_irq1(&pics[0], 2, 0);
619 /* look at requested irq */
620 irq = pic_get_irq(&pics[0]);
624 pic_irq_requested = 8 + irq2;
626 /* from master pic */
627 pic_irq_requested = irq;
629 global_env->hard_interrupt_request = 1;
633 int cpu_x86_get_pic_interrupt(CPUX86State *env)
635 int irq, irq2, intno;
637 /* signal the pic that the irq was acked by the CPU */
638 irq = pic_irq_requested;
641 pics[1].isr |= (1 << irq2);
642 pics[1].irr &= ~(1 << irq2);
644 intno = pics[1].irq_base + irq2;
646 intno = pics[0].irq_base + irq;
648 pics[0].isr |= (1 << irq);
649 pics[0].irr &= ~(1 << irq);
653 void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
658 s = &pics[addr >> 7];
663 memset(s, 0, sizeof(PicState));
667 hw_error("single mode not supported");
669 hw_error("level sensitive irq not supported");
670 } else if (val & 0x08) {
672 s->read_reg_select = val & 1;
674 s->special_mask = (val >> 5) & 1;
679 s->rotate_on_autoeoi = val >> 7;
681 case 0x20: /* end of interrupt */
683 priority = get_priority(s, s->isr);
685 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
688 s->priority_add = (s->priority_add + 1) & 7;
692 s->isr &= ~(1 << priority);
695 s->priority_add = (val + 1) & 7;
699 s->isr &= ~(1 << priority);
700 s->priority_add = (priority + 1) & 7;
705 switch(s->init_state) {
711 s->irq_base = val & 0xf8;
722 s->auto_eoi = (val >> 1) & 1;
729 uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr)
732 s = &pics[addr >> 7];
735 if (s->read_reg_select)
746 register_ioport_write(0x20, 2, pic_ioport_write, 1);
747 register_ioport_read(0x20, 2, pic_ioport_read, 1);
748 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
749 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
752 /***********************************************************/
753 /* 8253 PIT emulation */
755 #define PIT_FREQ 1193182
757 #define RW_STATE_LSB 0
758 #define RW_STATE_MSB 1
759 #define RW_STATE_WORD0 2
760 #define RW_STATE_WORD1 3
761 #define RW_STATE_LATCHED_WORD0 4
762 #define RW_STATE_LATCHED_WORD1 5
764 typedef struct PITChannelState {
765 int count; /* can be 65536 */
766 uint16_t latched_count;
769 uint8_t bcd; /* not supported */
770 uint8_t gate; /* timer start */
771 int64_t count_load_time;
772 int64_t count_last_edge_check_time;
775 PITChannelState pit_channels[3];
777 int pit_min_timer_count = 0;
779 int64_t ticks_per_sec;
781 int64_t get_clock(void)
784 gettimeofday(&tv, NULL);
785 return tv.tv_sec * 1000000LL + tv.tv_usec;
788 int64_t cpu_get_ticks(void)
791 asm("rdtsc" : "=A" (val));
795 void cpu_calibrate_ticks(void)
800 ticks = cpu_get_ticks();
802 usec = get_clock() - usec;
803 ticks = cpu_get_ticks() - ticks;
804 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
807 /* compute with 96 bit intermediate result: (a*b)/c */
808 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
813 #ifdef WORDS_BIGENDIAN
823 rl = (uint64_t)u.l.low * (uint64_t)b;
824 rh = (uint64_t)u.l.high * (uint64_t)b;
827 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
831 static int pit_get_count(PITChannelState *s)
836 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
842 counter = (s->count - d) & 0xffff;
845 counter = s->count - (d % s->count);
851 /* get pit output bit */
852 static int pit_get_out(PITChannelState *s)
857 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
861 out = (d >= s->count);
864 out = (d < s->count);
867 if ((d % s->count) == 0 && d != 0)
873 out = (d % s->count) < (s->count >> 1);
877 out = (d == s->count);
883 /* get the number of 0 to 1 transitions we had since we call this
885 /* XXX: maybe better to use ticks precision to avoid getting edges
886 twice if checks are done at very small intervals */
887 static int pit_get_out_edges(PITChannelState *s)
893 ticks = cpu_get_ticks();
894 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
895 PIT_FREQ, ticks_per_sec);
896 d2 = muldiv64(ticks - s->count_load_time,
897 PIT_FREQ, ticks_per_sec);
898 s->count_last_edge_check_time = ticks;
902 if (d1 < s->count && d2 >= s->count)
916 v = s->count - (s->count >> 1);
917 d1 = (d1 + v) / s->count;
918 d2 = (d2 + v) / s->count;
923 if (d1 < s->count && d2 >= s->count)
932 static inline void pit_load_count(PITChannelState *s, int val)
936 s->count_load_time = cpu_get_ticks();
937 s->count_last_edge_check_time = s->count_load_time;
939 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
941 "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
942 PIT_FREQ / pit_min_timer_count);
946 void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
956 s = &pit_channels[channel];
957 access = (val >> 4) & 3;
960 s->latched_count = pit_get_count(s);
961 s->rw_state = RW_STATE_LATCHED_WORD0;
964 s->mode = (val >> 1) & 7;
966 s->rw_state = access - 1 + RW_STATE_LSB;
970 s = &pit_channels[addr];
971 switch(s->rw_state) {
973 pit_load_count(s, val);
976 pit_load_count(s, val << 8);
980 if (s->rw_state & 1) {
981 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
983 s->latched_count = val;
991 uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
997 s = &pit_channels[addr];
998 switch(s->rw_state) {
1001 case RW_STATE_WORD0:
1002 case RW_STATE_WORD1:
1003 count = pit_get_count(s);
1004 if (s->rw_state & 1)
1005 ret = (count >> 8) & 0xff;
1008 if (s->rw_state & 2)
1012 case RW_STATE_LATCHED_WORD0:
1013 case RW_STATE_LATCHED_WORD1:
1014 if (s->rw_state & 1)
1015 ret = s->latched_count >> 8;
1017 ret = s->latched_count & 0xff;
1024 void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1026 speaker_data_on = (val >> 1) & 1;
1027 pit_channels[2].gate = val & 1;
1030 uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
1033 out = pit_get_out(&pit_channels[2]);
1034 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5);
1042 cpu_calibrate_ticks();
1044 for(i = 0;i < 3; i++) {
1045 s = &pit_channels[i];
1048 pit_load_count(s, 0);
1051 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1052 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1054 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1055 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1058 /***********************************************************/
1059 /* serial port emulation */
1063 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1065 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1066 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1067 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1068 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1070 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1071 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1073 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1074 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1075 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1076 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1078 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1079 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1080 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1081 #define UART_LSR_FE 0x08 /* Frame error indicator */
1082 #define UART_LSR_PE 0x04 /* Parity error indicator */
1083 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1084 #define UART_LSR_DR 0x01 /* Receiver data ready */
1086 typedef struct SerialState {
1088 uint8_t rbr; /* receive register */
1090 uint8_t iir; /* read only */
1093 uint8_t lsr; /* read only */
1098 SerialState serial_ports[1];
1100 void serial_update_irq(void)
1102 SerialState *s = &serial_ports[0];
1104 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1105 s->iir = UART_IIR_RDI;
1106 } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
1107 s->iir = UART_IIR_THRI;
1109 s->iir = UART_IIR_NO_INT;
1111 if (s->iir != UART_IIR_NO_INT) {
1112 pic_set_irq(UART_IRQ, 1);
1114 pic_set_irq(UART_IRQ, 0);
1118 void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1120 SerialState *s = &serial_ports[0];
1128 if (s->lcr & UART_LCR_DLAB) {
1129 s->divider = (s->divider & 0xff00) | val;
1131 s->lsr &= ~UART_LSR_THRE;
1132 serial_update_irq();
1136 ret = write(1, &ch, 1);
1138 s->lsr |= UART_LSR_THRE;
1139 s->lsr |= UART_LSR_TEMT;
1140 serial_update_irq();
1144 if (s->lcr & UART_LCR_DLAB) {
1145 s->divider = (s->divider & 0x00ff) | (val << 8);
1148 serial_update_irq();
1170 uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1172 SerialState *s = &serial_ports[0];
1179 if (s->lcr & UART_LCR_DLAB) {
1180 ret = s->divider & 0xff;
1183 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1184 serial_update_irq();
1188 if (s->lcr & UART_LCR_DLAB) {
1189 ret = (s->divider >> 8) & 0xff;
1216 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1217 static int term_got_escape;
1219 void term_print_help(void)
1222 "C-a h print this help\n"
1223 "C-a x exit emulatior\n"
1224 "C-a b send break (magic sysrq)\n"
1225 "C-a C-a send C-a\n"
1229 /* called when a char is received */
1230 void serial_received_byte(SerialState *s, int ch)
1232 if (term_got_escape) {
1233 term_got_escape = 0;
1244 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1245 serial_update_irq();
1250 } else if (ch == TERM_ESCAPE) {
1251 term_got_escape = 1;
1255 s->lsr |= UART_LSR_DR;
1256 serial_update_irq();
1260 /* init terminal so that we can grab keys */
1261 static struct termios oldtty;
1263 static void term_exit(void)
1265 tcsetattr (0, TCSANOW, &oldtty);
1268 static void term_init(void)
1272 tcgetattr (0, &tty);
1275 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
1276 |INLCR|IGNCR|ICRNL|IXON);
1277 tty.c_oflag |= OPOST;
1278 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
1279 tty.c_cflag &= ~(CSIZE|PARENB);
1282 tty.c_cc[VTIME] = 0;
1284 tcsetattr (0, TCSANOW, &tty);
1288 fcntl(0, F_SETFL, O_NONBLOCK);
1291 void serial_init(void)
1293 SerialState *s = &serial_ports[0];
1295 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1297 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1298 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1303 /***********************************************************/
1304 /* ne2000 emulation */
1306 //#define DEBUG_NE2000
1308 #define NE2000_IOPORT 0x300
1309 #define NE2000_IRQ 9
1311 #define MAX_ETH_FRAME_SIZE 1514
1313 #define E8390_CMD 0x00 /* The command register (for all pages) */
1314 /* Page 0 register offsets. */
1315 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1316 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1317 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1318 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1319 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1320 #define EN0_TSR 0x04 /* Transmit status reg RD */
1321 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1322 #define EN0_NCR 0x05 /* Number of collision reg RD */
1323 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1324 #define EN0_FIFO 0x06 /* FIFO RD */
1325 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1326 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1327 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1328 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1329 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1330 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1331 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1332 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1333 #define EN0_RSR 0x0c /* rx status reg RD */
1334 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1335 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1336 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1337 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1338 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1339 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1340 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1342 #define EN1_PHYS 0x11
1343 #define EN1_CURPAG 0x17
1344 #define EN1_MULT 0x18
1346 /* Register accessed at EN_CMD, the 8390 base addr. */
1347 #define E8390_STOP 0x01 /* Stop and reset the chip */
1348 #define E8390_START 0x02 /* Start the chip, clear reset */
1349 #define E8390_TRANS 0x04 /* Transmit a frame */
1350 #define E8390_RREAD 0x08 /* Remote read */
1351 #define E8390_RWRITE 0x10 /* Remote write */
1352 #define E8390_NODMA 0x20 /* Remote DMA */
1353 #define E8390_PAGE0 0x00 /* Select page chip registers */
1354 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1355 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1357 /* Bits in EN0_ISR - Interrupt status register */
1358 #define ENISR_RX 0x01 /* Receiver, no error */
1359 #define ENISR_TX 0x02 /* Transmitter, no error */
1360 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1361 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1362 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1363 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1364 #define ENISR_RDC 0x40 /* remote dma complete */
1365 #define ENISR_RESET 0x80 /* Reset completed */
1366 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1368 /* Bits in received packet status byte and EN0_RSR*/
1369 #define ENRSR_RXOK 0x01 /* Received a good packet */
1370 #define ENRSR_CRC 0x02 /* CRC error */
1371 #define ENRSR_FAE 0x04 /* frame alignment error */
1372 #define ENRSR_FO 0x08 /* FIFO overrun */
1373 #define ENRSR_MPA 0x10 /* missed pkt */
1374 #define ENRSR_PHY 0x20 /* physical/multicast address */
1375 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1376 #define ENRSR_DEF 0x80 /* deferring */
1378 /* Transmitted packet status, EN0_TSR. */
1379 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1380 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1381 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1382 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1383 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1384 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1385 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1386 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1388 #define NE2000_MEM_SIZE 32768
1390 typedef struct NE2000State {
1403 uint8_t phys[6]; /* mac address */
1405 uint8_t mult[8]; /* multicast mask array */
1406 uint8_t mem[NE2000_MEM_SIZE];
1409 NE2000State ne2000_state;
1411 char network_script[1024];
1413 void ne2000_reset(void)
1415 NE2000State *s = &ne2000_state;
1418 s->isr = ENISR_RESET;
1428 /* duplicate prom data */
1429 for(i = 15;i >= 0; i--) {
1430 s->mem[2 * i] = s->mem[i];
1431 s->mem[2 * i + 1] = s->mem[i];
1435 void ne2000_update_irq(NE2000State *s)
1438 isr = s->isr & s->imr;
1440 pic_set_irq(NE2000_IRQ, 1);
1442 pic_set_irq(NE2000_IRQ, 0);
1448 int fd, ret, pid, status;
1450 fd = open("/dev/net/tun", O_RDWR);
1452 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1455 memset(&ifr, 0, sizeof(ifr));
1456 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1457 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1458 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1460 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1464 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1465 fcntl(fd, F_SETFL, O_NONBLOCK);
1468 /* try to launch network init script */
1472 execl(network_script, network_script, ifr.ifr_name, NULL);
1475 while (waitpid(pid, &status, 0) != pid);
1476 if (!WIFEXITED(status) ||
1477 WEXITSTATUS(status) != 0) {
1478 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1479 network_script, ifr.ifr_name);
1485 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1488 printf("NE2000: sending packet size=%d\n", size);
1490 write(net_fd, buf, size);
1493 /* return true if the NE2000 can receive more data */
1494 int ne2000_can_receive(NE2000State *s)
1496 int avail, index, boundary;
1498 if (s->cmd & E8390_STOP)
1500 index = s->curpag << 8;
1501 boundary = s->boundary << 8;
1502 if (index < boundary)
1503 avail = boundary - index;
1505 avail = (s->stop - s->start) - (index - boundary);
1506 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1511 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1514 int total_len, next, avail, len, index;
1516 #if defined(DEBUG_NE2000)
1517 printf("NE2000: received len=%d\n", size);
1520 index = s->curpag << 8;
1521 /* 4 bytes for header */
1522 total_len = size + 4;
1523 /* address for next packet (4 bytes for CRC) */
1524 next = index + ((total_len + 4 + 255) & ~0xff);
1525 if (next >= s->stop)
1526 next -= (s->stop - s->start);
1527 /* prepare packet header */
1529 p[0] = ENRSR_RXOK; /* receive status */
1532 p[3] = total_len >> 8;
1535 /* write packet data */
1537 avail = s->stop - index;
1541 memcpy(s->mem + index, buf, len);
1544 if (index == s->stop)
1548 s->curpag = next >> 8;
1550 /* now we can signal we have receive something */
1552 ne2000_update_irq(s);
1555 void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1557 NE2000State *s = &ne2000_state;
1562 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
1564 if (addr == E8390_CMD) {
1565 /* control register */
1567 if (val & E8390_START) {
1568 /* test specific case: zero length transfert */
1569 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
1571 s->isr |= ENISR_RDC;
1572 ne2000_update_irq(s);
1573 /* XXX: find a better solution for irqs */
1574 cpu_x86_interrupt(global_env);
1576 if (val & E8390_TRANS) {
1577 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
1578 /* signal end of transfert */
1581 ne2000_update_irq(s);
1586 offset = addr | (page << 4);
1589 s->start = val << 8;
1599 ne2000_update_irq(s);
1605 s->tcnt = (s->tcnt & 0xff00) | val;
1608 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
1611 s->rsar = (s->rsar & 0xff00) | val;
1614 s->rsar = (s->rsar & 0x00ff) | (val << 8);
1617 s->rcnt = (s->rcnt & 0xff00) | val;
1620 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
1627 ne2000_update_irq(s);
1629 case EN1_PHYS ... EN1_PHYS + 5:
1630 s->phys[offset - EN1_PHYS] = val;
1635 case EN1_MULT ... EN1_MULT + 7:
1636 s->mult[offset - EN1_MULT] = val;
1642 uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr)
1644 NE2000State *s = &ne2000_state;
1645 int offset, page, ret;
1648 if (addr == E8390_CMD) {
1652 offset = addr | (page << 4);
1663 case EN1_PHYS ... EN1_PHYS + 5:
1664 ret = s->phys[offset - EN1_PHYS];
1669 case EN1_MULT ... EN1_MULT + 7:
1670 ret = s->mult[offset - EN1_MULT];
1678 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
1683 void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1685 NE2000State *s = &ne2000_state;
1689 printf("NE2000: asic write val=0x%04x\n", val);
1691 p = s->mem + s->rsar;
1692 if (s->dcfg & 0x01) {
1705 if (s->rsar == s->stop)
1708 /* signal end of transfert */
1709 s->isr |= ENISR_RDC;
1710 ne2000_update_irq(s);
1714 uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr)
1716 NE2000State *s = &ne2000_state;
1720 p = s->mem + s->rsar;
1721 if (s->dcfg & 0x01) {
1723 ret = p[0] | (p[1] << 8);
1733 if (s->rsar == s->stop)
1736 /* signal end of transfert */
1737 s->isr |= ENISR_RDC;
1738 ne2000_update_irq(s);
1741 printf("NE2000: asic read val=0x%04x\n", ret);
1746 void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1748 /* nothing to do (end of reset pulse) */
1751 uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr)
1757 void ne2000_init(void)
1759 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
1760 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
1762 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
1763 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
1764 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
1765 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
1767 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
1768 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
1772 /***********************************************************/
1777 /* Bits of HD_STATUS */
1778 #define ERR_STAT 0x01
1779 #define INDEX_STAT 0x02
1780 #define ECC_STAT 0x04 /* Corrected error */
1781 #define DRQ_STAT 0x08
1782 #define SEEK_STAT 0x10
1783 #define SRV_STAT 0x10
1784 #define WRERR_STAT 0x20
1785 #define READY_STAT 0x40
1786 #define BUSY_STAT 0x80
1788 /* Bits for HD_ERROR */
1789 #define MARK_ERR 0x01 /* Bad address mark */
1790 #define TRK0_ERR 0x02 /* couldn't find track 0 */
1791 #define ABRT_ERR 0x04 /* Command aborted */
1792 #define MCR_ERR 0x08 /* media change request */
1793 #define ID_ERR 0x10 /* ID field not found */
1794 #define MC_ERR 0x20 /* media changed */
1795 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
1796 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
1797 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
1799 /* Bits of HD_NSECTOR */
1803 #define TAG_MASK 0xf8
1805 #define IDE_CMD_RESET 0x04
1806 #define IDE_CMD_DISABLE_IRQ 0x02
1808 /* ATA/ATAPI Commands pre T13 Spec */
1809 #define WIN_NOP 0x00
1811 * 0x01->0x02 Reserved
1813 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
1815 * 0x04->0x07 Reserved
1817 #define WIN_SRST 0x08 /* ATAPI soft reset command */
1818 #define WIN_DEVICE_RESET 0x08
1820 * 0x09->0x0F Reserved
1822 #define WIN_RECAL 0x10
1823 #define WIN_RESTORE WIN_RECAL
1825 * 0x10->0x1F Reserved
1827 #define WIN_READ 0x20 /* 28-Bit */
1828 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
1829 #define WIN_READ_LONG 0x22 /* 28-Bit */
1830 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
1831 #define WIN_READ_EXT 0x24 /* 48-Bit */
1832 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
1833 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
1834 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
1838 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
1840 * 0x2A->0x2F Reserved
1842 #define WIN_WRITE 0x30 /* 28-Bit */
1843 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
1844 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
1845 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
1846 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
1847 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
1848 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
1849 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
1850 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
1851 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
1853 * 0x3A->0x3B Reserved
1855 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
1857 * 0x3D->0x3F Reserved
1859 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
1860 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
1861 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
1863 * 0x43->0x4F Reserved
1865 #define WIN_FORMAT 0x50
1867 * 0x51->0x5F Reserved
1869 #define WIN_INIT 0x60
1871 * 0x61->0x5F Reserved
1873 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
1874 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
1875 #define WIN_DIAGNOSE 0x90
1876 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
1877 #define WIN_DOWNLOAD_MICROCODE 0x92
1878 #define WIN_STANDBYNOW2 0x94
1879 #define WIN_STANDBY2 0x96
1880 #define WIN_SETIDLE2 0x97
1881 #define WIN_CHECKPOWERMODE2 0x98
1882 #define WIN_SLEEPNOW2 0x99
1886 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
1887 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
1888 #define WIN_QUEUED_SERVICE 0xA2
1889 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
1890 #define CFA_ERASE_SECTORS 0xC0
1891 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
1892 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
1893 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
1894 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
1895 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
1896 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
1897 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
1898 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
1899 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
1900 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
1901 #define WIN_GETMEDIASTATUS 0xDA
1902 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
1903 #define WIN_POSTBOOT 0xDC
1904 #define WIN_PREBOOT 0xDD
1905 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
1906 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
1907 #define WIN_STANDBYNOW1 0xE0
1908 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
1909 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
1910 #define WIN_SETIDLE1 0xE3
1911 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
1912 #define WIN_CHECKPOWERMODE1 0xE5
1913 #define WIN_SLEEPNOW1 0xE6
1914 #define WIN_FLUSH_CACHE 0xE7
1915 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
1916 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
1917 /* SET_FEATURES 0x22 or 0xDD */
1918 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
1919 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
1920 #define WIN_MEDIAEJECT 0xED
1921 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
1922 #define WIN_SETFEATURES 0xEF /* set special drive features */
1923 #define EXABYTE_ENABLE_NEST 0xF0
1924 #define WIN_SECURITY_SET_PASS 0xF1
1925 #define WIN_SECURITY_UNLOCK 0xF2
1926 #define WIN_SECURITY_ERASE_PREPARE 0xF3
1927 #define WIN_SECURITY_ERASE_UNIT 0xF4
1928 #define WIN_SECURITY_FREEZE_LOCK 0xF5
1929 #define WIN_SECURITY_DISABLE 0xF6
1930 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
1931 #define WIN_SET_MAX 0xF9
1932 #define DISABLE_SEAGATE 0xFB
1934 #define MAX_MULT_SECTORS 16
1940 typedef void EndTransferFunc(struct IDEState *);
1942 typedef struct IDEState {
1944 int cylinders, heads, sectors;
1957 /* 0x3f6 command, only meaningful for drive 0 */
1959 /* depends on bit 4 in select, only meaningful for drive 0 */
1960 struct IDEState *cur_drive;
1961 BlockDriverState *bs;
1962 EndTransferFunc *end_transfer_func;
1965 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
1968 BlockDriverState *bs_table[MAX_DISKS];
1969 IDEState ide_state[MAX_DISKS];
1971 static void padstr(char *str, const char *src, int len)
1974 for(i = 0; i < len; i++) {
1979 *(char *)((long)str ^ 1) = v;
1984 static void ide_identify(IDEState *s)
1987 unsigned int oldsize;
1989 memset(s->io_buffer, 0, 512);
1990 p = (uint16_t *)s->io_buffer;
1992 stw(p + 1, s->cylinders);
1993 stw(p + 3, s->heads);
1994 stw(p + 4, 512 * s->sectors); /* sectors */
1995 stw(p + 5, 512); /* sector size */
1996 stw(p + 6, s->sectors);
1997 stw(p + 20, 3); /* buffer type */
1998 stw(p + 21, 512); /* cache size in sectors */
1999 stw(p + 22, 4); /* ecc bytes */
2000 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40);
2001 // stw(p + 47, MAX_MULT_SECTORS);
2002 stw(p + 48, 1); /* dword I/O */
2003 stw(p + 49, 1 << 9); /* LBA supported, no DMA */
2004 stw(p + 51, 0x200); /* PIO transfer cycle */
2005 stw(p + 52, 0x200); /* DMA transfer cycle */
2006 stw(p + 54, s->cylinders);
2007 stw(p + 55, s->heads);
2008 stw(p + 56, s->sectors);
2009 oldsize = s->cylinders * s->heads * s->sectors;
2010 stw(p + 57, oldsize);
2011 stw(p + 58, oldsize >> 16);
2012 if (s->mult_sectors)
2013 stw(p + 59, 0x100 | s->mult_sectors);
2014 stw(p + 60, s->nb_sectors);
2015 stw(p + 61, s->nb_sectors >> 16);
2016 stw(p + 80, (1 << 1) | (1 << 2));
2017 stw(p + 82, (1 << 14));
2018 stw(p + 83, (1 << 14));
2019 stw(p + 84, (1 << 14));
2020 stw(p + 85, (1 << 14));
2022 stw(p + 87, (1 << 14));
2025 static inline void ide_abort_command(IDEState *s)
2027 s->status = READY_STAT | ERR_STAT;
2028 s->error = ABRT_ERR;
2031 static inline void ide_set_irq(IDEState *s)
2033 if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) {
2034 pic_set_irq(s->irq, 1);
2035 cpu_x86_interrupt(global_env);
2039 /* prepare data transfer and tell what to do after */
2040 static void ide_transfer_start(IDEState *s, int size,
2041 EndTransferFunc *end_transfer_func)
2043 s->end_transfer_func = end_transfer_func;
2044 s->data_ptr = s->io_buffer;
2045 s->data_end = s->io_buffer + size;
2046 s->status |= DRQ_STAT;
2049 static void ide_transfer_stop(IDEState *s)
2051 s->end_transfer_func = ide_transfer_stop;
2052 s->data_ptr = s->io_buffer;
2053 s->data_end = s->io_buffer;
2054 s->status &= ~DRQ_STAT;
2057 static int64_t ide_get_sector(IDEState *s)
2060 if (s->select & 0x40) {
2062 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
2063 (s->lcyl << 8) | s->sector;
2065 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
2066 (s->select & 0x0f) * s->sectors +
2072 static void ide_set_sector(IDEState *s, int64_t sector_num)
2074 unsigned int cyl, r;
2075 if (s->select & 0x40) {
2076 s->select = (s->select & 0xf0) | (sector_num >> 24);
2077 s->hcyl = (sector_num >> 16);
2078 s->lcyl = (sector_num >> 8);
2079 s->sector = (sector_num);
2081 cyl = sector_num / (s->heads * s->sectors);
2082 r = sector_num % (s->heads * s->sectors);
2085 s->select = (s->select & 0xf0) | (r / s->sectors);
2086 s->sector = (r % s->sectors) + 1;
2090 static void ide_sector_read(IDEState *s)
2095 s->status = READY_STAT | SEEK_STAT;
2096 sector_num = ide_get_sector(s);
2098 if (s->nsector == 0xff) {
2099 /* no more sector to read from disk */
2100 ide_transfer_stop(s);
2102 #if defined(DEBUG_IDE)
2103 printf("read sector=%Ld\n", sector_num);
2105 ret = bdrv_read(s->bs, sector_num, s->io_buffer, 1);
2106 ide_transfer_start(s, 512, ide_sector_read);
2109 ide_set_sector(s, sector_num + 1);
2112 static void ide_sector_write(IDEState *s)
2117 s->status = READY_STAT | SEEK_STAT;
2118 sector_num = ide_get_sector(s);
2119 #if defined(DEBUG_IDE)
2120 printf("write sector=%Ld\n", sector_num);
2122 ret = bdrv_write(s->bs, sector_num, s->io_buffer, 1);
2124 if (s->nsector == 0) {
2125 /* no more sector to write */
2126 ide_transfer_stop(s);
2128 ide_transfer_start(s, 512, ide_sector_write);
2130 ide_set_sector(s, sector_num + 1);
2134 void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
2136 IDEState *s = ide_state[0].cur_drive;
2141 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
2163 unit = (val >> 4) & 1;
2164 s = &ide_state[unit];
2165 ide_state[0].cur_drive = s;
2171 #if defined(DEBUG_IDE)
2172 printf("ide: CMD=%02x\n", val);
2179 s->status = READY_STAT;
2180 ide_transfer_start(s, 512, ide_transfer_stop);
2182 ide_abort_command(s);
2188 s->status = READY_STAT;
2192 if (s->nsector > MAX_MULT_SECTORS ||
2194 (s->nsector & (s->nsector - 1)) != 0) {
2195 ide_abort_command(s);
2197 s->mult_sectors = s->nsector;
2198 s->status = READY_STAT;
2207 case WIN_WRITE_ONCE:
2208 s->status = SEEK_STAT;
2209 ide_transfer_start(s, 512, ide_sector_write);
2212 ide_abort_command(s);
2219 uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr)
2221 IDEState *s = ide_state[0].cur_drive;
2250 pic_set_irq(s->irq, 0);
2254 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2259 uint32_t ide_status_read(CPUX86State *env, uint32_t addr)
2261 IDEState *s = ide_state[0].cur_drive;
2265 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2270 void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
2272 IDEState *s = &ide_state[0];
2273 /* common for both drives */
2277 void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
2279 IDEState *s = ide_state[0].cur_drive;
2283 *(uint16_t *)p = tswap16(val);
2286 if (p >= s->data_end)
2287 s->end_transfer_func(s);
2290 uint32_t ide_data_readw(CPUX86State *env, uint32_t addr)
2292 IDEState *s = ide_state[0].cur_drive;
2297 ret = tswap16(*(uint16_t *)p);
2300 if (p >= s->data_end)
2301 s->end_transfer_func(s);
2305 void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
2307 IDEState *s = ide_state[0].cur_drive;
2311 *(uint32_t *)p = tswap32(val);
2314 if (p >= s->data_end)
2315 s->end_transfer_func(s);
2318 uint32_t ide_data_readl(CPUX86State *env, uint32_t addr)
2320 IDEState *s = ide_state[0].cur_drive;
2325 ret = tswap32(*(uint32_t *)p);
2328 if (p >= s->data_end)
2329 s->end_transfer_func(s);
2333 void ide_reset(IDEState *s)
2335 s->mult_sectors = MAX_MULT_SECTORS;
2336 s->status = READY_STAT;
2347 for(i = 0; i < MAX_DISKS; i++) {
2349 s->bs = bs_table[i];
2351 bdrv_get_geometry(s->bs, &nb_sectors);
2352 cylinders = nb_sectors / (16 * 63);
2353 if (cylinders > 16383)
2355 else if (cylinders < 2)
2357 s->cylinders = cylinders;
2360 s->nb_sectors = nb_sectors;
2365 register_ioport_write(0x1f0, 8, ide_ioport_write, 1);
2366 register_ioport_read(0x1f0, 8, ide_ioport_read, 1);
2367 register_ioport_read(0x3f6, 1, ide_status_read, 1);
2368 register_ioport_write(0x3f6, 1, ide_cmd_write, 1);
2371 register_ioport_write(0x1f0, 2, ide_data_writew, 2);
2372 register_ioport_read(0x1f0, 2, ide_data_readw, 2);
2373 register_ioport_write(0x1f0, 4, ide_data_writel, 4);
2374 register_ioport_read(0x1f0, 4, ide_data_readl, 4);
2377 /***********************************************************/
2378 /* cpu signal handler */
2379 static void host_segv_handler(int host_signum, siginfo_t *info,
2382 if (cpu_signal_handler(host_signum, info, puc))
2388 static int timer_irq_pending;
2389 static int timer_irq_count;
2391 static void host_alarm_handler(int host_signum, siginfo_t *info,
2394 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2395 some drift between cpu_get_ticks() and the interrupt time. So
2396 we queue some interrupts to avoid missing some */
2397 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
2398 if (timer_irq_count) {
2399 if (timer_irq_count > 2)
2400 timer_irq_count = 2;
2402 /* just exit from the cpu to have a chance to handle timers */
2403 cpu_x86_interrupt(global_env);
2404 timer_irq_pending = 1;
2408 /* main execution loop */
2410 CPUState *cpu_gdbstub_get_env(void *opaque)
2415 void main_loop(void *opaque)
2417 struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
2418 int ret, n, timeout;
2420 CPUState *env = global_env;
2424 ret = cpu_x86_exec(env);
2426 /* if hlt instruction, we wait until the next IRQ */
2427 if (ret == EXCP_HLT)
2431 /* poll any events */
2434 if (!(serial_ports[0].lsr & UART_LSR_DR)) {
2437 pf->events = POLLIN;
2441 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
2444 pf->events = POLLIN;
2448 if (gdbstub_fd > 0) {
2450 pf->fd = gdbstub_fd;
2451 pf->events = POLLIN;
2455 ret = poll(ufds, pf - ufds, timeout);
2457 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
2458 n = read(0, &ch, 1);
2460 serial_received_byte(&serial_ports[0], ch);
2463 if (net_ufd && (net_ufd->revents & POLLIN)) {
2464 uint8_t buf[MAX_ETH_FRAME_SIZE];
2466 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
2469 memset(buf + n, 0, 60 - n);
2472 ne2000_receive(&ne2000_state, buf, n);
2475 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
2477 /* stop emulation if requested by gdb */
2478 n = read(gdbstub_fd, buf, 1);
2485 if (timer_irq_pending) {
2488 timer_irq_pending = 0;
2497 printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
2498 "usage: vl [options] bzImage [kernel parameters...]\n"
2500 "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
2501 "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
2503 "General options:\n"
2504 "-initrd file use 'file' as initial ram disk\n"
2505 "-hda file use 'file' as hard disk 0 image\n"
2506 "-hdb file use 'file' as hard disk 1 image\n"
2507 "-m megs set virtual RAM size to megs MB\n"
2508 "-n script set network init script [default=%s]\n"
2511 "-s wait gdb connection to port %d\n"
2512 "-p port change gdb connection port\n"
2513 "-d output log in /tmp/vl.log\n"
2515 "During emulation, use C-a h to get terminal commands:\n",
2516 DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT);
2521 struct option long_options[] = {
2522 { "initrd", 1, NULL, 0, },
2523 { "hda", 1, NULL, 0, },
2524 { "hdb", 1, NULL, 0, },
2525 { NULL, 0, NULL, 0 },
2528 int main(int argc, char **argv)
2530 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
2531 struct linux_params *params;
2532 struct sigaction act;
2533 struct itimerval itv;
2535 const char *tmpdir, *initrd_filename;
2536 const char *hd_filename[MAX_DISKS];
2538 /* we never want that malloc() uses mmap() */
2539 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
2540 initrd_filename = NULL;
2541 for(i = 0; i < MAX_DISKS; i++)
2542 hd_filename[i] = NULL;
2543 phys_ram_size = 32 * 1024 * 1024;
2544 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
2546 gdbstub_port = DEFAULT_GDBSTUB_PORT;
2548 c = getopt_long_only(argc, argv, "hm:dn:sp:", long_options, &long_index);
2553 switch(long_index) {
2555 initrd_filename = optarg;
2558 hd_filename[0] = optarg;
2561 hd_filename[1] = optarg;
2569 phys_ram_size = atoi(optarg) * 1024 * 1024;
2570 if (phys_ram_size <= 0)
2577 pstrcpy(network_script, sizeof(network_script), optarg);
2583 gdbstub_port = atoi(optarg);
2592 logfile = fopen(DEBUG_LOGFILE, "w");
2594 perror(DEBUG_LOGFILE);
2597 setvbuf(logfile, NULL, _IOLBF, 0);
2600 /* open the virtual block devices */
2601 for(i = 0; i < MAX_DISKS; i++) {
2602 if (hd_filename[i]) {
2603 bs_table[i] = bdrv_open(hd_filename[i]);
2605 fprintf(stderr, "vl: could not open hard disk image '%s\n",
2612 /* init network tun interface */
2615 /* init the memory */
2616 tmpdir = getenv("VLTMPDIR");
2619 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
2620 if (mkstemp(phys_ram_file) < 0) {
2621 fprintf(stderr, "Could not create temporary memory file '%s'\n",
2625 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
2626 if (phys_ram_fd < 0) {
2627 fprintf(stderr, "Could not open temporary memory file '%s'\n",
2631 ftruncate(phys_ram_fd, phys_ram_size);
2632 unlink(phys_ram_file);
2633 phys_ram_base = mmap((void *)PHYS_RAM_BASE, phys_ram_size,
2634 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
2636 if (phys_ram_base == MAP_FAILED) {
2637 fprintf(stderr, "Could not map physical memory\n");
2641 /* now we can load the kernel */
2642 ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
2644 fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
2650 if (initrd_filename) {
2651 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
2652 if (initrd_size < 0) {
2653 fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
2659 /* init kernel params */
2660 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
2661 memset(params, 0, sizeof(struct linux_params));
2662 params->mount_root_rdonly = 0;
2663 params->cl_magic = 0xA33F;
2664 params->cl_offset = params->commandline - (uint8_t *)params;
2665 params->ext_mem_k = (phys_ram_size / 1024) - 1024;
2666 for(i = optind + 1; i < argc; i++) {
2667 if (i != optind + 1)
2668 pstrcat(params->commandline, sizeof(params->commandline), " ");
2669 pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
2671 params->loader_type = 0x01;
2672 if (initrd_size > 0) {
2673 params->initrd_start = INITRD_LOAD_ADDR;
2674 params->initrd_size = initrd_size;
2676 params->orig_video_lines = 25;
2677 params->orig_video_cols = 80;
2679 /* init basic PC hardware */
2681 register_ioport_write(0x80, 1, ioport80_write, 1);
2683 register_ioport_write(0x3d4, 2, vga_ioport_write, 1);
2692 /* setup cpu signal handlers for MMU / self modifying code handling */
2693 sigfillset(&act.sa_mask);
2694 act.sa_flags = SA_SIGINFO;
2695 act.sa_sigaction = host_segv_handler;
2696 sigaction(SIGSEGV, &act, NULL);
2697 sigaction(SIGBUS, &act, NULL);
2699 act.sa_sigaction = host_alarm_handler;
2700 sigaction(SIGALRM, &act, NULL);
2702 /* init CPU state */
2705 cpu_single_env = env;
2707 /* setup basic memory access */
2708 env->cr[0] = 0x00000033;
2709 cpu_x86_init_mmu(env);
2711 memset(params->idt_table, 0, sizeof(params->idt_table));
2713 params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
2714 params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
2716 env->idt.base = (void *)params->idt_table;
2717 env->idt.limit = sizeof(params->idt_table) - 1;
2718 env->gdt.base = (void *)params->gdt_table;
2719 env->gdt.limit = sizeof(params->gdt_table) - 1;
2721 cpu_x86_load_seg(env, R_CS, KERNEL_CS);
2722 cpu_x86_load_seg(env, R_DS, KERNEL_DS);
2723 cpu_x86_load_seg(env, R_ES, KERNEL_DS);
2724 cpu_x86_load_seg(env, R_SS, KERNEL_DS);
2725 cpu_x86_load_seg(env, R_FS, KERNEL_DS);
2726 cpu_x86_load_seg(env, R_GS, KERNEL_DS);
2728 env->eip = KERNEL_LOAD_ADDR;
2729 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
2732 itv.it_interval.tv_sec = 0;
2733 itv.it_interval.tv_usec = 1000;
2734 itv.it_value.tv_sec = 0;
2735 itv.it_value.tv_usec = 10 * 1000;
2736 setitimer(ITIMER_REAL, &itv, NULL);
2737 /* we probe the tick duration of the kernel to inform the user if
2738 the emulated kernel requested a too high timer frequency */
2739 getitimer(ITIMER_REAL, &itv);
2740 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
2744 cpu_gdbstub(NULL, main_loop, gdbstub_port);