vcs.maemo.org Git - kernel-power/blob - usbhost/drivers/usb2/musb/musbhsdma.c

   1 /*
   2  * MUSB OTG driver - support for Mentor's DMA controller
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2007 by Texas Instruments
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19  * 02110-1301 USA
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33 #include <linux/device.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/platform_device.h>
  36 #include "musb_core.h"
  37 #include "musbhsdma.h"
  38
  39 static int dma_controller_start(struct dma_controller *c)
  40 {
  41         /* nothing to do */
  42         return 0;
  43 }
  44
  45 static void dma_channel_release(struct dma_channel *channel);
  46
  47 static int dma_controller_stop(struct dma_controller *c)
  48 {
  49         struct musb_dma_controller *controller = container_of(c,
  50                         struct musb_dma_controller, controller);
  51         struct musb *musb = controller->private_data;
  52         struct dma_channel *channel;
  53         u8 bit;
  54
  55         if (controller->used_channels != 0) {
  56                 dev_err(musb->controller,
  57                         "Stopping DMA controller while channel active\n");
  58
  59                 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  60                         if (controller->used_channels & (1 << bit)) {
  61                                 channel = &controller->channel[bit].channel;
  62                                 dma_channel_release(channel);
  63
  64                                 if (!controller->used_channels)
  65                                         break;
  66                         }
  67                 }
  68         }
  69
  70         return 0;
  71 }
  72
  73 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
  74                                 struct musb_hw_ep *hw_ep, u8 transmit)
  75 {
  76         struct musb_dma_controller *controller = container_of(c,
  77                         struct musb_dma_controller, controller);
  78         struct musb_dma_channel *musb_channel = NULL;
  79         struct dma_channel *channel = NULL;
  80         u8 bit;
  81
  82         /* musb on omap3 has a problem with using dma channels simultaneously
  83          * so we will only allocate 1 dma channel at a time to avoid problems
  84          * related to that bug
  85          */
  86         for (bit = 0; bit < 1; bit++) {
  87                 if (controller->used_channels & (1 << bit))
  88                         continue;
  89
  90                 controller->used_channels |= (1 << bit);
  91                 musb_channel = &(controller->channel[bit]);
  92                 musb_channel->controller = controller;
  93                 musb_channel->idx = bit;
  94                 musb_channel->epnum = hw_ep->epnum;
  95                 musb_channel->transmit = transmit;
  96                 channel = &(musb_channel->channel);
  97                 channel->private_data = musb_channel;
  98                 channel->status = MUSB_DMA_STATUS_FREE;
  99                 channel->max_len = 0x7fffffff;
 100                 /* always use mode1 */
 101                 channel->desired_mode = true;
 102                 channel->actual_len = 0;
 103
 104                 break;
 105         }
 106
 107         return channel;
 108 }
 109
 110 static void dma_channel_release(struct dma_channel *channel)
 111 {
 112         struct musb_dma_channel *musb_channel = channel->private_data;
 113
 114         channel->actual_len = 0;
 115         musb_channel->start_addr = 0;
 116         musb_channel->len = 0;
 117
 118         musb_channel->controller->used_channels &=
 119                 ~(1 << musb_channel->idx);
 120
 121         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 122 }
 123
 124 static void configure_channel(struct dma_channel *channel,
 125                                 u16 packet_sz, u8 mode,
 126                                 dma_addr_t dma_addr, u32 len)
 127 {
 128         struct musb_dma_channel *musb_channel = channel->private_data;
 129         struct musb_dma_controller *controller = musb_channel->controller;
 130         void __iomem *mbase = controller->base;
 131         u8 bchannel = musb_channel->idx;
 132         u16 csr = 0;
 133
 134         DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
 135                         channel, packet_sz, dma_addr, len, mode);
 136
 137         if (mode)
 138                 csr |= MUSB_HSDMA_MODE1;
 139
 140         if (packet_sz >= 64)
 141                 csr |= MUSB_HSDMA_BURSTMODE_INCR16;
 142         else if (packet_sz >= 32)
 143                 csr |= MUSB_HSDMA_BURSTMODE_INCR8;
 144         else if (packet_sz >= 16)
 145                 csr |= MUSB_HSDMA_BURSTMODE_INCR4;
 146
 147         csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 148                 | MUSB_HSDMA_ENABLE
 149                 | MUSB_HSDMA_IRQENABLE
 150                 | (musb_channel->transmit
 151                                 ? MUSB_HSDMA_TRANSMIT
 152                                 : 0);
 153
 154         /* address/count */
 155         musb_write_hsdma_addr(mbase, bchannel, dma_addr);
 156         musb_write_hsdma_count(mbase, bchannel, len);
 157
 158         /* control (this should start things) */
 159         musb_writew(mbase,
 160                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 161                 csr);
 162 }
 163
 164 static int dma_channel_program(struct dma_channel *channel,
 165                                 u16 packet_sz, u8 mode,
 166                                 dma_addr_t dma_addr, u32 len)
 167 {
 168         struct musb_dma_channel *musb_channel = channel->private_data;
 169
 170         DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
 171                 musb_channel->epnum,
 172                 musb_channel->transmit ? "Tx" : "Rx",
 173                 packet_sz, dma_addr, len, mode);
 174
 175         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 176                 channel->status == MUSB_DMA_STATUS_BUSY);
 177
 178         channel->actual_len = 0;
 179         musb_channel->start_addr = dma_addr;
 180         musb_channel->len = len;
 181         musb_channel->max_packet_sz = packet_sz;
 182         channel->status = MUSB_DMA_STATUS_BUSY;
 183
 184         configure_channel(channel, packet_sz, mode, dma_addr, len);
 185
 186         return true;
 187 }
 188
 189 static int dma_channel_abort(struct dma_channel *channel)
 190 {
 191         struct musb_dma_channel *musb_channel = channel->private_data;
 192         void __iomem *mbase = musb_channel->controller->base;
 193
 194         u32 addr = 0;
 195         u16 csr;
 196         u8 bchannel = musb_channel->idx;
 197
 198         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 199                 if (musb_channel->transmit) {
 200
 201                         csr = musb_readw(mbase,
 202                                 MUSB_EP_OFFSET(musb_channel->epnum,
 203                                                 MUSB_TXCSR));
 204                         csr &= ~(MUSB_TXCSR_AUTOSET |
 205                                  MUSB_TXCSR_DMAENAB);
 206                         musb_writew(mbase,
 207                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
 208                                 csr);
 209                         csr &= ~MUSB_TXCSR_DMAMODE;
 210                         musb_writew(mbase,
 211                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
 212                                 csr);
 213                 } else {
 214                         csr = musb_readw(mbase,
 215                                 MUSB_EP_OFFSET(musb_channel->epnum,
 216                                                 MUSB_RXCSR));
 217                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 218                                  MUSB_RXCSR_DMAENAB);
 219                         musb_writew(mbase,
 220                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
 221                                 csr);
 222                         csr &= ~MUSB_RXCSR_DMAMODE;
 223                         musb_writew(mbase,
 224                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
 225                                 csr);
 226                         addr = musb_read_hsdma_addr(mbase, bchannel);
 227                         channel->actual_len = addr - musb_channel->start_addr;
 228                 }
 229
 230                 musb_writew(mbase,
 231                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 232                         0);
 233                 musb_write_hsdma_addr(mbase, bchannel, 0);
 234                 musb_write_hsdma_count(mbase, bchannel, 0);
 235                 channel->status = MUSB_DMA_STATUS_FREE;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static irqreturn_t dma_controller_irq(int irq, void *private_data)
 242 {
 243         struct musb_dma_controller *controller = private_data;
 244         struct musb *musb = controller->private_data;
 245         struct musb_dma_channel *mchannel;
 246         struct dma_channel *channel;
 247
 248         void __iomem *mbase = controller->base;
 249
 250         irqreturn_t retval = IRQ_NONE;
 251
 252         unsigned long flags;
 253
 254         u8 bchannel;
 255         u8 int_hsdma;
 256
 257         u32 addr;
 258         u16 csr;
 259
 260         spin_lock_irqsave(&musb->lock, flags);
 261
 262         int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 263         if (!int_hsdma)
 264                 goto done;
 265
 266         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 267                 u8 devctl;
 268
 269                 if (!(int_hsdma & (1 << bchannel)))
 270                         continue;
 271
 272                 mchannel = &(controller->channel[bchannel]);
 273                 channel = &mchannel->channel;
 274
 275                 csr = musb_readw(mbase, MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 276                                         MUSB_HSDMA_CONTROL));
 277
 278                 if (csr & MUSB_HSDMA_BUSERROR) {
 279                         mchannel->channel.status = MUSB_DMA_STATUS_BUS_ABORT;
 280                         goto done;
 281                 }
 282
 283                 addr = musb_read_hsdma_addr(mbase, bchannel);
 284                 channel->actual_len = addr - mchannel->start_addr;
 285
 286                 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", channel,
 287                                 mchannel->start_addr, addr,
 288                                 channel->actual_len, mchannel->len,
 289                                 (channel->actual_len < mchannel->len) ?
 290                                 "=> reconfig 0" : "=> complete");
 291
 292                 devctl = musb_readb(mbase, MUSB_DEVCTL);
 293                 channel->status = MUSB_DMA_STATUS_FREE;
 294
 295                 /* completed */
 296                 if ((devctl & MUSB_DEVCTL_HM) && (mchannel->transmit)
 297                                 && ((channel->desired_mode == 0)
 298                                 || (channel->actual_len &
 299                                 (mchannel->max_packet_sz - 1)))) {
 300                         u8 txcsr;
 301
 302                         musb_ep_select(mbase, mchannel->epnum);
 303                         txcsr = musb_readw(mbase, MUSB_EP_OFFSET(
 304                                                 mchannel->epnum, MUSB_TXCSR));
 305                         txcsr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_AUTOSET);
 306                         musb_writew(mbase, MUSB_EP_OFFSET(mchannel->epnum,
 307                                                 MUSB_TXCSR), txcsr);
 308                         txcsr &= ~MUSB_TXCSR_DMAMODE;
 309                         txcsr |= MUSB_TXCSR_TXPKTRDY;
 310                         /* Send out the packet */
 311                         musb_writew(mbase, MUSB_EP_OFFSET(mchannel->epnum,
 312                                                 MUSB_TXCSR), txcsr);
 313                 } else {
 314                         musb_dma_completion(musb, mchannel->epnum,
 315                                         mchannel->transmit);
 316                 }
 317         }
 318
 319 #ifdef CONFIG_BLACKFIN
 320         /* Clear DMA interrup flags */
 321         musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
 322 #endif
 323
 324         retval = IRQ_HANDLED;
 325 done:
 326         spin_unlock_irqrestore(&musb->lock, flags);
 327         return retval;
 328 }
 329
 330 void dma_controller_destroy(struct dma_controller *c)
 331 {
 332         struct musb_dma_controller *controller = container_of(c,
 333                         struct musb_dma_controller, controller);
 334
 335         if (!controller)
 336                 return;
 337
 338         if (controller->irq)
 339                 free_irq(controller->irq, c);
 340
 341         kfree(controller);
 342 }
 343
 344 struct dma_controller *__init
 345 dma_controller_create(struct musb *musb, void __iomem *base)
 346 {
 347         struct musb_dma_controller *controller;
 348         struct device *dev = musb->controller;
 349         struct platform_device *pdev = to_platform_device(dev);
 350         int irq = platform_get_irq(pdev, 1);
 351
 352         if (irq == 0) {
 353                 dev_err(dev, "No DMA interrupt line!\n");
 354                 return NULL;
 355         }
 356
 357         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 358         if (!controller)
 359                 return NULL;
 360
 361         controller->channel_count = MUSB_HSDMA_CHANNELS;
 362         controller->private_data = musb;
 363         controller->base = base;
 364
 365         controller->controller.start = dma_controller_start;
 366         controller->controller.stop = dma_controller_stop;
 367         controller->controller.channel_alloc = dma_channel_allocate;
 368         controller->controller.channel_release = dma_channel_release;
 369         controller->controller.channel_program = dma_channel_program;
 370         controller->controller.channel_abort = dma_channel_abort;
 371
 372         if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
 373                         dev_name(musb->controller), &controller->controller)) {
 374                 dev_err(dev, "request_irq %d failed!\n", irq);
 375                 dma_controller_destroy(&controller->controller);
 376
 377                 return NULL;
 378         }
 379
 380         controller->irq = irq;
 381
 382         return &controller->controller;
 383 }