2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 static struct musb *the_musb;
116 static struct musb_ctx ctx;
118 #ifndef CONFIG_MUSB_PIO_ONLY
119 static int __initdata use_dma = 1;
121 static int __initdata use_dma;
123 module_param(use_dma, bool, 0);
124 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
126 unsigned musb_debug = 0;
127 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
128 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
130 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
131 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
133 #define MUSB_VERSION "6.0"
135 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
137 #define MUSB_DRIVER_NAME "musb_hdrc"
138 const char musb_driver_name[] = MUSB_DRIVER_NAME;
140 MODULE_DESCRIPTION(DRIVER_INFO);
141 MODULE_AUTHOR(DRIVER_AUTHOR);
142 MODULE_LICENSE("GPL");
143 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
146 void musb_force_term(void __iomem *addr, enum musb_term term)
150 /* activate pulldown resistors on datalines */
151 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
152 r |= ISP1704_OTG_CTRL_DP_PULLDOWN | ISP1704_OTG_CTRL_DM_PULLDOWN;
153 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
155 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
156 /* clear speed-selection bits */
157 r &= ~ISP1704_FUNC_CTRL_XCVRSELECT_MASK;
158 /* set new speed-selection bits */
161 case MUSB_TERM_HOST_HIGHSPEED:
162 r |= ISP1704_FUNC_CTRL_HIGH_SPEED;
163 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
164 r &= ~ISP1704_FUNC_CTRL_OPMODE;
167 case MUSB_TERM_HOST_FULLSPEED:
168 r |= ISP1704_FUNC_CTRL_FULL_SPEED;
169 r |= ISP1704_FUNC_CTRL_TERMSELECT;
170 r &= ~ISP1704_FUNC_CTRL_OPMODE;
173 case MUSB_TERM_HOST_LOWSPEED:
174 r |= ISP1704_FUNC_CTRL_LOW_SPEED;
175 r |= ISP1704_FUNC_CTRL_TERMSELECT;
176 r &= ~ISP1704_FUNC_CTRL_OPMODE;
180 ERR("Unknown musb termination\n");
184 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
190 static inline int musb_verify_charger(void __iomem *addr)
194 /* Reset the transceiver */
195 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
196 r |= ISP1704_FUNC_CTRL_RESET;
197 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
200 /* Set normal mode */
201 r &= ~(ISP1704_FUNC_CTRL_RESET | (3 << ISP1704_FUNC_CTRL_OPMODE));
202 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
204 /* Clear the DP and DM pull-down bits */
205 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
206 r &= ~(ISP1704_OTG_CTRL_DP_PULLDOWN | ISP1704_OTG_CTRL_DM_PULLDOWN);
207 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
209 /* Enable strong pull-up on DP (1.5K) and reset */
210 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
211 r |= ISP1704_FUNC_CTRL_TERMSELECT | ISP1704_FUNC_CTRL_RESET;
212 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
215 /* Read the line state */
216 if (musb_ulpi_readb(addr, ISP1704_DEBUG)) {
217 /* Is it a charger or PS2 connection */
219 /* Enable weak pull-up resistor on DP */
220 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
221 r |= ISP1704_PWR_CTRL_DP_WKPU_EN;
222 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
224 /* Disable strong pull-up on DP (1.5K) */
225 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
226 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
227 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
229 /* Enable weak pull-down resistor on DM */
230 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
231 r |= ISP1704_OTG_CTRL_DM_PULLDOWN;
232 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
234 /* It's a charger if the line states are clear */
235 if (!(musb_ulpi_readb(addr, ISP1704_DEBUG)))
238 /* Disable weak pull-up resistor on DP */
239 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
240 r &= ~ISP1704_PWR_CTRL_DP_WKPU_EN;
241 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
245 /* Disable strong pull-up on DP (1.5K) */
246 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
247 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
248 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
254 /* Bad connections with the charger may lead into the transceiver
255 * thinking that a device was just connected. We can wait for 5 ms to
256 * ensure that these cases will generate SUSPEND interrupt and not
257 * RESET. Reading and writing to the transceiver may still cause
258 * RESET interrupts. We mask out RESET/RESUME interrupts to
261 static int check_charger;
262 static int musb_charger_detect(struct musb *musb)
264 unsigned long timeout;
269 testmode = musb_readb(musb->mregs,MUSB_TESTMODE);
273 /* Using ulpi with musb is quite tricky. The following code
274 * was written based on the ulpi application note.
276 * The order of reads and writes and quite important, don't
277 * change it unless you really know what you're doing
280 switch(musb->xceiv->state) {
281 case OTG_STATE_B_IDLE:
282 /* we always reset transceiver */
285 /* HACK: ULPI tends to get stuck when booting with
286 * the cable connected
288 r = musb_readb(musb->mregs, MUSB_DEVCTL);
289 if ((r & MUSB_DEVCTL_VBUS)
290 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
291 musb_save_ctx_and_suspend(&musb->g, 0);
292 musb_restore_ctx_and_resume(&musb->g);
293 if (musb->board && musb->board->set_pm_limits)
294 musb->board->set_pm_limits(
295 musb->controller, 1);
298 /* disable RESET and RESUME interrupts */
299 r = musb_readb(musb->mregs, MUSB_INTRUSBE);
300 r &= ~(MUSB_INTR_RESUME | MUSB_INTR_RESET);
301 musb_writeb(musb->mregs, MUSB_INTRUSBE, r);
303 if (musb->board && musb->board->xceiv_reset)
304 musb->board->xceiv_reset();
306 /* then we resume to sync with controller */
307 r = musb_readb(musb->mregs, MUSB_POWER);
308 musb_writeb(musb->mregs, MUSB_POWER,
309 r | MUSB_POWER_RESUME);
311 musb_writeb(musb->mregs, MUSB_POWER,
312 r & ~MUSB_POWER_RESUME);
314 /* now we set SW control bit in PWR_CTRL register */
315 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL,
316 ISP1704_PWR_CTRL_SWCTRL);
318 r = musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL);
319 r |= (ISP1704_PWR_CTRL_SWCTRL | ISP1704_PWR_CTRL_DPVSRC_EN);
321 /* and finally enable manual charger detection */
322 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
325 timeout = jiffies + msecs_to_jiffies(300);
326 while (!time_after(jiffies, timeout)) {
327 /* Check if there is a charger */
328 vdat = !!(musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL)
329 & ISP1704_PWR_CTRL_VDAT_DET);
334 vdat = musb_verify_charger(musb->mregs);
336 r &= ~ISP1704_PWR_CTRL_DPVSRC_EN;
338 /* Clear DPVSRC_EN, otherwise usb communication doesn't work */
339 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
347 if (vdat && !(testmode & MUSB_TEST_FORCE_HOST)) {
348 /* REVISIT: This code works only with dedicated chargers!
349 * When support for HOST/HUB chargers is added, don't
354 otg_set_suspend(musb->xceiv, 1);
355 musb->is_charger = 1;
357 /* enable interrupts */
358 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
360 /* Make sure the communication starts normally */
361 r = musb_readb(musb->mregs, MUSB_POWER);
362 musb_writeb(musb->mregs, MUSB_POWER,
363 r | MUSB_POWER_RESUME);
365 musb_writeb(musb->mregs, MUSB_POWER,
366 r & ~MUSB_POWER_RESUME);
374 /*-------------------------------------------------------------------------*/
376 static inline struct musb *dev_to_musb(struct device *dev)
378 #ifdef CONFIG_USB_MUSB_HDRC_HCD
379 /* usbcore insists dev->driver_data is a "struct hcd *" */
380 return hcd_to_musb(dev_get_drvdata(dev));
382 return dev_get_drvdata(dev);
386 /*-------------------------------------------------------------------------*/
388 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
391 * Load an endpoint's FIFO
393 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
395 void __iomem *fifo = hw_ep->fifo;
399 DBG(6, "%cX ep%d fifo %p count %d buf %p\n",
400 'T', hw_ep->epnum, fifo, len, src);
402 /* we can't assume unaligned reads work */
403 if (likely((0x01 & (unsigned long) src) == 0)) {
406 /* best case is 32bit-aligned source address */
407 if ((0x02 & (unsigned long) src) == 0) {
409 writesl(fifo, src + index, len >> 2);
410 index += len & ~0x03;
413 musb_writew(fifo, 0, *(u16 *)&src[index]);
418 writesw(fifo, src + index, len >> 1);
419 index += len & ~0x01;
423 musb_writeb(fifo, 0, src[index]);
426 writesb(fifo, src, len);
431 * Unload an endpoint's FIFO
433 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
435 void __iomem *fifo = hw_ep->fifo;
437 DBG(6, "%cX ep%d fifo %p count %d buf %p\n",
438 'R', hw_ep->epnum, fifo, len, dst);
440 /* we can't assume unaligned writes work */
441 if (likely((0x01 & (unsigned long) dst) == 0)) {
444 /* best case is 32bit-aligned destination address */
445 if ((0x02 & (unsigned long) dst) == 0) {
447 readsl(fifo, dst, len >> 2);
451 *(u16 *)&dst[index] = musb_readw(fifo, 0);
456 readsw(fifo, dst, len >> 1);
461 dst[index] = musb_readb(fifo, 0);
464 readsb(fifo, dst, len);
468 #endif /* normal PIO */
471 /*-------------------------------------------------------------------------*/
473 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
474 static const u8 musb_test_packet[53] = {
475 /* implicit SYNC then DATA0 to start */
478 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
480 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
482 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
483 /* JJJJJJJKKKKKKK x8 */
484 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
486 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
487 /* JKKKKKKK x10, JK */
488 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
490 /* implicit CRC16 then EOP to end */
493 void musb_load_testpacket(struct musb *musb)
495 void __iomem *regs = musb->endpoints[0].regs;
497 musb_ep_select(musb->mregs, 0);
498 musb_write_fifo(musb->control_ep,
499 sizeof(musb_test_packet), musb_test_packet);
500 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
503 /*-------------------------------------------------------------------------*/
505 const char *otg_state_string(struct musb *musb)
507 switch (musb->xceiv->state) {
508 case OTG_STATE_A_IDLE: return "a_idle";
509 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
510 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
511 case OTG_STATE_A_HOST: return "a_host";
512 case OTG_STATE_A_SUSPEND: return "a_suspend";
513 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
514 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
515 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
516 case OTG_STATE_B_IDLE: return "b_idle";
517 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
518 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
519 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
520 case OTG_STATE_B_HOST: return "b_host";
521 default: return "UNDEFINED";
525 #ifdef CONFIG_USB_MUSB_OTG
528 * See also USB_OTG_1-3.pdf 6.6.5 Timers
529 * REVISIT: Are the other timers done in the hardware?
531 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
534 * Handles OTG hnp timeouts, such as b_ase0_brst
536 void musb_otg_timer_func(unsigned long data)
538 struct musb *musb = (struct musb *)data;
540 spin_lock_irqsave(&musb->lock, flags);
541 switch (musb->xceiv->state) {
542 case OTG_STATE_B_WAIT_ACON:
543 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
544 musb_g_disconnect(musb);
545 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
548 case OTG_STATE_A_WAIT_BCON:
549 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
553 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
555 musb->ignore_disconnect = 0;
556 spin_unlock_irqrestore(&musb->lock, flags);
559 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
562 * Stops the B-device HNP state. Caller must take care of locking.
564 void musb_hnp_stop(struct musb *musb)
566 struct usb_hcd *hcd = musb_to_hcd(musb);
567 void __iomem *mbase = musb->mregs;
570 switch (musb->xceiv->state) {
571 case OTG_STATE_A_PERIPHERAL:
572 case OTG_STATE_A_WAIT_VFALL:
573 case OTG_STATE_A_WAIT_BCON:
574 DBG(1, "HNP: Switching back to A-host\n");
575 musb_g_disconnect(musb);
576 musb->xceiv->state = OTG_STATE_A_IDLE;
580 case OTG_STATE_B_HOST:
581 DBG(1, "HNP: Disabling HR\n");
582 hcd->self.is_b_host = 0;
583 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
585 reg = musb_readb(mbase, MUSB_POWER);
586 reg |= MUSB_POWER_SUSPENDM;
587 musb_writeb(mbase, MUSB_POWER, reg);
588 /* REVISIT: Start SESSION_REQUEST here? */
591 DBG(1, "HNP: Stopping in unknown state %s\n",
592 otg_state_string(musb));
596 * When returning to A state after HNP, avoid hub_port_rebounce(),
597 * which cause occasional OPT A "Did not receive reset after connect"
600 musb->port1_status &=
601 ~(1 << USB_PORT_FEAT_C_CONNECTION);
607 * Interrupt Service Routine to record USB "global" interrupts.
608 * Since these do not happen often and signify things of
609 * paramount importance, it seems OK to check them individually;
610 * the order of the tests is specified in the manual
612 * @param musb instance pointer
613 * @param int_usb register contents
618 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
622 irqreturn_t handled = IRQ_NONE;
623 void __iomem *mbase = musb->mregs;
626 testmode = musb_readb(mbase,MUSB_TESTMODE);
627 if(testmode & MUSB_TEST_FORCE_HOST) {
628 if(int_usb & MUSB_INTR_SESSREQ) {
629 DBG(1,"Piggybacking CONNECT on SESS REQ\n");
630 musb->int_usb |= MUSB_INTR_CONNECT;
634 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
637 /* in host mode, the peripheral may issue remote wakeup.
638 * in peripheral mode, the host may resume the link.
639 * spurious RESUME irqs happen too, paired with SUSPEND.
641 if (int_usb & MUSB_INTR_RESUME) {
642 handled = IRQ_HANDLED;
643 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
645 if (devctl & MUSB_DEVCTL_HM) {
646 #ifdef CONFIG_USB_MUSB_HDRC_HCD
647 switch (musb->xceiv->state) {
648 case OTG_STATE_A_SUSPEND:
649 /* remote wakeup? later, GetPortStatus
650 * will stop RESUME signaling
653 if (power & MUSB_POWER_SUSPENDM) {
655 musb->int_usb &= ~MUSB_INTR_SUSPEND;
656 DBG(2, "Spurious SUSPENDM\n");
660 power &= ~MUSB_POWER_SUSPENDM;
661 musb_writeb(mbase, MUSB_POWER,
662 power | MUSB_POWER_RESUME);
664 musb->port1_status |=
665 (USB_PORT_STAT_C_SUSPEND << 16)
666 | MUSB_PORT_STAT_RESUME;
667 musb->rh_timer = jiffies
668 + msecs_to_jiffies(20);
670 musb->xceiv->state = OTG_STATE_A_HOST;
672 usb_hcd_resume_root_hub(musb_to_hcd(musb));
674 case OTG_STATE_B_WAIT_ACON:
675 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
680 WARNING("bogus %s RESUME (%s)\n",
682 otg_state_string(musb));
686 switch (musb->xceiv->state) {
687 #ifdef CONFIG_USB_MUSB_HDRC_HCD
688 case OTG_STATE_A_WAIT_BCON:
689 case OTG_STATE_A_HOST:
690 case OTG_STATE_A_SUSPEND:
691 /* possibly DISCONNECT is upcoming */
692 musb->xceiv->state = OTG_STATE_A_HOST;
693 usb_hcd_resume_root_hub(musb_to_hcd(musb));
696 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
697 case OTG_STATE_B_WAIT_ACON:
698 case OTG_STATE_B_PERIPHERAL:
699 /* disconnect while suspended? we may
700 * not get a disconnect irq...
702 if ((devctl & MUSB_DEVCTL_VBUS)
703 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
705 musb->int_usb |= MUSB_INTR_DISCONNECT;
706 musb->int_usb &= ~MUSB_INTR_SUSPEND;
711 case OTG_STATE_B_IDLE:
712 musb->int_usb &= ~MUSB_INTR_SUSPEND;
716 WARNING("bogus %s RESUME (%s)\n",
718 otg_state_string(musb));
723 #ifdef CONFIG_USB_MUSB_HDRC_HCD
724 /* see manual for the order of the tests */
725 if (int_usb & MUSB_INTR_SESSREQ) {
726 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
728 /* IRQ arrives from ID pin sense or (later, if VBUS power
729 * is removed) SRP. responses are time critical:
730 * - turn on VBUS (with silicon-specific mechanism)
731 * - go through A_WAIT_VRISE
732 * - ... to A_WAIT_BCON.
733 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
734 * NOTE : Spurious SESS_REQ int's detected, which should
735 * be discarded silently.
737 if ((devctl & MUSB_DEVCTL_VBUS)
738 && host_mode(musb->mregs)) {
739 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
740 musb->ep0_stage = MUSB_EP0_START;
741 musb->xceiv->state = OTG_STATE_A_IDLE;
743 musb_set_vbus(musb, 1);
745 DBG(5,"discarding SESSREQ INT: VBUS < SessEnd\n");
748 handled = IRQ_HANDLED;
751 if (int_usb & MUSB_INTR_VBUSERROR) {
754 /* During connection as an A-Device, we may see a short
755 * current spikes causing voltage drop, because of cable
756 * and peripheral capacitance combined with vbus draw.
757 * (So: less common with truly self-powered devices, where
758 * vbus doesn't act like a power supply.)
760 * Such spikes are short; usually less than ~500 usec, max
761 * of ~2 msec. That is, they're not sustained overcurrent
762 * errors, though they're reported using VBUSERROR irqs.
764 * Workarounds: (a) hardware: use self powered devices.
765 * (b) software: ignore non-repeated VBUS errors.
767 * REVISIT: do delays from lots of DEBUG_KERNEL checks
768 * make trouble here, keeping VBUS < 4.4V ?
770 switch (musb->xceiv->state) {
771 case OTG_STATE_A_HOST:
772 /* recovery is dicey once we've gotten past the
773 * initial stages of enumeration, but if VBUS
774 * stayed ok at the other end of the link, and
775 * another reset is due (at least for high speed,
776 * to redo the chirp etc), it might work OK...
778 case OTG_STATE_A_WAIT_BCON:
779 case OTG_STATE_A_WAIT_VRISE:
780 if (musb->vbuserr_retry) {
781 musb->vbuserr_retry--;
783 devctl |= MUSB_DEVCTL_SESSION;
784 musb_writeb(mbase, MUSB_DEVCTL, devctl);
786 musb->port1_status |=
787 (1 << USB_PORT_FEAT_OVER_CURRENT)
788 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
795 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
796 otg_state_string(musb),
799 switch (devctl & MUSB_DEVCTL_VBUS) {
800 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
801 s = "<SessEnd"; break;
802 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
803 s = "<AValid"; break;
804 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
805 s = "<VBusValid"; break;
806 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
810 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
813 /* go through A_WAIT_VFALL then start a new session */
815 musb_set_vbus(musb, 0);
816 handled = IRQ_HANDLED;
819 if (int_usb & MUSB_INTR_SUSPEND) {
820 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
821 otg_state_string(musb), devctl, power);
822 handled = IRQ_HANDLED;
824 switch (musb->xceiv->state) {
825 #ifdef CONFIG_USB_MUSB_OTG
826 case OTG_STATE_A_PERIPHERAL:
828 * We cannot stop HNP here, devctl BDEVICE might be
833 case OTG_STATE_B_IDLE:
834 if (!musb->is_active)
836 case OTG_STATE_B_PERIPHERAL:
837 musb_g_suspend(musb);
838 musb->is_active = is_otg_enabled(musb)
839 && musb->xceiv->gadget->b_hnp_enable;
840 if (musb->is_active) {
841 #ifdef CONFIG_USB_MUSB_OTG
842 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
843 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
844 musb_otg_timer.data = (unsigned long)musb;
845 mod_timer(&musb_otg_timer, jiffies
846 + msecs_to_jiffies(TB_ASE0_BRST));
850 case OTG_STATE_A_WAIT_BCON:
851 if (musb->a_wait_bcon != 0)
852 musb_platform_try_idle(musb, jiffies
853 + msecs_to_jiffies(musb->a_wait_bcon));
855 case OTG_STATE_A_HOST:
856 if(testmode & MUSB_TEST_FORCE_HOST) {
857 // musb->int_usb |= MUSB_INTR_RESUME;
861 musb->xceiv->state = OTG_STATE_A_SUSPEND;
862 musb->is_active = is_otg_enabled(musb)
863 && musb->xceiv->host->b_hnp_enable;
866 case OTG_STATE_B_HOST:
867 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
868 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
871 /* "should not happen" */
877 if (int_usb & MUSB_INTR_CONNECT) {
878 struct usb_hcd *hcd = musb_to_hcd(musb);
880 handled = IRQ_HANDLED;
882 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
885 musb->ep0_stage = MUSB_EP0_START;
887 #ifdef CONFIG_USB_MUSB_OTG
888 /* flush endpoints when transitioning from Device Mode */
889 if (is_peripheral_active(musb)) {
890 /* REVISIT HNP; just force disconnect */
892 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
893 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
894 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
896 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
897 |USB_PORT_STAT_HIGH_SPEED
898 |USB_PORT_STAT_ENABLE
900 musb->port1_status |= USB_PORT_STAT_CONNECTION
901 |(USB_PORT_STAT_C_CONNECTION << 16);
903 if (testmode & MUSB_TEST_FORCE_HOST) {
905 void __iomem *mbase = musb->mregs;
907 musb_force_term(musb->mregs,MUSB_TERM_HOST_HIGHSPEED);
909 r = musb_ulpi_readb(mbase, ISP1704_DEBUG);
910 DBG(1,"Linestate %x\n",r);
913 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
914 reg = musb_readb(mbase, MUSB_TESTMODE);
915 reg &= ~MUSB_TEST_FORCE_FS;
916 reg &= ~MUSB_TEST_FORCE_HS;
917 musb_writeb(mbase, MUSB_TESTMODE, reg);
919 reg = musb_readb(mbase, MUSB_POWER);
920 reg &= ~MUSB_POWER_HSENAB;
921 musb_writeb(mbase, MUSB_POWER, reg);
923 musb_force_term(musb->mregs,MUSB_TERM_HOST_LOWSPEED);
926 /*High or full speed*/
927 reg = musb_readb(mbase, MUSB_TESTMODE);
928 if(reg & MUSB_TEST_FORCE_HS) {
930 reg &= ~MUSB_TEST_FORCE_FS;
931 musb_writeb(mbase, MUSB_TESTMODE, reg);
933 reg = musb_readb(mbase, MUSB_POWER);
934 reg |= MUSB_POWER_HSENAB;
935 musb_writeb(mbase, MUSB_POWER, reg);
938 reg |= MUSB_TEST_FORCE_FS;
939 musb_writeb(mbase, MUSB_TESTMODE, reg);
941 reg = musb_readb(mbase, MUSB_POWER);
942 reg &= ~MUSB_POWER_HSENAB;
943 musb_writeb(mbase, MUSB_POWER, reg);
946 musb_force_term(mbase,MUSB_TERM_HOST_FULLSPEED);
952 WARNING("Invalid line state of %d\n",r);
958 /* high vs full speed is just a guess until after reset */
959 if (devctl & MUSB_DEVCTL_LSDEV)
960 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
964 usb_hcd_poll_rh_status(hcd);
966 usb_hcd_resume_root_hub(hcd);
970 /* indicate new connection to OTG machine */
971 switch (musb->xceiv->state) {
972 case OTG_STATE_B_PERIPHERAL:
973 if (int_usb & MUSB_INTR_SUSPEND) {
974 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
975 musb->xceiv->state = OTG_STATE_B_HOST;
976 hcd->self.is_b_host = 1;
977 int_usb &= ~MUSB_INTR_SUSPEND;
979 DBG(1, "CONNECT as b_peripheral???\n");
981 case OTG_STATE_B_WAIT_ACON:
982 DBG(1, "HNP: Waiting to switch to b_host state\n");
983 musb->xceiv->state = OTG_STATE_B_HOST;
984 hcd->self.is_b_host = 1;
987 if ((devctl & MUSB_DEVCTL_VBUS)
988 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
989 musb->xceiv->state = OTG_STATE_A_HOST;
990 hcd->self.is_b_host = 0;
994 DBG(1, "CONNECT (%s) devctl %02x\n",
995 otg_state_string(musb), devctl);
997 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
999 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
1000 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
1001 otg_state_string(musb),
1002 MUSB_MODE(musb), devctl);
1003 handled = IRQ_HANDLED;
1005 switch (musb->xceiv->state) {
1006 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1007 case OTG_STATE_A_HOST:
1008 case OTG_STATE_A_SUSPEND:
1009 usb_hcd_resume_root_hub(musb_to_hcd(musb));
1010 musb_root_disconnect(musb);
1011 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
1012 musb_platform_try_idle(musb, jiffies
1013 + msecs_to_jiffies(musb->a_wait_bcon));
1016 #ifdef CONFIG_USB_MUSB_OTG
1017 case OTG_STATE_B_HOST:
1018 musb_hnp_stop(musb);
1020 case OTG_STATE_A_PERIPHERAL:
1021 musb_hnp_stop(musb);
1022 musb_root_disconnect(musb);
1024 case OTG_STATE_B_WAIT_ACON:
1027 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1028 case OTG_STATE_B_PERIPHERAL:
1029 case OTG_STATE_B_IDLE:
1030 /* Workaround for a problem of Vbus quickly dropping
1031 * during Certification tests.
1033 * Undo the workaround on disconnect
1036 /* Disable suspend so we can write to ULPI */
1037 r = musb_readb(musb->mregs, MUSB_POWER);
1038 musb_writeb(musb->mregs, MUSB_POWER,
1039 r & ~MUSB_POWER_ENSUSPEND);
1040 musb_ulpi_writeb(musb->mregs,
1041 ISP1704_USB_INTFALL, 0x1f);
1042 musb_ulpi_writeb(musb->mregs,
1043 ISP1704_USB_INTRISE, 0x1f);
1044 musb_writeb(musb->mregs, MUSB_POWER,
1045 r | MUSB_POWER_ENSUSPEND);
1047 musb_g_disconnect(musb);
1048 /** UGLY UGLY HACK: Windows problems with multiple
1051 * This is necessary to notify gadget driver this was
1052 * a physical disconnection and not only a port reset.
1054 if (musb->gadget_driver->vbus_disconnect)
1055 musb->gadget_driver->vbus_disconnect(&musb->g);
1060 WARNING("unhandled DISCONNECT transition (%s)\n",
1061 otg_state_string(musb));
1066 /* mentor saves a bit: bus reset and babble share the same irq.
1067 * only host sees babble; only peripheral sees bus reset.
1069 if (int_usb & MUSB_INTR_RESET) {
1070 handled = IRQ_HANDLED;
1071 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
1073 * Looks like non-HS BABBLE can be ignored, but
1074 * HS BABBLE is an error condition. For HS the solution
1075 * is to avoid babble in the first place and fix what
1076 * caused BABBLE. When HS BABBLE happens we can only
1079 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
1080 DBG(1, "BABBLE devctl: %02x\n", devctl);
1082 ERR("Stopping host session -- babble\n");
1083 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1085 } else if (is_peripheral_capable()) {
1086 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
1087 switch (musb->xceiv->state) {
1088 #ifdef CONFIG_USB_OTG
1089 case OTG_STATE_A_SUSPEND:
1090 /* We need to ignore disconnect on suspend
1091 * otherwise tusb 2.0 won't reconnect after a
1092 * power cycle, which breaks otg compliance.
1094 musb->ignore_disconnect = 1;
1097 case OTG_STATE_A_HOST:
1098 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
1099 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
1100 DBG(1, "HNP: Setting timer as %s\n",
1101 otg_state_string(musb));
1102 musb_otg_timer.data = (unsigned long)musb;
1103 mod_timer(&musb_otg_timer, jiffies
1104 + msecs_to_jiffies(100));
1106 case OTG_STATE_A_PERIPHERAL:
1107 musb_hnp_stop(musb);
1109 case OTG_STATE_B_WAIT_ACON:
1110 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
1111 otg_state_string(musb));
1112 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1116 case OTG_STATE_B_IDLE:
1117 /* Workaround the charger detection problems */
1118 if ((devctl & MUSB_DEVCTL_VBUS)
1119 != (3 << MUSB_DEVCTL_VBUS_SHIFT))
1123 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1125 case OTG_STATE_B_PERIPHERAL:
1126 /* Workaround for a problem of Vbus quickly dropping
1127 * during Certification tests.
1129 * The guess is that vbus drops due to the circuitry
1130 * for overcurrent protection and that makes transceiver
1131 * think VBUS is not valid anymore. Transceiver will
1132 * then send an RXCMD to PHY which will cause it to
1133 * disconnect from the bus even though we disable the
1136 musb_ulpi_writeb(musb->mregs,
1137 ISP1704_USB_INTFALL, 0x1d);
1138 musb_ulpi_writeb(musb->mregs,
1139 ISP1704_USB_INTRISE, 0x1d);
1144 DBG(1, "Unhandled BUS RESET as %s\n",
1145 otg_state_string(musb));
1151 /* REVISIT ... this would be for multiplexing periodic endpoints, or
1152 * supporting transfer phasing to prevent exceeding ISO bandwidth
1153 * limits of a given frame or microframe.
1155 * It's not needed for peripheral side, which dedicates endpoints;
1156 * though it _might_ use SOF irqs for other purposes.
1158 * And it's not currently needed for host side, which also dedicates
1159 * endpoints, relies on TX/RX interval registers, and isn't claimed
1160 * to support ISO transfers yet.
1162 if (int_usb & MUSB_INTR_SOF) {
1163 void __iomem *mbase = musb->mregs;
1164 struct musb_hw_ep *ep;
1168 DBG(6, "START_OF_FRAME\n");
1169 handled = IRQ_HANDLED;
1171 /* start any periodic Tx transfers waiting for current frame */
1172 frame = musb_readw(mbase, MUSB_FRAME);
1173 ep = musb->endpoints;
1174 for (epnum = 1; (epnum < musb->nr_endpoints)
1175 && (musb->epmask >= (1 << epnum));
1178 * FIXME handle framecounter wraps (12 bits)
1179 * eliminate duplicated StartUrb logic
1181 if (ep->dwWaitFrame >= frame) {
1182 ep->dwWaitFrame = 0;
1183 pr_debug("SOF --> periodic TX%s on %d\n",
1184 ep->tx_channel ? " DMA" : "",
1186 if (!ep->tx_channel)
1187 musb_h_tx_start(musb, epnum);
1189 cppi_hostdma_start(musb, epnum);
1191 } /* end of for loop */
1195 schedule_work(&musb->irq_work);
1200 /*-------------------------------------------------------------------------*/
1203 * Program the HDRC to start (enable interrupts, dma, etc.).
1205 void musb_start(struct musb *musb)
1207 void __iomem *regs = musb->mregs;
1208 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1211 DBG(2, "<== devctl %02x\n", devctl);
1213 /* Ensure the clocks are on */
1214 if (musb->set_clock)
1215 musb->set_clock(musb->clock, 1);
1217 clk_enable(musb->clock);
1219 /* Set INT enable registers, enable interrupts */
1220 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
1221 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
1222 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1224 musb_writeb(regs, MUSB_TESTMODE, 0);
1226 power = MUSB_POWER_ISOUPDATE | MUSB_POWER_SOFTCONN
1227 | MUSB_POWER_HSENAB;
1229 /* ENSUSPEND wedges tusb */
1231 power |= MUSB_POWER_ENSUSPEND;
1233 /* put into basic highspeed mode and start session */
1234 musb_writeb(regs, MUSB_POWER, power);
1236 musb->is_active = 0;
1237 devctl = musb_readb(regs, MUSB_DEVCTL);
1238 devctl &= ~MUSB_DEVCTL_SESSION;
1240 if (is_otg_enabled(musb)) {
1241 /* session started after:
1242 * (a) ID-grounded irq, host mode;
1243 * (b) vbus present/connect IRQ, peripheral mode;
1244 * (c) peripheral initiates, using SRP
1246 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1247 musb->is_active = 1;
1249 devctl |= MUSB_DEVCTL_SESSION;
1251 } else if (is_host_enabled(musb)) {
1252 /* assume ID pin is hard-wired to ground */
1253 devctl |= MUSB_DEVCTL_SESSION;
1255 } else /* peripheral is enabled */ {
1256 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1257 musb->is_active = 1;
1259 musb_platform_enable(musb);
1260 musb_writeb(regs, MUSB_DEVCTL, devctl);
1264 static void musb_generic_disable(struct musb *musb)
1266 void __iomem *mbase = musb->mregs;
1269 /* Clocks need to be turned on with OFF-mode */
1270 if (musb->set_clock)
1271 musb->set_clock(musb->clock, 1);
1273 clk_enable(musb->clock);
1275 /* disable interrupts */
1276 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1277 musb_writew(mbase, MUSB_INTRTXE, 0);
1278 musb_writew(mbase, MUSB_INTRRXE, 0);
1281 musb_writeb(mbase, MUSB_DEVCTL, 0);
1283 /* flush pending interrupts */
1284 temp = musb_readb(mbase, MUSB_INTRUSB);
1285 temp = musb_readw(mbase, MUSB_INTRTX);
1286 temp = musb_readw(mbase, MUSB_INTRRX);
1290 void musb_emergency_stop(void)
1295 musb_stop(the_musb);
1297 EXPORT_SYMBOL_GPL(musb_emergency_stop);
1300 * Make the HDRC stop (disable interrupts, etc.);
1301 * reversible by musb_start
1302 * called on gadget driver unregister
1303 * with controller locked, irqs blocked
1304 * acts as a NOP unless some role activated the hardware
1306 void musb_stop(struct musb *musb)
1308 /* stop IRQs, timers, ... */
1309 musb_platform_disable(musb);
1310 musb_generic_disable(musb);
1311 DBG(3, "HDRC disabled\n");
1314 * - mark host and/or peripheral drivers unusable/inactive
1315 * - disable DMA (and enable it in HdrcStart)
1316 * - make sure we can musb_start() after musb_stop(); with
1317 * OTG mode, gadget driver module rmmod/modprobe cycles that
1320 musb_platform_try_idle(musb, 0);
1323 static void musb_shutdown(struct platform_device *pdev)
1325 struct musb *musb = dev_to_musb(&pdev->dev);
1326 unsigned long flags;
1328 spin_lock_irqsave(&musb->lock, flags);
1329 musb_platform_disable(musb);
1330 musb_generic_disable(musb);
1332 clk_put(musb->clock);
1335 spin_unlock_irqrestore(&musb->lock, flags);
1337 /* FIXME power down */
1341 /*-------------------------------------------------------------------------*/
1344 * The silicon either has hard-wired endpoint configurations, or else
1345 * "dynamic fifo" sizing. The driver has support for both, though at this
1346 * writing only the dynamic sizing is very well tested. Since we switched
1347 * away from compile-time hardware parameters, we can no longer rely on
1348 * dead code elimination to leave only the relevant one in the object file.
1350 * We don't currently use dynamic fifo setup capability to do anything
1351 * more than selecting one of a bunch of predefined configurations.
1353 #if defined(CONFIG_USB_TUSB6010) || \
1354 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1355 static ushort __initdata fifo_mode = 4;
1357 static ushort __initdata fifo_mode = 2;
1360 /* "modprobe ... fifo_mode=1" etc */
1361 module_param(fifo_mode, ushort, 0);
1362 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1365 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1366 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1370 enum fifo_style style;
1376 * tables defining fifo_mode values. define more if you like.
1377 * for host side, make sure both halves of ep1 are set up.
1380 /* mode 0 - fits in 2KB */
1381 static struct fifo_cfg __initdata mode_0_cfg[] = {
1382 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1383 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1384 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1385 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1386 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1389 /* mode 1 - fits in 4KB */
1390 static struct fifo_cfg __initdata mode_1_cfg[] = {
1391 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1392 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1393 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1394 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1395 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1398 /* mode 2 - fits in 4KB */
1399 static struct fifo_cfg __initdata mode_2_cfg[] = {
1400 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1401 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1402 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1403 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1404 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1405 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1408 /* mode 3 - fits in 4KB */
1409 static struct fifo_cfg __initdata mode_3_cfg[] = {
1410 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1411 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1412 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1413 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1414 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1415 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1418 /* mode 4 - fits in 16KB */
1419 static struct fifo_cfg __initdata mode_4_cfg[] = {
1420 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1421 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1422 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1423 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1424 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1425 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1426 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1427 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1428 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1429 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1430 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1431 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1432 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1433 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1434 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1435 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 64, },
1436 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1437 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 64, },
1438 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1439 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1440 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1441 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 256, },
1442 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1443 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 256, },
1444 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 256, },
1445 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 4096, },
1446 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1447 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1450 /* mode 5 - fits in 16KB */
1451 static struct fifo_cfg __initdata mode_5_cfg[] = {
1452 /* phonet or mass storage */
1453 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1454 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1457 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1458 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1461 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1462 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1465 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1466 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1467 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 16, },
1470 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1471 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1472 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 16, },
1475 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1476 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1478 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1479 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1481 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1482 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1484 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1485 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1489 * configure a fifo; for non-shared endpoints, this may be called
1490 * once for a tx fifo and once for an rx fifo.
1492 * returns negative errno or offset for next fifo.
1495 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1496 const struct fifo_cfg *cfg, u16 offset)
1498 void __iomem *mbase = musb->mregs;
1500 u16 maxpacket = cfg->maxpacket;
1501 u16 c_off = offset >> 3;
1504 /* expect hw_ep has already been zero-initialized */
1506 size = ffs(max(maxpacket, (u16) 8)) - 1;
1507 maxpacket = 1 << size;
1510 if (cfg->mode == BUF_DOUBLE) {
1511 if ((offset + (maxpacket << 1)) >
1512 (1 << (musb->config->ram_bits + 2)))
1514 c_size |= MUSB_FIFOSZ_DPB;
1516 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1520 /* configure the FIFO */
1521 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1523 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1524 /* EP0 reserved endpoint for control, bidirectional;
1525 * EP1 reserved for bulk, two unidirection halves.
1527 if (hw_ep->epnum == 1)
1528 musb->bulk_ep = hw_ep;
1529 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1531 switch (cfg->style) {
1533 musb_write_txfifosz(mbase, c_size);
1534 musb_write_txfifoadd(mbase, c_off);
1535 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1536 hw_ep->max_packet_sz_tx = maxpacket;
1537 ctx.txfifosz[hw_ep->epnum] = c_size;
1538 ctx.txfifoadd[hw_ep->epnum] = c_off;
1541 musb_write_rxfifosz(mbase, c_size);
1542 musb_write_rxfifoadd(mbase, c_off);
1543 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1544 hw_ep->max_packet_sz_rx = maxpacket;
1545 ctx.rxfifosz[hw_ep->epnum] = c_size;
1546 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1549 musb_write_txfifosz(mbase, c_size);
1550 musb_write_txfifoadd(mbase, c_off);
1551 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1552 hw_ep->max_packet_sz_rx = maxpacket;
1554 musb_write_rxfifosz(mbase, c_size);
1555 musb_write_rxfifoadd(mbase, c_off);
1556 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1557 hw_ep->max_packet_sz_tx = maxpacket;
1559 /* Save the context of endpoints. */
1560 ctx.rxfifosz[hw_ep->epnum] = c_size;
1561 ctx.txfifosz[hw_ep->epnum] = c_size;
1562 ctx.txfifoadd[hw_ep->epnum] = c_off;
1563 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1565 hw_ep->is_shared_fifo = true;
1569 /* NOTE rx and tx endpoint irqs aren't managed separately,
1570 * which happens to be ok
1572 musb->epmask |= (1 << hw_ep->epnum);
1574 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1577 static struct fifo_cfg __initdata ep0_cfg = {
1578 .style = FIFO_RXTX, .maxpacket = 64,
1581 static int __init ep_config_from_table(struct musb *musb)
1583 const struct fifo_cfg *cfg;
1586 struct musb_hw_ep *hw_ep = musb->endpoints;
1588 if (machine_is_nokia_rx51())
1591 switch (fifo_mode) {
1597 n = ARRAY_SIZE(mode_0_cfg);
1601 n = ARRAY_SIZE(mode_1_cfg);
1605 n = ARRAY_SIZE(mode_2_cfg);
1609 n = ARRAY_SIZE(mode_3_cfg);
1613 n = ARRAY_SIZE(mode_4_cfg);
1617 n = ARRAY_SIZE(mode_5_cfg);
1621 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1622 musb_driver_name, fifo_mode);
1625 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1626 /* assert(offset > 0) */
1628 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1629 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1632 for (i = 0; i < n; i++) {
1633 u8 epn = cfg->hw_ep_num;
1635 if (epn >= musb->config->num_eps) {
1636 pr_debug("%s: invalid ep %d\n",
1637 musb_driver_name, epn);
1640 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1642 pr_debug("%s: mem overrun, ep %d\n",
1643 musb_driver_name, epn);
1647 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1650 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1652 n + 1, musb->config->num_eps * 2 - 1,
1653 offset, (1 << (musb->config->ram_bits + 2)));
1655 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1656 if (!musb->bulk_ep) {
1657 pr_debug("%s: missing bulk\n", musb_driver_name);
1667 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1668 * @param musb the controller
1670 static int __init ep_config_from_hw(struct musb *musb)
1673 struct musb_hw_ep *hw_ep;
1674 void *mbase = musb->mregs;
1677 DBG(2, "<== static silicon ep config\n");
1679 /* FIXME pick up ep0 maxpacket size */
1681 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1682 musb_ep_select(mbase, epnum);
1683 hw_ep = musb->endpoints + epnum;
1685 ret = musb_read_fifosize(musb, hw_ep, epnum);
1689 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1691 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1692 /* pick an RX/TX endpoint for bulk */
1693 if (hw_ep->max_packet_sz_tx < 512
1694 || hw_ep->max_packet_sz_rx < 512)
1697 /* REVISIT: this algorithm is lazy, we should at least
1698 * try to pick a double buffered endpoint.
1702 musb->bulk_ep = hw_ep;
1706 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1707 if (!musb->bulk_ep) {
1708 pr_debug("%s: missing bulk\n", musb_driver_name);
1716 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1718 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1719 * configure endpoints, or take their config from silicon
1721 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1728 u16 hwvers, rev_major, rev_minor;
1729 char aInfo[78], aRevision[32], aDate[12];
1730 void __iomem *mbase = musb->mregs;
1734 /* log core options (read using indexed model) */
1735 musb_ep_select(mbase, 0);
1736 reg = musb_read_configdata(mbase);
1738 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1739 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1740 strcat(aInfo, ", dyn FIFOs");
1741 if (reg & MUSB_CONFIGDATA_MPRXE) {
1742 strcat(aInfo, ", bulk combine");
1744 musb->bulk_combine = true;
1746 strcat(aInfo, " (X)"); /* no driver support */
1749 if (reg & MUSB_CONFIGDATA_MPTXE) {
1750 strcat(aInfo, ", bulk split");
1752 musb->bulk_split = true;
1754 strcat(aInfo, " (X)"); /* no driver support */
1757 if (reg & MUSB_CONFIGDATA_HBRXE) {
1758 strcat(aInfo, ", HB-ISO Rx");
1759 strcat(aInfo, " (X)"); /* no driver support */
1761 if (reg & MUSB_CONFIGDATA_HBTXE) {
1762 strcat(aInfo, ", HB-ISO Tx");
1763 strcat(aInfo, " (X)"); /* no driver support */
1765 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1766 strcat(aInfo, ", SoftConn");
1768 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1769 musb_driver_name, reg, aInfo);
1772 data = musb_readl(mbase, 0x404);
1773 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1774 (data >> 16) & 0xff, (data >> 24) & 0xff);
1775 /* FIXME ID2 and ID3 are unused */
1776 data = musb_readl(mbase, 0x408);
1777 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1778 data = musb_readl(mbase, 0x40c);
1779 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1780 reg = musb_readb(mbase, 0x400);
1781 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1785 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1786 musb->is_multipoint = 1;
1789 musb->is_multipoint = 0;
1791 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1792 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1794 "%s: kernel must blacklist external hubs\n",
1800 /* log release info */
1801 hwvers = musb_read_hwvers(mbase);
1802 rev_major = (hwvers >> 10) & 0x1f;
1803 rev_minor = hwvers & 0x3ff;
1804 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1805 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1806 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1807 musb_driver_name, type, aRevision, aDate);
1810 musb_configure_ep0(musb);
1812 /* discover endpoint configuration */
1813 musb->nr_endpoints = 1;
1816 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1817 if (musb->config->dyn_fifo)
1818 status = ep_config_from_table(musb);
1820 ERR("reconfigure software for Dynamic FIFOs\n");
1824 if (!musb->config->dyn_fifo)
1825 status = ep_config_from_hw(musb);
1827 ERR("reconfigure software for static FIFOs\n");
1835 /* finish init, and print endpoint config */
1836 for (i = 0; i < musb->nr_endpoints; i++) {
1837 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1839 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1840 #ifdef CONFIG_USB_TUSB6010
1841 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1842 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1843 hw_ep->fifo_sync_va =
1844 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1847 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1849 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1852 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1853 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1854 /* init list of in and out qhs */
1855 INIT_LIST_HEAD(&hw_ep->in_list);
1856 INIT_LIST_HEAD(&hw_ep->out_list);
1857 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1858 hw_ep->rx_reinit = 1;
1859 hw_ep->tx_reinit = 1;
1862 if (hw_ep->max_packet_sz_tx) {
1864 "%s: hw_ep %d%s, %smax %d\n",
1865 musb_driver_name, i,
1866 hw_ep->is_shared_fifo ? "shared" : "tx",
1867 hw_ep->tx_double_buffered
1868 ? "doublebuffer, " : "",
1869 hw_ep->max_packet_sz_tx);
1871 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1873 "%s: hw_ep %d%s, %smax %d\n",
1874 musb_driver_name, i,
1876 hw_ep->rx_double_buffered
1877 ? "doublebuffer, " : "",
1878 hw_ep->max_packet_sz_rx);
1880 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1881 DBG(1, "hw_ep %d not configured\n", i);
1887 /*-------------------------------------------------------------------------*/
1889 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1891 static irqreturn_t generic_interrupt(int irq, void *__hci)
1893 unsigned long flags;
1894 irqreturn_t retval = IRQ_NONE;
1895 struct musb *musb = __hci;
1897 spin_lock_irqsave(&musb->lock, flags);
1899 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1900 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1901 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1903 while (musb->int_usb || musb->int_tx || musb->int_rx)
1904 retval |= musb_interrupt(musb);
1906 spin_unlock_irqrestore(&musb->lock, flags);
1908 /* REVISIT we sometimes get spurious IRQs on g_ep0
1911 if (retval != IRQ_HANDLED)
1912 DBG(5, "spurious?\n");
1918 #define generic_interrupt NULL
1922 * handle all the irqs defined by the HDRC core. for now we expect: other
1923 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1924 * will be assigned, and the irq will already have been acked.
1926 * called in irq context with spinlock held, irqs blocked
1928 irqreturn_t musb_interrupt(struct musb *musb)
1930 irqreturn_t retval = IRQ_NONE;
1931 u8 devctl, power, int_usb;
1935 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1936 power = musb_readb(musb->mregs, MUSB_POWER);
1938 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1939 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1940 musb->int_usb, musb->int_tx, musb->int_rx);
1942 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1943 if (is_otg_enabled(musb)|| is_peripheral_enabled(musb))
1944 if (!musb->gadget_driver) {
1945 DBG(5, "No gadget driver loaded\n");
1953 /* the core can interrupt us for multiple reasons; docs have
1954 * a generic interrupt flowchart to follow
1956 int_usb = musb->int_usb;
1958 int_usb &= ~MUSB_INTR_SOF;
1960 retval |= musb_stage0_irq(musb, int_usb, devctl, power);
1962 /* "stage 1" is handling endpoint irqs */
1964 /* handle endpoint 0 first */
1965 if (musb->int_tx & 1) {
1967 if (devctl & MUSB_DEVCTL_HM)
1968 retval |= musb_h_ep0_irq(musb);
1970 retval |= musb_g_ep0_irq(musb);
1973 /* TX on endpoints 1-15 */
1974 reg = musb->int_tx >> 1;
1979 /* musb_ep_select(musb->mregs, ep_num); */
1980 /* REVISIT just retval |= ep->tx_irq(...) */
1981 retval = IRQ_HANDLED;
1982 if (devctl & MUSB_DEVCTL_HM) {
1983 if (is_host_capable())
1984 musb_host_tx(musb, ep_num);
1986 if (is_peripheral_capable())
1987 musb_g_tx(musb, ep_num);
1994 /* RX on endpoints 1-15 */
1995 reg = musb->int_rx >> 1;
2000 /* musb_ep_select(musb->mregs, ep_num); */
2001 /* REVISIT just retval = ep->rx_irq(...) */
2002 retval = IRQ_HANDLED;
2003 if (devctl & MUSB_DEVCTL_HM) {
2004 if (is_host_capable())
2005 musb_host_rx(musb, ep_num);
2007 if (is_peripheral_capable())
2008 musb_g_rx(musb, ep_num, false);
2020 #ifndef CONFIG_MUSB_PIO_ONLY
2021 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
2023 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2025 /* called with controller lock already held */
2028 #ifndef CONFIG_USB_TUSB_OMAP_DMA
2029 if (!cppi_ti_dma()) {
2031 if (devctl & MUSB_DEVCTL_HM)
2032 musb_h_ep0_irq(musb);
2034 musb_g_ep0_irq(musb);
2038 /* endpoints 1..15 */
2040 if (devctl & MUSB_DEVCTL_HM) {
2041 if (is_host_capable())
2042 musb_host_tx(musb, epnum);
2044 if (is_peripheral_capable())
2045 musb_g_tx(musb, epnum);
2049 if (devctl & MUSB_DEVCTL_HM) {
2050 if (is_host_capable())
2051 musb_host_rx(musb, epnum);
2053 if (is_peripheral_capable())
2054 musb_g_rx(musb, epnum, true);
2061 /*-------------------------------------------------------------------------*/
2066 musb_charger_show(struct device *dev, struct device_attribute *attr, char *buf)
2068 struct musb *musb = dev_to_musb(dev);
2070 return sprintf(buf, "%d\n", (musb->is_charger ?
2071 musb->is_charger : musb_charger_detect(musb)));
2073 static DEVICE_ATTR(charger, 0444, musb_charger_show, NULL);
2076 musb_amp_show(struct device *dev, struct device_attribute *attr, char *buf)
2078 struct musb *musb = dev_to_musb(dev);
2080 return sprintf(buf, "%d\n", musb->power_draw);
2082 static DEVICE_ATTR(mA, 0444, musb_amp_show, NULL);
2085 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
2087 struct musb *musb = dev_to_musb(dev);
2090 mutex_lock(&musb->mutex);
2091 ret = sprintf(buf, "%s\n", otg_state_string(musb));
2092 mutex_unlock(&musb->mutex);
2098 musb_connect_show(struct device *dev, struct device_attribute *attr, char *buf)
2100 struct musb *musb = dev_to_musb(dev);
2101 unsigned long flags;
2104 spin_lock_irqsave(&musb->lock, flags);
2105 ret = sprintf(buf, "%d\n", musb->softconnect);
2106 spin_unlock_irqrestore(&musb->lock, flags);
2112 musb_connect_store(struct device *dev, struct device_attribute *attr,
2113 const char *buf, size_t n)
2115 struct musb *musb = dev_to_musb(dev);
2116 unsigned long flags;
2121 status = sscanf(buf, "%u", &val);
2123 printk(KERN_ERR "invalid parameter, %d\n", status);
2127 spin_lock_irqsave(&musb->lock, flags);
2129 power = musb_readb(musb->mregs, MUSB_POWER);
2132 power |= MUSB_POWER_SOFTCONN;
2134 power &= ~MUSB_POWER_SOFTCONN;
2136 musb->softconnect = !!val;
2137 musb_writeb(musb->mregs, MUSB_POWER, power);
2139 spin_unlock_irqrestore(&musb->lock, flags);
2143 static DEVICE_ATTR(connect, 0644, musb_connect_show, musb_connect_store);
2146 musb_mode_store(struct device *dev, struct device_attribute *attr,
2147 const char *buf, size_t n)
2149 struct musb *musb = dev_to_musb(dev);
2152 mutex_lock(&musb->mutex);
2153 if (sysfs_streq(buf, "host"))
2154 status = musb_platform_set_mode(musb, MUSB_HOST);
2155 else if (sysfs_streq(buf, "peripheral"))
2156 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2157 else if (sysfs_streq(buf, "otg"))
2158 status = musb_platform_set_mode(musb, MUSB_OTG);
2161 mutex_unlock(&musb->mutex);
2163 return (status == 0) ? n : status;
2165 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
2168 musb_vbus_store(struct device *dev, struct device_attribute *attr,
2169 const char *buf, size_t n)
2171 struct musb *musb = dev_to_musb(dev);
2172 unsigned long flags;
2175 if (sscanf(buf, "%lu", &val) < 1) {
2176 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
2180 spin_lock_irqsave(&musb->lock, flags);
2181 musb->a_wait_bcon = val;
2182 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
2183 musb->is_active = 0;
2184 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
2185 spin_unlock_irqrestore(&musb->lock, flags);
2191 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
2193 struct musb *musb = dev_to_musb(dev);
2194 unsigned long flags;
2198 spin_lock_irqsave(&musb->lock, flags);
2199 val = musb->a_wait_bcon;
2200 vbus = musb_platform_get_vbus_status(musb);
2201 spin_unlock_irqrestore(&musb->lock, flags);
2203 return sprintf(buf, "Vbus %s, timeout %lu\n",
2204 vbus ? "on" : "off", val);
2206 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
2208 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2211 musb_suspend_show(struct device *dev, struct device_attribute *attr, char *buf)
2213 struct musb *musb = dev_to_musb(dev);
2215 return sprintf(buf, "%d\n", musb->is_suspended);
2217 static DEVICE_ATTR(suspend, 0444, musb_suspend_show, NULL);
2219 /* Gadget drivers can't know that a host is connected so they might want
2220 * to start SRP, but users can. This allows userspace to trigger SRP.
2223 musb_srp_store(struct device *dev, struct device_attribute *attr,
2224 const char *buf, size_t n)
2226 struct musb *musb = dev_to_musb(dev);
2229 if (sscanf(buf, "%hu", &srp) != 1
2231 printk(KERN_ERR "SRP: Value must be 1\n");
2236 musb_g_wakeup(musb);
2240 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
2242 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2246 /* Only used to provide driver mode change events */
2247 static void musb_irq_work(struct work_struct *data)
2249 struct musb *musb = container_of(data, struct musb, irq_work);
2250 static int old_state, old_ma, old_suspend;
2252 if (musb->xceiv->state != old_state) {
2253 old_state = musb->xceiv->state;
2254 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2256 if (musb->power_draw != old_ma) {
2257 old_ma = musb->power_draw;
2258 sysfs_notify(&musb->controller->kobj, NULL, "mA");
2260 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2261 if (old_suspend != musb->is_suspended) {
2262 old_suspend = musb->is_suspended;
2263 sysfs_notify(&musb->controller->kobj, NULL, "suspend");
2268 /* --------------------------------------------------------------------------
2272 static struct musb *__init
2273 allocate_instance(struct device *dev,
2274 struct musb_hdrc_config *config, void __iomem *mbase)
2277 struct musb_hw_ep *ep;
2279 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2280 struct usb_hcd *hcd;
2282 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2285 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2287 musb = hcd_to_musb(hcd);
2289 hcd->uses_new_polling = 1;
2291 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2293 musb = kzalloc(sizeof *musb, GFP_KERNEL);
2296 dev_set_drvdata(dev, musb);
2300 musb->mregs = mbase;
2301 musb->ctrl_base = mbase;
2302 musb->nIrq = -ENODEV;
2303 musb->config = config;
2304 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2305 for (epnum = 0, ep = musb->endpoints;
2306 epnum < musb->config->num_eps;
2312 musb->controller = dev;
2316 static void musb_free(struct musb *musb)
2318 /* this has multiple entry modes. it handles fault cleanup after
2319 * probe(), where things may be partially set up, as well as rmmod
2320 * cleanup after everything's been de-activated.
2324 device_remove_file(musb->controller, &dev_attr_mA);
2325 device_remove_file(musb->controller, &dev_attr_connect);
2326 device_remove_file(musb->controller, &dev_attr_charger);
2327 device_remove_file(musb->controller, &dev_attr_mode);
2328 device_remove_file(musb->controller, &dev_attr_vbus);
2329 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2330 device_remove_file(musb->controller, &dev_attr_suspend);
2331 device_remove_file(musb->controller, &dev_attr_srp);
2335 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2336 musb_gadget_cleanup(musb);
2339 if (musb->nIrq >= 0) {
2341 disable_irq_wake(musb->nIrq);
2342 free_irq(musb->nIrq, musb);
2344 if (is_dma_capable() && musb->dma_controller) {
2345 struct dma_controller *c = musb->dma_controller;
2348 dma_controller_destroy(c);
2351 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2352 musb_platform_exit(musb);
2353 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2356 clk_disable(musb->clock);
2357 clk_put(musb->clock);
2360 #ifdef CONFIG_USB_MUSB_OTG
2361 put_device(musb->xceiv->dev);
2364 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2365 usb_put_hcd(musb_to_hcd(musb));
2372 * Perform generic per-controller initialization.
2374 * @pDevice: the controller (already clocked, etc)
2376 * @mregs: virtual address of controller registers,
2377 * not yet corrected for platform-specific offsets
2380 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2384 struct musb_hdrc_platform_data *plat = dev->platform_data;
2386 /* The driver might handle more features than the board; OK.
2387 * Fail when the board needs a feature that's not enabled.
2390 dev_dbg(dev, "no platform_data?\n");
2393 switch (plat->mode) {
2395 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2400 case MUSB_PERIPHERAL:
2401 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2407 #ifdef CONFIG_USB_MUSB_OTG
2413 dev_err(dev, "incompatible Kconfig role setting\n");
2418 musb = allocate_instance(dev, plat->config, ctrl);
2424 spin_lock_init(&musb->lock);
2425 mutex_init(&musb->mutex);
2426 musb->board = plat->board;
2427 musb->board_mode = plat->mode;
2428 musb->board_set_power = plat->set_power;
2429 musb->set_clock = plat->set_clock;
2430 musb->min_power = plat->min_power;
2431 musb->use_dma = use_dma;
2433 /* Clock usage is chip-specific ... functional clock (DaVinci,
2434 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2435 * code does is make sure a clock handle is available; platform
2436 * code manages it during start/stop and suspend/resume.
2439 musb->clock = clk_get(dev, plat->clock);
2440 if (IS_ERR(musb->clock)) {
2441 status = PTR_ERR(musb->clock);
2447 /* assume vbus is off */
2449 /* platform adjusts musb->mregs and musb->isr if needed,
2450 * and activates clocks
2452 musb->isr = generic_interrupt;
2453 status = musb_platform_init(musb);
2462 #ifndef CONFIG_MUSB_PIO_ONLY
2463 if (use_dma && dev->dma_mask) {
2464 struct dma_controller *c;
2466 c = dma_controller_create(musb, musb->mregs);
2467 musb->dma_controller = c;
2472 /* ideally this would be abstracted in platform setup */
2473 if (!musb->use_dma || !musb->dma_controller)
2474 dev->dma_mask = NULL;
2476 /* be sure interrupts are disabled before connecting ISR */
2477 musb_platform_disable(musb);
2478 musb_generic_disable(musb);
2480 /* setup musb parts of the core (especially endpoints) */
2481 status = musb_core_init(plat->config->multipoint
2482 ? MUSB_CONTROLLER_MHDRC
2483 : MUSB_CONTROLLER_HDRC, musb);
2487 /* Init IRQ workqueue before request_irq */
2488 INIT_WORK(&musb->irq_work, musb_irq_work);
2490 /* attach to the IRQ */
2491 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2492 dev_err(dev, "request_irq %d failed!\n", nIrq);
2497 /* FIXME this handles wakeup irqs wrong */
2498 if (enable_irq_wake(nIrq) == 0) {
2500 device_init_wakeup(dev, 1);
2505 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2508 switch (musb->board_mode) {
2509 case MUSB_HOST: s = "Host"; break;
2510 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2511 default: s = "OTG"; break;
2514 (is_dma_capable() && musb->dma_controller)
2518 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2519 /* host side needs more setup, except for no-host modes */
2520 if (musb->board_mode != MUSB_PERIPHERAL) {
2521 struct usb_hcd *hcd = musb_to_hcd(musb);
2523 if (musb->board_mode == MUSB_OTG)
2524 hcd->self.otg_port = 1;
2525 musb->xceiv->host = &hcd->self;
2526 hcd->power_budget = 2 * (plat->power ? : 250);
2528 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2530 /* For the host-only role, we can activate right away.
2531 * (We expect the ID pin to be forcibly grounded!!)
2532 * Otherwise, wait till the gadget driver hooks up.
2534 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2535 MUSB_HST_MODE(musb);
2536 musb->xceiv->default_a = 1;
2537 musb->xceiv->state = OTG_STATE_A_IDLE;
2539 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2543 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2545 musb_readb(musb->mregs, MUSB_DEVCTL),
2546 (!host_mode(musb->mregs)
2549 } else /* peripheral is enabled */ {
2550 MUSB_DEV_MODE(musb);
2551 musb->xceiv->default_a = 0;
2552 musb->xceiv->state = OTG_STATE_B_IDLE;
2554 status = musb_gadget_setup(musb);
2558 DBG(1, "%s mode, status %d, dev%02x\n",
2559 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2561 musb_readb(musb->mregs, MUSB_DEVCTL));
2565 if (!(musb_debug_create("driver/musb_hdrc", musb)))
2566 DBG(1, "could not create procfs entry\n");
2569 status = device_create_file(dev, &dev_attr_mA);
2570 status = device_create_file(dev, &dev_attr_connect);
2571 status = device_create_file(dev, &dev_attr_charger);
2572 status = device_create_file(dev, &dev_attr_mode);
2573 status = device_create_file(dev, &dev_attr_vbus);
2574 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2575 status = device_create_file(dev, &dev_attr_suspend);
2576 status = device_create_file(dev, &dev_attr_srp);
2577 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2583 /* Resets the controller. Has to be done. Without this, most likely
2584 * the state machine inside the transceiver doesn't get fixed properly
2586 musb_save_ctx_and_suspend(&musb->g, 0);
2587 musb_restore_ctx_and_resume(&musb->g);
2593 device_remove_file(dev, &dev_attr_mA);
2594 device_remove_file(dev, &dev_attr_connect);
2595 device_remove_file(dev, &dev_attr_charger);
2596 device_remove_file(musb->controller, &dev_attr_mode);
2597 device_remove_file(musb->controller, &dev_attr_vbus);
2598 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2599 device_remove_file(musb->controller, &dev_attr_suspend);
2600 device_remove_file(musb->controller, &dev_attr_srp);
2603 musb_platform_exit(musb);
2605 dev_err(musb->controller,
2606 "musb_init_controller failed with status %d\n", status);
2609 clk_put(musb->clock);
2610 device_init_wakeup(dev, 0);
2617 /*-------------------------------------------------------------------------*/
2619 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2620 * bridge to a platform device; this driver then suffices.
2623 #ifndef CONFIG_MUSB_PIO_ONLY
2624 static u64 *orig_dma_mask;
2627 static int __init musb_probe(struct platform_device *pdev)
2629 struct device *dev = &pdev->dev;
2630 int irq = platform_get_irq(pdev, 0);
2631 struct resource *iomem;
2634 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2635 if (!iomem || irq == 0)
2638 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2640 dev_err(dev, "ioremap failed\n");
2644 #ifndef CONFIG_MUSB_PIO_ONLY
2645 /* clobbered by use_dma=n */
2646 orig_dma_mask = dev->dma_mask;
2648 /* Store initial mask for USB interrupts */
2649 ctx.intrusbe = 0xf7;
2651 return musb_init_controller(dev, irq, base);
2654 static int __devexit musb_remove(struct platform_device *pdev)
2656 struct musb *musb = dev_to_musb(&pdev->dev);
2657 void __iomem *ctrl_base = musb->ctrl_base;
2659 /* this gets called on rmmod.
2660 * - Host mode: host may still be active
2661 * - Peripheral mode: peripheral is deactivated (or never-activated)
2662 * - OTG mode: both roles are deactivated (or never-activated)
2664 musb_shutdown(pdev);
2665 musb_debug_delete("driver/musb_hdrc", musb);
2666 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2667 if (musb->board_mode == MUSB_HOST)
2668 usb_remove_hcd(musb_to_hcd(musb));
2672 device_init_wakeup(&pdev->dev, 0);
2673 #ifndef CONFIG_MUSB_PIO_ONLY
2674 pdev->dev.dma_mask = orig_dma_mask;
2681 void musb_save_ctx(struct musb *musb)
2683 ctx.power = musb_readb(musb->mregs, MUSB_POWER);
2684 ctx.intrtxe = musb_readw(musb->mregs, MUSB_INTRTXE);
2685 ctx.intrrxe = musb_readw(musb->mregs, MUSB_INTRRXE);
2686 ctx.intrusbe = musb_readb(musb->mregs, MUSB_INTRUSBE);
2687 ctx.devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2690 void musb_restore_ctx(struct musb *musb)
2693 musb_writeb(musb->mregs, MUSB_POWER, ctx.power);
2694 musb_writew(musb->mregs, MUSB_INTRTX, 0x00);
2695 musb_writew(musb->mregs, MUSB_INTRTXE, ctx.intrtxe);
2696 musb_writew(musb->mregs, MUSB_INTRRX, 0x00);
2697 musb_writew(musb->mregs, MUSB_INTRRXE, ctx.intrrxe);
2698 musb_writeb(musb->mregs, MUSB_INTRUSB, 0x00);
2699 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
2700 musb_writeb(musb->mregs, MUSB_DEVCTL, ctx.devctl);
2702 /* iterate over every endpoint, select it and restore its context */
2703 for (i = 0; i < musb->config->num_eps; i++) {
2704 musb_writeb(musb->mregs, MUSB_INDEX, i);
2705 musb_writeb(musb->mregs, MUSB_RXFIFOSZ, ctx.rxfifosz[i]);
2706 musb_writeb(musb->mregs, MUSB_TXFIFOSZ, ctx.txfifosz[i]);
2707 musb_writew(musb->mregs, MUSB_TXFIFOADD, ctx.txfifoadd[i]);
2708 musb_writew(musb->mregs, MUSB_RXFIFOADD, ctx.rxfifoadd[i]);
2712 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2714 unsigned long flags;
2715 struct musb *musb = dev_to_musb(&pdev->dev);
2720 spin_lock_irqsave(&musb->lock, flags);
2722 if (is_peripheral_active(musb)) {
2723 /* FIXME force disconnect unless we know USB will wake
2724 * the system up quickly enough to respond ...
2726 } else if (is_host_active(musb)) {
2727 /* we know all the children are suspended; sometimes
2728 * they will even be wakeup-enabled.
2733 musb_save_ctx(musb);
2735 if (musb->set_clock)
2736 musb->set_clock(musb->clock, 0);
2738 clk_disable(musb->clock);
2740 spin_unlock_irqrestore(&musb->lock, flags);
2744 static int musb_resume(struct platform_device *pdev)
2746 unsigned long flags;
2747 struct musb *musb = dev_to_musb(&pdev->dev);
2752 spin_lock_irqsave(&musb->lock, flags);
2754 if (musb->set_clock)
2755 musb->set_clock(musb->clock, 1);
2757 clk_enable(musb->clock);
2759 /* restore context */
2760 musb_restore_ctx(musb);
2762 /* for static cmos like DaVinci, register values were preserved
2763 * unless for some reason the whole soc powered down and we're
2764 * not treating that as a whole-system restart (e.g. swsusp)
2766 spin_unlock_irqrestore(&musb->lock, flags);
2771 #define musb_suspend NULL
2772 #define musb_resume NULL
2775 static struct platform_driver musb_driver = {
2777 .name = (char *)musb_driver_name,
2778 .bus = &platform_bus_type,
2779 .owner = THIS_MODULE,
2781 .remove = __devexit_p(musb_remove),
2782 .shutdown = musb_shutdown,
2783 .suspend = musb_suspend,
2784 .resume = musb_resume,
2787 /*-------------------------------------------------------------------------*/
2789 static int __init musb_init(void)
2791 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2796 pr_info("%s: version " MUSB_VERSION ", "
2797 #ifdef CONFIG_MUSB_PIO_ONLY
2799 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2801 #elif defined(CONFIG_USB_INVENTRA_DMA)
2803 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2809 #ifdef CONFIG_USB_MUSB_OTG
2810 "otg (peripheral+host)"
2811 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2813 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2817 musb_driver_name, musb_debug);
2818 return platform_driver_probe(&musb_driver, musb_probe);
2821 /* make us init after usbcore and before usb
2822 * gadget and host-side drivers start to register
2824 subsys_initcall(musb_init);
2826 static void __exit musb_cleanup(void)
2828 platform_driver_unregister(&musb_driver);
2830 module_exit(musb_cleanup);