4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 /* XXX: move that elsewhere */
37 static uint16_t *gen_opc_ptr;
38 static uint32_t *gen_opparam_ptr;
39 int __op_param1, __op_param2, __op_param3;
40 #ifdef USE_DIRECT_JUMP
41 int __op_jmp0, __op_jmp1;
45 static inline void flush_icache_range(unsigned long start, unsigned long stop)
51 static inline void flush_icache_range(unsigned long start, unsigned long stop)
57 static inline void flush_icache_range(unsigned long start, unsigned long stop)
64 #define MIN_CACHE_LINE_SIZE 8 /* conservative value */
66 static void inline flush_icache_range(unsigned long start, unsigned long stop)
70 p = start & ~(MIN_CACHE_LINE_SIZE - 1);
71 stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
73 for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
74 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
76 asm volatile ("sync" : : : "memory");
77 for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
78 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
80 asm volatile ("sync" : : : "memory");
81 asm volatile ("isync" : : : "memory");
86 static inline void flush_icache_range(unsigned long start, unsigned long stop)
94 static void inline flush_icache_range(unsigned long start, unsigned long stop)
98 p = start & ~(8UL - 1UL);
99 stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
101 for (; p < stop; p += 8)
102 __asm__ __volatile__("flush\t%0" : : "r" (p));
108 static inline void flush_icache_range(unsigned long start, unsigned long stop)
110 register unsigned long _beg __asm ("a1") = start;
111 register unsigned long _end __asm ("a2") = stop;
112 register unsigned long _flg __asm ("a3") = 0;
113 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
117 extern FILE *logfile;
120 #define PREFIX_REPZ 0x01
121 #define PREFIX_REPNZ 0x02
122 #define PREFIX_LOCK 0x04
123 #define PREFIX_DATA 0x08
124 #define PREFIX_ADR 0x10
126 typedef struct DisasContext {
127 /* current insn context */
128 int override; /* -1 if no override */
131 uint8_t *pc; /* pc = eip + cs_base */
132 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
133 static state change (stop translation) */
134 /* current block context */
135 uint8_t *cs_base; /* base of CS segment */
136 int code32; /* 32 bit code segment */
137 int ss32; /* 32 bit stack segment */
138 int cc_op; /* current CC operation */
139 int addseg; /* non zero if either DS/ES/SS have a non zero base */
140 int f_st; /* currently unused */
141 int vm86; /* vm86 mode */
144 int tf; /* TF cpu flag */
145 TranslationBlock *tb;
148 /* i386 arith/logic operations */
168 OP_SHL1, /* undocumented */
173 #define DEF(s, n, copy_size) INDEX_op_ ## s,
174 #include "opc-i386.h"
191 /* I386 int registers */
192 OR_EAX, /* MUST be even numbered */
200 OR_TMP0, /* temporary operand register */
202 OR_A0, /* temporary register used when doing address evaluation */
203 OR_ZERO, /* fixed zero register */
207 typedef void (GenOpFunc)(void);
208 typedef void (GenOpFunc1)(long);
209 typedef void (GenOpFunc2)(long, long);
210 typedef void (GenOpFunc3)(long, long, long);
212 static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
245 static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
278 static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
301 static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
371 static GenOpFunc *gen_op_movl_A0_reg[8] = {
382 static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
394 gen_op_addl_A0_EAX_s1,
395 gen_op_addl_A0_ECX_s1,
396 gen_op_addl_A0_EDX_s1,
397 gen_op_addl_A0_EBX_s1,
398 gen_op_addl_A0_ESP_s1,
399 gen_op_addl_A0_EBP_s1,
400 gen_op_addl_A0_ESI_s1,
401 gen_op_addl_A0_EDI_s1,
404 gen_op_addl_A0_EAX_s2,
405 gen_op_addl_A0_ECX_s2,
406 gen_op_addl_A0_EDX_s2,
407 gen_op_addl_A0_EBX_s2,
408 gen_op_addl_A0_ESP_s2,
409 gen_op_addl_A0_EBP_s2,
410 gen_op_addl_A0_ESI_s2,
411 gen_op_addl_A0_EDI_s2,
414 gen_op_addl_A0_EAX_s3,
415 gen_op_addl_A0_ECX_s3,
416 gen_op_addl_A0_EDX_s3,
417 gen_op_addl_A0_EBX_s3,
418 gen_op_addl_A0_ESP_s3,
419 gen_op_addl_A0_EBP_s3,
420 gen_op_addl_A0_ESI_s3,
421 gen_op_addl_A0_EDI_s3,
425 static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
427 gen_op_cmovw_EAX_T1_T0,
428 gen_op_cmovw_ECX_T1_T0,
429 gen_op_cmovw_EDX_T1_T0,
430 gen_op_cmovw_EBX_T1_T0,
431 gen_op_cmovw_ESP_T1_T0,
432 gen_op_cmovw_EBP_T1_T0,
433 gen_op_cmovw_ESI_T1_T0,
434 gen_op_cmovw_EDI_T1_T0,
437 gen_op_cmovl_EAX_T1_T0,
438 gen_op_cmovl_ECX_T1_T0,
439 gen_op_cmovl_EDX_T1_T0,
440 gen_op_cmovl_EBX_T1_T0,
441 gen_op_cmovl_ESP_T1_T0,
442 gen_op_cmovl_EBP_T1_T0,
443 gen_op_cmovl_ESI_T1_T0,
444 gen_op_cmovl_EDI_T1_T0,
448 static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
449 gen_op_addl_T0_T1_cc,
453 gen_op_andl_T0_T1_cc,
454 gen_op_subl_T0_T1_cc,
455 gen_op_xorl_T0_T1_cc,
456 gen_op_cmpl_T0_T1_cc,
459 static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
461 gen_op_adcb_T0_T1_cc,
462 gen_op_sbbb_T0_T1_cc,
465 gen_op_adcw_T0_T1_cc,
466 gen_op_sbbw_T0_T1_cc,
469 gen_op_adcl_T0_T1_cc,
470 gen_op_sbbl_T0_T1_cc,
474 static const int cc_op_arithb[8] = {
485 static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
486 gen_op_cmpxchgb_T0_T1_EAX_cc,
487 gen_op_cmpxchgw_T0_T1_EAX_cc,
488 gen_op_cmpxchgl_T0_T1_EAX_cc,
491 static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
493 gen_op_rolb_T0_T1_cc,
494 gen_op_rorb_T0_T1_cc,
495 gen_op_rclb_T0_T1_cc,
496 gen_op_rcrb_T0_T1_cc,
497 gen_op_shlb_T0_T1_cc,
498 gen_op_shrb_T0_T1_cc,
499 gen_op_shlb_T0_T1_cc,
500 gen_op_sarb_T0_T1_cc,
503 gen_op_rolw_T0_T1_cc,
504 gen_op_rorw_T0_T1_cc,
505 gen_op_rclw_T0_T1_cc,
506 gen_op_rcrw_T0_T1_cc,
507 gen_op_shlw_T0_T1_cc,
508 gen_op_shrw_T0_T1_cc,
509 gen_op_shlw_T0_T1_cc,
510 gen_op_sarw_T0_T1_cc,
513 gen_op_roll_T0_T1_cc,
514 gen_op_rorl_T0_T1_cc,
515 gen_op_rcll_T0_T1_cc,
516 gen_op_rcrl_T0_T1_cc,
517 gen_op_shll_T0_T1_cc,
518 gen_op_shrl_T0_T1_cc,
519 gen_op_shll_T0_T1_cc,
520 gen_op_sarl_T0_T1_cc,
524 static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
526 gen_op_shldw_T0_T1_im_cc,
527 gen_op_shrdw_T0_T1_im_cc,
530 gen_op_shldl_T0_T1_im_cc,
531 gen_op_shrdl_T0_T1_im_cc,
535 static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
537 gen_op_shldw_T0_T1_ECX_cc,
538 gen_op_shrdw_T0_T1_ECX_cc,
541 gen_op_shldl_T0_T1_ECX_cc,
542 gen_op_shrdl_T0_T1_ECX_cc,
546 static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
549 gen_op_btsw_T0_T1_cc,
550 gen_op_btrw_T0_T1_cc,
551 gen_op_btcw_T0_T1_cc,
555 gen_op_btsl_T0_T1_cc,
556 gen_op_btrl_T0_T1_cc,
557 gen_op_btcl_T0_T1_cc,
561 static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
572 static GenOpFunc *gen_op_lds_T0_A0[3] = {
577 static GenOpFunc *gen_op_ldu_T0_A0[3] = {
582 /* sign does not matter */
583 static GenOpFunc *gen_op_ld_T0_A0[3] = {
589 static GenOpFunc *gen_op_ld_T1_A0[3] = {
595 static GenOpFunc *gen_op_st_T0_A0[3] = {
601 /* the _a32 and _a16 string operations use A0 as the base register. */
603 #define STRINGOP(x) \
604 gen_op_ ## x ## b_fast, \
605 gen_op_ ## x ## w_fast, \
606 gen_op_ ## x ## l_fast, \
607 gen_op_ ## x ## b_a32, \
608 gen_op_ ## x ## w_a32, \
609 gen_op_ ## x ## l_a32, \
610 gen_op_ ## x ## b_a16, \
611 gen_op_ ## x ## w_a16, \
612 gen_op_ ## x ## l_a16,
614 static GenOpFunc *gen_op_movs[9 * 2] = {
619 static GenOpFunc *gen_op_stos[9 * 2] = {
624 static GenOpFunc *gen_op_lods[9 * 2] = {
629 static GenOpFunc *gen_op_scas[9 * 3] = {
635 static GenOpFunc *gen_op_cmps[9 * 3] = {
641 static GenOpFunc *gen_op_ins[9 * 2] = {
647 static GenOpFunc *gen_op_outs[9 * 2] = {
653 static inline void gen_string_ds(DisasContext *s, int ot, GenOpFunc **func)
657 override = s->override;
660 if (s->addseg && override < 0)
663 gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
671 gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
672 /* 16 address, always override */
678 static inline void gen_string_es(DisasContext *s, int ot, GenOpFunc **func)
695 static GenOpFunc *gen_op_in[3] = {
701 static GenOpFunc *gen_op_out[3] = {
718 static GenOpFunc3 *gen_jcc_sub[3][8] = {
750 static GenOpFunc2 *gen_op_loop[2][4] = {
765 static GenOpFunc *gen_setcc_slow[8] = {
776 static GenOpFunc *gen_setcc_sub[3][8] = {
781 gen_op_setbe_T0_subb,
785 gen_op_setle_T0_subb,
791 gen_op_setbe_T0_subw,
795 gen_op_setle_T0_subw,
801 gen_op_setbe_T0_subl,
805 gen_op_setle_T0_subl,
809 static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
815 gen_op_fsubr_ST0_FT0,
817 gen_op_fdivr_ST0_FT0,
820 /* NOTE the exception in "r" op ordering */
821 static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
826 gen_op_fsubr_STN_ST0,
828 gen_op_fdivr_STN_ST0,
832 static void gen_op(DisasContext *s1, int op, int ot, int d, int s)
835 gen_op_mov_TN_reg[ot][0][d]();
837 gen_op_mov_TN_reg[ot][1][s]();
838 if (op == OP_ADCL || op == OP_SBBL) {
839 if (s1->cc_op != CC_OP_DYNAMIC)
840 gen_op_set_cc_op(s1->cc_op);
841 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
842 s1->cc_op = CC_OP_DYNAMIC;
844 gen_op_arith_T0_T1_cc[op]();
845 s1->cc_op = cc_op_arithb[op] + ot;
847 if (d != OR_TMP0 && op != OP_CMPL)
848 gen_op_mov_reg_T0[ot][d]();
851 static void gen_opi(DisasContext *s1, int op, int ot, int d, int c)
853 gen_op_movl_T1_im(c);
854 gen_op(s1, op, ot, d, OR_TMP1);
857 static void gen_inc(DisasContext *s1, int ot, int d, int c)
860 gen_op_mov_TN_reg[ot][0][d]();
861 if (s1->cc_op != CC_OP_DYNAMIC)
862 gen_op_set_cc_op(s1->cc_op);
865 s1->cc_op = CC_OP_INCB + ot;
868 s1->cc_op = CC_OP_DECB + ot;
871 gen_op_mov_reg_T0[ot][d]();
874 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
877 gen_op_mov_TN_reg[ot][0][d]();
879 gen_op_mov_TN_reg[ot][1][s]();
880 /* for zero counts, flags are not updated, so must do it dynamically */
881 if (s1->cc_op != CC_OP_DYNAMIC)
882 gen_op_set_cc_op(s1->cc_op);
884 gen_op_shift_T0_T1_cc[ot][op]();
887 gen_op_mov_reg_T0[ot][d]();
888 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
891 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
893 /* currently not optimized */
894 gen_op_movl_T1_im(c);
895 gen_shift(s1, op, ot, d, OR_TMP1);
898 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
905 int mod, rm, code, override, must_add_seg;
907 override = s->override;
908 must_add_seg = s->addseg;
911 mod = (modrm >> 6) & 3;
923 code = ldub(s->pc++);
924 scale = (code >> 6) & 3;
925 index = (code >> 3) & 7;
940 disp = (int8_t)ldub(s->pc++);
950 gen_op_movl_A0_reg[base]();
952 gen_op_addl_A0_im(disp);
954 gen_op_movl_A0_im(disp);
956 if (havesib && (index != 4 || scale != 0)) {
957 gen_op_addl_A0_reg_sN[scale][index]();
961 if (base == R_EBP || base == R_ESP)
966 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
974 gen_op_movl_A0_im(disp);
975 rm = 0; /* avoid SS override */
982 disp = (int8_t)ldub(s->pc++);
992 gen_op_movl_A0_reg[R_EBX]();
993 gen_op_addl_A0_reg_sN[0][R_ESI]();
996 gen_op_movl_A0_reg[R_EBX]();
997 gen_op_addl_A0_reg_sN[0][R_EDI]();
1000 gen_op_movl_A0_reg[R_EBP]();
1001 gen_op_addl_A0_reg_sN[0][R_ESI]();
1004 gen_op_movl_A0_reg[R_EBP]();
1005 gen_op_addl_A0_reg_sN[0][R_EDI]();
1008 gen_op_movl_A0_reg[R_ESI]();
1011 gen_op_movl_A0_reg[R_EDI]();
1014 gen_op_movl_A0_reg[R_EBP]();
1018 gen_op_movl_A0_reg[R_EBX]();
1022 gen_op_addl_A0_im(disp);
1023 gen_op_andl_A0_ffff();
1027 if (rm == 2 || rm == 3 || rm == 6)
1032 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
1042 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1044 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1046 int mod, rm, opreg, disp;
1048 mod = (modrm >> 6) & 3;
1053 gen_op_mov_TN_reg[ot][0][reg]();
1054 gen_op_mov_reg_T0[ot][rm]();
1056 gen_op_mov_TN_reg[ot][0][rm]();
1058 gen_op_mov_reg_T0[ot][reg]();
1061 gen_lea_modrm(s, modrm, &opreg, &disp);
1064 gen_op_mov_TN_reg[ot][0][reg]();
1065 gen_op_st_T0_A0[ot]();
1067 gen_op_ld_T0_A0[ot]();
1069 gen_op_mov_reg_T0[ot][reg]();
1074 static inline uint32_t insn_get(DisasContext *s, int ot)
1096 static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1098 TranslationBlock *tb;
1103 jcc_op = (b >> 1) & 7;
1105 /* we optimize the cmp/jcc case */
1109 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1112 /* some jumps are easy to compute */
1139 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1142 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1154 if (s->cc_op != CC_OP_DYNAMIC)
1155 gen_op_set_cc_op(s->cc_op);
1158 gen_setcc_slow[jcc_op]();
1164 func((long)tb, val, next_eip);
1166 func((long)tb, next_eip, val);
1171 static void gen_setcc(DisasContext *s, int b)
1177 jcc_op = (b >> 1) & 7;
1179 /* we optimize the cmp/jcc case */
1183 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1188 /* some jumps are easy to compute */
1206 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1209 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1217 if (s->cc_op != CC_OP_DYNAMIC)
1218 gen_op_set_cc_op(s->cc_op);
1219 func = gen_setcc_slow[jcc_op];
1228 /* move T0 to seg_reg and compute if the CPU state may change */
1229 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1232 gen_op_movl_seg_T0(seg_reg, cur_eip);
1234 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]),
1235 offsetof(CPUX86State,seg_cache[seg_reg].base));
1236 if (!s->addseg && seg_reg < R_FS)
1237 s->is_jmp = 2; /* abort translation because the register may
1238 have a non zero base */
1241 /* generate a push. It depends on ss32, addseg and dflag */
1242 static void gen_push_T0(DisasContext *s)
1252 gen_op_pushl_ss32_T0();
1254 gen_op_pushw_ss32_T0();
1258 gen_op_pushl_ss16_T0();
1260 gen_op_pushw_ss16_T0();
1264 /* two step pop is necessary for precise exceptions */
1265 static void gen_pop_T0(DisasContext *s)
1275 gen_op_popl_ss32_T0();
1277 gen_op_popw_ss32_T0();
1281 gen_op_popl_ss16_T0();
1283 gen_op_popw_ss16_T0();
1287 static inline void gen_stack_update(DisasContext *s, int addend)
1291 gen_op_addl_ESP_2();
1292 else if (addend == 4)
1293 gen_op_addl_ESP_4();
1295 gen_op_addl_ESP_im(addend);
1298 gen_op_addw_ESP_2();
1299 else if (addend == 4)
1300 gen_op_addw_ESP_4();
1302 gen_op_addw_ESP_im(addend);
1306 static void gen_pop_update(DisasContext *s)
1308 gen_stack_update(s, 2 << s->dflag);
1311 static void gen_stack_A0(DisasContext *s)
1313 gen_op_movl_A0_ESP();
1315 gen_op_andl_A0_ffff();
1316 gen_op_movl_T1_A0();
1318 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
1321 /* NOTE: wrap around in 16 bit not fully handled */
1322 static void gen_pusha(DisasContext *s)
1325 gen_op_movl_A0_ESP();
1326 gen_op_addl_A0_im(-16 << s->dflag);
1328 gen_op_andl_A0_ffff();
1329 gen_op_movl_T1_A0();
1331 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
1332 for(i = 0;i < 8; i++) {
1333 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1334 gen_op_st_T0_A0[OT_WORD + s->dflag]();
1335 gen_op_addl_A0_im(2 << s->dflag);
1337 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1340 /* NOTE: wrap around in 16 bit not fully handled */
1341 static void gen_popa(DisasContext *s)
1344 gen_op_movl_A0_ESP();
1346 gen_op_andl_A0_ffff();
1347 gen_op_movl_T1_A0();
1348 gen_op_addl_T1_im(16 << s->dflag);
1350 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
1351 for(i = 0;i < 8; i++) {
1352 /* ESP is not reloaded */
1354 gen_op_ld_T0_A0[OT_WORD + s->dflag]();
1355 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1357 gen_op_addl_A0_im(2 << s->dflag);
1359 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1362 /* NOTE: wrap around in 16 bit not fully handled */
1363 /* XXX: check this */
1364 static void gen_enter(DisasContext *s, int esp_addend, int level)
1366 int ot, level1, addend, opsize;
1368 ot = s->dflag + OT_WORD;
1371 opsize = 2 << s->dflag;
1373 gen_op_movl_A0_ESP();
1374 gen_op_addl_A0_im(-opsize);
1376 gen_op_andl_A0_ffff();
1377 gen_op_movl_T1_A0();
1379 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
1381 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1382 gen_op_st_T0_A0[ot]();
1385 gen_op_addl_A0_im(-opsize);
1386 gen_op_addl_T0_im(-opsize);
1387 gen_op_st_T0_A0[ot]();
1389 gen_op_addl_A0_im(-opsize);
1390 /* XXX: add st_T1_A0 ? */
1391 gen_op_movl_T0_T1();
1392 gen_op_st_T0_A0[ot]();
1394 gen_op_mov_reg_T1[ot][R_EBP]();
1395 addend = -esp_addend;
1397 addend -= opsize * (level1 + 1);
1398 gen_op_addl_T1_im(addend);
1399 gen_op_mov_reg_T1[ot][R_ESP]();
1402 static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1404 if (s->cc_op != CC_OP_DYNAMIC)
1405 gen_op_set_cc_op(s->cc_op);
1406 gen_op_jmp_im(cur_eip);
1407 gen_op_raise_exception(trapno);
1411 /* an interrupt is different from an exception because of the
1412 priviledge checks */
1413 static void gen_interrupt(DisasContext *s, int intno,
1414 unsigned int cur_eip, unsigned int next_eip)
1416 if (s->cc_op != CC_OP_DYNAMIC)
1417 gen_op_set_cc_op(s->cc_op);
1418 gen_op_jmp_im(cur_eip);
1419 gen_op_raise_interrupt(intno, next_eip);
1423 /* generate a jump to eip. No segment change must happen before as a
1424 direct call to the next block may occur */
1425 static void gen_jmp(DisasContext *s, unsigned int eip)
1427 TranslationBlock *tb = s->tb;
1429 if (s->cc_op != CC_OP_DYNAMIC)
1430 gen_op_set_cc_op(s->cc_op);
1431 gen_op_jmp_tb_next((long)tb, eip);
1435 /* return the next pc address. Return -1 if no insn found. *is_jmp_ptr
1436 is set to true if the instruction sets the PC (last instruction of
1438 long disas_insn(DisasContext *s, uint8_t *pc_start)
1440 int b, prefixes, aflag, dflag;
1442 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1443 unsigned int next_eip;
1453 /* check prefixes */
1456 prefixes |= PREFIX_REPZ;
1459 prefixes |= PREFIX_REPNZ;
1462 prefixes |= PREFIX_LOCK;
1483 prefixes |= PREFIX_DATA;
1486 prefixes |= PREFIX_ADR;
1490 if (prefixes & PREFIX_DATA)
1492 if (prefixes & PREFIX_ADR)
1495 s->prefix = prefixes;
1499 /* lock generation */
1500 if (prefixes & PREFIX_LOCK)
1503 /* now check op code */
1507 /**************************/
1508 /* extended op code */
1509 b = ldub(s->pc++) | 0x100;
1512 /**************************/
1530 ot = dflag ? OT_LONG : OT_WORD;
1533 case 0: /* OP Ev, Gv */
1534 modrm = ldub(s->pc++);
1535 reg = ((modrm >> 3) & 7) + OR_EAX;
1536 mod = (modrm >> 6) & 3;
1539 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1540 gen_op_ld_T0_A0[ot]();
1543 opreg = OR_EAX + rm;
1545 gen_op(s, op, ot, opreg, reg);
1546 if (mod != 3 && op != 7) {
1547 gen_op_st_T0_A0[ot]();
1550 case 1: /* OP Gv, Ev */
1551 modrm = ldub(s->pc++);
1552 mod = (modrm >> 6) & 3;
1553 reg = ((modrm >> 3) & 7) + OR_EAX;
1556 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1557 gen_op_ld_T1_A0[ot]();
1560 opreg = OR_EAX + rm;
1562 gen_op(s, op, ot, reg, opreg);
1564 case 2: /* OP A, Iv */
1565 val = insn_get(s, ot);
1566 gen_opi(s, op, ot, OR_EAX, val);
1572 case 0x80: /* GRP1 */
1581 ot = dflag ? OT_LONG : OT_WORD;
1583 modrm = ldub(s->pc++);
1584 mod = (modrm >> 6) & 3;
1586 op = (modrm >> 3) & 7;
1589 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1590 gen_op_ld_T0_A0[ot]();
1593 opreg = rm + OR_EAX;
1600 val = insn_get(s, ot);
1603 val = (int8_t)insn_get(s, OT_BYTE);
1607 gen_opi(s, op, ot, opreg, val);
1608 if (op != 7 && mod != 3) {
1609 gen_op_st_T0_A0[ot]();
1614 /**************************/
1615 /* inc, dec, and other misc arith */
1616 case 0x40 ... 0x47: /* inc Gv */
1617 ot = dflag ? OT_LONG : OT_WORD;
1618 gen_inc(s, ot, OR_EAX + (b & 7), 1);
1620 case 0x48 ... 0x4f: /* dec Gv */
1621 ot = dflag ? OT_LONG : OT_WORD;
1622 gen_inc(s, ot, OR_EAX + (b & 7), -1);
1624 case 0xf6: /* GRP3 */
1629 ot = dflag ? OT_LONG : OT_WORD;
1631 modrm = ldub(s->pc++);
1632 mod = (modrm >> 6) & 3;
1634 op = (modrm >> 3) & 7;
1636 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1637 gen_op_ld_T0_A0[ot]();
1639 gen_op_mov_TN_reg[ot][0][rm]();
1644 val = insn_get(s, ot);
1645 gen_op_movl_T1_im(val);
1646 gen_op_testl_T0_T1_cc();
1647 s->cc_op = CC_OP_LOGICB + ot;
1652 gen_op_st_T0_A0[ot]();
1654 gen_op_mov_reg_T0[ot][rm]();
1658 gen_op_negl_T0_cc();
1660 gen_op_st_T0_A0[ot]();
1662 gen_op_mov_reg_T0[ot][rm]();
1664 s->cc_op = CC_OP_SUBB + ot;
1669 gen_op_mulb_AL_T0();
1672 gen_op_mulw_AX_T0();
1676 gen_op_mull_EAX_T0();
1679 s->cc_op = CC_OP_MUL;
1684 gen_op_imulb_AL_T0();
1687 gen_op_imulw_AX_T0();
1691 gen_op_imull_EAX_T0();
1694 s->cc_op = CC_OP_MUL;
1699 gen_op_divb_AL_T0(pc_start - s->cs_base);
1702 gen_op_divw_AX_T0(pc_start - s->cs_base);
1706 gen_op_divl_EAX_T0(pc_start - s->cs_base);
1713 gen_op_idivb_AL_T0(pc_start - s->cs_base);
1716 gen_op_idivw_AX_T0(pc_start - s->cs_base);
1720 gen_op_idivl_EAX_T0(pc_start - s->cs_base);
1729 case 0xfe: /* GRP4 */
1730 case 0xff: /* GRP5 */
1734 ot = dflag ? OT_LONG : OT_WORD;
1736 modrm = ldub(s->pc++);
1737 mod = (modrm >> 6) & 3;
1739 op = (modrm >> 3) & 7;
1740 if (op >= 2 && b == 0xfe) {
1744 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1745 if (op != 3 && op != 5)
1746 gen_op_ld_T0_A0[ot]();
1748 gen_op_mov_TN_reg[ot][0][rm]();
1752 case 0: /* inc Ev */
1753 gen_inc(s, ot, OR_TMP0, 1);
1755 gen_op_st_T0_A0[ot]();
1757 gen_op_mov_reg_T0[ot][rm]();
1759 case 1: /* dec Ev */
1760 gen_inc(s, ot, OR_TMP0, -1);
1762 gen_op_st_T0_A0[ot]();
1764 gen_op_mov_reg_T0[ot][rm]();
1766 case 2: /* call Ev */
1767 /* XXX: optimize if memory (no and is necessary) */
1769 gen_op_andl_T0_ffff();
1771 next_eip = s->pc - s->cs_base;
1772 gen_op_movl_T0_im(next_eip);
1776 case 3: /* lcall Ev */
1777 /* push return segment + offset */
1778 gen_op_movl_T0_seg(R_CS);
1780 next_eip = s->pc - s->cs_base;
1781 gen_op_movl_T0_im(next_eip);
1784 gen_op_ld_T1_A0[ot]();
1785 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
1786 gen_op_lduw_T0_A0();
1787 gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
1788 gen_op_movl_T0_T1();
1792 case 4: /* jmp Ev */
1794 gen_op_andl_T0_ffff();
1798 case 5: /* ljmp Ev */
1799 gen_op_ld_T1_A0[ot]();
1800 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
1801 gen_op_lduw_T0_A0();
1802 gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
1803 gen_op_movl_T0_T1();
1807 case 6: /* push Ev */
1815 case 0x84: /* test Ev, Gv */
1820 ot = dflag ? OT_LONG : OT_WORD;
1822 modrm = ldub(s->pc++);
1823 mod = (modrm >> 6) & 3;
1825 reg = (modrm >> 3) & 7;
1827 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
1828 gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
1829 gen_op_testl_T0_T1_cc();
1830 s->cc_op = CC_OP_LOGICB + ot;
1833 case 0xa8: /* test eAX, Iv */
1838 ot = dflag ? OT_LONG : OT_WORD;
1839 val = insn_get(s, ot);
1841 gen_op_mov_TN_reg[ot][0][OR_EAX]();
1842 gen_op_movl_T1_im(val);
1843 gen_op_testl_T0_T1_cc();
1844 s->cc_op = CC_OP_LOGICB + ot;
1847 case 0x98: /* CWDE/CBW */
1849 gen_op_movswl_EAX_AX();
1851 gen_op_movsbw_AX_AL();
1853 case 0x99: /* CDQ/CWD */
1855 gen_op_movslq_EDX_EAX();
1857 gen_op_movswl_DX_AX();
1859 case 0x1af: /* imul Gv, Ev */
1860 case 0x69: /* imul Gv, Ev, I */
1862 ot = dflag ? OT_LONG : OT_WORD;
1863 modrm = ldub(s->pc++);
1864 reg = ((modrm >> 3) & 7) + OR_EAX;
1865 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
1867 val = insn_get(s, ot);
1868 gen_op_movl_T1_im(val);
1869 } else if (b == 0x6b) {
1870 val = insn_get(s, OT_BYTE);
1871 gen_op_movl_T1_im(val);
1873 gen_op_mov_TN_reg[ot][1][reg]();
1876 if (ot == OT_LONG) {
1877 gen_op_imull_T0_T1();
1879 gen_op_imulw_T0_T1();
1881 gen_op_mov_reg_T0[ot][reg]();
1882 s->cc_op = CC_OP_MUL;
1885 case 0x1c1: /* xadd Ev, Gv */
1889 ot = dflag ? OT_LONG : OT_WORD;
1890 modrm = ldub(s->pc++);
1891 reg = (modrm >> 3) & 7;
1892 mod = (modrm >> 6) & 3;
1895 gen_op_mov_TN_reg[ot][0][reg]();
1896 gen_op_mov_TN_reg[ot][1][rm]();
1897 gen_op_addl_T0_T1_cc();
1898 gen_op_mov_reg_T0[ot][rm]();
1899 gen_op_mov_reg_T1[ot][reg]();
1901 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1902 gen_op_mov_TN_reg[ot][0][reg]();
1903 gen_op_ld_T1_A0[ot]();
1904 gen_op_addl_T0_T1_cc();
1905 gen_op_st_T0_A0[ot]();
1906 gen_op_mov_reg_T1[ot][reg]();
1908 s->cc_op = CC_OP_ADDB + ot;
1911 case 0x1b1: /* cmpxchg Ev, Gv */
1915 ot = dflag ? OT_LONG : OT_WORD;
1916 modrm = ldub(s->pc++);
1917 reg = (modrm >> 3) & 7;
1918 mod = (modrm >> 6) & 3;
1919 gen_op_mov_TN_reg[ot][1][reg]();
1922 gen_op_mov_TN_reg[ot][0][rm]();
1923 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
1924 gen_op_mov_reg_T0[ot][rm]();
1926 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1927 gen_op_ld_T0_A0[ot]();
1928 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
1929 gen_op_st_T0_A0[ot]();
1931 s->cc_op = CC_OP_SUBB + ot;
1933 case 0x1c7: /* cmpxchg8b */
1934 modrm = ldub(s->pc++);
1935 mod = (modrm >> 6) & 3;
1938 if (s->cc_op != CC_OP_DYNAMIC)
1939 gen_op_set_cc_op(s->cc_op);
1940 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1942 s->cc_op = CC_OP_EFLAGS;
1945 /**************************/
1947 case 0x50 ... 0x57: /* push */
1948 gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
1951 case 0x58 ... 0x5f: /* pop */
1952 ot = dflag ? OT_LONG : OT_WORD;
1954 gen_op_mov_reg_T0[ot][b & 7]();
1957 case 0x60: /* pusha */
1960 case 0x61: /* popa */
1963 case 0x68: /* push Iv */
1965 ot = dflag ? OT_LONG : OT_WORD;
1967 val = insn_get(s, ot);
1969 val = (int8_t)insn_get(s, OT_BYTE);
1970 gen_op_movl_T0_im(val);
1973 case 0x8f: /* pop Ev */
1974 ot = dflag ? OT_LONG : OT_WORD;
1975 modrm = ldub(s->pc++);
1977 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
1980 case 0xc8: /* enter */
1985 level = ldub(s->pc++);
1986 gen_enter(s, val, level);
1989 case 0xc9: /* leave */
1990 /* XXX: exception not precise (ESP is updated before potential exception) */
1992 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1993 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
1995 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
1996 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
1999 ot = dflag ? OT_LONG : OT_WORD;
2000 gen_op_mov_reg_T0[ot][R_EBP]();
2003 case 0x06: /* push es */
2004 case 0x0e: /* push cs */
2005 case 0x16: /* push ss */
2006 case 0x1e: /* push ds */
2007 gen_op_movl_T0_seg(b >> 3);
2010 case 0x1a0: /* push fs */
2011 case 0x1a8: /* push gs */
2012 gen_op_movl_T0_seg((b >> 3) & 7);
2015 case 0x07: /* pop es */
2016 case 0x17: /* pop ss */
2017 case 0x1f: /* pop ds */
2019 gen_movl_seg_T0(s, b >> 3, pc_start - s->cs_base);
2022 case 0x1a1: /* pop fs */
2023 case 0x1a9: /* pop gs */
2025 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2029 /**************************/
2032 case 0x89: /* mov Gv, Ev */
2036 ot = dflag ? OT_LONG : OT_WORD;
2037 modrm = ldub(s->pc++);
2038 reg = (modrm >> 3) & 7;
2040 /* generate a generic store */
2041 gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2044 case 0xc7: /* mov Ev, Iv */
2048 ot = dflag ? OT_LONG : OT_WORD;
2049 modrm = ldub(s->pc++);
2050 mod = (modrm >> 6) & 3;
2052 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2053 val = insn_get(s, ot);
2054 gen_op_movl_T0_im(val);
2056 gen_op_st_T0_A0[ot]();
2058 gen_op_mov_reg_T0[ot][modrm & 7]();
2061 case 0x8b: /* mov Ev, Gv */
2065 ot = dflag ? OT_LONG : OT_WORD;
2066 modrm = ldub(s->pc++);
2067 reg = (modrm >> 3) & 7;
2069 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2070 gen_op_mov_reg_T0[ot][reg]();
2072 case 0x8e: /* mov seg, Gv */
2073 ot = dflag ? OT_LONG : OT_WORD;
2074 modrm = ldub(s->pc++);
2075 reg = (modrm >> 3) & 7;
2076 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2077 if (reg >= 6 || reg == R_CS)
2079 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2081 case 0x8c: /* mov Gv, seg */
2082 ot = dflag ? OT_LONG : OT_WORD;
2083 modrm = ldub(s->pc++);
2084 reg = (modrm >> 3) & 7;
2087 gen_op_movl_T0_seg(reg);
2088 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2091 case 0x1b6: /* movzbS Gv, Eb */
2092 case 0x1b7: /* movzwS Gv, Eb */
2093 case 0x1be: /* movsbS Gv, Eb */
2094 case 0x1bf: /* movswS Gv, Eb */
2097 /* d_ot is the size of destination */
2098 d_ot = dflag + OT_WORD;
2099 /* ot is the size of source */
2100 ot = (b & 1) + OT_BYTE;
2101 modrm = ldub(s->pc++);
2102 reg = ((modrm >> 3) & 7) + OR_EAX;
2103 mod = (modrm >> 6) & 3;
2107 gen_op_mov_TN_reg[ot][0][rm]();
2108 switch(ot | (b & 8)) {
2110 gen_op_movzbl_T0_T0();
2113 gen_op_movsbl_T0_T0();
2116 gen_op_movzwl_T0_T0();
2120 gen_op_movswl_T0_T0();
2123 gen_op_mov_reg_T0[d_ot][reg]();
2125 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2127 gen_op_lds_T0_A0[ot]();
2129 gen_op_ldu_T0_A0[ot]();
2131 gen_op_mov_reg_T0[d_ot][reg]();
2136 case 0x8d: /* lea */
2137 ot = dflag ? OT_LONG : OT_WORD;
2138 modrm = ldub(s->pc++);
2139 reg = (modrm >> 3) & 7;
2140 /* we must ensure that no segment is added */
2144 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2146 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2149 case 0xa0: /* mov EAX, Ov */
2151 case 0xa2: /* mov Ov, EAX */
2156 ot = dflag ? OT_LONG : OT_WORD;
2158 offset_addr = insn_get(s, OT_LONG);
2160 offset_addr = insn_get(s, OT_WORD);
2161 gen_op_movl_A0_im(offset_addr);
2162 /* handle override */
2164 int override, must_add_seg;
2165 must_add_seg = s->addseg;
2166 if (s->override >= 0) {
2167 override = s->override;
2173 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
2177 gen_op_ld_T0_A0[ot]();
2178 gen_op_mov_reg_T0[ot][R_EAX]();
2180 gen_op_mov_TN_reg[ot][0][R_EAX]();
2181 gen_op_st_T0_A0[ot]();
2184 case 0xd7: /* xlat */
2185 gen_op_movl_A0_reg[R_EBX]();
2186 gen_op_addl_A0_AL();
2188 gen_op_andl_A0_ffff();
2189 /* handle override */
2191 int override, must_add_seg;
2192 must_add_seg = s->addseg;
2194 if (s->override >= 0) {
2195 override = s->override;
2201 gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
2204 gen_op_ldub_T0_A0();
2205 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2207 case 0xb0 ... 0xb7: /* mov R, Ib */
2208 val = insn_get(s, OT_BYTE);
2209 gen_op_movl_T0_im(val);
2210 gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2212 case 0xb8 ... 0xbf: /* mov R, Iv */
2213 ot = dflag ? OT_LONG : OT_WORD;
2214 val = insn_get(s, ot);
2215 reg = OR_EAX + (b & 7);
2216 gen_op_movl_T0_im(val);
2217 gen_op_mov_reg_T0[ot][reg]();
2220 case 0x91 ... 0x97: /* xchg R, EAX */
2221 ot = dflag ? OT_LONG : OT_WORD;
2226 case 0x87: /* xchg Ev, Gv */
2230 ot = dflag ? OT_LONG : OT_WORD;
2231 modrm = ldub(s->pc++);
2232 reg = (modrm >> 3) & 7;
2233 mod = (modrm >> 6) & 3;
2237 gen_op_mov_TN_reg[ot][0][reg]();
2238 gen_op_mov_TN_reg[ot][1][rm]();
2239 gen_op_mov_reg_T0[ot][rm]();
2240 gen_op_mov_reg_T1[ot][reg]();
2242 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2243 gen_op_mov_TN_reg[ot][0][reg]();
2244 /* for xchg, lock is implicit */
2245 if (!(prefixes & PREFIX_LOCK))
2247 gen_op_ld_T1_A0[ot]();
2248 gen_op_st_T0_A0[ot]();
2249 if (!(prefixes & PREFIX_LOCK))
2251 gen_op_mov_reg_T1[ot][reg]();
2254 case 0xc4: /* les Gv */
2257 case 0xc5: /* lds Gv */
2260 case 0x1b2: /* lss Gv */
2263 case 0x1b4: /* lfs Gv */
2266 case 0x1b5: /* lgs Gv */
2269 ot = dflag ? OT_LONG : OT_WORD;
2270 modrm = ldub(s->pc++);
2271 reg = (modrm >> 3) & 7;
2272 mod = (modrm >> 6) & 3;
2275 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2276 gen_op_ld_T1_A0[ot]();
2277 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2278 /* load the segment first to handle exceptions properly */
2279 gen_op_lduw_T0_A0();
2280 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2281 /* then put the data */
2282 gen_op_mov_reg_T1[ot][reg]();
2285 /************************/
2296 ot = dflag ? OT_LONG : OT_WORD;
2298 modrm = ldub(s->pc++);
2299 mod = (modrm >> 6) & 3;
2301 op = (modrm >> 3) & 7;
2304 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2305 gen_op_ld_T0_A0[ot]();
2308 opreg = rm + OR_EAX;
2313 gen_shift(s, op, ot, opreg, OR_ECX);
2316 shift = ldub(s->pc++);
2318 gen_shifti(s, op, ot, opreg, shift);
2322 gen_op_st_T0_A0[ot]();
2337 case 0x1a4: /* shld imm */
2341 case 0x1a5: /* shld cl */
2345 case 0x1ac: /* shrd imm */
2349 case 0x1ad: /* shrd cl */
2353 ot = dflag ? OT_LONG : OT_WORD;
2354 modrm = ldub(s->pc++);
2355 mod = (modrm >> 6) & 3;
2357 reg = (modrm >> 3) & 7;
2360 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2361 gen_op_ld_T0_A0[ot]();
2363 gen_op_mov_TN_reg[ot][0][rm]();
2365 gen_op_mov_TN_reg[ot][1][reg]();
2368 val = ldub(s->pc++);
2371 gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2372 if (op == 0 && ot != OT_WORD)
2373 s->cc_op = CC_OP_SHLB + ot;
2375 s->cc_op = CC_OP_SARB + ot;
2378 if (s->cc_op != CC_OP_DYNAMIC)
2379 gen_op_set_cc_op(s->cc_op);
2380 gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2381 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2384 gen_op_st_T0_A0[ot]();
2386 gen_op_mov_reg_T0[ot][rm]();
2390 /************************/
2393 modrm = ldub(s->pc++);
2394 mod = (modrm >> 6) & 3;
2396 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2400 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2402 case 0x00 ... 0x07: /* fxxxs */
2403 case 0x10 ... 0x17: /* fixxxl */
2404 case 0x20 ... 0x27: /* fxxxl */
2405 case 0x30 ... 0x37: /* fixxx */
2412 gen_op_flds_FT0_A0();
2415 gen_op_fildl_FT0_A0();
2418 gen_op_fldl_FT0_A0();
2422 gen_op_fild_FT0_A0();
2426 gen_op_fp_arith_ST0_FT0[op1]();
2428 /* fcomp needs pop */
2433 case 0x08: /* flds */
2434 case 0x0a: /* fsts */
2435 case 0x0b: /* fstps */
2436 case 0x18: /* fildl */
2437 case 0x1a: /* fistl */
2438 case 0x1b: /* fistpl */
2439 case 0x28: /* fldl */
2440 case 0x2a: /* fstl */
2441 case 0x2b: /* fstpl */
2442 case 0x38: /* filds */
2443 case 0x3a: /* fists */
2444 case 0x3b: /* fistps */
2451 gen_op_flds_ST0_A0();
2454 gen_op_fildl_ST0_A0();
2457 gen_op_fldl_ST0_A0();
2461 gen_op_fild_ST0_A0();
2468 gen_op_fsts_ST0_A0();
2471 gen_op_fistl_ST0_A0();
2474 gen_op_fstl_ST0_A0();
2478 gen_op_fist_ST0_A0();
2486 case 0x0c: /* fldenv mem */
2487 gen_op_fldenv_A0(s->dflag);
2489 case 0x0d: /* fldcw mem */
2492 case 0x0e: /* fnstenv mem */
2493 gen_op_fnstenv_A0(s->dflag);
2495 case 0x0f: /* fnstcw mem */
2498 case 0x1d: /* fldt mem */
2500 gen_op_fldt_ST0_A0();
2502 case 0x1f: /* fstpt mem */
2503 gen_op_fstt_ST0_A0();
2506 case 0x2c: /* frstor mem */
2507 gen_op_frstor_A0(s->dflag);
2509 case 0x2e: /* fnsave mem */
2510 gen_op_fnsave_A0(s->dflag);
2512 case 0x2f: /* fnstsw mem */
2515 case 0x3c: /* fbld */
2517 gen_op_fbld_ST0_A0();
2519 case 0x3e: /* fbstp */
2520 gen_op_fbst_ST0_A0();
2523 case 0x3d: /* fildll */
2525 gen_op_fildll_ST0_A0();
2527 case 0x3f: /* fistpll */
2528 gen_op_fistll_ST0_A0();
2535 /* register float ops */
2539 case 0x08: /* fld sti */
2541 gen_op_fmov_ST0_STN((opreg + 1) & 7);
2543 case 0x09: /* fxchg sti */
2544 gen_op_fxchg_ST0_STN(opreg);
2546 case 0x0a: /* grp d9/2 */
2554 case 0x0c: /* grp d9/4 */
2564 gen_op_fcom_ST0_FT0();
2573 case 0x0d: /* grp d9/5 */
2582 gen_op_fldl2t_ST0();
2586 gen_op_fldl2e_ST0();
2594 gen_op_fldlg2_ST0();
2598 gen_op_fldln2_ST0();
2609 case 0x0e: /* grp d9/6 */
2620 case 3: /* fpatan */
2623 case 4: /* fxtract */
2626 case 5: /* fprem1 */
2629 case 6: /* fdecstp */
2633 case 7: /* fincstp */
2638 case 0x0f: /* grp d9/7 */
2643 case 1: /* fyl2xp1 */
2649 case 3: /* fsincos */
2652 case 5: /* fscale */
2655 case 4: /* frndint */
2667 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
2668 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
2669 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
2675 gen_op_fp_arith_STN_ST0[op1](opreg);
2679 gen_op_fmov_FT0_STN(opreg);
2680 gen_op_fp_arith_ST0_FT0[op1]();
2684 case 0x02: /* fcom */
2685 gen_op_fmov_FT0_STN(opreg);
2686 gen_op_fcom_ST0_FT0();
2688 case 0x03: /* fcomp */
2689 gen_op_fmov_FT0_STN(opreg);
2690 gen_op_fcom_ST0_FT0();
2693 case 0x15: /* da/5 */
2695 case 1: /* fucompp */
2696 gen_op_fmov_FT0_STN(1);
2697 gen_op_fucom_ST0_FT0();
2710 case 3: /* fninit */
2717 case 0x1d: /* fucomi */
2718 if (s->cc_op != CC_OP_DYNAMIC)
2719 gen_op_set_cc_op(s->cc_op);
2720 gen_op_fmov_FT0_STN(opreg);
2721 gen_op_fucomi_ST0_FT0();
2722 s->cc_op = CC_OP_EFLAGS;
2724 case 0x1e: /* fcomi */
2725 if (s->cc_op != CC_OP_DYNAMIC)
2726 gen_op_set_cc_op(s->cc_op);
2727 gen_op_fmov_FT0_STN(opreg);
2728 gen_op_fcomi_ST0_FT0();
2729 s->cc_op = CC_OP_EFLAGS;
2731 case 0x2a: /* fst sti */
2732 gen_op_fmov_STN_ST0(opreg);
2734 case 0x2b: /* fstp sti */
2735 gen_op_fmov_STN_ST0(opreg);
2738 case 0x2c: /* fucom st(i) */
2739 gen_op_fmov_FT0_STN(opreg);
2740 gen_op_fucom_ST0_FT0();
2742 case 0x2d: /* fucomp st(i) */
2743 gen_op_fmov_FT0_STN(opreg);
2744 gen_op_fucom_ST0_FT0();
2747 case 0x33: /* de/3 */
2749 case 1: /* fcompp */
2750 gen_op_fmov_FT0_STN(1);
2751 gen_op_fcom_ST0_FT0();
2759 case 0x3c: /* df/4 */
2762 gen_op_fnstsw_EAX();
2768 case 0x3d: /* fucomip */
2769 if (s->cc_op != CC_OP_DYNAMIC)
2770 gen_op_set_cc_op(s->cc_op);
2771 gen_op_fmov_FT0_STN(opreg);
2772 gen_op_fucomi_ST0_FT0();
2774 s->cc_op = CC_OP_EFLAGS;
2776 case 0x3e: /* fcomip */
2777 if (s->cc_op != CC_OP_DYNAMIC)
2778 gen_op_set_cc_op(s->cc_op);
2779 gen_op_fmov_FT0_STN(opreg);
2780 gen_op_fcomi_ST0_FT0();
2782 s->cc_op = CC_OP_EFLAGS;
2789 /************************/
2792 case 0xa4: /* movsS */
2797 ot = dflag ? OT_LONG : OT_WORD;
2799 if (prefixes & PREFIX_REPZ) {
2800 gen_string_ds(s, ot, gen_op_movs + 9);
2802 gen_string_ds(s, ot, gen_op_movs);
2806 case 0xaa: /* stosS */
2811 ot = dflag ? OT_LONG : OT_WORD;
2813 if (prefixes & PREFIX_REPZ) {
2814 gen_string_es(s, ot, gen_op_stos + 9);
2816 gen_string_es(s, ot, gen_op_stos);
2819 case 0xac: /* lodsS */
2824 ot = dflag ? OT_LONG : OT_WORD;
2825 if (prefixes & PREFIX_REPZ) {
2826 gen_string_ds(s, ot, gen_op_lods + 9);
2828 gen_string_ds(s, ot, gen_op_lods);
2831 case 0xae: /* scasS */
2836 ot = dflag ? OT_LONG : OT_WORD;
2837 if (prefixes & PREFIX_REPNZ) {
2838 if (s->cc_op != CC_OP_DYNAMIC)
2839 gen_op_set_cc_op(s->cc_op);
2840 gen_string_es(s, ot, gen_op_scas + 9 * 2);
2841 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2842 } else if (prefixes & PREFIX_REPZ) {
2843 if (s->cc_op != CC_OP_DYNAMIC)
2844 gen_op_set_cc_op(s->cc_op);
2845 gen_string_es(s, ot, gen_op_scas + 9);
2846 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2848 gen_string_es(s, ot, gen_op_scas);
2849 s->cc_op = CC_OP_SUBB + ot;
2853 case 0xa6: /* cmpsS */
2858 ot = dflag ? OT_LONG : OT_WORD;
2859 if (prefixes & PREFIX_REPNZ) {
2860 if (s->cc_op != CC_OP_DYNAMIC)
2861 gen_op_set_cc_op(s->cc_op);
2862 gen_string_ds(s, ot, gen_op_cmps + 9 * 2);
2863 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2864 } else if (prefixes & PREFIX_REPZ) {
2865 if (s->cc_op != CC_OP_DYNAMIC)
2866 gen_op_set_cc_op(s->cc_op);
2867 gen_string_ds(s, ot, gen_op_cmps + 9);
2868 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2870 gen_string_ds(s, ot, gen_op_cmps);
2871 s->cc_op = CC_OP_SUBB + ot;
2874 case 0x6c: /* insS */
2876 if (s->cpl > s->iopl || s->vm86) {
2877 /* NOTE: even for (E)CX = 0 the exception is raised */
2878 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2883 ot = dflag ? OT_LONG : OT_WORD;
2884 if (prefixes & PREFIX_REPZ) {
2885 gen_string_es(s, ot, gen_op_ins + 9);
2887 gen_string_es(s, ot, gen_op_ins);
2891 case 0x6e: /* outsS */
2893 if (s->cpl > s->iopl || s->vm86) {
2894 /* NOTE: even for (E)CX = 0 the exception is raised */
2895 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2900 ot = dflag ? OT_LONG : OT_WORD;
2901 if (prefixes & PREFIX_REPZ) {
2902 gen_string_ds(s, ot, gen_op_outs + 9);
2904 gen_string_ds(s, ot, gen_op_outs);
2909 /************************/
2913 if (s->cpl > s->iopl || s->vm86) {
2914 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2919 ot = dflag ? OT_LONG : OT_WORD;
2920 val = ldub(s->pc++);
2921 gen_op_movl_T0_im(val);
2923 gen_op_mov_reg_T1[ot][R_EAX]();
2928 if (s->cpl > s->iopl || s->vm86) {
2929 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2934 ot = dflag ? OT_LONG : OT_WORD;
2935 val = ldub(s->pc++);
2936 gen_op_movl_T0_im(val);
2937 gen_op_mov_TN_reg[ot][1][R_EAX]();
2943 if (s->cpl > s->iopl || s->vm86) {
2944 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2949 ot = dflag ? OT_LONG : OT_WORD;
2950 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
2952 gen_op_mov_reg_T1[ot][R_EAX]();
2957 if (s->cpl > s->iopl || s->vm86) {
2958 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
2963 ot = dflag ? OT_LONG : OT_WORD;
2964 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
2965 gen_op_mov_TN_reg[ot][1][R_EAX]();
2970 /************************/
2972 case 0xc2: /* ret im */
2976 gen_stack_update(s, val + (2 << s->dflag));
2978 gen_op_andl_T0_ffff();
2982 case 0xc3: /* ret */
2986 gen_op_andl_T0_ffff();
2990 case 0xca: /* lret im */
2996 gen_op_ld_T0_A0[1 + s->dflag]();
2998 gen_op_andl_T0_ffff();
2999 /* NOTE: keeping EIP updated is not a problem in case of
3003 gen_op_addl_A0_im(2 << s->dflag);
3004 gen_op_ld_T0_A0[1 + s->dflag]();
3005 gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
3006 /* add stack offset */
3007 gen_stack_update(s, val + (4 << s->dflag));
3010 case 0xcb: /* lret */
3013 case 0xcf: /* iret */
3014 if (s->vm86 && s->iopl != 3) {
3015 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3017 /* XXX: not restartable */
3020 gen_op_ld_T0_A0[1 + s->dflag]();
3022 gen_op_andl_T0_ffff();
3023 /* NOTE: keeping EIP updated is not a problem in case of
3027 gen_op_addl_A0_im(2 << s->dflag);
3028 gen_op_ld_T0_A0[1 + s->dflag]();
3030 gen_op_addl_A0_im(2 << s->dflag);
3031 gen_op_ld_T1_A0[1 + s->dflag]();
3032 gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
3033 gen_op_movl_T0_T1();
3035 gen_op_movl_eflags_T0();
3037 gen_op_movw_eflags_T0();
3039 gen_stack_update(s, (6 << s->dflag));
3040 s->cc_op = CC_OP_EFLAGS;
3044 case 0xe8: /* call im */
3046 unsigned int next_eip;
3047 ot = dflag ? OT_LONG : OT_WORD;
3048 val = insn_get(s, ot);
3049 next_eip = s->pc - s->cs_base;
3053 gen_op_movl_T0_im(next_eip);
3058 case 0x9a: /* lcall im */
3060 unsigned int selector, offset;
3061 /* XXX: not restartable */
3063 ot = dflag ? OT_LONG : OT_WORD;
3064 offset = insn_get(s, ot);
3065 selector = insn_get(s, OT_WORD);
3067 /* push return segment + offset */
3068 gen_op_movl_T0_seg(R_CS);
3070 next_eip = s->pc - s->cs_base;
3071 gen_op_movl_T0_im(next_eip);
3074 /* change cs and pc */
3075 gen_op_movl_T0_im(selector);
3076 gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
3077 gen_op_jmp_im((unsigned long)offset);
3081 case 0xe9: /* jmp */
3082 ot = dflag ? OT_LONG : OT_WORD;
3083 val = insn_get(s, ot);
3084 val += s->pc - s->cs_base;
3089 case 0xea: /* ljmp im */
3091 unsigned int selector, offset;
3093 ot = dflag ? OT_LONG : OT_WORD;
3094 offset = insn_get(s, ot);
3095 selector = insn_get(s, OT_WORD);
3097 /* change cs and pc */
3098 gen_op_movl_T0_im(selector);
3099 gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
3100 gen_op_jmp_im((unsigned long)offset);
3104 case 0xeb: /* jmp Jb */
3105 val = (int8_t)insn_get(s, OT_BYTE);
3106 val += s->pc - s->cs_base;
3111 case 0x70 ... 0x7f: /* jcc Jb */
3112 val = (int8_t)insn_get(s, OT_BYTE);
3114 case 0x180 ... 0x18f: /* jcc Jv */
3116 val = insn_get(s, OT_LONG);
3118 val = (int16_t)insn_get(s, OT_WORD);
3121 next_eip = s->pc - s->cs_base;
3125 gen_jcc(s, b, val, next_eip);
3128 case 0x190 ... 0x19f: /* setcc Gv */
3129 modrm = ldub(s->pc++);
3131 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3133 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3134 ot = dflag ? OT_LONG : OT_WORD;
3135 modrm = ldub(s->pc++);
3136 reg = (modrm >> 3) & 7;
3137 mod = (modrm >> 6) & 3;
3140 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3141 gen_op_ld_T1_A0[ot]();
3144 gen_op_mov_TN_reg[ot][1][rm]();
3146 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3149 /************************/
3151 case 0x9c: /* pushf */
3152 if (s->vm86 && s->iopl != 3) {
3153 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3155 if (s->cc_op != CC_OP_DYNAMIC)
3156 gen_op_set_cc_op(s->cc_op);
3157 gen_op_movl_T0_eflags();
3161 case 0x9d: /* popf */
3162 if (s->vm86 && s->iopl != 3) {
3163 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3167 gen_op_movl_eflags_T0();
3169 gen_op_movw_eflags_T0();
3172 s->cc_op = CC_OP_EFLAGS;
3173 s->is_jmp = 2; /* abort translation because TF flag may change */
3176 case 0x9e: /* sahf */
3177 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3178 if (s->cc_op != CC_OP_DYNAMIC)
3179 gen_op_set_cc_op(s->cc_op);
3180 gen_op_movb_eflags_T0();
3181 s->cc_op = CC_OP_EFLAGS;
3183 case 0x9f: /* lahf */
3184 if (s->cc_op != CC_OP_DYNAMIC)
3185 gen_op_set_cc_op(s->cc_op);
3186 gen_op_movl_T0_eflags();
3187 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3189 case 0xf5: /* cmc */
3190 if (s->cc_op != CC_OP_DYNAMIC)
3191 gen_op_set_cc_op(s->cc_op);
3193 s->cc_op = CC_OP_EFLAGS;
3195 case 0xf8: /* clc */
3196 if (s->cc_op != CC_OP_DYNAMIC)
3197 gen_op_set_cc_op(s->cc_op);
3199 s->cc_op = CC_OP_EFLAGS;
3201 case 0xf9: /* stc */
3202 if (s->cc_op != CC_OP_DYNAMIC)
3203 gen_op_set_cc_op(s->cc_op);
3205 s->cc_op = CC_OP_EFLAGS;
3207 case 0xfc: /* cld */
3210 case 0xfd: /* std */
3214 /************************/
3215 /* bit operations */
3216 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3217 ot = dflag ? OT_LONG : OT_WORD;
3218 modrm = ldub(s->pc++);
3219 op = (modrm >> 3) & 7;
3220 mod = (modrm >> 6) & 3;
3223 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3224 gen_op_ld_T0_A0[ot]();
3226 gen_op_mov_TN_reg[ot][0][rm]();
3229 val = ldub(s->pc++);
3230 gen_op_movl_T1_im(val);
3234 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3235 s->cc_op = CC_OP_SARB + ot;
3238 gen_op_st_T0_A0[ot]();
3240 gen_op_mov_reg_T0[ot][rm]();
3243 case 0x1a3: /* bt Gv, Ev */
3246 case 0x1ab: /* bts */
3249 case 0x1b3: /* btr */
3252 case 0x1bb: /* btc */
3255 ot = dflag ? OT_LONG : OT_WORD;
3256 modrm = ldub(s->pc++);
3257 reg = (modrm >> 3) & 7;
3258 mod = (modrm >> 6) & 3;
3260 gen_op_mov_TN_reg[OT_LONG][1][reg]();
3262 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3263 /* specific case: we need to add a displacement */
3265 gen_op_add_bitw_A0_T1();
3267 gen_op_add_bitl_A0_T1();
3268 gen_op_ld_T0_A0[ot]();
3270 gen_op_mov_TN_reg[ot][0][rm]();
3272 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3273 s->cc_op = CC_OP_SARB + ot;
3276 gen_op_st_T0_A0[ot]();
3278 gen_op_mov_reg_T0[ot][rm]();
3281 case 0x1bc: /* bsf */
3282 case 0x1bd: /* bsr */
3283 ot = dflag ? OT_LONG : OT_WORD;
3284 modrm = ldub(s->pc++);
3285 reg = (modrm >> 3) & 7;
3286 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3287 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3288 /* NOTE: we always write back the result. Intel doc says it is
3289 undefined if T0 == 0 */
3290 gen_op_mov_reg_T0[ot][reg]();
3291 s->cc_op = CC_OP_LOGICB + ot;
3293 /************************/
3295 case 0x27: /* daa */
3296 if (s->cc_op != CC_OP_DYNAMIC)
3297 gen_op_set_cc_op(s->cc_op);
3299 s->cc_op = CC_OP_EFLAGS;
3301 case 0x2f: /* das */
3302 if (s->cc_op != CC_OP_DYNAMIC)
3303 gen_op_set_cc_op(s->cc_op);
3305 s->cc_op = CC_OP_EFLAGS;
3307 case 0x37: /* aaa */
3308 if (s->cc_op != CC_OP_DYNAMIC)
3309 gen_op_set_cc_op(s->cc_op);
3311 s->cc_op = CC_OP_EFLAGS;
3313 case 0x3f: /* aas */
3314 if (s->cc_op != CC_OP_DYNAMIC)
3315 gen_op_set_cc_op(s->cc_op);
3317 s->cc_op = CC_OP_EFLAGS;
3319 case 0xd4: /* aam */
3320 val = ldub(s->pc++);
3322 s->cc_op = CC_OP_LOGICB;
3324 case 0xd5: /* aad */
3325 val = ldub(s->pc++);
3327 s->cc_op = CC_OP_LOGICB;
3329 /************************/
3331 case 0x90: /* nop */
3333 case 0x9b: /* fwait */
3335 case 0xcc: /* int3 */
3336 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3338 case 0xcd: /* int N */
3339 val = ldub(s->pc++);
3340 /* XXX: add error code for vm86 GPF */
3342 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3344 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3346 case 0xce: /* into */
3347 if (s->cc_op != CC_OP_DYNAMIC)
3348 gen_op_set_cc_op(s->cc_op);
3349 gen_op_into(s->pc - s->cs_base);
3351 case 0xfa: /* cli */
3353 if (s->cpl <= s->iopl) {
3356 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3362 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3366 case 0xfb: /* sti */
3368 if (s->cpl <= s->iopl) {
3371 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3377 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3381 case 0x62: /* bound */
3382 ot = dflag ? OT_LONG : OT_WORD;
3383 modrm = ldub(s->pc++);
3384 reg = (modrm >> 3) & 7;
3385 mod = (modrm >> 6) & 3;
3388 gen_op_mov_reg_T0[ot][reg]();
3389 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3391 gen_op_boundw(pc_start - s->cs_base);
3393 gen_op_boundl(pc_start - s->cs_base);
3395 case 0x1c8 ... 0x1cf: /* bswap reg */
3397 gen_op_mov_TN_reg[OT_LONG][0][reg]();
3399 gen_op_mov_reg_T0[OT_LONG][reg]();
3401 case 0xd6: /* salc */
3402 if (s->cc_op != CC_OP_DYNAMIC)
3403 gen_op_set_cc_op(s->cc_op);
3406 case 0xe0: /* loopnz */
3407 case 0xe1: /* loopz */
3408 if (s->cc_op != CC_OP_DYNAMIC)
3409 gen_op_set_cc_op(s->cc_op);
3411 case 0xe2: /* loop */
3412 case 0xe3: /* jecxz */
3413 val = (int8_t)insn_get(s, OT_BYTE);
3414 next_eip = s->pc - s->cs_base;
3418 gen_op_loop[s->aflag][b & 3](val, next_eip);
3421 case 0x131: /* rdtsc */
3424 case 0x1a2: /* cpuid */
3427 case 0xf4: /* hlt */
3428 /* XXX: if cpl == 0, then should do something else */
3429 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3431 case 0x102: /* lar */
3432 case 0x103: /* lsl */
3435 ot = dflag ? OT_LONG : OT_WORD;
3436 modrm = ldub(s->pc++);
3437 reg = (modrm >> 3) & 7;
3438 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3439 gen_op_mov_TN_reg[ot][1][reg]();
3440 if (s->cc_op != CC_OP_DYNAMIC)
3441 gen_op_set_cc_op(s->cc_op);
3446 s->cc_op = CC_OP_EFLAGS;
3447 gen_op_mov_reg_T1[ot][reg]();
3452 /* lock generation */
3453 if (s->prefix & PREFIX_LOCK)
3457 /* XXX: ensure that no lock was generated */
3461 #define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
3462 #define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
3464 /* flags read by an operation */
3465 static uint16_t opc_read_flags[NB_OPS] = {
3466 [INDEX_op_aas] = CC_A,
3467 [INDEX_op_aaa] = CC_A,
3468 [INDEX_op_das] = CC_A | CC_C,
3469 [INDEX_op_daa] = CC_A | CC_C,
3471 [INDEX_op_adcb_T0_T1_cc] = CC_C,
3472 [INDEX_op_adcw_T0_T1_cc] = CC_C,
3473 [INDEX_op_adcl_T0_T1_cc] = CC_C,
3474 [INDEX_op_sbbb_T0_T1_cc] = CC_C,
3475 [INDEX_op_sbbw_T0_T1_cc] = CC_C,
3476 [INDEX_op_sbbl_T0_T1_cc] = CC_C,
3478 /* subtle: due to the incl/decl implementation, C is used */
3479 [INDEX_op_incl_T0_cc] = CC_C,
3480 [INDEX_op_decl_T0_cc] = CC_C,
3482 [INDEX_op_into] = CC_O,
3484 [INDEX_op_jb_subb] = CC_C,
3485 [INDEX_op_jb_subw] = CC_C,
3486 [INDEX_op_jb_subl] = CC_C,
3488 [INDEX_op_jz_subb] = CC_Z,
3489 [INDEX_op_jz_subw] = CC_Z,
3490 [INDEX_op_jz_subl] = CC_Z,
3492 [INDEX_op_jbe_subb] = CC_Z | CC_C,
3493 [INDEX_op_jbe_subw] = CC_Z | CC_C,
3494 [INDEX_op_jbe_subl] = CC_Z | CC_C,
3496 [INDEX_op_js_subb] = CC_S,
3497 [INDEX_op_js_subw] = CC_S,
3498 [INDEX_op_js_subl] = CC_S,
3500 [INDEX_op_jl_subb] = CC_O | CC_S,
3501 [INDEX_op_jl_subw] = CC_O | CC_S,
3502 [INDEX_op_jl_subl] = CC_O | CC_S,
3504 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
3505 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
3506 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
3508 [INDEX_op_loopnzw] = CC_Z,
3509 [INDEX_op_loopnzl] = CC_Z,
3510 [INDEX_op_loopzw] = CC_Z,
3511 [INDEX_op_loopzl] = CC_Z,
3513 [INDEX_op_seto_T0_cc] = CC_O,
3514 [INDEX_op_setb_T0_cc] = CC_C,
3515 [INDEX_op_setz_T0_cc] = CC_Z,
3516 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
3517 [INDEX_op_sets_T0_cc] = CC_S,
3518 [INDEX_op_setp_T0_cc] = CC_P,
3519 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
3520 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
3522 [INDEX_op_setb_T0_subb] = CC_C,
3523 [INDEX_op_setb_T0_subw] = CC_C,
3524 [INDEX_op_setb_T0_subl] = CC_C,
3526 [INDEX_op_setz_T0_subb] = CC_Z,
3527 [INDEX_op_setz_T0_subw] = CC_Z,
3528 [INDEX_op_setz_T0_subl] = CC_Z,
3530 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
3531 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
3532 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
3534 [INDEX_op_sets_T0_subb] = CC_S,
3535 [INDEX_op_sets_T0_subw] = CC_S,
3536 [INDEX_op_sets_T0_subl] = CC_S,
3538 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
3539 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
3540 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
3542 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
3543 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
3544 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
3546 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
3547 [INDEX_op_cmc] = CC_C,
3548 [INDEX_op_salc] = CC_C,
3550 [INDEX_op_rclb_T0_T1_cc] = CC_C,
3551 [INDEX_op_rclw_T0_T1_cc] = CC_C,
3552 [INDEX_op_rcll_T0_T1_cc] = CC_C,
3553 [INDEX_op_rcrb_T0_T1_cc] = CC_C,
3554 [INDEX_op_rcrw_T0_T1_cc] = CC_C,
3555 [INDEX_op_rcrl_T0_T1_cc] = CC_C,
3558 /* flags written by an operation */
3559 static uint16_t opc_write_flags[NB_OPS] = {
3560 [INDEX_op_addl_T0_T1_cc] = CC_OSZAPC,
3561 [INDEX_op_orl_T0_T1_cc] = CC_OSZAPC,
3562 [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
3563 [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
3564 [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
3565 [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
3566 [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
3567 [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
3568 [INDEX_op_andl_T0_T1_cc] = CC_OSZAPC,
3569 [INDEX_op_subl_T0_T1_cc] = CC_OSZAPC,
3570 [INDEX_op_xorl_T0_T1_cc] = CC_OSZAPC,
3571 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
3572 [INDEX_op_negl_T0_cc] = CC_OSZAPC,
3573 /* subtle: due to the incl/decl implementation, C is used */
3574 [INDEX_op_incl_T0_cc] = CC_OSZAPC,
3575 [INDEX_op_decl_T0_cc] = CC_OSZAPC,
3576 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
3578 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
3579 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
3580 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
3581 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
3582 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
3583 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
3584 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
3585 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
3588 [INDEX_op_aam] = CC_OSZAPC,
3589 [INDEX_op_aad] = CC_OSZAPC,
3590 [INDEX_op_aas] = CC_OSZAPC,
3591 [INDEX_op_aaa] = CC_OSZAPC,
3592 [INDEX_op_das] = CC_OSZAPC,
3593 [INDEX_op_daa] = CC_OSZAPC,
3595 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
3596 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
3597 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
3598 [INDEX_op_clc] = CC_C,
3599 [INDEX_op_stc] = CC_C,
3600 [INDEX_op_cmc] = CC_C,
3602 [INDEX_op_rolb_T0_T1_cc] = CC_O | CC_C,
3603 [INDEX_op_rolw_T0_T1_cc] = CC_O | CC_C,
3604 [INDEX_op_roll_T0_T1_cc] = CC_O | CC_C,
3605 [INDEX_op_rorb_T0_T1_cc] = CC_O | CC_C,
3606 [INDEX_op_rorw_T0_T1_cc] = CC_O | CC_C,
3607 [INDEX_op_rorl_T0_T1_cc] = CC_O | CC_C,
3609 [INDEX_op_rclb_T0_T1_cc] = CC_O | CC_C,
3610 [INDEX_op_rclw_T0_T1_cc] = CC_O | CC_C,
3611 [INDEX_op_rcll_T0_T1_cc] = CC_O | CC_C,
3612 [INDEX_op_rcrb_T0_T1_cc] = CC_O | CC_C,
3613 [INDEX_op_rcrw_T0_T1_cc] = CC_O | CC_C,
3614 [INDEX_op_rcrl_T0_T1_cc] = CC_O | CC_C,
3616 [INDEX_op_shlb_T0_T1_cc] = CC_OSZAPC,
3617 [INDEX_op_shlw_T0_T1_cc] = CC_OSZAPC,
3618 [INDEX_op_shll_T0_T1_cc] = CC_OSZAPC,
3620 [INDEX_op_shrb_T0_T1_cc] = CC_OSZAPC,
3621 [INDEX_op_shrw_T0_T1_cc] = CC_OSZAPC,
3622 [INDEX_op_shrl_T0_T1_cc] = CC_OSZAPC,
3624 [INDEX_op_sarb_T0_T1_cc] = CC_OSZAPC,
3625 [INDEX_op_sarw_T0_T1_cc] = CC_OSZAPC,
3626 [INDEX_op_sarl_T0_T1_cc] = CC_OSZAPC,
3628 [INDEX_op_shldw_T0_T1_ECX_cc] = CC_OSZAPC,
3629 [INDEX_op_shldl_T0_T1_ECX_cc] = CC_OSZAPC,
3630 [INDEX_op_shldw_T0_T1_im_cc] = CC_OSZAPC,
3631 [INDEX_op_shldl_T0_T1_im_cc] = CC_OSZAPC,
3633 [INDEX_op_shrdw_T0_T1_ECX_cc] = CC_OSZAPC,
3634 [INDEX_op_shrdl_T0_T1_ECX_cc] = CC_OSZAPC,
3635 [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
3636 [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
3638 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
3639 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
3640 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
3641 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
3642 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
3643 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
3644 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
3645 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
3647 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
3648 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
3649 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
3650 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
3653 #define STRINGOP(x) \
3654 [INDEX_op_ ## x ## b_fast] = CC_OSZAPC, \
3655 [INDEX_op_ ## x ## w_fast] = CC_OSZAPC, \
3656 [INDEX_op_ ## x ## l_fast] = CC_OSZAPC, \
3657 [INDEX_op_ ## x ## b_a32] = CC_OSZAPC, \
3658 [INDEX_op_ ## x ## w_a32] = CC_OSZAPC, \
3659 [INDEX_op_ ## x ## l_a32] = CC_OSZAPC, \
3660 [INDEX_op_ ## x ## b_a16] = CC_OSZAPC, \
3661 [INDEX_op_ ## x ## w_a16] = CC_OSZAPC, \
3662 [INDEX_op_ ## x ## l_a16] = CC_OSZAPC,
3666 STRINGOP(repnz_scas)
3669 STRINGOP(repnz_cmps)
3671 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
3672 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
3673 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
3675 [INDEX_op_cmpxchg8b] = CC_Z,
3676 [INDEX_op_lar] = CC_Z,
3677 [INDEX_op_lsl] = CC_Z,
3678 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
3679 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
3682 /* simpler form of an operation if no flags need to be generated */
3683 static uint16_t opc_simpler[NB_OPS] = {
3684 [INDEX_op_addl_T0_T1_cc] = INDEX_op_addl_T0_T1,
3685 [INDEX_op_orl_T0_T1_cc] = INDEX_op_orl_T0_T1,
3686 [INDEX_op_andl_T0_T1_cc] = INDEX_op_andl_T0_T1,
3687 [INDEX_op_subl_T0_T1_cc] = INDEX_op_subl_T0_T1,
3688 [INDEX_op_xorl_T0_T1_cc] = INDEX_op_xorl_T0_T1,
3689 [INDEX_op_negl_T0_cc] = INDEX_op_negl_T0,
3690 [INDEX_op_incl_T0_cc] = INDEX_op_incl_T0,
3691 [INDEX_op_decl_T0_cc] = INDEX_op_decl_T0,
3693 [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
3694 [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
3695 [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
3697 [INDEX_op_rorb_T0_T1_cc] = INDEX_op_rorb_T0_T1,
3698 [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
3699 [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
3701 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
3702 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
3703 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
3705 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
3706 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
3707 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
3709 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
3710 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
3711 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
3714 static void optimize_flags_init(void)
3717 /* put default values in arrays */
3718 for(i = 0; i < NB_OPS; i++) {
3719 if (opc_simpler[i] == 0)
3724 /* CPU flags computation optimization: we move backward thru the
3725 generated code to see which flags are needed. The operation is
3726 modified if suitable */
3727 static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
3730 int live_flags, write_flags, op;
3732 opc_ptr = opc_buf + opc_buf_len;
3733 /* live_flags contains the flags needed by the next instructions
3734 in the code. At the end of the bloc, we consider that all the
3736 live_flags = CC_OSZAPC;
3737 while (opc_ptr > opc_buf) {
3739 /* if none of the flags written by the instruction is used,
3740 then we can try to find a simpler instruction */
3741 write_flags = opc_write_flags[op];
3742 if ((live_flags & write_flags) == 0) {
3743 *opc_ptr = opc_simpler[op];
3745 /* compute the live flags before the instruction */
3746 live_flags &= ~write_flags;
3747 live_flags |= opc_read_flags[op];
3753 static const char *op_str[] = {
3754 #define DEF(s, n, copy_size) #s,
3755 #include "opc-i386.h"
3759 static uint8_t op_nb_args[] = {
3760 #define DEF(s, n, copy_size) n,
3761 #include "opc-i386.h"
3765 static void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
3767 const uint16_t *opc_ptr;
3768 const uint32_t *opparam_ptr;
3772 opparam_ptr = opparam_buf;
3776 fprintf(logfile, "0x%04x: %s",
3777 (int)(opc_ptr - opc_buf - 1), op_str[c]);
3778 for(i = 0; i < n; i++) {
3779 fprintf(logfile, " 0x%x", opparam_ptr[i]);
3781 fprintf(logfile, "\n");
3782 if (c == INDEX_op_end)
3790 /* XXX: make safe guess about sizes */
3791 #define MAX_OP_PER_INSTR 32
3792 #define OPC_BUF_SIZE 512
3793 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
3795 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
3797 static uint16_t gen_opc_buf[OPC_BUF_SIZE];
3798 static uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
3799 static uint32_t gen_opc_pc[OPC_BUF_SIZE];
3800 static uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
3802 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
3803 basic block 'tb'. If search_pc is TRUE, also generate PC
3804 information for each intermediate instruction. */
3805 static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
3807 DisasContext dc1, *dc = &dc1;
3809 uint16_t *gen_opc_end;
3815 /* generate intermediate code */
3816 pc_start = (uint8_t *)tb->pc;
3817 cs_base = (uint8_t *)tb->cs_base;
3820 dc->code32 = (flags >> GEN_FLAG_CODE32_SHIFT) & 1;
3821 dc->ss32 = (flags >> GEN_FLAG_SS32_SHIFT) & 1;
3822 dc->addseg = (flags >> GEN_FLAG_ADDSEG_SHIFT) & 1;
3823 dc->f_st = (flags >> GEN_FLAG_ST_SHIFT) & 7;
3824 dc->vm86 = (flags >> GEN_FLAG_VM_SHIFT) & 1;
3825 dc->cpl = (flags >> GEN_FLAG_CPL_SHIFT) & 3;
3826 dc->iopl = (flags >> GEN_FLAG_IOPL_SHIFT) & 3;
3827 dc->tf = (flags >> GEN_FLAG_TF_SHIFT) & 1;
3828 dc->cc_op = CC_OP_DYNAMIC;
3829 dc->cs_base = cs_base;
3832 gen_opc_ptr = gen_opc_buf;
3833 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3834 gen_opparam_ptr = gen_opparam_buf;
3841 j = gen_opc_ptr - gen_opc_buf;
3845 gen_opc_instr_start[lj++] = 0;
3846 gen_opc_pc[lj] = (uint32_t)pc_ptr;
3847 gen_opc_instr_start[lj] = 1;
3850 ret = disas_insn(dc, pc_ptr);
3852 /* we trigger an illegal instruction operation only if it
3853 is the first instruction. Otherwise, we simply stop
3854 generating the code just before it */
3855 if (pc_ptr == pc_start)
3860 pc_ptr = (void *)ret;
3861 /* if single step mode, we generate only one instruction and
3862 generate an exception */
3865 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
3866 (pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));
3867 /* we must store the eflags state if it is not already done */
3868 if (dc->is_jmp != 3) {
3869 if (dc->cc_op != CC_OP_DYNAMIC)
3870 gen_op_set_cc_op(dc->cc_op);
3871 if (dc->is_jmp != 1) {
3872 /* we add an additionnal jmp to update the simulated PC */
3873 gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
3877 gen_op_raise_exception(EXCP01_SSTP);
3879 if (dc->is_jmp != 3) {
3880 /* indicate that the hash table must be used to find the next TB */
3884 *gen_opc_ptr = INDEX_op_end;
3888 fprintf(logfile, "----------------\n");
3889 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3890 disas(logfile, pc_start, pc_ptr - pc_start,
3891 dc->code32 ? DISAS_I386_I386 : DISAS_I386_I8086);
3892 fprintf(logfile, "\n");
3894 fprintf(logfile, "OP:\n");
3895 dump_ops(gen_opc_buf, gen_opparam_buf);
3896 fprintf(logfile, "\n");
3900 /* optimize flag computations */
3901 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
3905 fprintf(logfile, "AFTER FLAGS OPT:\n");
3906 dump_ops(gen_opc_buf, gen_opparam_buf);
3907 fprintf(logfile, "\n");
3911 tb->size = pc_ptr - pc_start;
3916 /* return non zero if the very first instruction is invalid so that
3917 the virtual CPU can trigger an exception.
3919 '*gen_code_size_ptr' contains the size of the generated code (host
3922 int cpu_x86_gen_code(TranslationBlock *tb,
3923 int max_code_size, int *gen_code_size_ptr)
3925 uint8_t *gen_code_buf;
3928 if (gen_intermediate_code(tb, 0) < 0)
3931 /* generate machine code */
3932 tb->tb_next_offset[0] = 0xffff;
3933 tb->tb_next_offset[1] = 0xffff;
3934 gen_code_buf = tb->tc_ptr;
3935 gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
3936 #ifdef USE_DIRECT_JUMP
3941 gen_opc_buf, gen_opparam_buf);
3942 flush_icache_range((unsigned long)gen_code_buf, (unsigned long)(gen_code_buf + gen_code_size));
3944 *gen_code_size_ptr = gen_code_size;
3947 fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
3948 disas(logfile, gen_code_buf, *gen_code_size_ptr, DISAS_TARGET);
3949 fprintf(logfile, "\n");
3956 static const unsigned short opc_copy_size[] = {
3957 #define DEF(s, n, copy_size) copy_size,
3958 #include "opc-i386.h"
3962 /* The simulated PC corresponding to
3963 'searched_pc' in the generated code is searched. 0 is returned if
3964 found. *found_pc contains the found PC.
3966 int cpu_x86_search_pc(TranslationBlock *tb,
3967 uint32_t *found_pc, unsigned long searched_pc)
3970 unsigned long tc_ptr;
3973 if (gen_intermediate_code(tb, 1) < 0)
3976 /* find opc index corresponding to search_pc */
3977 tc_ptr = (unsigned long)tb->tc_ptr;
3978 if (searched_pc < tc_ptr)
3981 opc_ptr = gen_opc_buf;
3984 if (c == INDEX_op_end)
3986 tc_ptr += opc_copy_size[c];
3987 if (searched_pc < tc_ptr)
3991 j = opc_ptr - gen_opc_buf;
3992 /* now find start of instruction before */
3993 while (gen_opc_instr_start[j] == 0)
3995 *found_pc = gen_opc_pc[j];
4000 CPUX86State *cpu_x86_init(void)
4006 cpu_x86_tblocks_init();
4008 env = malloc(sizeof(CPUX86State));
4011 memset(env, 0, sizeof(CPUX86State));
4012 /* basic FPU init */
4013 for(i = 0;i < 8; i++)
4016 /* flags setup : we activate the IRQs by default as in user mode */
4017 env->eflags = 0x2 | IF_MASK;
4019 /* init various static tables */
4022 optimize_flags_init();
4028 void cpu_x86_close(CPUX86State *env)
4033 static const char *cc_op_str[] = {
4066 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
4069 char cc_op_name[32];
4071 eflags = env->eflags;
4072 fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
4073 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
4074 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c]\n",
4075 env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
4076 env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
4078 eflags & DF_MASK ? 'D' : '-',
4079 eflags & CC_O ? 'O' : '-',
4080 eflags & CC_S ? 'S' : '-',
4081 eflags & CC_Z ? 'Z' : '-',
4082 eflags & CC_A ? 'A' : '-',
4083 eflags & CC_P ? 'P' : '-',
4084 eflags & CC_C ? 'C' : '-');
4085 fprintf(f, "CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x\n",
4092 if (flags & X86_DUMP_CCOP) {
4093 if ((unsigned)env->cc_op < CC_OP_NB)
4094 strcpy(cc_op_name, cc_op_str[env->cc_op]);
4096 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
4097 fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
4098 env->cc_src, env->cc_dst, cc_op_name);
4100 if (flags & X86_DUMP_FPU) {
4101 fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
4102 (double)env->fpregs[0],
4103 (double)env->fpregs[1],
4104 (double)env->fpregs[2],
4105 (double)env->fpregs[3]);
4106 fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
4107 (double)env->fpregs[4],
4108 (double)env->fpregs[5],
4109 (double)env->fpregs[7],
4110 (double)env->fpregs[8]);