2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
60 static const int tcg_target_reg_alloc_order[] = {
76 static const int tcg_target_call_iarg_regs[6] = {
85 static const int tcg_target_call_oarg_regs[2] = {
90 static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
92 return (val << ((sizeof(tcg_target_long) * 8 - bits))
93 >> (sizeof(tcg_target_long) * 8 - bits)) == val;
96 static inline int check_fit_i32(uint32_t val, unsigned int bits)
98 return ((val << (32 - bits)) >> (32 - bits)) == val;
101 static void patch_reloc(uint8_t *code_ptr, int type,
102 tcg_target_long value, tcg_target_long addend)
107 if (value != (uint32_t)value)
109 *(uint32_t *)code_ptr = value;
111 case R_SPARC_WDISP22:
112 value -= (long)code_ptr;
114 if (!check_fit_tl(value, 22))
116 *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
123 /* maximum number of register used for input function arguments */
124 static inline int tcg_target_get_call_iarg_regs_count(int flags)
129 /* parse target specific constraints */
130 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
137 case 'L': /* qemu_ld/st constraint */
138 ct->ct |= TCG_CT_REG;
139 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
140 tcg_regset_reset_reg(ct->u.regs, TCG_REG_I0);
141 tcg_regset_reset_reg(ct->u.regs, TCG_REG_I1);
144 ct->ct |= TCG_CT_CONST_S11;
147 ct->ct |= TCG_CT_CONST_S13;
157 /* test if a constant matches the constraint */
158 static inline int tcg_target_const_match(tcg_target_long val,
159 const TCGArgConstraint *arg_ct)
164 if (ct & TCG_CT_CONST)
166 else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
168 else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
174 #define INSN_OP(x) ((x) << 30)
175 #define INSN_OP2(x) ((x) << 22)
176 #define INSN_OP3(x) ((x) << 19)
177 #define INSN_OPF(x) ((x) << 5)
178 #define INSN_RD(x) ((x) << 25)
179 #define INSN_RS1(x) ((x) << 14)
180 #define INSN_RS2(x) (x)
181 #define INSN_ASI(x) ((x) << 5)
183 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
184 #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
186 #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
203 #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
205 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
206 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
207 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
208 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
209 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
210 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
211 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
212 #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
213 #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
214 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
215 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
216 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
217 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
218 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
219 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
221 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
222 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
223 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
225 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
226 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
227 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
229 #define WRY (INSN_OP(2) | INSN_OP3(0x30))
230 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
231 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
232 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
233 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
234 #define CALL INSN_OP(1)
235 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
236 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
237 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
238 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
239 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
240 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
241 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
242 #define STB (INSN_OP(3) | INSN_OP3(0x05))
243 #define STH (INSN_OP(3) | INSN_OP3(0x06))
244 #define STW (INSN_OP(3) | INSN_OP3(0x04))
245 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
246 #define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
247 #define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
248 #define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
249 #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
250 #define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
251 #define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
252 #define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
253 #define STBA (INSN_OP(3) | INSN_OP3(0x15))
254 #define STHA (INSN_OP(3) | INSN_OP3(0x16))
255 #define STWA (INSN_OP(3) | INSN_OP3(0x14))
256 #define STXA (INSN_OP(3) | INSN_OP3(0x1e))
258 #ifndef ASI_PRIMARY_LITTLE
259 #define ASI_PRIMARY_LITTLE 0x88
262 static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
265 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
269 static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset,
272 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
276 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
278 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
281 static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
283 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
286 static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
288 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
291 static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
293 if (check_fit_i32(arg, 13))
294 tcg_out_movi_imm13(s, ret, arg);
296 tcg_out_sethi(s, ret, arg);
298 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
302 static inline void tcg_out_movi(TCGContext *s, TCGType type,
303 int ret, tcg_target_long arg)
305 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
306 if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) {
307 // XXX ret may be I5, need another temp
308 tcg_out_movi_imm32(s, TCG_REG_I5, arg >> 32);
309 tcg_out_arithi(s, TCG_REG_I5, TCG_REG_I5, 32, SHIFT_SLLX);
310 tcg_out_movi_imm32(s, ret, arg);
311 tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
314 tcg_out_movi_imm32(s, ret, arg);
317 static inline void tcg_out_ld_raw(TCGContext *s, int ret,
320 tcg_out_sethi(s, ret, arg);
321 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
322 INSN_IMM13(arg & 0x3ff));
325 static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
328 if (!check_fit_tl(arg, 10))
329 tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
330 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
331 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
332 INSN_IMM13(arg & 0x3ff));
334 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
335 INSN_IMM13(arg & 0x3ff));
339 static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
341 if (check_fit_tl(offset, 13))
342 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
345 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
346 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
351 static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
352 int offset, int op, int asi)
354 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
355 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
356 INSN_ASI(asi) | INSN_RS2(addr));
359 static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
360 int arg1, tcg_target_long arg2)
362 if (type == TCG_TYPE_I32)
363 tcg_out_ldst(s, ret, arg1, arg2, LDUW);
365 tcg_out_ldst(s, ret, arg1, arg2, LDX);
368 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
369 int arg1, tcg_target_long arg2)
371 if (type == TCG_TYPE_I32)
372 tcg_out_ldst(s, arg, arg1, arg2, STW);
374 tcg_out_ldst(s, arg, arg1, arg2, STX);
377 static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
379 if (val == 0 || val == -1)
380 tcg_out32(s, WRY | INSN_IMM13(val));
382 fprintf(stderr, "unimplemented sety %ld\n", (long)val);
385 static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
388 if (check_fit_tl(val, 13))
389 tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
391 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
392 tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
397 static inline void tcg_out_nop(TCGContext *s)
399 tcg_out_sethi(s, TCG_REG_G0, 0);
402 static void tcg_out_branch(TCGContext *s, int opc, int label_index)
405 TCGLabel *l = &s->labels[label_index];
408 val = l->u.value - (tcg_target_long)s->code_ptr;
409 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
410 | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
412 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
413 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
417 static const uint8_t tcg_cond_to_bcond[10] = {
418 [TCG_COND_EQ] = COND_E,
419 [TCG_COND_NE] = COND_NE,
420 [TCG_COND_LT] = COND_L,
421 [TCG_COND_GE] = COND_GE,
422 [TCG_COND_LE] = COND_LE,
423 [TCG_COND_GT] = COND_G,
424 [TCG_COND_LTU] = COND_CS,
425 [TCG_COND_GEU] = COND_CC,
426 [TCG_COND_LEU] = COND_LEU,
427 [TCG_COND_GTU] = COND_GU,
430 static void tcg_out_brcond(TCGContext *s, int cond,
431 TCGArg arg1, TCGArg arg2, int const_arg2,
434 if (const_arg2 && arg2 == 0)
435 /* orcc %g0, r, %g0 */
436 tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC);
438 /* subcc r1, r2, %g0 */
439 tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC);
440 tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index);
444 /* Generate global QEMU prologue and epilogue code */
445 void tcg_target_qemu_prologue(TCGContext *s)
447 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
448 INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
449 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
450 INSN_RS2(TCG_REG_G0));
454 #if defined(CONFIG_SOFTMMU)
455 extern void __ldb_mmu(void);
456 extern void __ldw_mmu(void);
457 extern void __ldl_mmu(void);
458 extern void __ldq_mmu(void);
460 extern void __stb_mmu(void);
461 extern void __stw_mmu(void);
462 extern void __stl_mmu(void);
463 extern void __stq_mmu(void);
466 static const void * const qemu_ld_helpers[4] = {
473 static const void * const qemu_st_helpers[4] = {
481 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
484 int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
485 #if defined(CONFIG_SOFTMMU)
486 uint8_t *label1_ptr, *label2_ptr;
497 #if TARGET_LONG_BITS == 32
503 #if defined(CONFIG_SOFTMMU)
504 /* srl addr_reg, x, r1 */
505 tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
507 /* and addr_reg, x, r0 */
508 tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
512 tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
516 tcg_out_arithi(s, r1, r1, offsetof(CPUState, tlb_table[mem_index][0].addr_read),
519 /* ld [env + r1], r1 */
520 tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op);
522 /* subcc r0, r1, %g0 */
523 tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC);
527 label1_ptr = s->code_ptr;
530 /* mov (delay slot)*/
531 tcg_out_mov(s, r0, addr_reg);
533 /* XXX: move that code at the end of the TB */
534 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
535 - (tcg_target_ulong)s->code_ptr) >> 2)
537 /* mov (delay slot)*/
538 tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index);
542 /* sll i0, 24/56, i0 */
543 tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
544 sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL);
545 /* sra i0, 24/56, data_reg */
546 tcg_out_arithi(s, data_reg, TCG_REG_I0,
547 sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA);
550 /* sll i0, 16/48, i0 */
551 tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
552 sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL);
553 /* sra i0, 16/48, data_reg */
554 tcg_out_arithi(s, data_reg, TCG_REG_I0,
555 sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA);
559 tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
560 /* sra i0, 32, data_reg */
561 tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
569 tcg_out_mov(s, data_reg, TCG_REG_I0);
575 label2_ptr = s->code_ptr;
579 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
580 INSN_OFF22((unsigned long)label1_ptr -
581 (unsigned long)s->code_ptr));
583 /* ld [r1 + x], r1 */
584 tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) -
585 offsetof(CPUTLBEntry, addr_read), ld_op);
587 tcg_out_arith(s, r0, r1, r0, ARITH_ADD);
594 /* ldub [r0], data_reg */
595 tcg_out_ldst(s, data_reg, r0, 0, LDUB);
598 /* ldsb [r0], data_reg */
599 tcg_out_ldst(s, data_reg, r0, 0, LDSB);
602 #ifdef TARGET_WORDS_BIGENDIAN
603 /* lduh [r0], data_reg */
604 tcg_out_ldst(s, data_reg, r0, 0, LDUH);
606 /* lduha [r0] ASI_PRIMARY_LITTLE, data_reg */
607 tcg_out_ldst_asi(s, data_reg, r0, 0, LDUHA, ASI_PRIMARY_LITTLE);
611 #ifdef TARGET_WORDS_BIGENDIAN
612 /* ldsh [r0], data_reg */
613 tcg_out_ldst(s, data_reg, r0, 0, LDSH);
615 /* ldsha [r0] ASI_PRIMARY_LITTLE, data_reg */
616 tcg_out_ldst_asi(s, data_reg, r0, 0, LDSHA, ASI_PRIMARY_LITTLE);
620 #ifdef TARGET_WORDS_BIGENDIAN
621 /* lduw [r0], data_reg */
622 tcg_out_ldst(s, data_reg, r0, 0, LDUW);
624 /* lduwa [r0] ASI_PRIMARY_LITTLE, data_reg */
625 tcg_out_ldst_asi(s, data_reg, r0, 0, LDUWA, ASI_PRIMARY_LITTLE);
629 #ifdef TARGET_WORDS_BIGENDIAN
630 /* ldsw [r0], data_reg */
631 tcg_out_ldst(s, data_reg, r0, 0, LDSW);
633 /* ldswa [r0] ASI_PRIMARY_LITTLE, data_reg */
634 tcg_out_ldst_asi(s, data_reg, r0, 0, LDSWA, ASI_PRIMARY_LITTLE);
638 #ifdef TARGET_WORDS_BIGENDIAN
639 /* ldx [r0], data_reg */
640 tcg_out_ldst(s, data_reg, r0, 0, LDX);
642 /* ldxa [r0] ASI_PRIMARY_LITTLE, data_reg */
643 tcg_out_ldst_asi(s, data_reg, r0, 0, LDXA, ASI_PRIMARY_LITTLE);
650 #if defined(CONFIG_SOFTMMU)
652 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
653 INSN_OFF22((unsigned long)label2_ptr -
654 (unsigned long)s->code_ptr));
658 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
661 int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
662 #if defined(CONFIG_SOFTMMU)
663 uint8_t *label1_ptr, *label2_ptr;
675 #if TARGET_LONG_BITS == 32
681 #if defined(CONFIG_SOFTMMU)
682 /* srl addr_reg, x, r1 */
683 tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
685 /* and addr_reg, x, r0 */
686 tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
690 tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
694 tcg_out_arithi(s, r1, r1,
695 offsetof(CPUState, tlb_table[mem_index][0].addr_write),
698 /* ld [env + r1], r1 */
699 tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op);
701 /* subcc r0, r1, %g0 */
702 tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC);
706 label1_ptr = s->code_ptr;
708 /* mov (delay slot)*/
709 tcg_out_mov(s, r0, addr_reg);
713 /* sll i0, 24/56, i0 */
714 tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
715 sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL);
716 /* sra i0, 24/56, data_reg */
717 tcg_out_arithi(s, data_reg, TCG_REG_I0,
718 sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA);
721 /* sll i0, 16/48, i0 */
722 tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0,
723 sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL);
724 /* sra i0, 16/48, data_reg */
725 tcg_out_arithi(s, data_reg, TCG_REG_I0,
726 sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA);
730 tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
731 /* sra i0, 32, data_reg */
732 tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
740 tcg_out_mov(s, data_reg, TCG_REG_I0);
744 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
745 - (tcg_target_ulong)s->code_ptr) >> 2)
747 /* mov (delay slot)*/
748 tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index);
752 label2_ptr = s->code_ptr;
756 *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
757 INSN_OFF22((unsigned long)label1_ptr -
758 (unsigned long)s->code_ptr));
760 /* ld [r1 + x], r1 */
761 tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) -
762 offsetof(CPUTLBEntry, addr_write), ld_op);
764 tcg_out_arith(s, r0, r1, r0, ARITH_ADD);
771 /* stb data_reg, [r0] */
772 tcg_out_ldst(s, data_reg, r0, 0, STB);
775 #ifdef TARGET_WORDS_BIGENDIAN
776 /* sth data_reg, [r0] */
777 tcg_out_ldst(s, data_reg, r0, 0, STH);
779 /* stha data_reg, [r0] ASI_PRIMARY_LITTLE */
780 tcg_out_ldst_asi(s, data_reg, r0, 0, STHA, ASI_PRIMARY_LITTLE);
784 #ifdef TARGET_WORDS_BIGENDIAN
785 /* stw data_reg, [r0] */
786 tcg_out_ldst(s, data_reg, r0, 0, STW);
788 /* stwa data_reg, [r0] ASI_PRIMARY_LITTLE */
789 tcg_out_ldst_asi(s, data_reg, r0, 0, STWA, ASI_PRIMARY_LITTLE);
793 #ifdef TARGET_WORDS_BIGENDIAN
794 /* stx data_reg, [r0] */
795 tcg_out_ldst(s, data_reg, r0, 0, STX);
797 /* stxa data_reg, [r0] ASI_PRIMARY_LITTLE */
798 tcg_out_ldst_asi(s, data_reg, r0, 0, STXA, ASI_PRIMARY_LITTLE);
805 #if defined(CONFIG_SOFTMMU)
807 *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
808 INSN_OFF22((unsigned long)label2_ptr -
809 (unsigned long)s->code_ptr));
813 static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
814 const int *const_args)
819 case INDEX_op_exit_tb:
820 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
821 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
823 tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
824 INSN_RS2(TCG_REG_G0));
826 case INDEX_op_goto_tb:
827 if (s->tb_jmp_offset) {
828 /* direct jump method */
829 tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
830 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
831 INSN_IMM13((args[0] & 0x1fff)));
832 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
834 /* indirect jump method */
835 tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
836 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
837 INSN_RS2(TCG_REG_G0));
840 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
844 tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
845 - (tcg_target_ulong)s->code_ptr) >> 2)
849 tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
850 tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
851 INSN_RS2(TCG_REG_G0));
857 tcg_out_branch(s, COND_A, args[0]);
860 case INDEX_op_movi_i32:
861 tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
864 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
865 #define OP_32_64(x) \
866 glue(glue(case INDEX_op_, x), _i32:) \
867 glue(glue(case INDEX_op_, x), _i64:)
869 #define OP_32_64(x) \
870 glue(glue(case INDEX_op_, x), _i32:)
873 tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
876 tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
879 tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
882 tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
884 case INDEX_op_ld_i32:
885 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
886 case INDEX_op_ld32u_i64:
888 tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
891 tcg_out_ldst(s, args[0], args[1], args[2], STB);
894 tcg_out_ldst(s, args[0], args[1], args[2], STH);
896 case INDEX_op_st_i32:
897 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
898 case INDEX_op_st32_i64:
900 tcg_out_ldst(s, args[0], args[1], args[2], STW);
917 case INDEX_op_shl_i32:
920 case INDEX_op_shr_i32:
923 case INDEX_op_sar_i32:
926 case INDEX_op_mul_i32:
929 case INDEX_op_div2_i32:
930 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
938 case INDEX_op_divu2_i32:
939 #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
948 case INDEX_op_brcond_i32:
949 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
953 case INDEX_op_qemu_ld8u:
954 tcg_out_qemu_ld(s, args, 0);
956 case INDEX_op_qemu_ld8s:
957 tcg_out_qemu_ld(s, args, 0 | 4);
959 case INDEX_op_qemu_ld16u:
960 tcg_out_qemu_ld(s, args, 1);
962 case INDEX_op_qemu_ld16s:
963 tcg_out_qemu_ld(s, args, 1 | 4);
965 case INDEX_op_qemu_ld32u:
966 tcg_out_qemu_ld(s, args, 2);
968 case INDEX_op_qemu_ld32s:
969 tcg_out_qemu_ld(s, args, 2 | 4);
971 case INDEX_op_qemu_st8:
972 tcg_out_qemu_st(s, args, 0);
974 case INDEX_op_qemu_st16:
975 tcg_out_qemu_st(s, args, 1);
977 case INDEX_op_qemu_st32:
978 tcg_out_qemu_st(s, args, 2);
981 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
982 case INDEX_op_movi_i64:
983 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
985 case INDEX_op_ld32s_i64:
986 tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
988 case INDEX_op_ld_i64:
989 tcg_out_ldst(s, args[0], args[1], args[2], LDX);
991 case INDEX_op_st_i64:
992 tcg_out_ldst(s, args[0], args[1], args[2], STX);
994 case INDEX_op_shl_i64:
997 case INDEX_op_shr_i64:
1000 case INDEX_op_sar_i64:
1003 case INDEX_op_mul_i64:
1006 case INDEX_op_div2_i64:
1009 case INDEX_op_divu2_i64:
1013 case INDEX_op_brcond_i64:
1014 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1017 case INDEX_op_qemu_ld64:
1018 tcg_out_qemu_ld(s, args, 3);
1020 case INDEX_op_qemu_st64:
1021 tcg_out_qemu_st(s, args, 3);
1026 if (const_args[2]) {
1027 tcg_out_arithi(s, args[0], args[1], args[2], c);
1029 tcg_out_arith(s, args[0], args[1], args[2], c);
1034 fprintf(stderr, "unknown opcode 0x%x\n", opc);
1039 static const TCGTargetOpDef sparc_op_defs[] = {
1040 { INDEX_op_exit_tb, { } },
1041 { INDEX_op_goto_tb, { } },
1042 { INDEX_op_call, { "ri" } },
1043 { INDEX_op_jmp, { "ri" } },
1044 { INDEX_op_br, { } },
1046 { INDEX_op_mov_i32, { "r", "r" } },
1047 { INDEX_op_movi_i32, { "r" } },
1048 { INDEX_op_ld8u_i32, { "r", "r" } },
1049 { INDEX_op_ld8s_i32, { "r", "r" } },
1050 { INDEX_op_ld16u_i32, { "r", "r" } },
1051 { INDEX_op_ld16s_i32, { "r", "r" } },
1052 { INDEX_op_ld_i32, { "r", "r" } },
1053 { INDEX_op_st8_i32, { "r", "r" } },
1054 { INDEX_op_st16_i32, { "r", "r" } },
1055 { INDEX_op_st_i32, { "r", "r" } },
1057 { INDEX_op_add_i32, { "r", "r", "rJ" } },
1058 { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1059 { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
1060 { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
1061 { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1062 { INDEX_op_and_i32, { "r", "r", "rJ" } },
1063 { INDEX_op_or_i32, { "r", "r", "rJ" } },
1064 { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1066 { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1067 { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1068 { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1070 { INDEX_op_brcond_i32, { "r", "ri" } },
1072 { INDEX_op_qemu_ld8u, { "r", "L" } },
1073 { INDEX_op_qemu_ld8s, { "r", "L" } },
1074 { INDEX_op_qemu_ld16u, { "r", "L" } },
1075 { INDEX_op_qemu_ld16s, { "r", "L" } },
1076 { INDEX_op_qemu_ld32u, { "r", "L" } },
1077 { INDEX_op_qemu_ld32s, { "r", "L" } },
1079 { INDEX_op_qemu_st8, { "L", "L" } },
1080 { INDEX_op_qemu_st16, { "L", "L" } },
1081 { INDEX_op_qemu_st32, { "L", "L" } },
1083 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1084 { INDEX_op_mov_i64, { "r", "r" } },
1085 { INDEX_op_movi_i64, { "r" } },
1086 { INDEX_op_ld8u_i64, { "r", "r" } },
1087 { INDEX_op_ld8s_i64, { "r", "r" } },
1088 { INDEX_op_ld16u_i64, { "r", "r" } },
1089 { INDEX_op_ld16s_i64, { "r", "r" } },
1090 { INDEX_op_ld32u_i64, { "r", "r" } },
1091 { INDEX_op_ld32s_i64, { "r", "r" } },
1092 { INDEX_op_ld_i64, { "r", "r" } },
1093 { INDEX_op_st8_i64, { "r", "r" } },
1094 { INDEX_op_st16_i64, { "r", "r" } },
1095 { INDEX_op_st32_i64, { "r", "r" } },
1096 { INDEX_op_st_i64, { "r", "r" } },
1098 { INDEX_op_add_i64, { "r", "r", "rJ" } },
1099 { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1100 { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
1101 { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
1102 { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1103 { INDEX_op_and_i64, { "r", "r", "rJ" } },
1104 { INDEX_op_or_i64, { "r", "r", "rJ" } },
1105 { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1107 { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1108 { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1109 { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1111 { INDEX_op_brcond_i64, { "r", "ri" } },
1116 void tcg_target_init(TCGContext *s)
1118 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1119 #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1120 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1122 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1138 tcg_regset_clear(s->reserved_regs);
1139 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1140 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1141 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1142 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1143 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1144 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1145 tcg_add_target_add_op_defs(sparc_op_defs);