2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 static uint8_t *tb_ret_addr;
28 #define LINKAGE_AREA_SIZE 24
29 #define BACK_CHAIN_OFFSET 8
31 #define LINKAGE_AREA_SIZE 8
32 #define BACK_CHAIN_OFFSET 4
36 #if TARGET_PHYS_ADDR_BITS <= 32
37 #define ADDEND_OFFSET 0
39 #define ADDEND_OFFSET 4
43 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
79 static const int tcg_target_reg_alloc_order[] = {
119 static const int tcg_target_call_iarg_regs[] = {
130 static const int tcg_target_call_oarg_regs[2] = {
135 static const int tcg_target_callee_save_regs[] = {
156 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
158 tcg_target_long disp;
160 disp = target - (tcg_target_long) pc;
161 if ((disp << 6) >> 6 != disp)
164 return disp & 0x3fffffc;
167 static void reloc_pc24 (void *pc, tcg_target_long target)
169 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
170 | reloc_pc24_val (pc, target);
173 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
175 tcg_target_long disp;
177 disp = target - (tcg_target_long) pc;
178 if (disp != (int16_t) disp)
181 return disp & 0xfffc;
184 static void reloc_pc14 (void *pc, tcg_target_long target)
186 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
187 | reloc_pc14_val (pc, target);
190 static void patch_reloc(uint8_t *code_ptr, int type,
191 tcg_target_long value, tcg_target_long addend)
196 reloc_pc14 (code_ptr, value);
199 reloc_pc24 (code_ptr, value);
206 /* maximum number of register used for input function arguments */
207 static int tcg_target_get_call_iarg_regs_count(int flags)
209 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
212 /* parse target specific constraints */
213 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
219 case 'A': case 'B': case 'C': case 'D':
220 ct->ct |= TCG_CT_REG;
221 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
224 ct->ct |= TCG_CT_REG;
225 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
227 #ifdef CONFIG_SOFTMMU
228 case 'L': /* qemu_ld constraint */
229 ct->ct |= TCG_CT_REG;
230 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
231 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
232 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
234 case 'K': /* qemu_st[8..32] constraint */
235 ct->ct |= TCG_CT_REG;
236 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
237 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
238 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
239 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
240 #if TARGET_LONG_BITS == 64
241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
244 case 'M': /* qemu_st64 constraint */
245 ct->ct |= TCG_CT_REG;
246 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
247 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
248 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
249 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
256 ct->ct |= TCG_CT_REG;
257 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
260 ct->ct |= TCG_CT_REG;
261 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
262 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
273 /* test if a constant matches the constraint */
274 static int tcg_target_const_match(tcg_target_long val,
275 const TCGArgConstraint *arg_ct)
280 if (ct & TCG_CT_CONST)
285 #define OPCD(opc) ((opc)<<26)
286 #define XO31(opc) (OPCD(31)|((opc)<<1))
287 #define XO19(opc) (OPCD(19)|((opc)<<1))
299 #define ADDI OPCD(14)
300 #define ADDIS OPCD(15)
302 #define ORIS OPCD(25)
303 #define XORI OPCD(26)
304 #define XORIS OPCD(27)
305 #define ANDI OPCD(28)
306 #define ANDIS OPCD(29)
307 #define MULLI OPCD( 7)
308 #define CMPLI OPCD(10)
309 #define CMPI OPCD(11)
311 #define LWZU OPCD(33)
312 #define STWU OPCD(37)
314 #define RLWINM OPCD(21)
316 #define BCLR XO19( 16)
317 #define BCCTR XO19(528)
318 #define CRAND XO19(257)
319 #define CRANDC XO19(129)
320 #define CRNAND XO19(225)
321 #define CROR XO19(449)
323 #define EXTSB XO31(954)
324 #define EXTSH XO31(922)
325 #define ADD XO31(266)
326 #define ADDE XO31(138)
327 #define ADDC XO31( 10)
328 #define AND XO31( 28)
329 #define SUBF XO31( 40)
330 #define SUBFC XO31( 8)
331 #define SUBFE XO31(136)
333 #define XOR XO31(316)
334 #define MULLW XO31(235)
335 #define MULHWU XO31( 11)
336 #define DIVW XO31(491)
337 #define DIVWU XO31(459)
339 #define CMPL XO31( 32)
340 #define LHBRX XO31(790)
341 #define LWBRX XO31(534)
342 #define STHBRX XO31(918)
343 #define STWBRX XO31(662)
344 #define MFSPR XO31(339)
345 #define MTSPR XO31(467)
346 #define SRAWI XO31(824)
347 #define NEG XO31(104)
349 #define LBZX XO31( 87)
350 #define LHZX XO31(276)
351 #define LHAX XO31(343)
352 #define LWZX XO31( 23)
353 #define STBX XO31(215)
354 #define STHX XO31(407)
355 #define STWX XO31(151)
357 #define SPR(a,b) ((((a)<<5)|(b))<<11)
359 #define CTR SPR(9, 0)
361 #define SLW XO31( 24)
362 #define SRW XO31(536)
363 #define SRAW XO31(792)
366 #define STMW OPCD(47)
369 #define TRAP (TW | TO (31))
371 #define RT(r) ((r)<<21)
372 #define RS(r) ((r)<<21)
373 #define RA(r) ((r)<<16)
374 #define RB(r) ((r)<<11)
375 #define TO(t) ((t)<<21)
376 #define SH(s) ((s)<<11)
377 #define MB(b) ((b)<<6)
378 #define ME(e) ((e)<<1)
379 #define BO(o) ((o)<<21)
383 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
384 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
386 #define BF(n) ((n)<<23)
387 #define BI(n, c) (((c)+((n)*4))<<16)
388 #define BT(n, c) (((c)+((n)*4))<<21)
389 #define BA(n, c) (((c)+((n)*4))<<16)
390 #define BB(n, c) (((c)+((n)*4))<<11)
392 #define BO_COND_TRUE BO (12)
393 #define BO_COND_FALSE BO (4)
394 #define BO_ALWAYS BO (20)
403 static const uint32_t tcg_to_bc[10] = {
404 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
405 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
406 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
407 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
408 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
409 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
410 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
411 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
412 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
413 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
416 static void tcg_out_mov(TCGContext *s, int ret, int arg)
418 tcg_out32 (s, OR | SAB (arg, ret, arg));
421 static void tcg_out_movi(TCGContext *s, TCGType type,
422 int ret, tcg_target_long arg)
424 if (arg == (int16_t) arg)
425 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
427 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
429 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
433 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
434 int offset, int op1, int op2)
436 if (offset == (int16_t) offset)
437 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
439 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
440 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
444 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
446 tcg_target_long disp;
448 disp = target - (tcg_target_long) s->code_ptr;
449 if ((disp << 6) >> 6 == disp)
450 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
452 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
453 tcg_out32 (s, MTSPR | RS (0) | CTR);
454 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
458 #if defined(CONFIG_SOFTMMU)
460 #include "../../softmmu_defs.h"
462 static void *qemu_ld_helpers[4] = {
469 static void *qemu_st_helpers[4] = {
477 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
479 int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
480 #ifdef CONFIG_SOFTMMU
482 void *label1_ptr, *label2_ptr;
484 #if TARGET_LONG_BITS == 64
494 #if TARGET_LONG_BITS == 64
500 #ifdef CONFIG_SOFTMMU
505 tcg_out32 (s, (RLWINM
508 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
509 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
510 | ME (31 - CPU_TLB_ENTRY_BITS)
513 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
517 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
520 tcg_out32 (s, (RLWINM
524 | MB ((32 - s_bits) & 31)
525 | ME (31 - TARGET_PAGE_BITS)
529 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
530 #if TARGET_LONG_BITS == 64
531 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
532 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
533 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
536 label1_ptr = s->code_ptr;
538 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
542 #if TARGET_LONG_BITS == 32
543 tcg_out_mov (s, 3, addr_reg);
544 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
546 tcg_out_mov (s, 3, addr_reg2);
547 tcg_out_mov (s, 4, addr_reg);
548 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
551 tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
554 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
557 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
563 tcg_out_mov (s, data_reg, 3);
567 if (data_reg2 == 4) {
568 tcg_out_mov (s, 0, 4);
569 tcg_out_mov (s, 4, 3);
570 tcg_out_mov (s, 3, 0);
573 tcg_out_mov (s, data_reg2, 3);
574 tcg_out_mov (s, 3, 4);
578 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
579 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
583 label2_ptr = s->code_ptr;
586 /* label1: fast path */
588 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
591 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
595 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
596 - offsetof (CPUTLBEntry, addr_read))
598 /* r0 = env->tlb_table[mem_index][index].addend */
599 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
600 /* r0 = env->tlb_table[mem_index][index].addend + addr */
602 #else /* !CONFIG_SOFTMMU */
607 #ifdef TARGET_WORDS_BIGENDIAN
615 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
618 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
619 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
622 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
623 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
627 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
628 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
630 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
633 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
634 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
638 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
639 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
640 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r1));
643 if (r0 == data_reg2) {
644 tcg_out32 (s, LWZ | RT (0) | RA (r0));
645 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
646 tcg_out_mov (s, data_reg2, 0);
649 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
650 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
656 #ifdef CONFIG_SOFTMMU
657 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
661 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
663 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
664 #ifdef CONFIG_SOFTMMU
666 void *label1_ptr, *label2_ptr;
668 #if TARGET_LONG_BITS == 64
678 #if TARGET_LONG_BITS == 64
683 #ifdef CONFIG_SOFTMMU
688 tcg_out32 (s, (RLWINM
691 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
692 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
693 | ME (31 - CPU_TLB_ENTRY_BITS)
696 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
700 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
703 tcg_out32 (s, (RLWINM
707 | MB ((32 - opc) & 31)
708 | ME (31 - TARGET_PAGE_BITS)
712 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
713 #if TARGET_LONG_BITS == 64
714 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
715 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
716 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
719 label1_ptr = s->code_ptr;
721 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
725 #if TARGET_LONG_BITS == 32
726 tcg_out_mov (s, 3, addr_reg);
729 tcg_out_mov (s, 3, addr_reg2);
730 tcg_out_mov (s, 4, addr_reg);
731 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
740 tcg_out32 (s, (RLWINM
748 tcg_out32 (s, (RLWINM
756 tcg_out_mov (s, ir, data_reg);
759 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
762 tcg_out_mov (s, ir++, data_reg2);
763 tcg_out_mov (s, ir, data_reg);
768 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
769 tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
770 label2_ptr = s->code_ptr;
773 /* label1: fast path */
775 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
781 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
782 - offsetof (CPUTLBEntry, addr_write))
784 /* r0 = env->tlb_table[mem_index][index].addend */
785 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
786 /* r0 = env->tlb_table[mem_index][index].addend + addr */
788 #else /* !CONFIG_SOFTMMU */
793 #ifdef TARGET_WORDS_BIGENDIAN
800 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
803 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
804 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
807 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
808 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
812 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
813 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
814 tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
817 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
818 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
823 #ifdef CONFIG_SOFTMMU
824 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
828 void tcg_target_qemu_prologue (TCGContext *s)
834 + TCG_STATIC_CALL_ARGS_SIZE
835 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
837 frame_size = (frame_size + 15) & ~15;
839 tcg_out32 (s, MFSPR | RT (0) | LR);
840 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
841 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
843 | RS (tcg_target_callee_save_regs[i])
845 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
848 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET));
850 tcg_out32 (s, MTSPR | RS (3) | CTR);
851 tcg_out32 (s, BCCTR | BO_ALWAYS);
852 tb_ret_addr = s->code_ptr;
854 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
856 | RT (tcg_target_callee_save_regs[i])
858 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
861 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET));
862 tcg_out32 (s, MTSPR | RS (0) | LR);
863 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
864 tcg_out32 (s, BCLR | BO_ALWAYS);
867 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
868 tcg_target_long arg2)
870 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
873 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
874 tcg_target_long arg2)
876 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
879 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
884 if (si == (int16_t) si)
885 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
887 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
888 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
889 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
893 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
895 ppc_addi (s, reg, reg, val);
898 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
899 int const_arg2, int cr)
908 if ((int16_t) arg2 == arg2) {
913 else if ((uint16_t) arg2 == arg2) {
928 if ((int16_t) arg2 == arg2) {
943 if ((uint16_t) arg2 == arg2) {
959 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
962 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
963 tcg_out32 (s, op | RA (arg1) | RB (0));
966 tcg_out32 (s, op | RA (arg1) | RB (arg2));
971 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
973 TCGLabel *l = &s->labels[label_index];
976 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
978 uint16_t val = *(uint16_t *) &s->code_ptr[2];
980 /* Thanks to Andrzej Zaborowski */
981 tcg_out32 (s, bc | (val & 0xfffc));
982 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
986 static void tcg_out_brcond (TCGContext *s, int cond,
987 TCGArg arg1, TCGArg arg2, int const_arg2,
990 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
991 tcg_out_bc (s, tcg_to_bc[cond], label_index);
994 /* XXX: we implement it at the target level to avoid having to
995 handle cross basic blocks temporaries */
996 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
997 const int *const_args)
999 int cond = args[4], label_index = args[5], op;
1000 struct { int bit1; int bit2; int cond2; } bits[] = {
1001 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1002 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1003 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1004 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1005 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1006 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1007 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1008 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1009 }, *b = &bits[cond];
1014 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1015 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1016 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1017 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1027 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1028 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1029 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1030 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1031 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1032 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1038 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index);
1041 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1044 long disp = addr - jmp_addr;
1045 unsigned long patch_size;
1047 ptr = (uint32_t *)jmp_addr;
1049 if ((disp << 6) >> 6 != disp) {
1050 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1051 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1052 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1053 ptr[3] = 0x4e800420; /* brctr */
1056 /* patch the branch destination */
1058 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1061 ptr[0] = 0x60000000; /* nop */
1062 ptr[1] = 0x60000000;
1063 ptr[2] = 0x60000000;
1064 ptr[3] = 0x60000000;
1069 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1072 static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1073 const int *const_args)
1076 case INDEX_op_exit_tb:
1077 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1078 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1080 case INDEX_op_goto_tb:
1081 if (s->tb_jmp_offset) {
1082 /* direct jump method */
1084 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1090 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1094 TCGLabel *l = &s->labels[args[0]];
1097 tcg_out_b (s, 0, l->u.value);
1100 uint32_t val = *(uint32_t *) s->code_ptr;
1102 /* Thanks to Andrzej Zaborowski */
1103 tcg_out32 (s, B | (val & 0x3fffffc));
1104 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1109 if (const_args[0]) {
1110 tcg_out_b (s, LK, args[0]);
1113 tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1114 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1118 if (const_args[0]) {
1119 tcg_out_b (s, 0, args[0]);
1122 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1123 tcg_out32 (s, BCCTR | BO_ALWAYS);
1126 case INDEX_op_movi_i32:
1127 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1129 case INDEX_op_ld8u_i32:
1130 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1132 case INDEX_op_ld8s_i32:
1133 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1134 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1136 case INDEX_op_ld16u_i32:
1137 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1139 case INDEX_op_ld16s_i32:
1140 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1142 case INDEX_op_ld_i32:
1143 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1145 case INDEX_op_st8_i32:
1146 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1148 case INDEX_op_st16_i32:
1149 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1151 case INDEX_op_st_i32:
1152 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1155 case INDEX_op_add_i32:
1157 ppc_addi (s, args[0], args[1], args[2]);
1159 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1161 case INDEX_op_sub_i32:
1163 ppc_addi (s, args[0], args[1], -args[2]);
1165 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1168 case INDEX_op_and_i32:
1169 if (const_args[2]) {
1170 if ((args[2] & 0xffff) == args[2])
1171 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1172 else if ((args[2] & 0xffff0000) == args[2])
1173 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1174 | ((args[2] >> 16) & 0xffff));
1176 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1177 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1181 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1183 case INDEX_op_or_i32:
1184 if (const_args[2]) {
1185 if (args[2] & 0xffff) {
1186 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1187 | (args[2] & 0xffff));
1189 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1190 | ((args[2] >> 16) & 0xffff));
1193 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1194 | ((args[2] >> 16) & 0xffff));
1198 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1200 case INDEX_op_xor_i32:
1201 if (const_args[2]) {
1202 if ((args[2] & 0xffff) == args[2])
1203 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1204 | (args[2] & 0xffff));
1205 else if ((args[2] & 0xffff0000) == args[2])
1206 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1207 | ((args[2] >> 16) & 0xffff));
1209 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1210 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1214 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1217 case INDEX_op_mul_i32:
1218 if (const_args[2]) {
1219 if (args[2] == (int16_t) args[2])
1220 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1221 | (args[2] & 0xffff));
1223 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1224 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1228 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1231 case INDEX_op_div_i32:
1232 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1235 case INDEX_op_divu_i32:
1236 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1239 case INDEX_op_rem_i32:
1240 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1241 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1242 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1245 case INDEX_op_remu_i32:
1246 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1247 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1248 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1251 case INDEX_op_mulu2_i32:
1252 if (args[0] == args[2] || args[0] == args[3]) {
1253 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1254 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1255 tcg_out_mov (s, args[0], 0);
1258 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1259 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1263 case INDEX_op_shl_i32:
1264 if (const_args[2]) {
1265 tcg_out32 (s, (RLWINM
1275 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1277 case INDEX_op_shr_i32:
1278 if (const_args[2]) {
1279 tcg_out32 (s, (RLWINM
1289 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1291 case INDEX_op_sar_i32:
1293 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1295 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1298 case INDEX_op_add2_i32:
1299 if (args[0] == args[3] || args[0] == args[5]) {
1300 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1301 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1302 tcg_out_mov (s, args[0], 0);
1305 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1306 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1309 case INDEX_op_sub2_i32:
1310 if (args[0] == args[3] || args[0] == args[5]) {
1311 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1312 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1313 tcg_out_mov (s, args[0], 0);
1316 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1317 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1321 case INDEX_op_brcond_i32:
1326 args[3] = r1 is const
1327 args[4] = label_index
1329 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1331 case INDEX_op_brcond2_i32:
1332 tcg_out_brcond2(s, args, const_args);
1335 case INDEX_op_neg_i32:
1336 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1339 case INDEX_op_qemu_ld8u:
1340 tcg_out_qemu_ld(s, args, 0);
1342 case INDEX_op_qemu_ld8s:
1343 tcg_out_qemu_ld(s, args, 0 | 4);
1345 case INDEX_op_qemu_ld16u:
1346 tcg_out_qemu_ld(s, args, 1);
1348 case INDEX_op_qemu_ld16s:
1349 tcg_out_qemu_ld(s, args, 1 | 4);
1351 case INDEX_op_qemu_ld32u:
1352 tcg_out_qemu_ld(s, args, 2);
1354 case INDEX_op_qemu_ld64:
1355 tcg_out_qemu_ld(s, args, 3);
1357 case INDEX_op_qemu_st8:
1358 tcg_out_qemu_st(s, args, 0);
1360 case INDEX_op_qemu_st16:
1361 tcg_out_qemu_st(s, args, 1);
1363 case INDEX_op_qemu_st32:
1364 tcg_out_qemu_st(s, args, 2);
1366 case INDEX_op_qemu_st64:
1367 tcg_out_qemu_st(s, args, 3);
1370 case INDEX_op_ext8s_i32:
1371 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1373 case INDEX_op_ext16s_i32:
1374 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1378 tcg_dump_ops (s, stderr);
1383 static const TCGTargetOpDef ppc_op_defs[] = {
1384 { INDEX_op_exit_tb, { } },
1385 { INDEX_op_goto_tb, { } },
1386 { INDEX_op_call, { "ri" } },
1387 { INDEX_op_jmp, { "ri" } },
1388 { INDEX_op_br, { } },
1390 { INDEX_op_mov_i32, { "r", "r" } },
1391 { INDEX_op_movi_i32, { "r" } },
1392 { INDEX_op_ld8u_i32, { "r", "r" } },
1393 { INDEX_op_ld8s_i32, { "r", "r" } },
1394 { INDEX_op_ld16u_i32, { "r", "r" } },
1395 { INDEX_op_ld16s_i32, { "r", "r" } },
1396 { INDEX_op_ld_i32, { "r", "r" } },
1397 { INDEX_op_st8_i32, { "r", "r" } },
1398 { INDEX_op_st16_i32, { "r", "r" } },
1399 { INDEX_op_st_i32, { "r", "r" } },
1401 { INDEX_op_add_i32, { "r", "r", "ri" } },
1402 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1403 { INDEX_op_div_i32, { "r", "r", "r" } },
1404 { INDEX_op_divu_i32, { "r", "r", "r" } },
1405 { INDEX_op_rem_i32, { "r", "r", "r" } },
1406 { INDEX_op_remu_i32, { "r", "r", "r" } },
1407 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1408 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1409 { INDEX_op_and_i32, { "r", "r", "ri" } },
1410 { INDEX_op_or_i32, { "r", "r", "ri" } },
1411 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1413 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1414 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1415 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1417 { INDEX_op_brcond_i32, { "r", "ri" } },
1419 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1420 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1421 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1423 { INDEX_op_neg_i32, { "r", "r" } },
1425 #if TARGET_LONG_BITS == 32
1426 { INDEX_op_qemu_ld8u, { "r", "L" } },
1427 { INDEX_op_qemu_ld8s, { "r", "L" } },
1428 { INDEX_op_qemu_ld16u, { "r", "L" } },
1429 { INDEX_op_qemu_ld16s, { "r", "L" } },
1430 { INDEX_op_qemu_ld32u, { "r", "L" } },
1431 { INDEX_op_qemu_ld32s, { "r", "L" } },
1432 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1434 { INDEX_op_qemu_st8, { "K", "K" } },
1435 { INDEX_op_qemu_st16, { "K", "K" } },
1436 { INDEX_op_qemu_st32, { "K", "K" } },
1437 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1439 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1440 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1441 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1442 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1443 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1444 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1445 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1447 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1448 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1449 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1450 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1453 { INDEX_op_ext8s_i32, { "r", "r" } },
1454 { INDEX_op_ext16s_i32, { "r", "r" } },
1459 void tcg_target_init(TCGContext *s)
1461 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1462 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1474 (1 << TCG_REG_R10) |
1475 (1 << TCG_REG_R11) |
1479 tcg_regset_clear(s->reserved_regs);
1480 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1481 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1483 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1486 tcg_add_target_add_op_defs(ppc_op_defs);