vcs.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28    Optional alignment check
  29    128-bit float
  30    Tagged add/sub
  31 */
  32
  33 #include <stdarg.h>
  34 #include <stdlib.h>
  35 #include <stdio.h>
  36 #include <string.h>
  37 #include <inttypes.h>
  38
  39 #include "cpu.h"
  40 #include "exec-all.h"
  41 #include "disas.h"
  42
  43 #define DEBUG_DISAS
  44
  45 #define DYNAMIC_PC  1 /* dynamic pc value */
  46 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  47                          according to jump_pc[T2] */
  48
  49 typedef struct DisasContext {
  50     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  51     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  52     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  53     int is_br;
  54     int mem_idx;
  55     struct TranslationBlock *tb;
  56 } DisasContext;
  57
  58 static uint16_t *gen_opc_ptr;
  59 static uint32_t *gen_opparam_ptr;
  60 extern FILE *logfile;
  61 extern int loglevel;
  62
  63 enum {
  64 #define DEF(s,n,copy_size) INDEX_op_ ## s,
  65 #include "opc.h"
  66 #undef DEF
  67     NB_OPS
  68 };
  69
  70 #include "gen-op.h"
  71
  72 // This function uses non-native bit order
  73 #define GET_FIELD(X, FROM, TO) \
  74   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  75
  76 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  77 #define GET_FIELD_SP(X, FROM, TO) \
  78     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  79
  80 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  81 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
  82
  83 #ifdef TARGET_SPARC64
  84 #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
  85 #else
  86 #define DFPREG(r) (r)
  87 #endif
  88
  89 #ifdef USE_DIRECT_JUMP
  90 #define TBPARAM(x)
  91 #else
  92 #define TBPARAM(x) (long)(x)
  93 #endif
  94
  95 static int sign_extend(int x, int len)
  96 {
  97     len = 32 - len;
  98     return (x << len) >> len;
  99 }
 100
 101 #define IS_IMM (insn & (1<<13))
 102
 103 static void disas_sparc_insn(DisasContext * dc);
 104
 105 static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
 106     {
 107      gen_op_movl_g0_T0,
 108      gen_op_movl_g1_T0,
 109      gen_op_movl_g2_T0,
 110      gen_op_movl_g3_T0,
 111      gen_op_movl_g4_T0,
 112      gen_op_movl_g5_T0,
 113      gen_op_movl_g6_T0,
 114      gen_op_movl_g7_T0,
 115      gen_op_movl_o0_T0,
 116      gen_op_movl_o1_T0,
 117      gen_op_movl_o2_T0,
 118      gen_op_movl_o3_T0,
 119      gen_op_movl_o4_T0,
 120      gen_op_movl_o5_T0,
 121      gen_op_movl_o6_T0,
 122      gen_op_movl_o7_T0,
 123      gen_op_movl_l0_T0,
 124      gen_op_movl_l1_T0,
 125      gen_op_movl_l2_T0,
 126      gen_op_movl_l3_T0,
 127      gen_op_movl_l4_T0,
 128      gen_op_movl_l5_T0,
 129      gen_op_movl_l6_T0,
 130      gen_op_movl_l7_T0,
 131      gen_op_movl_i0_T0,
 132      gen_op_movl_i1_T0,
 133      gen_op_movl_i2_T0,
 134      gen_op_movl_i3_T0,
 135      gen_op_movl_i4_T0,
 136      gen_op_movl_i5_T0,
 137      gen_op_movl_i6_T0,
 138      gen_op_movl_i7_T0,
 139      },
 140     {
 141      gen_op_movl_g0_T1,
 142      gen_op_movl_g1_T1,
 143      gen_op_movl_g2_T1,
 144      gen_op_movl_g3_T1,
 145      gen_op_movl_g4_T1,
 146      gen_op_movl_g5_T1,
 147      gen_op_movl_g6_T1,
 148      gen_op_movl_g7_T1,
 149      gen_op_movl_o0_T1,
 150      gen_op_movl_o1_T1,
 151      gen_op_movl_o2_T1,
 152      gen_op_movl_o3_T1,
 153      gen_op_movl_o4_T1,
 154      gen_op_movl_o5_T1,
 155      gen_op_movl_o6_T1,
 156      gen_op_movl_o7_T1,
 157      gen_op_movl_l0_T1,
 158      gen_op_movl_l1_T1,
 159      gen_op_movl_l2_T1,
 160      gen_op_movl_l3_T1,
 161      gen_op_movl_l4_T1,
 162      gen_op_movl_l5_T1,
 163      gen_op_movl_l6_T1,
 164      gen_op_movl_l7_T1,
 165      gen_op_movl_i0_T1,
 166      gen_op_movl_i1_T1,
 167      gen_op_movl_i2_T1,
 168      gen_op_movl_i3_T1,
 169      gen_op_movl_i4_T1,
 170      gen_op_movl_i5_T1,
 171      gen_op_movl_i6_T1,
 172      gen_op_movl_i7_T1,
 173      }
 174 };
 175
 176 static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
 177     {
 178      gen_op_movl_T0_g0,
 179      gen_op_movl_T0_g1,
 180      gen_op_movl_T0_g2,
 181      gen_op_movl_T0_g3,
 182      gen_op_movl_T0_g4,
 183      gen_op_movl_T0_g5,
 184      gen_op_movl_T0_g6,
 185      gen_op_movl_T0_g7,
 186      gen_op_movl_T0_o0,
 187      gen_op_movl_T0_o1,
 188      gen_op_movl_T0_o2,
 189      gen_op_movl_T0_o3,
 190      gen_op_movl_T0_o4,
 191      gen_op_movl_T0_o5,
 192      gen_op_movl_T0_o6,
 193      gen_op_movl_T0_o7,
 194      gen_op_movl_T0_l0,
 195      gen_op_movl_T0_l1,
 196      gen_op_movl_T0_l2,
 197      gen_op_movl_T0_l3,
 198      gen_op_movl_T0_l4,
 199      gen_op_movl_T0_l5,
 200      gen_op_movl_T0_l6,
 201      gen_op_movl_T0_l7,
 202      gen_op_movl_T0_i0,
 203      gen_op_movl_T0_i1,
 204      gen_op_movl_T0_i2,
 205      gen_op_movl_T0_i3,
 206      gen_op_movl_T0_i4,
 207      gen_op_movl_T0_i5,
 208      gen_op_movl_T0_i6,
 209      gen_op_movl_T0_i7,
 210      },
 211     {
 212      gen_op_movl_T1_g0,
 213      gen_op_movl_T1_g1,
 214      gen_op_movl_T1_g2,
 215      gen_op_movl_T1_g3,
 216      gen_op_movl_T1_g4,
 217      gen_op_movl_T1_g5,
 218      gen_op_movl_T1_g6,
 219      gen_op_movl_T1_g7,
 220      gen_op_movl_T1_o0,
 221      gen_op_movl_T1_o1,
 222      gen_op_movl_T1_o2,
 223      gen_op_movl_T1_o3,
 224      gen_op_movl_T1_o4,
 225      gen_op_movl_T1_o5,
 226      gen_op_movl_T1_o6,
 227      gen_op_movl_T1_o7,
 228      gen_op_movl_T1_l0,
 229      gen_op_movl_T1_l1,
 230      gen_op_movl_T1_l2,
 231      gen_op_movl_T1_l3,
 232      gen_op_movl_T1_l4,
 233      gen_op_movl_T1_l5,
 234      gen_op_movl_T1_l6,
 235      gen_op_movl_T1_l7,
 236      gen_op_movl_T1_i0,
 237      gen_op_movl_T1_i1,
 238      gen_op_movl_T1_i2,
 239      gen_op_movl_T1_i3,
 240      gen_op_movl_T1_i4,
 241      gen_op_movl_T1_i5,
 242      gen_op_movl_T1_i6,
 243      gen_op_movl_T1_i7,
 244      },
 245     {
 246      gen_op_movl_T2_g0,
 247      gen_op_movl_T2_g1,
 248      gen_op_movl_T2_g2,
 249      gen_op_movl_T2_g3,
 250      gen_op_movl_T2_g4,
 251      gen_op_movl_T2_g5,
 252      gen_op_movl_T2_g6,
 253      gen_op_movl_T2_g7,
 254      gen_op_movl_T2_o0,
 255      gen_op_movl_T2_o1,
 256      gen_op_movl_T2_o2,
 257      gen_op_movl_T2_o3,
 258      gen_op_movl_T2_o4,
 259      gen_op_movl_T2_o5,
 260      gen_op_movl_T2_o6,
 261      gen_op_movl_T2_o7,
 262      gen_op_movl_T2_l0,
 263      gen_op_movl_T2_l1,
 264      gen_op_movl_T2_l2,
 265      gen_op_movl_T2_l3,
 266      gen_op_movl_T2_l4,
 267      gen_op_movl_T2_l5,
 268      gen_op_movl_T2_l6,
 269      gen_op_movl_T2_l7,
 270      gen_op_movl_T2_i0,
 271      gen_op_movl_T2_i1,
 272      gen_op_movl_T2_i2,
 273      gen_op_movl_T2_i3,
 274      gen_op_movl_T2_i4,
 275      gen_op_movl_T2_i5,
 276      gen_op_movl_T2_i6,
 277      gen_op_movl_T2_i7,
 278      }
 279 };
 280
 281 static GenOpFunc1 *gen_op_movl_TN_im[3] = {
 282     gen_op_movl_T0_im,
 283     gen_op_movl_T1_im,
 284     gen_op_movl_T2_im
 285 };
 286
 287 // Sign extending version
 288 static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
 289     gen_op_movl_T0_sim,
 290     gen_op_movl_T1_sim,
 291     gen_op_movl_T2_sim
 292 };
 293
 294 #ifdef TARGET_SPARC64
 295 #define GEN32(func, NAME) \
 296 static GenOpFunc *NAME ## _table [64] = {                                     \
 297 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 298 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 299 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 300 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 301 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 302 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 303 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 304 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 305 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
 306 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
 307 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
 308 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
 309 };                                                                            \
 310 static inline void func(int n)                                                \
 311 {                                                                             \
 312     NAME ## _table[n]();                                                      \
 313 }
 314 #else
 315 #define GEN32(func, NAME) \
 316 static GenOpFunc *NAME ## _table [32] = {                                     \
 317 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 318 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 319 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 320 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 321 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 322 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 323 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 324 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 325 };                                                                            \
 326 static inline void func(int n)                                                \
 327 {                                                                             \
 328     NAME ## _table[n]();                                                      \
 329 }
 330 #endif
 331
 332 /* floating point registers moves */
 333 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
 334 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
 335 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
 336 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
 337
 338 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
 339 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
 340 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
 341 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 342
 343 #ifdef TARGET_SPARC64
 344 // 'a' versions allowed to user depending on asi
 345 #if defined(CONFIG_USER_ONLY)
 346 #define supervisor(dc) 0
 347 #define gen_op_ldst(name)        gen_op_##name##_raw()
 348 #define OP_LD_TABLE(width)                                              \
 349     static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
 350     {                                                                   \
 351         int asi, offset;                                                \
 352                                                                         \
 353         if (IS_IMM) {                                                   \
 354             offset = GET_FIELD(insn, 25, 31);                           \
 355             if (is_ld)                                                  \
 356                 gen_op_ld_asi_reg(offset, size, sign);                  \
 357             else                                                        \
 358                 gen_op_st_asi_reg(offset, size, sign);                  \
 359             return;                                                     \
 360         }                                                               \
 361         asi = GET_FIELD(insn, 19, 26);                                  \
 362         switch (asi) {                                                  \
 363         case 0x80: /* Primary address space */                          \
 364             gen_op_##width##_raw();                                     \
 365             break;                                                      \
 366         default:                                                        \
 367             break;                                                      \
 368         }                                                               \
 369     }
 370
 371 #else
 372 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 373 #define OP_LD_TABLE(width)                                              \
 374     static GenOpFunc *gen_op_##width[] = {                              \
 375         &gen_op_##width##_user,                                         \
 376         &gen_op_##width##_kernel,                                       \
 377     };                                                                  \
 378                                                                         \
 379     static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
 380     {                                                                   \
 381         int asi, offset;                                                \
 382                                                                         \
 383         if (IS_IMM) {                                                   \
 384             offset = GET_FIELD(insn, 25, 31);                           \
 385             if (is_ld)                                                  \
 386                 gen_op_ld_asi_reg(offset, size, sign);                  \
 387             else                                                        \
 388                 gen_op_st_asi_reg(offset, size, sign);                  \
 389             return;                                                     \
 390         }                                                               \
 391         asi = GET_FIELD(insn, 19, 26);                                  \
 392         if (is_ld)                                                      \
 393             gen_op_ld_asi(asi, size, sign);                             \
 394         else                                                            \
 395             gen_op_st_asi(asi, size, sign);                             \
 396     }
 397
 398 #define supervisor(dc) (dc->mem_idx == 1)
 399 #endif
 400 #else
 401 #if defined(CONFIG_USER_ONLY)
 402 #define gen_op_ldst(name)        gen_op_##name##_raw()
 403 #define OP_LD_TABLE(width)
 404 #define supervisor(dc) 0
 405 #else
 406 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 407 #define OP_LD_TABLE(width)                                                    \
 408 static GenOpFunc *gen_op_##width[] = {                                        \
 409     &gen_op_##width##_user,                                                   \
 410     &gen_op_##width##_kernel,                                                 \
 411 };                                                                            \
 412                                                                               \
 413 static void gen_op_##width##a(int insn, int is_ld, int size, int sign)        \
 414 {                                                                             \
 415     int asi;                                                                  \
 416                                                                               \
 417     asi = GET_FIELD(insn, 19, 26);                                            \
 418     switch (asi) {                                                            \
 419         case 10: /* User data access */                                       \
 420             gen_op_##width##_user();                                          \
 421             break;                                                            \
 422         case 11: /* Supervisor data access */                                 \
 423             gen_op_##width##_kernel();                                        \
 424             break;                                                            \
 425         case 0x20 ... 0x2f: /* MMU passthrough */                             \
 426             if (is_ld)                                                        \
 427                 gen_op_ld_asi(asi, size, sign);                               \
 428             else                                                              \
 429                 gen_op_st_asi(asi, size, sign);                               \
 430             break;                                                            \
 431         default:                                                              \
 432             if (is_ld)                                                        \
 433                 gen_op_ld_asi(asi, size, sign);                               \
 434             else                                                              \
 435                 gen_op_st_asi(asi, size, sign);                               \
 436             break;                                                            \
 437     }                                                                         \
 438 }
 439
 440 #define supervisor(dc) (dc->mem_idx == 1)
 441 #endif
 442 #endif
 443
 444 OP_LD_TABLE(ld);
 445 OP_LD_TABLE(st);
 446 OP_LD_TABLE(ldub);
 447 OP_LD_TABLE(lduh);
 448 OP_LD_TABLE(ldsb);
 449 OP_LD_TABLE(ldsh);
 450 OP_LD_TABLE(stb);
 451 OP_LD_TABLE(sth);
 452 OP_LD_TABLE(std);
 453 OP_LD_TABLE(ldstub);
 454 OP_LD_TABLE(swap);
 455 OP_LD_TABLE(ldd);
 456 OP_LD_TABLE(stf);
 457 OP_LD_TABLE(stdf);
 458 OP_LD_TABLE(ldf);
 459 OP_LD_TABLE(lddf);
 460
 461 #ifdef TARGET_SPARC64
 462 OP_LD_TABLE(ldsw);
 463 OP_LD_TABLE(ldx);
 464 OP_LD_TABLE(stx);
 465 OP_LD_TABLE(cas);
 466 OP_LD_TABLE(casx);
 467 #endif
 468
 469 static inline void gen_movl_imm_TN(int reg, uint32_t imm)
 470 {
 471     gen_op_movl_TN_im[reg](imm);
 472 }
 473
 474 static inline void gen_movl_imm_T1(uint32_t val)
 475 {
 476     gen_movl_imm_TN(1, val);
 477 }
 478
 479 static inline void gen_movl_imm_T0(uint32_t val)
 480 {
 481     gen_movl_imm_TN(0, val);
 482 }
 483
 484 static inline void gen_movl_simm_TN(int reg, int32_t imm)
 485 {
 486     gen_op_movl_TN_sim[reg](imm);
 487 }
 488
 489 static inline void gen_movl_simm_T1(int32_t val)
 490 {
 491     gen_movl_simm_TN(1, val);
 492 }
 493
 494 static inline void gen_movl_simm_T0(int32_t val)
 495 {
 496     gen_movl_simm_TN(0, val);
 497 }
 498
 499 static inline void gen_movl_reg_TN(int reg, int t)
 500 {
 501     if (reg)
 502         gen_op_movl_reg_TN[t][reg] ();
 503     else
 504         gen_movl_imm_TN(t, 0);
 505 }
 506
 507 static inline void gen_movl_reg_T0(int reg)
 508 {
 509     gen_movl_reg_TN(reg, 0);
 510 }
 511
 512 static inline void gen_movl_reg_T1(int reg)
 513 {
 514     gen_movl_reg_TN(reg, 1);
 515 }
 516
 517 static inline void gen_movl_reg_T2(int reg)
 518 {
 519     gen_movl_reg_TN(reg, 2);
 520 }
 521
 522 static inline void gen_movl_TN_reg(int reg, int t)
 523 {
 524     if (reg)
 525         gen_op_movl_TN_reg[t][reg] ();
 526 }
 527
 528 static inline void gen_movl_T0_reg(int reg)
 529 {
 530     gen_movl_TN_reg(reg, 0);
 531 }
 532
 533 static inline void gen_movl_T1_reg(int reg)
 534 {
 535     gen_movl_TN_reg(reg, 1);
 536 }
 537
 538 static inline void gen_jmp_im(target_ulong pc)
 539 {
 540 #ifdef TARGET_SPARC64
 541     if (pc == (uint32_t)pc) {
 542         gen_op_jmp_im(pc);
 543     } else {
 544         gen_op_jmp_im64(pc >> 32, pc);
 545     }
 546 #else
 547     gen_op_jmp_im(pc);
 548 #endif
 549 }
 550
 551 static inline void gen_movl_npc_im(target_ulong npc)
 552 {
 553 #ifdef TARGET_SPARC64
 554     if (npc == (uint32_t)npc) {
 555         gen_op_movl_npc_im(npc);
 556     } else {
 557         gen_op_movq_npc_im64(npc >> 32, npc);
 558     }
 559 #else
 560     gen_op_movl_npc_im(npc);
 561 #endif
 562 }
 563
 564 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 565                                target_ulong pc, target_ulong npc)
 566 {
 567     TranslationBlock *tb;
 568
 569     tb = s->tb;
 570     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 571         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 572         /* jump to same page: we can use a direct jump */
 573         if (tb_num == 0)
 574             gen_op_goto_tb0(TBPARAM(tb));
 575         else
 576             gen_op_goto_tb1(TBPARAM(tb));
 577         gen_jmp_im(pc);
 578         gen_movl_npc_im(npc);
 579         gen_op_movl_T0_im((long)tb + tb_num);
 580         gen_op_exit_tb();
 581     } else {
 582         /* jump to another page: currently not optimized */
 583         gen_jmp_im(pc);
 584         gen_movl_npc_im(npc);
 585         gen_op_movl_T0_0();
 586         gen_op_exit_tb();
 587     }
 588 }
 589
 590 static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
 591 {
 592     int l1;
 593
 594     l1 = gen_new_label();
 595
 596     gen_op_jz_T2_label(l1);
 597
 598     gen_goto_tb(dc, 0, pc1, pc1 + 4);
 599
 600     gen_set_label(l1);
 601     gen_goto_tb(dc, 1, pc2, pc2 + 4);
 602 }
 603
 604 static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
 605 {
 606     int l1;
 607
 608     l1 = gen_new_label();
 609
 610     gen_op_jz_T2_label(l1);
 611
 612     gen_goto_tb(dc, 0, pc2, pc1);
 613
 614     gen_set_label(l1);
 615     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
 616 }
 617
 618 static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
 619 {
 620     gen_goto_tb(dc, 0, pc, npc);
 621 }
 622
 623 static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
 624 {
 625     int l1, l2;
 626
 627     l1 = gen_new_label();
 628     l2 = gen_new_label();
 629     gen_op_jz_T2_label(l1);
 630
 631     gen_movl_npc_im(npc1);
 632     gen_op_jmp_label(l2);
 633
 634     gen_set_label(l1);
 635     gen_movl_npc_im(npc2);
 636     gen_set_label(l2);
 637 }
 638
 639 /* call this function before using T2 as it may have been set for a jump */
 640 static inline void flush_T2(DisasContext * dc)
 641 {
 642     if (dc->npc == JUMP_PC) {
 643         gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
 644         dc->npc = DYNAMIC_PC;
 645     }
 646 }
 647
 648 static inline void save_npc(DisasContext * dc)
 649 {
 650     if (dc->npc == JUMP_PC) {
 651         gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
 652         dc->npc = DYNAMIC_PC;
 653     } else if (dc->npc != DYNAMIC_PC) {
 654         gen_movl_npc_im(dc->npc);
 655     }
 656 }
 657
 658 static inline void save_state(DisasContext * dc)
 659 {
 660     gen_jmp_im(dc->pc);
 661     save_npc(dc);
 662 }
 663
 664 static inline void gen_mov_pc_npc(DisasContext * dc)
 665 {
 666     if (dc->npc == JUMP_PC) {
 667         gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
 668         gen_op_mov_pc_npc();
 669         dc->pc = DYNAMIC_PC;
 670     } else if (dc->npc == DYNAMIC_PC) {
 671         gen_op_mov_pc_npc();
 672         dc->pc = DYNAMIC_PC;
 673     } else {
 674         dc->pc = dc->npc;
 675     }
 676 }
 677
 678 static GenOpFunc * const gen_cond[2][16] = {
 679     {
 680         gen_op_eval_ba,
 681         gen_op_eval_be,
 682         gen_op_eval_ble,
 683         gen_op_eval_bl,
 684         gen_op_eval_bleu,
 685         gen_op_eval_bcs,
 686         gen_op_eval_bneg,
 687         gen_op_eval_bvs,
 688         gen_op_eval_bn,
 689         gen_op_eval_bne,
 690         gen_op_eval_bg,
 691         gen_op_eval_bge,
 692         gen_op_eval_bgu,
 693         gen_op_eval_bcc,
 694         gen_op_eval_bpos,
 695         gen_op_eval_bvc,
 696     },
 697     {
 698 #ifdef TARGET_SPARC64
 699         gen_op_eval_ba,
 700         gen_op_eval_xbe,
 701         gen_op_eval_xble,
 702         gen_op_eval_xbl,
 703         gen_op_eval_xbleu,
 704         gen_op_eval_xbcs,
 705         gen_op_eval_xbneg,
 706         gen_op_eval_xbvs,
 707         gen_op_eval_bn,
 708         gen_op_eval_xbne,
 709         gen_op_eval_xbg,
 710         gen_op_eval_xbge,
 711         gen_op_eval_xbgu,
 712         gen_op_eval_xbcc,
 713         gen_op_eval_xbpos,
 714         gen_op_eval_xbvc,
 715 #endif
 716     },
 717 };
 718
 719 static GenOpFunc * const gen_fcond[4][16] = {
 720     {
 721         gen_op_eval_ba,
 722         gen_op_eval_fbne,
 723         gen_op_eval_fblg,
 724         gen_op_eval_fbul,
 725         gen_op_eval_fbl,
 726         gen_op_eval_fbug,
 727         gen_op_eval_fbg,
 728         gen_op_eval_fbu,
 729         gen_op_eval_bn,
 730         gen_op_eval_fbe,
 731         gen_op_eval_fbue,
 732         gen_op_eval_fbge,
 733         gen_op_eval_fbuge,
 734         gen_op_eval_fble,
 735         gen_op_eval_fbule,
 736         gen_op_eval_fbo,
 737     },
 738 #ifdef TARGET_SPARC64
 739     {
 740         gen_op_eval_ba,
 741         gen_op_eval_fbne_fcc1,
 742         gen_op_eval_fblg_fcc1,
 743         gen_op_eval_fbul_fcc1,
 744         gen_op_eval_fbl_fcc1,
 745         gen_op_eval_fbug_fcc1,
 746         gen_op_eval_fbg_fcc1,
 747         gen_op_eval_fbu_fcc1,
 748         gen_op_eval_bn,
 749         gen_op_eval_fbe_fcc1,
 750         gen_op_eval_fbue_fcc1,
 751         gen_op_eval_fbge_fcc1,
 752         gen_op_eval_fbuge_fcc1,
 753         gen_op_eval_fble_fcc1,
 754         gen_op_eval_fbule_fcc1,
 755         gen_op_eval_fbo_fcc1,
 756     },
 757     {
 758         gen_op_eval_ba,
 759         gen_op_eval_fbne_fcc2,
 760         gen_op_eval_fblg_fcc2,
 761         gen_op_eval_fbul_fcc2,
 762         gen_op_eval_fbl_fcc2,
 763         gen_op_eval_fbug_fcc2,
 764         gen_op_eval_fbg_fcc2,
 765         gen_op_eval_fbu_fcc2,
 766         gen_op_eval_bn,
 767         gen_op_eval_fbe_fcc2,
 768         gen_op_eval_fbue_fcc2,
 769         gen_op_eval_fbge_fcc2,
 770         gen_op_eval_fbuge_fcc2,
 771         gen_op_eval_fble_fcc2,
 772         gen_op_eval_fbule_fcc2,
 773         gen_op_eval_fbo_fcc2,
 774     },
 775     {
 776         gen_op_eval_ba,
 777         gen_op_eval_fbne_fcc3,
 778         gen_op_eval_fblg_fcc3,
 779         gen_op_eval_fbul_fcc3,
 780         gen_op_eval_fbl_fcc3,
 781         gen_op_eval_fbug_fcc3,
 782         gen_op_eval_fbg_fcc3,
 783         gen_op_eval_fbu_fcc3,
 784         gen_op_eval_bn,
 785         gen_op_eval_fbe_fcc3,
 786         gen_op_eval_fbue_fcc3,
 787         gen_op_eval_fbge_fcc3,
 788         gen_op_eval_fbuge_fcc3,
 789         gen_op_eval_fble_fcc3,
 790         gen_op_eval_fbule_fcc3,
 791         gen_op_eval_fbo_fcc3,
 792     },
 793 #else
 794     {}, {}, {},
 795 #endif
 796 };
 797
 798 #ifdef TARGET_SPARC64
 799 static void gen_cond_reg(int cond)
 800 {
 801         switch (cond) {
 802         case 0x1:
 803             gen_op_eval_brz();
 804             break;
 805         case 0x2:
 806             gen_op_eval_brlez();
 807             break;
 808         case 0x3:
 809             gen_op_eval_brlz();
 810             break;
 811         case 0x5:
 812             gen_op_eval_brnz();
 813             break;
 814         case 0x6:
 815             gen_op_eval_brgz();
 816             break;
 817         default:
 818         case 0x7:
 819             gen_op_eval_brgez();
 820             break;
 821         }
 822 }
 823 #endif
 824
 825 /* XXX: potentially incorrect if dynamic npc */
 826 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
 827 {
 828     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 829     target_ulong target = dc->pc + offset;
 830
 831     if (cond == 0x0) {
 832         /* unconditional not taken */
 833         if (a) {
 834             dc->pc = dc->npc + 4;
 835             dc->npc = dc->pc + 4;
 836         } else {
 837             dc->pc = dc->npc;
 838             dc->npc = dc->pc + 4;
 839         }
 840     } else if (cond == 0x8) {
 841         /* unconditional taken */
 842         if (a) {
 843             dc->pc = target;
 844             dc->npc = dc->pc + 4;
 845         } else {
 846             dc->pc = dc->npc;
 847             dc->npc = target;
 848         }
 849     } else {
 850         flush_T2(dc);
 851         gen_cond[cc][cond]();
 852         if (a) {
 853             gen_branch_a(dc, (long)dc->tb, target, dc->npc);
 854             dc->is_br = 1;
 855         } else {
 856             dc->pc = dc->npc;
 857             dc->jump_pc[0] = target;
 858             dc->jump_pc[1] = dc->npc + 4;
 859             dc->npc = JUMP_PC;
 860         }
 861     }
 862 }
 863
 864 /* XXX: potentially incorrect if dynamic npc */
 865 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
 866 {
 867     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 868     target_ulong target = dc->pc + offset;
 869
 870     if (cond == 0x0) {
 871         /* unconditional not taken */
 872         if (a) {
 873             dc->pc = dc->npc + 4;
 874             dc->npc = dc->pc + 4;
 875         } else {
 876             dc->pc = dc->npc;
 877             dc->npc = dc->pc + 4;
 878         }
 879     } else if (cond == 0x8) {
 880         /* unconditional taken */
 881         if (a) {
 882             dc->pc = target;
 883             dc->npc = dc->pc + 4;
 884         } else {
 885             dc->pc = dc->npc;
 886             dc->npc = target;
 887         }
 888     } else {
 889         flush_T2(dc);
 890         gen_fcond[cc][cond]();
 891         if (a) {
 892             gen_branch_a(dc, (long)dc->tb, target, dc->npc);
 893             dc->is_br = 1;
 894         } else {
 895             dc->pc = dc->npc;
 896             dc->jump_pc[0] = target;
 897             dc->jump_pc[1] = dc->npc + 4;
 898             dc->npc = JUMP_PC;
 899         }
 900     }
 901 }
 902
 903 #ifdef TARGET_SPARC64
 904 /* XXX: potentially incorrect if dynamic npc */
 905 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
 906 {
 907     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
 908     target_ulong target = dc->pc + offset;
 909
 910     flush_T2(dc);
 911     gen_cond_reg(cond);
 912     if (a) {
 913         gen_branch_a(dc, (long)dc->tb, target, dc->npc);
 914         dc->is_br = 1;
 915     } else {
 916         dc->pc = dc->npc;
 917         dc->jump_pc[0] = target;
 918         dc->jump_pc[1] = dc->npc + 4;
 919         dc->npc = JUMP_PC;
 920     }
 921 }
 922
 923 static GenOpFunc * const gen_fcmps[4] = {
 924     gen_op_fcmps,
 925     gen_op_fcmps_fcc1,
 926     gen_op_fcmps_fcc2,
 927     gen_op_fcmps_fcc3,
 928 };
 929
 930 static GenOpFunc * const gen_fcmpd[4] = {
 931     gen_op_fcmpd,
 932     gen_op_fcmpd_fcc1,
 933     gen_op_fcmpd_fcc2,
 934     gen_op_fcmpd_fcc3,
 935 };
 936 #endif
 937
 938 /* before an instruction, dc->pc must be static */
 939 static void disas_sparc_insn(DisasContext * dc)
 940 {
 941     unsigned int insn, opc, rs1, rs2, rd;
 942
 943     insn = ldl_code(dc->pc);
 944     opc = GET_FIELD(insn, 0, 1);
 945
 946     rd = GET_FIELD(insn, 2, 6);
 947     switch (opc) {
 948     case 0:                     /* branches/sethi */
 949         {
 950             unsigned int xop = GET_FIELD(insn, 7, 9);
 951             int32_t target;
 952             switch (xop) {
 953 #ifdef TARGET_SPARC64
 954             case 0x1:           /* V9 BPcc */
 955                 {
 956                     int cc;
 957
 958                     target = GET_FIELD_SP(insn, 0, 18);
 959                     target <<= 2;
 960                     target = sign_extend(target, 18);
 961                     cc = GET_FIELD_SP(insn, 20, 21);
 962                     if (cc == 0)
 963                         do_branch(dc, target, insn, 0);
 964                     else if (cc == 2)
 965                         do_branch(dc, target, insn, 1);
 966                     else
 967                         goto illegal_insn;
 968                     goto jmp_insn;
 969                 }
 970             case 0x3:           /* V9 BPr */
 971                 {
 972                     target = GET_FIELD_SP(insn, 0, 13) |
 973                         (GET_FIELD_SP(insn, 20, 21) >> 7);
 974                     target <<= 2;
 975                     target = sign_extend(target, 16);
 976                     rs1 = GET_FIELD(insn, 13, 17);
 977                     gen_movl_reg_T0(rs1);
 978                     do_branch_reg(dc, target, insn);
 979                     goto jmp_insn;
 980                 }
 981             case 0x5:           /* V9 FBPcc */
 982                 {
 983                     int cc = GET_FIELD_SP(insn, 20, 21);
 984 #if !defined(CONFIG_USER_ONLY)
 985                     gen_op_trap_ifnofpu();
 986 #endif
 987                     target = GET_FIELD_SP(insn, 0, 18);
 988                     target <<= 2;
 989                     target = sign_extend(target, 19);
 990                     do_fbranch(dc, target, insn, cc);
 991                     goto jmp_insn;
 992                 }
 993 #endif
 994             case 0x2:           /* BN+x */
 995                 {
 996                     target = GET_FIELD(insn, 10, 31);
 997                     target <<= 2;
 998                     target = sign_extend(target, 22);
 999                     do_branch(dc, target, insn, 0);
1000                     goto jmp_insn;
1001                 }
1002             case 0x6:           /* FBN+x */
1003                 {
1004 #if !defined(CONFIG_USER_ONLY)
1005                     gen_op_trap_ifnofpu();
1006 #endif
1007                     target = GET_FIELD(insn, 10, 31);
1008                     target <<= 2;
1009                     target = sign_extend(target, 22);
1010                     do_fbranch(dc, target, insn, 0);
1011                     goto jmp_insn;
1012                 }
1013             case 0x4:           /* SETHI */
1014 #define OPTIM
1015 #if defined(OPTIM)
1016                 if (rd) { // nop
1017 #endif
1018                     uint32_t value = GET_FIELD(insn, 10, 31);
1019                     gen_movl_imm_T0(value << 10);
1020                     gen_movl_T0_reg(rd);
1021 #if defined(OPTIM)
1022                 }
1023 #endif
1024                 break;
1025             case 0x0:           /* UNIMPL */
1026             default:
1027                 goto illegal_insn;
1028             }
1029             break;
1030         }
1031         break;
1032     case 1:
1033         /*CALL*/ {
1034             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1035
1036 #ifdef TARGET_SPARC64
1037             if (dc->pc == (uint32_t)dc->pc) {
1038                 gen_op_movl_T0_im(dc->pc);
1039             } else {
1040                 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1041             }
1042 #else
1043             gen_op_movl_T0_im(dc->pc);
1044 #endif
1045             gen_movl_T0_reg(15);
1046             target += dc->pc;
1047             gen_mov_pc_npc(dc);
1048             dc->npc = target;
1049         }
1050         goto jmp_insn;
1051     case 2:                     /* FPU & Logical Operations */
1052         {
1053             unsigned int xop = GET_FIELD(insn, 7, 12);
1054             if (xop == 0x3a) {  /* generate trap */
1055                 int cond;
1056
1057                 rs1 = GET_FIELD(insn, 13, 17);
1058                 gen_movl_reg_T0(rs1);
1059                 if (IS_IMM) {
1060                     rs2 = GET_FIELD(insn, 25, 31);
1061 #if defined(OPTIM)
1062                     if (rs2 != 0) {
1063 #endif
1064                         gen_movl_simm_T1(rs2);
1065                         gen_op_add_T1_T0();
1066 #if defined(OPTIM)
1067                     }
1068 #endif
1069                 } else {
1070                     rs2 = GET_FIELD(insn, 27, 31);
1071 #if defined(OPTIM)
1072                     if (rs2 != 0) {
1073 #endif
1074                         gen_movl_reg_T1(rs2);
1075                         gen_op_add_T1_T0();
1076 #if defined(OPTIM)
1077                     }
1078 #endif
1079                 }
1080                 save_state(dc);
1081                 cond = GET_FIELD(insn, 3, 6);
1082                 if (cond == 0x8) {
1083                     gen_op_trap_T0();
1084                     dc->is_br = 1;
1085                     goto jmp_insn;
1086                 } else if (cond != 0) {
1087 #ifdef TARGET_SPARC64
1088                     /* V9 icc/xcc */
1089                     int cc = GET_FIELD_SP(insn, 11, 12);
1090                     if (cc == 0)
1091                         gen_cond[0][cond]();
1092                     else if (cc == 2)
1093                         gen_cond[1][cond]();
1094                     else
1095                         goto illegal_insn;
1096 #else
1097                     gen_cond[0][cond]();
1098 #endif
1099                     gen_op_trapcc_T0();
1100                 }
1101             } else if (xop == 0x28) {
1102                 rs1 = GET_FIELD(insn, 13, 17);
1103                 switch(rs1) {
1104                 case 0: /* rdy */
1105                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1106                     gen_movl_T0_reg(rd);
1107                     break;
1108                 case 15: /* stbar / V9 membar */
1109                     break; /* no effect? */
1110 #ifdef TARGET_SPARC64
1111                 case 0x2: /* V9 rdccr */
1112                     gen_op_rdccr();
1113                     gen_movl_T0_reg(rd);
1114                     break;
1115                 case 0x3: /* V9 rdasi */
1116                     gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1117                     gen_movl_T0_reg(rd);
1118                     break;
1119                 case 0x4: /* V9 rdtick */
1120                     gen_op_rdtick();
1121                     gen_movl_T0_reg(rd);
1122                     break;
1123                 case 0x5: /* V9 rdpc */
1124                     gen_op_movl_T0_im(dc->pc);
1125                     gen_movl_T0_reg(rd);
1126                     break;
1127                 case 0x6: /* V9 rdfprs */
1128                     gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1129                     gen_movl_T0_reg(rd);
1130                     break;
1131                 case 0x17: /* Tick compare */
1132                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1133                     gen_movl_T0_reg(rd);
1134                     break;
1135                 case 0x18: /* System tick */
1136                     gen_op_rdtick(); // XXX
1137                     gen_movl_T0_reg(rd);
1138                     break;
1139                 case 0x19: /* System tick compare */
1140                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1141                     gen_movl_T0_reg(rd);
1142                     break;
1143                 case 0x10: /* Performance Control */
1144                 case 0x11: /* Performance Instrumentation Counter */
1145                 case 0x12: /* Dispatch Control */
1146                 case 0x13: /* Graphics Status */
1147                 case 0x14: /* Softint set, WO */
1148                 case 0x15: /* Softint clear, WO */
1149                 case 0x16: /* Softint write */
1150 #endif
1151                 default:
1152                     goto illegal_insn;
1153                 }
1154 #if !defined(CONFIG_USER_ONLY)
1155 #ifndef TARGET_SPARC64
1156             } else if (xop == 0x29) { /* rdpsr / V9 unimp */
1157                 if (!supervisor(dc))
1158                     goto priv_insn;
1159                 gen_op_rdpsr();
1160                 gen_movl_T0_reg(rd);
1161                 break;
1162 #endif
1163             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1164                 if (!supervisor(dc))
1165                     goto priv_insn;
1166 #ifdef TARGET_SPARC64
1167                 rs1 = GET_FIELD(insn, 13, 17);
1168                 switch (rs1) {
1169                 case 0: // tpc
1170                     gen_op_rdtpc();
1171                     break;
1172                 case 1: // tnpc
1173                     gen_op_rdtnpc();
1174                     break;
1175                 case 2: // tstate
1176                     gen_op_rdtstate();
1177                     break;
1178                 case 3: // tt
1179                     gen_op_rdtt();
1180                     break;
1181                 case 4: // tick
1182                     gen_op_rdtick();
1183                     break;
1184                 case 5: // tba
1185                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1186                     break;
1187                 case 6: // pstate
1188                     gen_op_rdpstate();
1189                     break;
1190                 case 7: // tl
1191                     gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1192                     break;
1193                 case 8: // pil
1194                     gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1195                     break;
1196                 case 9: // cwp
1197                     gen_op_rdcwp();
1198                     break;
1199                 case 10: // cansave
1200                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1201                     break;
1202                 case 11: // canrestore
1203                     gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1204                     break;
1205                 case 12: // cleanwin
1206                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1207                     break;
1208                 case 13: // otherwin
1209                     gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1210                     break;
1211                 case 14: // wstate
1212                     gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1213                     break;
1214                 case 31: // ver
1215                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1216                     break;
1217                 case 15: // fq
1218                 default:
1219                     goto illegal_insn;
1220                 }
1221 #else
1222                 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1223 #endif
1224                 gen_movl_T0_reg(rd);
1225                 break;
1226             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1227 #ifdef TARGET_SPARC64
1228                 gen_op_flushw();
1229 #else
1230                 if (!supervisor(dc))
1231                     goto priv_insn;
1232                 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1233                 gen_movl_T0_reg(rd);
1234 #endif
1235                 break;
1236 #endif
1237             } else if (xop == 0x34) {   /* FPU Operations */
1238 #if !defined(CONFIG_USER_ONLY)
1239                 gen_op_trap_ifnofpu();
1240 #endif
1241                 rs1 = GET_FIELD(insn, 13, 17);
1242                 rs2 = GET_FIELD(insn, 27, 31);
1243                 xop = GET_FIELD(insn, 18, 26);
1244                 switch (xop) {
1245                     case 0x1: /* fmovs */
1246                         gen_op_load_fpr_FT0(rs2);
1247                         gen_op_store_FT0_fpr(rd);
1248                         break;
1249                     case 0x5: /* fnegs */
1250                         gen_op_load_fpr_FT1(rs2);
1251                         gen_op_fnegs();
1252                         gen_op_store_FT0_fpr(rd);
1253                         break;
1254                     case 0x9: /* fabss */
1255                         gen_op_load_fpr_FT1(rs2);
1256                         gen_op_fabss();
1257                         gen_op_store_FT0_fpr(rd);
1258                         break;
1259                     case 0x29: /* fsqrts */
1260                         gen_op_load_fpr_FT1(rs2);
1261                         gen_op_fsqrts();
1262                         gen_op_store_FT0_fpr(rd);
1263                         break;
1264                     case 0x2a: /* fsqrtd */
1265                         gen_op_load_fpr_DT1(DFPREG(rs2));
1266                         gen_op_fsqrtd();
1267                         gen_op_store_DT0_fpr(DFPREG(rd));
1268                         break;
1269                     case 0x2b: /* fsqrtq */
1270                         goto nfpu_insn;
1271                     case 0x41:
1272                         gen_op_load_fpr_FT0(rs1);
1273                         gen_op_load_fpr_FT1(rs2);
1274                         gen_op_fadds();
1275                         gen_op_store_FT0_fpr(rd);
1276                         break;
1277                     case 0x42:
1278                         gen_op_load_fpr_DT0(DFPREG(rs1));
1279                         gen_op_load_fpr_DT1(DFPREG(rs2));
1280                         gen_op_faddd();
1281                         gen_op_store_DT0_fpr(DFPREG(rd));
1282                         break;
1283                     case 0x43: /* faddq */
1284                         goto nfpu_insn;
1285                     case 0x45:
1286                         gen_op_load_fpr_FT0(rs1);
1287                         gen_op_load_fpr_FT1(rs2);
1288                         gen_op_fsubs();
1289                         gen_op_store_FT0_fpr(rd);
1290                         break;
1291                     case 0x46:
1292                         gen_op_load_fpr_DT0(DFPREG(rs1));
1293                         gen_op_load_fpr_DT1(DFPREG(rs2));
1294                         gen_op_fsubd();
1295                         gen_op_store_DT0_fpr(DFPREG(rd));
1296                         break;
1297                     case 0x47: /* fsubq */
1298                         goto nfpu_insn;
1299                     case 0x49:
1300                         gen_op_load_fpr_FT0(rs1);
1301                         gen_op_load_fpr_FT1(rs2);
1302                         gen_op_fmuls();
1303                         gen_op_store_FT0_fpr(rd);
1304                         break;
1305                     case 0x4a:
1306                         gen_op_load_fpr_DT0(DFPREG(rs1));
1307                         gen_op_load_fpr_DT1(DFPREG(rs2));
1308                         gen_op_fmuld();
1309                         gen_op_store_DT0_fpr(rd);
1310                         break;
1311                     case 0x4b: /* fmulq */
1312                         goto nfpu_insn;
1313                     case 0x4d:
1314                         gen_op_load_fpr_FT0(rs1);
1315                         gen_op_load_fpr_FT1(rs2);
1316                         gen_op_fdivs();
1317                         gen_op_store_FT0_fpr(rd);
1318                         break;
1319                     case 0x4e:
1320                         gen_op_load_fpr_DT0(DFPREG(rs1));
1321                         gen_op_load_fpr_DT1(DFPREG(rs2));
1322                         gen_op_fdivd();
1323                         gen_op_store_DT0_fpr(DFPREG(rd));
1324                         break;
1325                     case 0x4f: /* fdivq */
1326                         goto nfpu_insn;
1327                     case 0x69:
1328                         gen_op_load_fpr_FT0(rs1);
1329                         gen_op_load_fpr_FT1(rs2);
1330                         gen_op_fsmuld();
1331                         gen_op_store_DT0_fpr(DFPREG(rd));
1332                         break;
1333                     case 0x6e: /* fdmulq */
1334                         goto nfpu_insn;
1335                     case 0xc4:
1336                         gen_op_load_fpr_FT1(rs2);
1337                         gen_op_fitos();
1338                         gen_op_store_FT0_fpr(rd);
1339                         break;
1340                     case 0xc6:
1341                         gen_op_load_fpr_DT1(DFPREG(rs2));
1342                         gen_op_fdtos();
1343                         gen_op_store_FT0_fpr(rd);
1344                         break;
1345                     case 0xc7: /* fqtos */
1346                         goto nfpu_insn;
1347                     case 0xc8:
1348                         gen_op_load_fpr_FT1(rs2);
1349                         gen_op_fitod();
1350                         gen_op_store_DT0_fpr(DFPREG(rd));
1351                         break;
1352                     case 0xc9:
1353                         gen_op_load_fpr_FT1(rs2);
1354                         gen_op_fstod();
1355                         gen_op_store_DT0_fpr(DFPREG(rd));
1356                         break;
1357                     case 0xcb: /* fqtod */
1358                         goto nfpu_insn;
1359                     case 0xcc: /* fitoq */
1360                         goto nfpu_insn;
1361                     case 0xcd: /* fstoq */
1362                         goto nfpu_insn;
1363                     case 0xce: /* fdtoq */
1364                         goto nfpu_insn;
1365                     case 0xd1:
1366                         gen_op_load_fpr_FT1(rs2);
1367                         gen_op_fstoi();
1368                         gen_op_store_FT0_fpr(rd);
1369                         break;
1370                     case 0xd2:
1371                         gen_op_load_fpr_DT1(rs2);
1372                         gen_op_fdtoi();
1373                         gen_op_store_FT0_fpr(rd);
1374                         break;
1375                     case 0xd3: /* fqtoi */
1376                         goto nfpu_insn;
1377 #ifdef TARGET_SPARC64
1378                     case 0x2: /* V9 fmovd */
1379                         gen_op_load_fpr_DT0(DFPREG(rs2));
1380                         gen_op_store_DT0_fpr(DFPREG(rd));
1381                         break;
1382                     case 0x6: /* V9 fnegd */
1383                         gen_op_load_fpr_DT1(DFPREG(rs2));
1384                         gen_op_fnegd();
1385                         gen_op_store_DT0_fpr(DFPREG(rd));
1386                         break;
1387                     case 0xa: /* V9 fabsd */
1388                         gen_op_load_fpr_DT1(DFPREG(rs2));
1389                         gen_op_fabsd();
1390                         gen_op_store_DT0_fpr(DFPREG(rd));
1391                         break;
1392                     case 0x81: /* V9 fstox */
1393                         gen_op_load_fpr_FT1(rs2);
1394                         gen_op_fstox();
1395                         gen_op_store_DT0_fpr(DFPREG(rd));
1396                         break;
1397                     case 0x82: /* V9 fdtox */
1398                         gen_op_load_fpr_DT1(DFPREG(rs2));
1399                         gen_op_fdtox();
1400                         gen_op_store_DT0_fpr(DFPREG(rd));
1401                         break;
1402                     case 0x84: /* V9 fxtos */
1403                         gen_op_load_fpr_DT1(DFPREG(rs2));
1404                         gen_op_fxtos();
1405                         gen_op_store_FT0_fpr(rd);
1406                         break;
1407                     case 0x88: /* V9 fxtod */
1408                         gen_op_load_fpr_DT1(DFPREG(rs2));
1409                         gen_op_fxtod();
1410                         gen_op_store_DT0_fpr(DFPREG(rd));
1411                         break;
1412                     case 0x3: /* V9 fmovq */
1413                     case 0x7: /* V9 fnegq */
1414                     case 0xb: /* V9 fabsq */
1415                     case 0x83: /* V9 fqtox */
1416                     case 0x8c: /* V9 fxtoq */
1417                         goto nfpu_insn;
1418 #endif
1419                     default:
1420                         goto illegal_insn;
1421                 }
1422             } else if (xop == 0x35) {   /* FPU Operations */
1423 #ifdef TARGET_SPARC64
1424                 int cond;
1425 #endif
1426 #if !defined(CONFIG_USER_ONLY)
1427                 gen_op_trap_ifnofpu();
1428 #endif
1429                 rs1 = GET_FIELD(insn, 13, 17);
1430                 rs2 = GET_FIELD(insn, 27, 31);
1431                 xop = GET_FIELD(insn, 18, 26);
1432 #ifdef TARGET_SPARC64
1433                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1434                     cond = GET_FIELD_SP(insn, 14, 17);
1435                     gen_op_load_fpr_FT0(rd);
1436                     gen_op_load_fpr_FT1(rs2);
1437                     rs1 = GET_FIELD(insn, 13, 17);
1438                     gen_movl_reg_T0(rs1);
1439                     flush_T2(dc);
1440                     gen_cond_reg(cond);
1441                     gen_op_fmovs_cc();
1442                     gen_op_store_FT0_fpr(rd);
1443                     break;
1444                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1445                     cond = GET_FIELD_SP(insn, 14, 17);
1446                     gen_op_load_fpr_DT0(rd);
1447                     gen_op_load_fpr_DT1(rs2);
1448                     flush_T2(dc);
1449                     rs1 = GET_FIELD(insn, 13, 17);
1450                     gen_movl_reg_T0(rs1);
1451                     gen_cond_reg(cond);
1452                     gen_op_fmovs_cc();
1453                     gen_op_store_DT0_fpr(rd);
1454                     break;
1455                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1456                     goto nfpu_insn;
1457                 }
1458 #endif
1459                 switch (xop) {
1460 #ifdef TARGET_SPARC64
1461                     case 0x001: /* V9 fmovscc %fcc0 */
1462                         cond = GET_FIELD_SP(insn, 14, 17);
1463                         gen_op_load_fpr_FT0(rd);
1464                         gen_op_load_fpr_FT1(rs2);
1465                         flush_T2(dc);
1466                         gen_fcond[0][cond]();
1467                         gen_op_fmovs_cc();
1468                         gen_op_store_FT0_fpr(rd);
1469                         break;
1470                     case 0x002: /* V9 fmovdcc %fcc0 */
1471                         cond = GET_FIELD_SP(insn, 14, 17);
1472                         gen_op_load_fpr_DT0(rd);
1473                         gen_op_load_fpr_DT1(rs2);
1474                         flush_T2(dc);
1475                         gen_fcond[0][cond]();
1476                         gen_op_fmovd_cc();
1477                         gen_op_store_DT0_fpr(rd);
1478                         break;
1479                     case 0x003: /* V9 fmovqcc %fcc0 */
1480                         goto nfpu_insn;
1481                     case 0x041: /* V9 fmovscc %fcc1 */
1482                         cond = GET_FIELD_SP(insn, 14, 17);
1483                         gen_op_load_fpr_FT0(rd);
1484                         gen_op_load_fpr_FT1(rs2);
1485                         flush_T2(dc);
1486                         gen_fcond[1][cond]();
1487                         gen_op_fmovs_cc();
1488                         gen_op_store_FT0_fpr(rd);
1489                         break;
1490                     case 0x042: /* V9 fmovdcc %fcc1 */
1491                         cond = GET_FIELD_SP(insn, 14, 17);
1492                         gen_op_load_fpr_DT0(rd);
1493                         gen_op_load_fpr_DT1(rs2);
1494                         flush_T2(dc);
1495                         gen_fcond[1][cond]();
1496                         gen_op_fmovd_cc();
1497                         gen_op_store_DT0_fpr(rd);
1498                         break;
1499                     case 0x043: /* V9 fmovqcc %fcc1 */
1500                         goto nfpu_insn;
1501                     case 0x081: /* V9 fmovscc %fcc2 */
1502                         cond = GET_FIELD_SP(insn, 14, 17);
1503                         gen_op_load_fpr_FT0(rd);
1504                         gen_op_load_fpr_FT1(rs2);
1505                         flush_T2(dc);
1506                         gen_fcond[2][cond]();
1507                         gen_op_fmovs_cc();
1508                         gen_op_store_FT0_fpr(rd);
1509                         break;
1510                     case 0x082: /* V9 fmovdcc %fcc2 */
1511                         cond = GET_FIELD_SP(insn, 14, 17);
1512                         gen_op_load_fpr_DT0(rd);
1513                         gen_op_load_fpr_DT1(rs2);
1514                         flush_T2(dc);
1515                         gen_fcond[2][cond]();
1516                         gen_op_fmovd_cc();
1517                         gen_op_store_DT0_fpr(rd);
1518                         break;
1519                     case 0x083: /* V9 fmovqcc %fcc2 */
1520                         goto nfpu_insn;
1521                     case 0x0c1: /* V9 fmovscc %fcc3 */
1522                         cond = GET_FIELD_SP(insn, 14, 17);
1523                         gen_op_load_fpr_FT0(rd);
1524                         gen_op_load_fpr_FT1(rs2);
1525                         flush_T2(dc);
1526                         gen_fcond[3][cond]();
1527                         gen_op_fmovs_cc();
1528                         gen_op_store_FT0_fpr(rd);
1529                         break;
1530                     case 0x0c2: /* V9 fmovdcc %fcc3 */
1531                         cond = GET_FIELD_SP(insn, 14, 17);
1532                         gen_op_load_fpr_DT0(rd);
1533                         gen_op_load_fpr_DT1(rs2);
1534                         flush_T2(dc);
1535                         gen_fcond[3][cond]();
1536                         gen_op_fmovd_cc();
1537                         gen_op_store_DT0_fpr(rd);
1538                         break;
1539                     case 0x0c3: /* V9 fmovqcc %fcc3 */
1540                         goto nfpu_insn;
1541                     case 0x101: /* V9 fmovscc %icc */
1542                         cond = GET_FIELD_SP(insn, 14, 17);
1543                         gen_op_load_fpr_FT0(rd);
1544                         gen_op_load_fpr_FT1(rs2);
1545                         flush_T2(dc);
1546                         gen_cond[0][cond]();
1547                         gen_op_fmovs_cc();
1548                         gen_op_store_FT0_fpr(rd);
1549                         break;
1550                     case 0x102: /* V9 fmovdcc %icc */
1551                         cond = GET_FIELD_SP(insn, 14, 17);
1552                         gen_op_load_fpr_DT0(rd);
1553                         gen_op_load_fpr_DT1(rs2);
1554                         flush_T2(dc);
1555                         gen_cond[0][cond]();
1556                         gen_op_fmovd_cc();
1557                         gen_op_store_DT0_fpr(rd);
1558                         break;
1559                     case 0x103: /* V9 fmovqcc %icc */
1560                         goto nfpu_insn;
1561                     case 0x181: /* V9 fmovscc %xcc */
1562                         cond = GET_FIELD_SP(insn, 14, 17);
1563                         gen_op_load_fpr_FT0(rd);
1564                         gen_op_load_fpr_FT1(rs2);
1565                         flush_T2(dc);
1566                         gen_cond[1][cond]();
1567                         gen_op_fmovs_cc();
1568                         gen_op_store_FT0_fpr(rd);
1569                         break;
1570                     case 0x182: /* V9 fmovdcc %xcc */
1571                         cond = GET_FIELD_SP(insn, 14, 17);
1572                         gen_op_load_fpr_DT0(rd);
1573                         gen_op_load_fpr_DT1(rs2);
1574                         flush_T2(dc);
1575                         gen_cond[1][cond]();
1576                         gen_op_fmovd_cc();
1577                         gen_op_store_DT0_fpr(rd);
1578                         break;
1579                     case 0x183: /* V9 fmovqcc %xcc */
1580                         goto nfpu_insn;
1581 #endif
1582                     case 0x51: /* V9 %fcc */
1583                         gen_op_load_fpr_FT0(rs1);
1584                         gen_op_load_fpr_FT1(rs2);
1585 #ifdef TARGET_SPARC64
1586                         gen_fcmps[rd & 3]();
1587 #else
1588                         gen_op_fcmps();
1589 #endif
1590                         break;
1591                     case 0x52: /* V9 %fcc */
1592                         gen_op_load_fpr_DT0(DFPREG(rs1));
1593                         gen_op_load_fpr_DT1(DFPREG(rs2));
1594 #ifdef TARGET_SPARC64
1595                         gen_fcmpd[rd & 3]();
1596 #else
1597                         gen_op_fcmpd();
1598 #endif
1599                         break;
1600                     case 0x53: /* fcmpq */
1601                         goto nfpu_insn;
1602                     case 0x55: /* fcmpes, V9 %fcc */
1603                         gen_op_load_fpr_FT0(rs1);
1604                         gen_op_load_fpr_FT1(rs2);
1605 #ifdef TARGET_SPARC64
1606                         gen_fcmps[rd & 3]();
1607 #else
1608                         gen_op_fcmps(); /* XXX should trap if qNaN or sNaN  */
1609 #endif
1610                         break;
1611                     case 0x56: /* fcmped, V9 %fcc */
1612                         gen_op_load_fpr_DT0(DFPREG(rs1));
1613                         gen_op_load_fpr_DT1(DFPREG(rs2));
1614 #ifdef TARGET_SPARC64
1615                         gen_fcmpd[rd & 3]();
1616 #else
1617                         gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN  */
1618 #endif
1619                         break;
1620                     case 0x57: /* fcmpeq */
1621                         goto nfpu_insn;
1622                     default:
1623                         goto illegal_insn;
1624                 }
1625 #if defined(OPTIM)
1626             } else if (xop == 0x2) {
1627                 // clr/mov shortcut
1628
1629                 rs1 = GET_FIELD(insn, 13, 17);
1630                 if (rs1 == 0) {
1631                     // or %g0, x, y -> mov T1, x; mov y, T1
1632                     if (IS_IMM) {       /* immediate */
1633                         rs2 = GET_FIELDs(insn, 19, 31);
1634                         gen_movl_simm_T1(rs2);
1635                     } else {            /* register */
1636                         rs2 = GET_FIELD(insn, 27, 31);
1637                         gen_movl_reg_T1(rs2);
1638                     }
1639                     gen_movl_T1_reg(rd);
1640                 } else {
1641                     gen_movl_reg_T0(rs1);
1642                     if (IS_IMM) {       /* immediate */
1643                         // or x, #0, y -> mov T1, x; mov y, T1
1644                         rs2 = GET_FIELDs(insn, 19, 31);
1645                         if (rs2 != 0) {
1646                             gen_movl_simm_T1(rs2);
1647                             gen_op_or_T1_T0();
1648                         }
1649                     } else {            /* register */
1650                         // or x, %g0, y -> mov T1, x; mov y, T1
1651                         rs2 = GET_FIELD(insn, 27, 31);
1652                         if (rs2 != 0) {
1653                             gen_movl_reg_T1(rs2);
1654                             gen_op_or_T1_T0();
1655                         }
1656                     }
1657                     gen_movl_T0_reg(rd);
1658                 }
1659 #endif
1660 #ifdef TARGET_SPARC64
1661             } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
1662                 rs1 = GET_FIELD(insn, 13, 17);
1663                 gen_movl_reg_T0(rs1);
1664                 if (IS_IMM) {   /* immediate */
1665                     rs2 = GET_FIELDs(insn, 20, 31);
1666                     gen_movl_simm_T1(rs2);
1667                 } else {                /* register */
1668                     rs2 = GET_FIELD(insn, 27, 31);
1669                     gen_movl_reg_T1(rs2);
1670                 }
1671                 gen_op_sll();
1672                 gen_movl_T0_reg(rd);
1673             } else if (xop == 0x26) { /* srl, V9 srlx */
1674                 rs1 = GET_FIELD(insn, 13, 17);
1675                 gen_movl_reg_T0(rs1);
1676                 if (IS_IMM) {   /* immediate */
1677                     rs2 = GET_FIELDs(insn, 20, 31);
1678                     gen_movl_simm_T1(rs2);
1679                 } else {                /* register */
1680                     rs2 = GET_FIELD(insn, 27, 31);
1681                     gen_movl_reg_T1(rs2);
1682                 }
1683                 if (insn & (1 << 12))
1684                     gen_op_srlx();
1685                 else
1686                     gen_op_srl();
1687                 gen_movl_T0_reg(rd);
1688             } else if (xop == 0x27) { /* sra, V9 srax */
1689                 rs1 = GET_FIELD(insn, 13, 17);
1690                 gen_movl_reg_T0(rs1);
1691                 if (IS_IMM) {   /* immediate */
1692                     rs2 = GET_FIELDs(insn, 20, 31);
1693                     gen_movl_simm_T1(rs2);
1694                 } else {                /* register */
1695                     rs2 = GET_FIELD(insn, 27, 31);
1696                     gen_movl_reg_T1(rs2);
1697                 }
1698                 if (insn & (1 << 12))
1699                     gen_op_srax();
1700                 else
1701                     gen_op_sra();
1702                 gen_movl_T0_reg(rd);
1703 #endif
1704             } else if (xop < 0x38) {
1705                 rs1 = GET_FIELD(insn, 13, 17);
1706                 gen_movl_reg_T0(rs1);
1707                 if (IS_IMM) {   /* immediate */
1708                     rs2 = GET_FIELDs(insn, 19, 31);
1709                     gen_movl_simm_T1(rs2);
1710                 } else {                /* register */
1711                     rs2 = GET_FIELD(insn, 27, 31);
1712                     gen_movl_reg_T1(rs2);
1713                 }
1714                 if (xop < 0x20) {
1715                     switch (xop & ~0x10) {
1716                     case 0x0:
1717                         if (xop & 0x10)
1718                             gen_op_add_T1_T0_cc();
1719                         else
1720                             gen_op_add_T1_T0();
1721                         break;
1722                     case 0x1:
1723                         gen_op_and_T1_T0();
1724                         if (xop & 0x10)
1725                             gen_op_logic_T0_cc();
1726                         break;
1727                     case 0x2:
1728                         gen_op_or_T1_T0();
1729                         if (xop & 0x10)
1730                             gen_op_logic_T0_cc();
1731                         break;
1732                     case 0x3:
1733                         gen_op_xor_T1_T0();
1734                         if (xop & 0x10)
1735                             gen_op_logic_T0_cc();
1736                         break;
1737                     case 0x4:
1738                         if (xop & 0x10)
1739                             gen_op_sub_T1_T0_cc();
1740                         else
1741                             gen_op_sub_T1_T0();
1742                         break;
1743                     case 0x5:
1744                         gen_op_andn_T1_T0();
1745                         if (xop & 0x10)
1746                             gen_op_logic_T0_cc();
1747                         break;
1748                     case 0x6:
1749                         gen_op_orn_T1_T0();
1750                         if (xop & 0x10)
1751                             gen_op_logic_T0_cc();
1752                         break;
1753                     case 0x7:
1754                         gen_op_xnor_T1_T0();
1755                         if (xop & 0x10)
1756                             gen_op_logic_T0_cc();
1757                         break;
1758                     case 0x8:
1759                         if (xop & 0x10)
1760                             gen_op_addx_T1_T0_cc();
1761                         else
1762                             gen_op_addx_T1_T0();
1763                         break;
1764                     case 0xa:
1765                         gen_op_umul_T1_T0();
1766                         if (xop & 0x10)
1767                             gen_op_logic_T0_cc();
1768                         break;
1769                     case 0xb:
1770                         gen_op_smul_T1_T0();
1771                         if (xop & 0x10)
1772                             gen_op_logic_T0_cc();
1773                         break;
1774                     case 0xc:
1775                         if (xop & 0x10)
1776                             gen_op_subx_T1_T0_cc();
1777                         else
1778                             gen_op_subx_T1_T0();
1779                         break;
1780                     case 0xe:
1781                         gen_op_udiv_T1_T0();
1782                         if (xop & 0x10)
1783                             gen_op_div_cc();
1784                         break;
1785                     case 0xf:
1786                         gen_op_sdiv_T1_T0();
1787                         if (xop & 0x10)
1788                             gen_op_div_cc();
1789                         break;
1790                     default:
1791                         goto illegal_insn;
1792                     }
1793                     gen_movl_T0_reg(rd);
1794                 } else {
1795                     switch (xop) {
1796 #ifdef TARGET_SPARC64
1797                     case 0x9: /* V9 mulx */
1798                         gen_op_mulx_T1_T0();
1799                         gen_movl_T0_reg(rd);
1800                         break;
1801                     case 0xd: /* V9 udivx */
1802                         gen_op_udivx_T1_T0();
1803                         gen_movl_T0_reg(rd);
1804                         break;
1805 #endif
1806                     case 0x20: /* taddcc */
1807                     case 0x21: /* tsubcc */
1808                     case 0x22: /* taddcctv */
1809                     case 0x23: /* tsubcctv */
1810                         goto illegal_insn;
1811                     case 0x24: /* mulscc */
1812                         gen_op_mulscc_T1_T0();
1813                         gen_movl_T0_reg(rd);
1814                         break;
1815 #ifndef TARGET_SPARC64
1816                     case 0x25:  /* sll */
1817                         gen_op_sll();
1818                         gen_movl_T0_reg(rd);
1819                         break;
1820                     case 0x26:  /* srl */
1821                         gen_op_srl();
1822                         gen_movl_T0_reg(rd);
1823                         break;
1824                     case 0x27:  /* sra */
1825                         gen_op_sra();
1826                         gen_movl_T0_reg(rd);
1827                         break;
1828 #endif
1829                     case 0x30:
1830                         {
1831                             switch(rd) {
1832                             case 0: /* wry */
1833                                 gen_op_xor_T1_T0();
1834                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
1835                                 break;
1836 #ifdef TARGET_SPARC64
1837                             case 0x2: /* V9 wrccr */
1838                                 gen_op_wrccr();
1839                                 break;
1840                             case 0x3: /* V9 wrasi */
1841                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1842                                 break;
1843                             case 0x6: /* V9 wrfprs */
1844                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1845                                 break;
1846                             case 0xf: /* V9 sir, nop if user */
1847 #if !defined(CONFIG_USER_ONLY)
1848                                 if (supervisor(dc))
1849                                     gen_op_sir();
1850 #endif
1851                                 break;
1852                             case 0x17: /* Tick compare */
1853 #if !defined(CONFIG_USER_ONLY)
1854                                 if (!supervisor(dc))
1855                                     goto illegal_insn;
1856 #endif
1857                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1858                                 break;
1859                             case 0x18: /* System tick */
1860 #if !defined(CONFIG_USER_ONLY)
1861                                 if (!supervisor(dc))
1862                                     goto illegal_insn;
1863 #endif
1864                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1865                                 break;
1866                             case 0x19: /* System tick compare */
1867 #if !defined(CONFIG_USER_ONLY)
1868                                 if (!supervisor(dc))
1869                                     goto illegal_insn;
1870 #endif
1871                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1872                                 break;
1873
1874                             case 0x10: /* Performance Control */
1875                             case 0x11: /* Performance Instrumentation Counter */
1876                             case 0x12: /* Dispatch Control */
1877                             case 0x13: /* Graphics Status */
1878                             case 0x14: /* Softint set */
1879                             case 0x15: /* Softint clear */
1880                             case 0x16: /* Softint write */
1881 #endif
1882                             default:
1883                                 goto illegal_insn;
1884                             }
1885                         }
1886                         break;
1887 #if !defined(CONFIG_USER_ONLY)
1888                     case 0x31: /* wrpsr, V9 saved, restored */
1889                         {
1890                             if (!supervisor(dc))
1891                                 goto priv_insn;
1892 #ifdef TARGET_SPARC64
1893                             switch (rd) {
1894                             case 0:
1895                                 gen_op_saved();
1896                                 break;
1897                             case 1:
1898                                 gen_op_restored();
1899                                 break;
1900                             default:
1901                                 goto illegal_insn;
1902                             }
1903 #else
1904                             gen_op_xor_T1_T0();
1905                             gen_op_wrpsr();
1906                             save_state(dc);
1907                             gen_op_next_insn();
1908                             gen_op_movl_T0_0();
1909                             gen_op_exit_tb();
1910                             dc->is_br = 1;
1911 #endif
1912                         }
1913                         break;
1914                     case 0x32: /* wrwim, V9 wrpr */
1915                         {
1916                             if (!supervisor(dc))
1917                                 goto priv_insn;
1918                             gen_op_xor_T1_T0();
1919 #ifdef TARGET_SPARC64
1920                             switch (rd) {
1921                             case 0: // tpc
1922                                 gen_op_wrtpc();
1923                                 break;
1924                             case 1: // tnpc
1925                                 gen_op_wrtnpc();
1926                                 break;
1927                             case 2: // tstate
1928                                 gen_op_wrtstate();
1929                                 break;
1930                             case 3: // tt
1931                                 gen_op_wrtt();
1932                                 break;
1933                             case 4: // tick
1934                                 gen_op_wrtick();
1935                                 break;
1936                             case 5: // tba
1937                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
1938                                 break;
1939                             case 6: // pstate
1940                                 gen_op_wrpstate();
1941                                 break;
1942                             case 7: // tl
1943                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
1944                                 break;
1945                             case 8: // pil
1946                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
1947                                 break;
1948                             case 9: // cwp
1949                                 gen_op_wrcwp();
1950                                 break;
1951                             case 10: // cansave
1952                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
1953                                 break;
1954                             case 11: // canrestore
1955                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
1956                                 break;
1957                             case 12: // cleanwin
1958                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
1959                                 break;
1960                             case 13: // otherwin
1961                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
1962                                 break;
1963                             case 14: // wstate
1964                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
1965                                 break;
1966                             default:
1967                                 goto illegal_insn;
1968                             }
1969 #else
1970                             gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
1971 #endif
1972                         }
1973                         break;
1974 #ifndef TARGET_SPARC64
1975                     case 0x33: /* wrtbr, V9 unimp */
1976                         {
1977                             if (!supervisor(dc))
1978                                 goto priv_insn;
1979                             gen_op_xor_T1_T0();
1980                             gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
1981                         }
1982                         break;
1983 #endif
1984 #endif
1985 #ifdef TARGET_SPARC64
1986                     case 0x2c: /* V9 movcc */
1987                         {
1988                             int cc = GET_FIELD_SP(insn, 11, 12);
1989                             int cond = GET_FIELD_SP(insn, 14, 17);
1990                             if (IS_IMM) {       /* immediate */
1991                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
1992                                 gen_movl_simm_T1(rs2);
1993                             }
1994                             else {
1995                                 rs2 = GET_FIELD_SP(insn, 0, 4);
1996                                 gen_movl_reg_T1(rs2);
1997                             }
1998                             gen_movl_reg_T0(rd);
1999                             flush_T2(dc);
2000                             if (insn & (1 << 18)) {
2001                                 if (cc == 0)
2002                                     gen_cond[0][cond]();
2003                                 else if (cc == 2)
2004                                     gen_cond[1][cond]();
2005                                 else
2006                                     goto illegal_insn;
2007                             } else {
2008                                 gen_fcond[cc][cond]();
2009                             }
2010                             gen_op_mov_cc();
2011                             gen_movl_T0_reg(rd);
2012                             break;
2013                         }
2014                     case 0x2d: /* V9 sdivx */
2015                         gen_op_sdivx_T1_T0();
2016                         gen_movl_T0_reg(rd);
2017                         break;
2018                     case 0x2e: /* V9 popc */
2019                         {
2020                             if (IS_IMM) {       /* immediate */
2021                                 rs2 = GET_FIELD_SPs(insn, 0, 12);
2022                                 gen_movl_simm_T1(rs2);
2023                                 // XXX optimize: popc(constant)
2024                             }
2025                             else {
2026                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2027                                 gen_movl_reg_T1(rs2);
2028                             }
2029                             gen_op_popc();
2030                             gen_movl_T0_reg(rd);
2031                         }
2032                     case 0x2f: /* V9 movr */
2033                         {
2034                             int cond = GET_FIELD_SP(insn, 10, 12);
2035                             rs1 = GET_FIELD(insn, 13, 17);
2036                             flush_T2(dc);
2037                             gen_movl_reg_T0(rs1);
2038                             gen_cond_reg(cond);
2039                             if (IS_IMM) {       /* immediate */
2040                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
2041                                 gen_movl_simm_T1(rs2);
2042                             }
2043                             else {
2044                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2045                                 gen_movl_reg_T1(rs2);
2046                             }
2047                             gen_movl_reg_T0(rd);
2048                             gen_op_mov_cc();
2049                             gen_movl_T0_reg(rd);
2050                             break;
2051                         }
2052                     case 0x36: /* UltraSparc shutdown, VIS */
2053                         {
2054                             // XXX
2055                         }
2056 #endif
2057                     default:
2058                         goto illegal_insn;
2059                     }
2060                 }
2061 #ifdef TARGET_SPARC64
2062             } else if (xop == 0x39) { /* V9 return */
2063                 rs1 = GET_FIELD(insn, 13, 17);
2064                 gen_movl_reg_T0(rs1);
2065                 if (IS_IMM) {   /* immediate */
2066                     rs2 = GET_FIELDs(insn, 19, 31);
2067 #if defined(OPTIM)
2068                     if (rs2) {
2069 #endif
2070                         gen_movl_simm_T1(rs2);
2071                         gen_op_add_T1_T0();
2072 #if defined(OPTIM)
2073                     }
2074 #endif
2075                 } else {                /* register */
2076                     rs2 = GET_FIELD(insn, 27, 31);
2077 #if defined(OPTIM)
2078                     if (rs2) {
2079 #endif
2080                         gen_movl_reg_T1(rs2);
2081                         gen_op_add_T1_T0();
2082 #if defined(OPTIM)
2083                     }
2084 #endif
2085                 }
2086                 gen_op_restore();
2087                 gen_mov_pc_npc(dc);
2088                 gen_op_movl_npc_T0();
2089                 dc->npc = DYNAMIC_PC;
2090                 goto jmp_insn;
2091 #endif
2092             } else {
2093                 rs1 = GET_FIELD(insn, 13, 17);
2094                 gen_movl_reg_T0(rs1);
2095                 if (IS_IMM) {   /* immediate */
2096                     rs2 = GET_FIELDs(insn, 19, 31);
2097 #if defined(OPTIM)
2098                     if (rs2) {
2099 #endif
2100                         gen_movl_simm_T1(rs2);
2101                         gen_op_add_T1_T0();
2102 #if defined(OPTIM)
2103                     }
2104 #endif
2105                 } else {                /* register */
2106                     rs2 = GET_FIELD(insn, 27, 31);
2107 #if defined(OPTIM)
2108                     if (rs2) {
2109 #endif
2110                         gen_movl_reg_T1(rs2);
2111                         gen_op_add_T1_T0();
2112 #if defined(OPTIM)
2113                     }
2114 #endif
2115                 }
2116                 switch (xop) {
2117                 case 0x38:      /* jmpl */
2118                     {
2119                         if (rd != 0) {
2120                             gen_op_movl_T1_im(dc->pc);
2121                             gen_movl_T1_reg(rd);
2122                         }
2123                         gen_mov_pc_npc(dc);
2124                         gen_op_movl_npc_T0();
2125                         dc->npc = DYNAMIC_PC;
2126                     }
2127                     goto jmp_insn;
2128 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2129                 case 0x39:      /* rett, V9 return */
2130                     {
2131                         if (!supervisor(dc))
2132                             goto priv_insn;
2133                         gen_mov_pc_npc(dc);
2134                         gen_op_movl_npc_T0();
2135                         dc->npc = DYNAMIC_PC;
2136                         gen_op_rett();
2137                     }
2138                     goto jmp_insn;
2139 #endif
2140                 case 0x3b: /* flush */
2141                     gen_op_flush_T0();
2142                     break;
2143                 case 0x3c:      /* save */
2144                     save_state(dc);
2145                     gen_op_save();
2146                     gen_movl_T0_reg(rd);
2147                     break;
2148                 case 0x3d:      /* restore */
2149                     save_state(dc);
2150                     gen_op_restore();
2151                     gen_movl_T0_reg(rd);
2152                     break;
2153 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2154                 case 0x3e:      /* V9 done/retry */
2155                     {
2156                         switch (rd) {
2157                         case 0:
2158                             if (!supervisor(dc))
2159                                 goto priv_insn;
2160                             dc->npc = DYNAMIC_PC;
2161                             dc->pc = DYNAMIC_PC;
2162                             gen_op_done();
2163                             goto jmp_insn;
2164                         case 1:
2165                             if (!supervisor(dc))
2166                                 goto priv_insn;
2167                             dc->npc = DYNAMIC_PC;
2168                             dc->pc = DYNAMIC_PC;
2169                             gen_op_retry();
2170                             goto jmp_insn;
2171                         default:
2172                             goto illegal_insn;
2173                         }
2174                     }
2175                     break;
2176 #endif
2177                 default:
2178                     goto illegal_insn;
2179                 }
2180             }
2181             break;
2182         }
2183         break;
2184     case 3:                     /* load/store instructions */
2185         {
2186             unsigned int xop = GET_FIELD(insn, 7, 12);
2187             rs1 = GET_FIELD(insn, 13, 17);
2188             gen_movl_reg_T0(rs1);
2189             if (IS_IMM) {       /* immediate */
2190                 rs2 = GET_FIELDs(insn, 19, 31);
2191 #if defined(OPTIM)
2192                 if (rs2 != 0) {
2193 #endif
2194                     gen_movl_simm_T1(rs2);
2195                     gen_op_add_T1_T0();
2196 #if defined(OPTIM)
2197                 }
2198 #endif
2199             } else {            /* register */
2200                 rs2 = GET_FIELD(insn, 27, 31);
2201 #if defined(OPTIM)
2202                 if (rs2 != 0) {
2203 #endif
2204                     gen_movl_reg_T1(rs2);
2205                     gen_op_add_T1_T0();
2206 #if defined(OPTIM)
2207                 }
2208 #endif
2209             }
2210             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2211                     (xop > 0x17 && xop < 0x1d ) || \
2212                     (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
2213                 switch (xop) {
2214                 case 0x0:       /* load word */
2215                     gen_op_ldst(ld);
2216                     break;
2217                 case 0x1:       /* load unsigned byte */
2218                     gen_op_ldst(ldub);
2219                     break;
2220                 case 0x2:       /* load unsigned halfword */
2221                     gen_op_ldst(lduh);
2222                     break;
2223                 case 0x3:       /* load double word */
2224                     gen_op_ldst(ldd);
2225                     gen_movl_T0_reg(rd + 1);
2226                     break;
2227                 case 0x9:       /* load signed byte */
2228                     gen_op_ldst(ldsb);
2229                     break;
2230                 case 0xa:       /* load signed halfword */
2231                     gen_op_ldst(ldsh);
2232                     break;
2233                 case 0xd:       /* ldstub -- XXX: should be atomically */
2234                     gen_op_ldst(ldstub);
2235                     break;
2236                 case 0x0f:      /* swap register with memory. Also atomically */
2237                     gen_movl_reg_T1(rd);
2238                     gen_op_ldst(swap);
2239                     break;
2240 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2241                 case 0x10:      /* load word alternate */
2242 #ifndef TARGET_SPARC64
2243                     if (!supervisor(dc))
2244                         goto priv_insn;
2245 #endif
2246                     gen_op_lda(insn, 1, 4, 0);
2247                     break;
2248                 case 0x11:      /* load unsigned byte alternate */
2249 #ifndef TARGET_SPARC64
2250                     if (!supervisor(dc))
2251                         goto priv_insn;
2252 #endif
2253                     gen_op_lduba(insn, 1, 1, 0);
2254                     break;
2255                 case 0x12:      /* load unsigned halfword alternate */
2256 #ifndef TARGET_SPARC64
2257                     if (!supervisor(dc))
2258                         goto priv_insn;
2259 #endif
2260                     gen_op_lduha(insn, 1, 2, 0);
2261                     break;
2262                 case 0x13:      /* load double word alternate */
2263 #ifndef TARGET_SPARC64
2264                     if (!supervisor(dc))
2265                         goto priv_insn;
2266 #endif
2267                     gen_op_ldda(insn, 1, 8, 0);
2268                     gen_movl_T0_reg(rd + 1);
2269                     break;
2270                 case 0x19:      /* load signed byte alternate */
2271 #ifndef TARGET_SPARC64
2272                     if (!supervisor(dc))
2273                         goto priv_insn;
2274 #endif
2275                     gen_op_ldsba(insn, 1, 1, 1);
2276                     break;
2277                 case 0x1a:      /* load signed halfword alternate */
2278 #ifndef TARGET_SPARC64
2279                     if (!supervisor(dc))
2280                         goto priv_insn;
2281 #endif
2282                     gen_op_ldsha(insn, 1, 2 ,1);
2283                     break;
2284                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
2285 #ifndef TARGET_SPARC64
2286                     if (!supervisor(dc))
2287                         goto priv_insn;
2288 #endif
2289                     gen_op_ldstuba(insn, 1, 1, 0);
2290                     break;
2291                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
2292 #ifndef TARGET_SPARC64
2293                     if (!supervisor(dc))
2294                         goto priv_insn;
2295 #endif
2296                     gen_movl_reg_T1(rd);
2297                     gen_op_swapa(insn, 1, 4, 0);
2298                     break;
2299
2300 #ifndef TARGET_SPARC64
2301                     /* avoid warnings */
2302                     (void) &gen_op_stfa;
2303                     (void) &gen_op_stdfa;
2304                     (void) &gen_op_ldfa;
2305                     (void) &gen_op_lddfa;
2306 #else
2307 #if !defined(CONFIG_USER_ONLY)
2308                     (void) &gen_op_cas;
2309                     (void) &gen_op_casx;
2310 #endif
2311 #endif
2312 #endif
2313 #ifdef TARGET_SPARC64
2314                 case 0x08: /* V9 ldsw */
2315                     gen_op_ldst(ldsw);
2316                     break;
2317                 case 0x0b: /* V9 ldx */
2318                     gen_op_ldst(ldx);
2319                     break;
2320                 case 0x18: /* V9 ldswa */
2321                     gen_op_ldswa(insn, 1, 4, 1);
2322                     break;
2323                 case 0x1b: /* V9 ldxa */
2324                     gen_op_ldxa(insn, 1, 8, 0);
2325                     break;
2326                 case 0x2d: /* V9 prefetch, no effect */
2327                     goto skip_move;
2328                 case 0x30: /* V9 ldfa */
2329                     gen_op_ldfa(insn, 1, 8, 0); // XXX
2330                     break;
2331                 case 0x33: /* V9 lddfa */
2332                     gen_op_lddfa(insn, 1, 8, 0); // XXX
2333
2334                     break;
2335                 case 0x3d: /* V9 prefetcha, no effect */
2336                     goto skip_move;
2337                 case 0x32: /* V9 ldqfa */
2338                     goto nfpu_insn;
2339 #endif
2340                 default:
2341                     goto illegal_insn;
2342                 }
2343                 gen_movl_T1_reg(rd);
2344 #ifdef TARGET_SPARC64
2345             skip_move: ;
2346 #endif
2347             } else if (xop >= 0x20 && xop < 0x24) {
2348 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2349                 gen_op_trap_ifnofpu();
2350 #endif
2351                 switch (xop) {
2352                 case 0x20:      /* load fpreg */
2353                     gen_op_ldst(ldf);
2354                     gen_op_store_FT0_fpr(rd);
2355                     break;
2356                 case 0x21:      /* load fsr */
2357                     gen_op_ldst(ldf);
2358                     gen_op_ldfsr();
2359                     break;
2360                 case 0x22:      /* load quad fpreg */
2361                     goto nfpu_insn;
2362                 case 0x23:      /* load double fpreg */
2363                     gen_op_ldst(lddf);
2364                     gen_op_store_DT0_fpr(DFPREG(rd));
2365                     break;
2366                 default:
2367                     goto illegal_insn;
2368                 }
2369             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2370                        xop == 0xe || xop == 0x1e) {
2371                 gen_movl_reg_T1(rd);
2372                 switch (xop) {
2373                 case 0x4:
2374                     gen_op_ldst(st);
2375                     break;
2376                 case 0x5:
2377                     gen_op_ldst(stb);
2378                     break;
2379                 case 0x6:
2380                     gen_op_ldst(sth);
2381                     break;
2382                 case 0x7:
2383                     flush_T2(dc);
2384                     gen_movl_reg_T2(rd + 1);
2385                     gen_op_ldst(std);
2386                     break;
2387 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2388                 case 0x14:
2389 #ifndef TARGET_SPARC64
2390                     if (!supervisor(dc))
2391                         goto priv_insn;
2392 #endif
2393                     gen_op_sta(insn, 0, 4, 0);
2394                     break;
2395                 case 0x15:
2396 #ifndef TARGET_SPARC64
2397                     if (!supervisor(dc))
2398                         goto priv_insn;
2399 #endif
2400                     gen_op_stba(insn, 0, 1, 0);
2401                     break;
2402                 case 0x16:
2403 #ifndef TARGET_SPARC64
2404                     if (!supervisor(dc))
2405                         goto priv_insn;
2406 #endif
2407                     gen_op_stha(insn, 0, 2, 0);
2408                     break;
2409                 case 0x17:
2410 #ifndef TARGET_SPARC64
2411                     if (!supervisor(dc))
2412                         goto priv_insn;
2413 #endif
2414                     flush_T2(dc);
2415                     gen_movl_reg_T2(rd + 1);
2416                     gen_op_stda(insn, 0, 8, 0);
2417                     break;
2418 #endif
2419 #ifdef TARGET_SPARC64
2420                 case 0x0e: /* V9 stx */
2421                     gen_op_ldst(stx);
2422                     break;
2423                 case 0x1e: /* V9 stxa */
2424                     gen_op_stxa(insn, 0, 8, 0); // XXX
2425                     break;
2426 #endif
2427                 default:
2428                     goto illegal_insn;
2429                 }
2430             } else if (xop > 0x23 && xop < 0x28) {
2431 #if !defined(CONFIG_USER_ONLY)
2432                 gen_op_trap_ifnofpu();
2433 #endif
2434                 switch (xop) {
2435                 case 0x24:
2436                     gen_op_load_fpr_FT0(rd);
2437                     gen_op_ldst(stf);
2438                     break;
2439                 case 0x25: /* stfsr, V9 stxfsr */
2440                     gen_op_stfsr();
2441                     gen_op_ldst(stf);
2442                     break;
2443                 case 0x26: /* stdfq */
2444                     goto nfpu_insn;
2445                 case 0x27:
2446                     gen_op_load_fpr_DT0(DFPREG(rd));
2447                     gen_op_ldst(stdf);
2448                     break;
2449                 default:
2450                     goto illegal_insn;
2451                 }
2452             } else if (xop > 0x33 && xop < 0x3f) {
2453 #ifdef TARGET_SPARC64
2454                 switch (xop) {
2455                 case 0x34: /* V9 stfa */
2456                     gen_op_stfa(insn, 0, 0, 0); // XXX
2457                     break;
2458                 case 0x37: /* V9 stdfa */
2459                     gen_op_stdfa(insn, 0, 0, 0); // XXX
2460                     break;
2461                 case 0x3c: /* V9 casa */
2462                     gen_op_casa(insn, 0, 4, 0); // XXX
2463                     break;
2464                 case 0x3e: /* V9 casxa */
2465                     gen_op_casxa(insn, 0, 8, 0); // XXX
2466                     break;
2467                 case 0x36: /* V9 stqfa */
2468                     goto nfpu_insn;
2469                 default:
2470                     goto illegal_insn;
2471                 }
2472 #else
2473                 goto illegal_insn;
2474 #endif
2475             }
2476             else
2477                 goto illegal_insn;
2478         }
2479         break;
2480     }
2481     /* default case for non jump instructions */
2482     if (dc->npc == DYNAMIC_PC) {
2483         dc->pc = DYNAMIC_PC;
2484         gen_op_next_insn();
2485     } else if (dc->npc == JUMP_PC) {
2486         /* we can do a static jump */
2487         gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
2488         dc->is_br = 1;
2489     } else {
2490         dc->pc = dc->npc;
2491         dc->npc = dc->npc + 4;
2492     }
2493  jmp_insn:
2494     return;
2495  illegal_insn:
2496     save_state(dc);
2497     gen_op_exception(TT_ILL_INSN);
2498     dc->is_br = 1;
2499     return;
2500 #if !defined(CONFIG_USER_ONLY)
2501  priv_insn:
2502     save_state(dc);
2503     gen_op_exception(TT_PRIV_INSN);
2504     dc->is_br = 1;
2505     return;
2506 #endif
2507  nfpu_insn:
2508     save_state(dc);
2509     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2510     dc->is_br = 1;
2511 }
2512
2513 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
2514                                                  int spc, CPUSPARCState *env)
2515 {
2516     target_ulong pc_start, last_pc;
2517     uint16_t *gen_opc_end;
2518     DisasContext dc1, *dc = &dc1;
2519     int j, lj = -1;
2520
2521     memset(dc, 0, sizeof(DisasContext));
2522     dc->tb = tb;
2523     pc_start = tb->pc;
2524     dc->pc = pc_start;
2525     last_pc = dc->pc;
2526     dc->npc = (target_ulong) tb->cs_base;
2527 #if defined(CONFIG_USER_ONLY)
2528     dc->mem_idx = 0;
2529 #else
2530     dc->mem_idx = ((env->psrs) != 0);
2531 #endif
2532     gen_opc_ptr = gen_opc_buf;
2533     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2534     gen_opparam_ptr = gen_opparam_buf;
2535     nb_gen_labels = 0;
2536
2537     do {
2538         if (env->nb_breakpoints > 0) {
2539             for(j = 0; j < env->nb_breakpoints; j++) {
2540                 if (env->breakpoints[j] == dc->pc) {
2541                     if (dc->pc != pc_start)
2542                         save_state(dc);
2543                     gen_op_debug();
2544                     gen_op_movl_T0_0();
2545                     gen_op_exit_tb();
2546                     dc->is_br = 1;
2547                     goto exit_gen_loop;
2548                 }
2549             }
2550         }
2551         if (spc) {
2552             if (loglevel > 0)
2553                 fprintf(logfile, "Search PC...\n");
2554             j = gen_opc_ptr - gen_opc_buf;
2555             if (lj < j) {
2556                 lj++;
2557                 while (lj < j)
2558                     gen_opc_instr_start[lj++] = 0;
2559                 gen_opc_pc[lj] = dc->pc;
2560                 gen_opc_npc[lj] = dc->npc;
2561                 gen_opc_instr_start[lj] = 1;
2562             }
2563         }
2564         last_pc = dc->pc;
2565         disas_sparc_insn(dc);
2566
2567         if (dc->is_br)
2568             break;
2569         /* if the next PC is different, we abort now */
2570         if (dc->pc != (last_pc + 4))
2571             break;
2572         /* if we reach a page boundary, we stop generation so that the
2573            PC of a TT_TFAULT exception is always in the right page */
2574         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2575             break;
2576         /* if single step mode, we generate only one instruction and
2577            generate an exception */
2578         if (env->singlestep_enabled) {
2579             gen_jmp_im(dc->pc);
2580             gen_op_movl_T0_0();
2581             gen_op_exit_tb();
2582             break;
2583         }
2584     } while ((gen_opc_ptr < gen_opc_end) &&
2585              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
2586
2587  exit_gen_loop:
2588     if (!dc->is_br) {
2589         if (dc->pc != DYNAMIC_PC &&
2590             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2591             /* static PC and NPC: we can use direct chaining */
2592             gen_branch(dc, (long)tb, dc->pc, dc->npc);
2593         } else {
2594             if (dc->pc != DYNAMIC_PC)
2595                 gen_jmp_im(dc->pc);
2596             save_npc(dc);
2597             gen_op_movl_T0_0();
2598             gen_op_exit_tb();
2599         }
2600     }
2601     *gen_opc_ptr = INDEX_op_end;
2602     if (spc) {
2603         j = gen_opc_ptr - gen_opc_buf;
2604         lj++;
2605         while (lj <= j)
2606             gen_opc_instr_start[lj++] = 0;
2607         tb->size = 0;
2608 #if 0
2609         if (loglevel > 0) {
2610             page_dump(logfile);
2611         }
2612 #endif
2613         gen_opc_jump_pc[0] = dc->jump_pc[0];
2614         gen_opc_jump_pc[1] = dc->jump_pc[1];
2615     } else {
2616         tb->size = last_pc + 4 - pc_start;
2617     }
2618 #ifdef DEBUG_DISAS
2619     if (loglevel & CPU_LOG_TB_IN_ASM) {
2620         fprintf(logfile, "--------------\n");
2621         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2622         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
2623         fprintf(logfile, "\n");
2624         if (loglevel & CPU_LOG_TB_OP) {
2625             fprintf(logfile, "OP:\n");
2626             dump_ops(gen_opc_buf, gen_opparam_buf);
2627             fprintf(logfile, "\n");
2628         }
2629     }
2630 #endif
2631     return 0;
2632 }
2633
2634 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
2635 {
2636     return gen_intermediate_code_internal(tb, 0, env);
2637 }
2638
2639 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
2640 {
2641     return gen_intermediate_code_internal(tb, 1, env);
2642 }
2643
2644 extern int ram_size;
2645
2646 void cpu_reset(CPUSPARCState *env)
2647 {
2648     memset(env, 0, sizeof(*env));
2649     tlb_flush(env, 1);
2650     env->cwp = 0;
2651     env->wim = 1;
2652     env->regwptr = env->regbase + (env->cwp * 16);
2653 #if defined(CONFIG_USER_ONLY)
2654     env->user_mode_only = 1;
2655 #else
2656     env->psrs = 1;
2657     env->psrps = 1;
2658     env->gregs[1] = ram_size;
2659 #ifdef TARGET_SPARC64
2660     env->pstate = PS_PRIV;
2661     env->version = GET_VER(env);
2662     env->pc = 0x1fff0000000ULL;
2663 #else
2664     env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
2665     env->pc = 0xffd00000;
2666 #endif
2667     env->npc = env->pc + 4;
2668 #endif
2669 }
2670
2671 CPUSPARCState *cpu_sparc_init(void)
2672 {
2673     CPUSPARCState *env;
2674
2675     env = qemu_mallocz(sizeof(CPUSPARCState));
2676     if (!env)
2677         return NULL;
2678     cpu_exec_init(env);
2679     cpu_reset(env);
2680     return (env);
2681 }
2682
2683 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
2684
2685 void cpu_dump_state(CPUState *env, FILE *f,
2686                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2687                     int flags)
2688 {
2689     int i, x;
2690
2691     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
2692     cpu_fprintf(f, "General Registers:\n");
2693     for (i = 0; i < 4; i++)
2694         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
2695     cpu_fprintf(f, "\n");
2696     for (; i < 8; i++)
2697         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
2698     cpu_fprintf(f, "\nCurrent Register Window:\n");
2699     for (x = 0; x < 3; x++) {
2700         for (i = 0; i < 4; i++)
2701             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
2702                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
2703                     env->regwptr[i + x * 8]);
2704         cpu_fprintf(f, "\n");
2705         for (; i < 8; i++)
2706             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
2707                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
2708                     env->regwptr[i + x * 8]);
2709         cpu_fprintf(f, "\n");
2710     }
2711     cpu_fprintf(f, "\nFloating Point Registers:\n");
2712     for (i = 0; i < 32; i++) {
2713         if ((i & 3) == 0)
2714             cpu_fprintf(f, "%%f%02d:", i);
2715         cpu_fprintf(f, " %016lf", env->fpr[i]);
2716         if ((i & 3) == 3)
2717             cpu_fprintf(f, "\n");
2718     }
2719     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
2720             GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
2721             GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
2722             env->psrs?'S':'-', env->psrps?'P':'-',
2723             env->psret?'E':'-', env->wim);
2724     cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
2725 }
2726
2727 #if defined(CONFIG_USER_ONLY)
2728 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
2729 {
2730     return addr;
2731 }
2732
2733 #else
2734 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
2735                                  int *access_index, target_ulong address, int rw,
2736                                  int is_user);
2737
2738 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
2739 {
2740     target_phys_addr_t phys_addr;
2741     int prot, access_index;
2742
2743     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
2744         return -1;
2745     return phys_addr;
2746 }
2747 #endif
2748
2749 void helper_flush(target_ulong addr)
2750 {
2751     addr &= ~7;
2752     tb_invalidate_page_range(addr, addr + 8);
2753 }