vcs.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28 */
  29
  30 #include <stdarg.h>
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <string.h>
  34 #include <inttypes.h>
  35
  36 #include "cpu.h"
  37 #include "exec-all.h"
  38 #include "disas.h"
  39 #include "tcg-op.h"
  40
  41 #define DEBUG_DISAS
  42
  43 #define DYNAMIC_PC  1 /* dynamic pc value */
  44 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  45                          according to jump_pc[T2] */
  46
  47 typedef struct DisasContext {
  48     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  49     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  50     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  51     int is_br;
  52     int mem_idx;
  53     int fpu_enabled;
  54     struct TranslationBlock *tb;
  55 } DisasContext;
  56
  57 typedef struct sparc_def_t sparc_def_t;
  58
  59 struct sparc_def_t {
  60     const unsigned char *name;
  61     target_ulong iu_version;
  62     uint32_t fpu_version;
  63     uint32_t mmu_version;
  64     uint32_t mmu_bm;
  65 };
  66
  67 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
  68
  69 extern FILE *logfile;
  70 extern int loglevel;
  71
  72 // This function uses non-native bit order
  73 #define GET_FIELD(X, FROM, TO) \
  74   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  75
  76 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  77 #define GET_FIELD_SP(X, FROM, TO) \
  78     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  79
  80 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  81 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  82
  83 #ifdef TARGET_SPARC64
  84 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  85 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
  86 #else
  87 #define DFPREG(r) (r & 0x1e)
  88 #define QFPREG(r) (r & 0x1c)
  89 #endif
  90
  91 static int sign_extend(int x, int len)
  92 {
  93     len = 32 - len;
  94     return (x << len) >> len;
  95 }
  96
  97 #define IS_IMM (insn & (1<<13))
  98
  99 static void disas_sparc_insn(DisasContext * dc);
 100
 101 static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
 102     {
 103      gen_op_movl_g0_T0,
 104      gen_op_movl_g1_T0,
 105      gen_op_movl_g2_T0,
 106      gen_op_movl_g3_T0,
 107      gen_op_movl_g4_T0,
 108      gen_op_movl_g5_T0,
 109      gen_op_movl_g6_T0,
 110      gen_op_movl_g7_T0,
 111      gen_op_movl_o0_T0,
 112      gen_op_movl_o1_T0,
 113      gen_op_movl_o2_T0,
 114      gen_op_movl_o3_T0,
 115      gen_op_movl_o4_T0,
 116      gen_op_movl_o5_T0,
 117      gen_op_movl_o6_T0,
 118      gen_op_movl_o7_T0,
 119      gen_op_movl_l0_T0,
 120      gen_op_movl_l1_T0,
 121      gen_op_movl_l2_T0,
 122      gen_op_movl_l3_T0,
 123      gen_op_movl_l4_T0,
 124      gen_op_movl_l5_T0,
 125      gen_op_movl_l6_T0,
 126      gen_op_movl_l7_T0,
 127      gen_op_movl_i0_T0,
 128      gen_op_movl_i1_T0,
 129      gen_op_movl_i2_T0,
 130      gen_op_movl_i3_T0,
 131      gen_op_movl_i4_T0,
 132      gen_op_movl_i5_T0,
 133      gen_op_movl_i6_T0,
 134      gen_op_movl_i7_T0,
 135      },
 136     {
 137      gen_op_movl_g0_T1,
 138      gen_op_movl_g1_T1,
 139      gen_op_movl_g2_T1,
 140      gen_op_movl_g3_T1,
 141      gen_op_movl_g4_T1,
 142      gen_op_movl_g5_T1,
 143      gen_op_movl_g6_T1,
 144      gen_op_movl_g7_T1,
 145      gen_op_movl_o0_T1,
 146      gen_op_movl_o1_T1,
 147      gen_op_movl_o2_T1,
 148      gen_op_movl_o3_T1,
 149      gen_op_movl_o4_T1,
 150      gen_op_movl_o5_T1,
 151      gen_op_movl_o6_T1,
 152      gen_op_movl_o7_T1,
 153      gen_op_movl_l0_T1,
 154      gen_op_movl_l1_T1,
 155      gen_op_movl_l2_T1,
 156      gen_op_movl_l3_T1,
 157      gen_op_movl_l4_T1,
 158      gen_op_movl_l5_T1,
 159      gen_op_movl_l6_T1,
 160      gen_op_movl_l7_T1,
 161      gen_op_movl_i0_T1,
 162      gen_op_movl_i1_T1,
 163      gen_op_movl_i2_T1,
 164      gen_op_movl_i3_T1,
 165      gen_op_movl_i4_T1,
 166      gen_op_movl_i5_T1,
 167      gen_op_movl_i6_T1,
 168      gen_op_movl_i7_T1,
 169      }
 170 };
 171
 172 static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
 173     {
 174      gen_op_movl_T0_g0,
 175      gen_op_movl_T0_g1,
 176      gen_op_movl_T0_g2,
 177      gen_op_movl_T0_g3,
 178      gen_op_movl_T0_g4,
 179      gen_op_movl_T0_g5,
 180      gen_op_movl_T0_g6,
 181      gen_op_movl_T0_g7,
 182      gen_op_movl_T0_o0,
 183      gen_op_movl_T0_o1,
 184      gen_op_movl_T0_o2,
 185      gen_op_movl_T0_o3,
 186      gen_op_movl_T0_o4,
 187      gen_op_movl_T0_o5,
 188      gen_op_movl_T0_o6,
 189      gen_op_movl_T0_o7,
 190      gen_op_movl_T0_l0,
 191      gen_op_movl_T0_l1,
 192      gen_op_movl_T0_l2,
 193      gen_op_movl_T0_l3,
 194      gen_op_movl_T0_l4,
 195      gen_op_movl_T0_l5,
 196      gen_op_movl_T0_l6,
 197      gen_op_movl_T0_l7,
 198      gen_op_movl_T0_i0,
 199      gen_op_movl_T0_i1,
 200      gen_op_movl_T0_i2,
 201      gen_op_movl_T0_i3,
 202      gen_op_movl_T0_i4,
 203      gen_op_movl_T0_i5,
 204      gen_op_movl_T0_i6,
 205      gen_op_movl_T0_i7,
 206      },
 207     {
 208      gen_op_movl_T1_g0,
 209      gen_op_movl_T1_g1,
 210      gen_op_movl_T1_g2,
 211      gen_op_movl_T1_g3,
 212      gen_op_movl_T1_g4,
 213      gen_op_movl_T1_g5,
 214      gen_op_movl_T1_g6,
 215      gen_op_movl_T1_g7,
 216      gen_op_movl_T1_o0,
 217      gen_op_movl_T1_o1,
 218      gen_op_movl_T1_o2,
 219      gen_op_movl_T1_o3,
 220      gen_op_movl_T1_o4,
 221      gen_op_movl_T1_o5,
 222      gen_op_movl_T1_o6,
 223      gen_op_movl_T1_o7,
 224      gen_op_movl_T1_l0,
 225      gen_op_movl_T1_l1,
 226      gen_op_movl_T1_l2,
 227      gen_op_movl_T1_l3,
 228      gen_op_movl_T1_l4,
 229      gen_op_movl_T1_l5,
 230      gen_op_movl_T1_l6,
 231      gen_op_movl_T1_l7,
 232      gen_op_movl_T1_i0,
 233      gen_op_movl_T1_i1,
 234      gen_op_movl_T1_i2,
 235      gen_op_movl_T1_i3,
 236      gen_op_movl_T1_i4,
 237      gen_op_movl_T1_i5,
 238      gen_op_movl_T1_i6,
 239      gen_op_movl_T1_i7,
 240      },
 241     {
 242      gen_op_movl_T2_g0,
 243      gen_op_movl_T2_g1,
 244      gen_op_movl_T2_g2,
 245      gen_op_movl_T2_g3,
 246      gen_op_movl_T2_g4,
 247      gen_op_movl_T2_g5,
 248      gen_op_movl_T2_g6,
 249      gen_op_movl_T2_g7,
 250      gen_op_movl_T2_o0,
 251      gen_op_movl_T2_o1,
 252      gen_op_movl_T2_o2,
 253      gen_op_movl_T2_o3,
 254      gen_op_movl_T2_o4,
 255      gen_op_movl_T2_o5,
 256      gen_op_movl_T2_o6,
 257      gen_op_movl_T2_o7,
 258      gen_op_movl_T2_l0,
 259      gen_op_movl_T2_l1,
 260      gen_op_movl_T2_l2,
 261      gen_op_movl_T2_l3,
 262      gen_op_movl_T2_l4,
 263      gen_op_movl_T2_l5,
 264      gen_op_movl_T2_l6,
 265      gen_op_movl_T2_l7,
 266      gen_op_movl_T2_i0,
 267      gen_op_movl_T2_i1,
 268      gen_op_movl_T2_i2,
 269      gen_op_movl_T2_i3,
 270      gen_op_movl_T2_i4,
 271      gen_op_movl_T2_i5,
 272      gen_op_movl_T2_i6,
 273      gen_op_movl_T2_i7,
 274      }
 275 };
 276
 277 static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
 278     gen_op_movl_T0_im,
 279     gen_op_movl_T1_im,
 280     gen_op_movl_T2_im
 281 };
 282
 283 // Sign extending version
 284 static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
 285     gen_op_movl_T0_sim,
 286     gen_op_movl_T1_sim,
 287     gen_op_movl_T2_sim
 288 };
 289
 290 #ifdef TARGET_SPARC64
 291 #define GEN32(func, NAME) \
 292 static GenOpFunc * const NAME ## _table [64] = {                              \
 293 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 294 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 295 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 296 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 297 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 298 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 299 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 300 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 301 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
 302 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
 303 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
 304 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
 305 };                                                                            \
 306 static inline void func(int n)                                                \
 307 {                                                                             \
 308     NAME ## _table[n]();                                                      \
 309 }
 310 #else
 311 #define GEN32(func, NAME) \
 312 static GenOpFunc *const NAME ## _table [32] = {                               \
 313 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 314 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 315 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 316 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 317 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 318 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 319 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 320 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 321 };                                                                            \
 322 static inline void func(int n)                                                \
 323 {                                                                             \
 324     NAME ## _table[n]();                                                      \
 325 }
 326 #endif
 327
 328 /* floating point registers moves */
 329 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
 330 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
 331 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
 332 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
 333
 334 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
 335 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
 336 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
 337 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 338
 339 #if defined(CONFIG_USER_ONLY)
 340 GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
 341 GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
 342 GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
 343 GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
 344 #endif
 345
 346 /* moves */
 347 #ifdef CONFIG_USER_ONLY
 348 #define supervisor(dc) 0
 349 #ifdef TARGET_SPARC64
 350 #define hypervisor(dc) 0
 351 #endif
 352 #define gen_op_ldst(name)        gen_op_##name##_raw()
 353 #else
 354 #define supervisor(dc) (dc->mem_idx >= 1)
 355 #ifdef TARGET_SPARC64
 356 #define hypervisor(dc) (dc->mem_idx == 2)
 357 #define OP_LD_TABLE(width)                                              \
 358     static GenOpFunc * const gen_op_##width[] = {                       \
 359         &gen_op_##width##_user,                                         \
 360         &gen_op_##width##_kernel,                                       \
 361         &gen_op_##width##_hypv,                                         \
 362     };
 363 #else
 364 #define OP_LD_TABLE(width)                                              \
 365     static GenOpFunc * const gen_op_##width[] = {                       \
 366         &gen_op_##width##_user,                                         \
 367         &gen_op_##width##_kernel,                                       \
 368     };
 369 #endif
 370 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 371 #endif
 372
 373 #ifndef CONFIG_USER_ONLY
 374 OP_LD_TABLE(ld);
 375 OP_LD_TABLE(st);
 376 OP_LD_TABLE(ldub);
 377 OP_LD_TABLE(lduh);
 378 OP_LD_TABLE(ldsb);
 379 OP_LD_TABLE(ldsh);
 380 OP_LD_TABLE(stb);
 381 OP_LD_TABLE(sth);
 382 OP_LD_TABLE(std);
 383 OP_LD_TABLE(ldstub);
 384 OP_LD_TABLE(swap);
 385 OP_LD_TABLE(ldd);
 386 OP_LD_TABLE(stf);
 387 OP_LD_TABLE(stdf);
 388 OP_LD_TABLE(ldf);
 389 OP_LD_TABLE(lddf);
 390
 391 #ifdef TARGET_SPARC64
 392 OP_LD_TABLE(lduw);
 393 OP_LD_TABLE(ldsw);
 394 OP_LD_TABLE(ldx);
 395 OP_LD_TABLE(stx);
 396 #endif
 397 #endif
 398
 399 /* asi moves */
 400 #ifdef TARGET_SPARC64
 401 static inline void gen_ld_asi(int insn, int size, int sign)
 402 {
 403     int asi, offset;
 404
 405     if (IS_IMM) {
 406         offset = GET_FIELD(insn, 25, 31);
 407         gen_op_ld_asi_reg(offset, size, sign);
 408     } else {
 409         asi = GET_FIELD(insn, 19, 26);
 410         gen_op_ld_asi(asi, size, sign);
 411     }
 412 }
 413
 414 static inline void gen_st_asi(int insn, int size)
 415 {
 416     int asi, offset;
 417
 418     if (IS_IMM) {
 419         offset = GET_FIELD(insn, 25, 31);
 420         gen_op_st_asi_reg(offset, size);
 421     } else {
 422         asi = GET_FIELD(insn, 19, 26);
 423         gen_op_st_asi(asi, size);
 424     }
 425 }
 426
 427 static inline void gen_ldf_asi(int insn, int size, int rd)
 428 {
 429     int asi, offset;
 430
 431     if (IS_IMM) {
 432         offset = GET_FIELD(insn, 25, 31);
 433         gen_op_ldf_asi_reg(offset, size, rd);
 434     } else {
 435         asi = GET_FIELD(insn, 19, 26);
 436         gen_op_ldf_asi(asi, size, rd);
 437     }
 438 }
 439
 440 static inline void gen_stf_asi(int insn, int size, int rd)
 441 {
 442     int asi, offset;
 443
 444     if (IS_IMM) {
 445         offset = GET_FIELD(insn, 25, 31);
 446         gen_op_stf_asi_reg(offset, size, rd);
 447     } else {
 448         asi = GET_FIELD(insn, 19, 26);
 449         gen_op_stf_asi(asi, size, rd);
 450     }
 451 }
 452
 453 static inline void gen_swap_asi(int insn)
 454 {
 455     int asi, offset;
 456
 457     if (IS_IMM) {
 458         offset = GET_FIELD(insn, 25, 31);
 459         gen_op_swap_asi_reg(offset);
 460     } else {
 461         asi = GET_FIELD(insn, 19, 26);
 462         gen_op_swap_asi(asi);
 463     }
 464 }
 465
 466 static inline void gen_ldstub_asi(int insn)
 467 {
 468     int asi, offset;
 469
 470     if (IS_IMM) {
 471         offset = GET_FIELD(insn, 25, 31);
 472         gen_op_ldstub_asi_reg(offset);
 473     } else {
 474         asi = GET_FIELD(insn, 19, 26);
 475         gen_op_ldstub_asi(asi);
 476     }
 477 }
 478
 479 static inline void gen_ldda_asi(int insn)
 480 {
 481     int asi, offset;
 482
 483     if (IS_IMM) {
 484         offset = GET_FIELD(insn, 25, 31);
 485         gen_op_ldda_asi_reg(offset);
 486     } else {
 487         asi = GET_FIELD(insn, 19, 26);
 488         gen_op_ldda_asi(asi);
 489     }
 490 }
 491
 492 static inline void gen_stda_asi(int insn)
 493 {
 494     int asi, offset;
 495
 496     if (IS_IMM) {
 497         offset = GET_FIELD(insn, 25, 31);
 498         gen_op_stda_asi_reg(offset);
 499     } else {
 500         asi = GET_FIELD(insn, 19, 26);
 501         gen_op_stda_asi(asi);
 502     }
 503 }
 504
 505 static inline void gen_cas_asi(int insn)
 506 {
 507     int asi, offset;
 508
 509     if (IS_IMM) {
 510         offset = GET_FIELD(insn, 25, 31);
 511         gen_op_cas_asi_reg(offset);
 512     } else {
 513         asi = GET_FIELD(insn, 19, 26);
 514         gen_op_cas_asi(asi);
 515     }
 516 }
 517
 518 static inline void gen_casx_asi(int insn)
 519 {
 520     int asi, offset;
 521
 522     if (IS_IMM) {
 523         offset = GET_FIELD(insn, 25, 31);
 524         gen_op_casx_asi_reg(offset);
 525     } else {
 526         asi = GET_FIELD(insn, 19, 26);
 527         gen_op_casx_asi(asi);
 528     }
 529 }
 530
 531 #elif !defined(CONFIG_USER_ONLY)
 532
 533 static inline void gen_ld_asi(int insn, int size, int sign)
 534 {
 535     int asi;
 536
 537     asi = GET_FIELD(insn, 19, 26);
 538     gen_op_ld_asi(asi, size, sign);
 539 }
 540
 541 static inline void gen_st_asi(int insn, int size)
 542 {
 543     int asi;
 544
 545     asi = GET_FIELD(insn, 19, 26);
 546     gen_op_st_asi(asi, size);
 547 }
 548
 549 static inline void gen_ldstub_asi(int insn)
 550 {
 551     int asi;
 552
 553     asi = GET_FIELD(insn, 19, 26);
 554     gen_op_ldstub_asi(asi);
 555 }
 556
 557 static inline void gen_swap_asi(int insn)
 558 {
 559     int asi;
 560
 561     asi = GET_FIELD(insn, 19, 26);
 562     gen_op_swap_asi(asi);
 563 }
 564
 565 static inline void gen_ldda_asi(int insn)
 566 {
 567     int asi;
 568
 569     asi = GET_FIELD(insn, 19, 26);
 570     gen_op_ld_asi(asi, 8, 0);
 571 }
 572
 573 static inline void gen_stda_asi(int insn)
 574 {
 575     int asi;
 576
 577     asi = GET_FIELD(insn, 19, 26);
 578     gen_op_st_asi(asi, 8);
 579 }
 580 #endif
 581
 582 static inline void gen_movl_imm_TN(int reg, uint32_t imm)
 583 {
 584     gen_op_movl_TN_im[reg](imm);
 585 }
 586
 587 static inline void gen_movl_imm_T1(uint32_t val)
 588 {
 589     gen_movl_imm_TN(1, val);
 590 }
 591
 592 static inline void gen_movl_imm_T0(uint32_t val)
 593 {
 594     gen_movl_imm_TN(0, val);
 595 }
 596
 597 static inline void gen_movl_simm_TN(int reg, int32_t imm)
 598 {
 599     gen_op_movl_TN_sim[reg](imm);
 600 }
 601
 602 static inline void gen_movl_simm_T1(int32_t val)
 603 {
 604     gen_movl_simm_TN(1, val);
 605 }
 606
 607 static inline void gen_movl_simm_T0(int32_t val)
 608 {
 609     gen_movl_simm_TN(0, val);
 610 }
 611
 612 static inline void gen_movl_reg_TN(int reg, int t)
 613 {
 614     if (reg)
 615         gen_op_movl_reg_TN[t][reg] ();
 616     else
 617         gen_movl_imm_TN(t, 0);
 618 }
 619
 620 static inline void gen_movl_reg_T0(int reg)
 621 {
 622     gen_movl_reg_TN(reg, 0);
 623 }
 624
 625 static inline void gen_movl_reg_T1(int reg)
 626 {
 627     gen_movl_reg_TN(reg, 1);
 628 }
 629
 630 static inline void gen_movl_reg_T2(int reg)
 631 {
 632     gen_movl_reg_TN(reg, 2);
 633 }
 634
 635 static inline void gen_movl_TN_reg(int reg, int t)
 636 {
 637     if (reg)
 638         gen_op_movl_TN_reg[t][reg] ();
 639 }
 640
 641 static inline void gen_movl_T0_reg(int reg)
 642 {
 643     gen_movl_TN_reg(reg, 0);
 644 }
 645
 646 static inline void gen_movl_T1_reg(int reg)
 647 {
 648     gen_movl_TN_reg(reg, 1);
 649 }
 650
 651 static inline void gen_jmp_im(target_ulong pc)
 652 {
 653 #ifdef TARGET_SPARC64
 654     if (pc == (uint32_t)pc) {
 655         gen_op_jmp_im(pc);
 656     } else {
 657         gen_op_jmp_im64(pc >> 32, pc);
 658     }
 659 #else
 660     gen_op_jmp_im(pc);
 661 #endif
 662 }
 663
 664 static inline void gen_movl_npc_im(target_ulong npc)
 665 {
 666 #ifdef TARGET_SPARC64
 667     if (npc == (uint32_t)npc) {
 668         gen_op_movl_npc_im(npc);
 669     } else {
 670         gen_op_movq_npc_im64(npc >> 32, npc);
 671     }
 672 #else
 673     gen_op_movl_npc_im(npc);
 674 #endif
 675 }
 676
 677 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 678                                target_ulong pc, target_ulong npc)
 679 {
 680     TranslationBlock *tb;
 681
 682     tb = s->tb;
 683     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 684         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 685         /* jump to same page: we can use a direct jump */
 686         tcg_gen_goto_tb(tb_num);
 687         gen_jmp_im(pc);
 688         gen_movl_npc_im(npc);
 689         tcg_gen_exit_tb((long)tb + tb_num);
 690     } else {
 691         /* jump to another page: currently not optimized */
 692         gen_jmp_im(pc);
 693         gen_movl_npc_im(npc);
 694         tcg_gen_exit_tb(0);
 695     }
 696 }
 697
 698 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
 699                                target_ulong pc2)
 700 {
 701     int l1;
 702
 703     l1 = gen_new_label();
 704
 705     gen_op_jz_T2_label(l1);
 706
 707     gen_goto_tb(dc, 0, pc1, pc1 + 4);
 708
 709     gen_set_label(l1);
 710     gen_goto_tb(dc, 1, pc2, pc2 + 4);
 711 }
 712
 713 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
 714                                 target_ulong pc2)
 715 {
 716     int l1;
 717
 718     l1 = gen_new_label();
 719
 720     gen_op_jz_T2_label(l1);
 721
 722     gen_goto_tb(dc, 0, pc2, pc1);
 723
 724     gen_set_label(l1);
 725     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
 726 }
 727
 728 static inline void gen_branch(DisasContext *dc, target_ulong pc,
 729                               target_ulong npc)
 730 {
 731     gen_goto_tb(dc, 0, pc, npc);
 732 }
 733
 734 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
 735 {
 736     int l1, l2;
 737
 738     l1 = gen_new_label();
 739     l2 = gen_new_label();
 740     gen_op_jz_T2_label(l1);
 741
 742     gen_movl_npc_im(npc1);
 743     gen_op_jmp_label(l2);
 744
 745     gen_set_label(l1);
 746     gen_movl_npc_im(npc2);
 747     gen_set_label(l2);
 748 }
 749
 750 /* call this function before using T2 as it may have been set for a jump */
 751 static inline void flush_T2(DisasContext * dc)
 752 {
 753     if (dc->npc == JUMP_PC) {
 754         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 755         dc->npc = DYNAMIC_PC;
 756     }
 757 }
 758
 759 static inline void save_npc(DisasContext * dc)
 760 {
 761     if (dc->npc == JUMP_PC) {
 762         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 763         dc->npc = DYNAMIC_PC;
 764     } else if (dc->npc != DYNAMIC_PC) {
 765         gen_movl_npc_im(dc->npc);
 766     }
 767 }
 768
 769 static inline void save_state(DisasContext * dc)
 770 {
 771     gen_jmp_im(dc->pc);
 772     save_npc(dc);
 773 }
 774
 775 static inline void gen_mov_pc_npc(DisasContext * dc)
 776 {
 777     if (dc->npc == JUMP_PC) {
 778         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 779         gen_op_mov_pc_npc();
 780         dc->pc = DYNAMIC_PC;
 781     } else if (dc->npc == DYNAMIC_PC) {
 782         gen_op_mov_pc_npc();
 783         dc->pc = DYNAMIC_PC;
 784     } else {
 785         dc->pc = dc->npc;
 786     }
 787 }
 788
 789 static GenOpFunc * const gen_cond[2][16] = {
 790     {
 791         gen_op_eval_bn,
 792         gen_op_eval_be,
 793         gen_op_eval_ble,
 794         gen_op_eval_bl,
 795         gen_op_eval_bleu,
 796         gen_op_eval_bcs,
 797         gen_op_eval_bneg,
 798         gen_op_eval_bvs,
 799         gen_op_eval_ba,
 800         gen_op_eval_bne,
 801         gen_op_eval_bg,
 802         gen_op_eval_bge,
 803         gen_op_eval_bgu,
 804         gen_op_eval_bcc,
 805         gen_op_eval_bpos,
 806         gen_op_eval_bvc,
 807     },
 808     {
 809 #ifdef TARGET_SPARC64
 810         gen_op_eval_bn,
 811         gen_op_eval_xbe,
 812         gen_op_eval_xble,
 813         gen_op_eval_xbl,
 814         gen_op_eval_xbleu,
 815         gen_op_eval_xbcs,
 816         gen_op_eval_xbneg,
 817         gen_op_eval_xbvs,
 818         gen_op_eval_ba,
 819         gen_op_eval_xbne,
 820         gen_op_eval_xbg,
 821         gen_op_eval_xbge,
 822         gen_op_eval_xbgu,
 823         gen_op_eval_xbcc,
 824         gen_op_eval_xbpos,
 825         gen_op_eval_xbvc,
 826 #endif
 827     },
 828 };
 829
 830 static GenOpFunc * const gen_fcond[4][16] = {
 831     {
 832         gen_op_eval_bn,
 833         gen_op_eval_fbne,
 834         gen_op_eval_fblg,
 835         gen_op_eval_fbul,
 836         gen_op_eval_fbl,
 837         gen_op_eval_fbug,
 838         gen_op_eval_fbg,
 839         gen_op_eval_fbu,
 840         gen_op_eval_ba,
 841         gen_op_eval_fbe,
 842         gen_op_eval_fbue,
 843         gen_op_eval_fbge,
 844         gen_op_eval_fbuge,
 845         gen_op_eval_fble,
 846         gen_op_eval_fbule,
 847         gen_op_eval_fbo,
 848     },
 849 #ifdef TARGET_SPARC64
 850     {
 851         gen_op_eval_bn,
 852         gen_op_eval_fbne_fcc1,
 853         gen_op_eval_fblg_fcc1,
 854         gen_op_eval_fbul_fcc1,
 855         gen_op_eval_fbl_fcc1,
 856         gen_op_eval_fbug_fcc1,
 857         gen_op_eval_fbg_fcc1,
 858         gen_op_eval_fbu_fcc1,
 859         gen_op_eval_ba,
 860         gen_op_eval_fbe_fcc1,
 861         gen_op_eval_fbue_fcc1,
 862         gen_op_eval_fbge_fcc1,
 863         gen_op_eval_fbuge_fcc1,
 864         gen_op_eval_fble_fcc1,
 865         gen_op_eval_fbule_fcc1,
 866         gen_op_eval_fbo_fcc1,
 867     },
 868     {
 869         gen_op_eval_bn,
 870         gen_op_eval_fbne_fcc2,
 871         gen_op_eval_fblg_fcc2,
 872         gen_op_eval_fbul_fcc2,
 873         gen_op_eval_fbl_fcc2,
 874         gen_op_eval_fbug_fcc2,
 875         gen_op_eval_fbg_fcc2,
 876         gen_op_eval_fbu_fcc2,
 877         gen_op_eval_ba,
 878         gen_op_eval_fbe_fcc2,
 879         gen_op_eval_fbue_fcc2,
 880         gen_op_eval_fbge_fcc2,
 881         gen_op_eval_fbuge_fcc2,
 882         gen_op_eval_fble_fcc2,
 883         gen_op_eval_fbule_fcc2,
 884         gen_op_eval_fbo_fcc2,
 885     },
 886     {
 887         gen_op_eval_bn,
 888         gen_op_eval_fbne_fcc3,
 889         gen_op_eval_fblg_fcc3,
 890         gen_op_eval_fbul_fcc3,
 891         gen_op_eval_fbl_fcc3,
 892         gen_op_eval_fbug_fcc3,
 893         gen_op_eval_fbg_fcc3,
 894         gen_op_eval_fbu_fcc3,
 895         gen_op_eval_ba,
 896         gen_op_eval_fbe_fcc3,
 897         gen_op_eval_fbue_fcc3,
 898         gen_op_eval_fbge_fcc3,
 899         gen_op_eval_fbuge_fcc3,
 900         gen_op_eval_fble_fcc3,
 901         gen_op_eval_fbule_fcc3,
 902         gen_op_eval_fbo_fcc3,
 903     },
 904 #else
 905     {}, {}, {},
 906 #endif
 907 };
 908
 909 #ifdef TARGET_SPARC64
 910 static void gen_cond_reg(int cond)
 911 {
 912         switch (cond) {
 913         case 0x1:
 914             gen_op_eval_brz();
 915             break;
 916         case 0x2:
 917             gen_op_eval_brlez();
 918             break;
 919         case 0x3:
 920             gen_op_eval_brlz();
 921             break;
 922         case 0x5:
 923             gen_op_eval_brnz();
 924             break;
 925         case 0x6:
 926             gen_op_eval_brgz();
 927             break;
 928         default:
 929         case 0x7:
 930             gen_op_eval_brgez();
 931             break;
 932         }
 933 }
 934 #endif
 935
 936 /* XXX: potentially incorrect if dynamic npc */
 937 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
 938 {
 939     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 940     target_ulong target = dc->pc + offset;
 941
 942     if (cond == 0x0) {
 943         /* unconditional not taken */
 944         if (a) {
 945             dc->pc = dc->npc + 4;
 946             dc->npc = dc->pc + 4;
 947         } else {
 948             dc->pc = dc->npc;
 949             dc->npc = dc->pc + 4;
 950         }
 951     } else if (cond == 0x8) {
 952         /* unconditional taken */
 953         if (a) {
 954             dc->pc = target;
 955             dc->npc = dc->pc + 4;
 956         } else {
 957             dc->pc = dc->npc;
 958             dc->npc = target;
 959         }
 960     } else {
 961         flush_T2(dc);
 962         gen_cond[cc][cond]();
 963         if (a) {
 964             gen_branch_a(dc, target, dc->npc);
 965             dc->is_br = 1;
 966         } else {
 967             dc->pc = dc->npc;
 968             dc->jump_pc[0] = target;
 969             dc->jump_pc[1] = dc->npc + 4;
 970             dc->npc = JUMP_PC;
 971         }
 972     }
 973 }
 974
 975 /* XXX: potentially incorrect if dynamic npc */
 976 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
 977 {
 978     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 979     target_ulong target = dc->pc + offset;
 980
 981     if (cond == 0x0) {
 982         /* unconditional not taken */
 983         if (a) {
 984             dc->pc = dc->npc + 4;
 985             dc->npc = dc->pc + 4;
 986         } else {
 987             dc->pc = dc->npc;
 988             dc->npc = dc->pc + 4;
 989         }
 990     } else if (cond == 0x8) {
 991         /* unconditional taken */
 992         if (a) {
 993             dc->pc = target;
 994             dc->npc = dc->pc + 4;
 995         } else {
 996             dc->pc = dc->npc;
 997             dc->npc = target;
 998         }
 999     } else {
1000         flush_T2(dc);
1001         gen_fcond[cc][cond]();
1002         if (a) {
1003             gen_branch_a(dc, target, dc->npc);
1004             dc->is_br = 1;
1005         } else {
1006             dc->pc = dc->npc;
1007             dc->jump_pc[0] = target;
1008             dc->jump_pc[1] = dc->npc + 4;
1009             dc->npc = JUMP_PC;
1010         }
1011     }
1012 }
1013
1014 #ifdef TARGET_SPARC64
1015 /* XXX: potentially incorrect if dynamic npc */
1016 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1017 {
1018     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1019     target_ulong target = dc->pc + offset;
1020
1021     flush_T2(dc);
1022     gen_cond_reg(cond);
1023     if (a) {
1024         gen_branch_a(dc, target, dc->npc);
1025         dc->is_br = 1;
1026     } else {
1027         dc->pc = dc->npc;
1028         dc->jump_pc[0] = target;
1029         dc->jump_pc[1] = dc->npc + 4;
1030         dc->npc = JUMP_PC;
1031     }
1032 }
1033
1034 static GenOpFunc * const gen_fcmps[4] = {
1035     gen_op_fcmps,
1036     gen_op_fcmps_fcc1,
1037     gen_op_fcmps_fcc2,
1038     gen_op_fcmps_fcc3,
1039 };
1040
1041 static GenOpFunc * const gen_fcmpd[4] = {
1042     gen_op_fcmpd,
1043     gen_op_fcmpd_fcc1,
1044     gen_op_fcmpd_fcc2,
1045     gen_op_fcmpd_fcc3,
1046 };
1047
1048 #if defined(CONFIG_USER_ONLY)
1049 static GenOpFunc * const gen_fcmpq[4] = {
1050     gen_op_fcmpq,
1051     gen_op_fcmpq_fcc1,
1052     gen_op_fcmpq_fcc2,
1053     gen_op_fcmpq_fcc3,
1054 };
1055 #endif
1056
1057 static GenOpFunc * const gen_fcmpes[4] = {
1058     gen_op_fcmpes,
1059     gen_op_fcmpes_fcc1,
1060     gen_op_fcmpes_fcc2,
1061     gen_op_fcmpes_fcc3,
1062 };
1063
1064 static GenOpFunc * const gen_fcmped[4] = {
1065     gen_op_fcmped,
1066     gen_op_fcmped_fcc1,
1067     gen_op_fcmped_fcc2,
1068     gen_op_fcmped_fcc3,
1069 };
1070
1071 #if defined(CONFIG_USER_ONLY)
1072 static GenOpFunc * const gen_fcmpeq[4] = {
1073     gen_op_fcmpeq,
1074     gen_op_fcmpeq_fcc1,
1075     gen_op_fcmpeq_fcc2,
1076     gen_op_fcmpeq_fcc3,
1077 };
1078 #endif
1079 #endif
1080
1081 static int gen_trap_ifnofpu(DisasContext * dc)
1082 {
1083 #if !defined(CONFIG_USER_ONLY)
1084     if (!dc->fpu_enabled) {
1085         save_state(dc);
1086         gen_op_exception(TT_NFPU_INSN);
1087         dc->is_br = 1;
1088         return 1;
1089     }
1090 #endif
1091     return 0;
1092 }
1093
1094 /* before an instruction, dc->pc must be static */
1095 static void disas_sparc_insn(DisasContext * dc)
1096 {
1097     unsigned int insn, opc, rs1, rs2, rd;
1098
1099     insn = ldl_code(dc->pc);
1100     opc = GET_FIELD(insn, 0, 1);
1101
1102     rd = GET_FIELD(insn, 2, 6);
1103     switch (opc) {
1104     case 0:                     /* branches/sethi */
1105         {
1106             unsigned int xop = GET_FIELD(insn, 7, 9);
1107             int32_t target;
1108             switch (xop) {
1109 #ifdef TARGET_SPARC64
1110             case 0x1:           /* V9 BPcc */
1111                 {
1112                     int cc;
1113
1114                     target = GET_FIELD_SP(insn, 0, 18);
1115                     target = sign_extend(target, 18);
1116                     target <<= 2;
1117                     cc = GET_FIELD_SP(insn, 20, 21);
1118                     if (cc == 0)
1119                         do_branch(dc, target, insn, 0);
1120                     else if (cc == 2)
1121                         do_branch(dc, target, insn, 1);
1122                     else
1123                         goto illegal_insn;
1124                     goto jmp_insn;
1125                 }
1126             case 0x3:           /* V9 BPr */
1127                 {
1128                     target = GET_FIELD_SP(insn, 0, 13) |
1129                         (GET_FIELD_SP(insn, 20, 21) << 14);
1130                     target = sign_extend(target, 16);
1131                     target <<= 2;
1132                     rs1 = GET_FIELD(insn, 13, 17);
1133                     gen_movl_reg_T0(rs1);
1134                     do_branch_reg(dc, target, insn);
1135                     goto jmp_insn;
1136                 }
1137             case 0x5:           /* V9 FBPcc */
1138                 {
1139                     int cc = GET_FIELD_SP(insn, 20, 21);
1140                     if (gen_trap_ifnofpu(dc))
1141                         goto jmp_insn;
1142                     target = GET_FIELD_SP(insn, 0, 18);
1143                     target = sign_extend(target, 19);
1144                     target <<= 2;
1145                     do_fbranch(dc, target, insn, cc);
1146                     goto jmp_insn;
1147                 }
1148 #else
1149             case 0x7:           /* CBN+x */
1150                 {
1151                     goto ncp_insn;
1152                 }
1153 #endif
1154             case 0x2:           /* BN+x */
1155                 {
1156                     target = GET_FIELD(insn, 10, 31);
1157                     target = sign_extend(target, 22);
1158                     target <<= 2;
1159                     do_branch(dc, target, insn, 0);
1160                     goto jmp_insn;
1161                 }
1162             case 0x6:           /* FBN+x */
1163                 {
1164                     if (gen_trap_ifnofpu(dc))
1165                         goto jmp_insn;
1166                     target = GET_FIELD(insn, 10, 31);
1167                     target = sign_extend(target, 22);
1168                     target <<= 2;
1169                     do_fbranch(dc, target, insn, 0);
1170                     goto jmp_insn;
1171                 }
1172             case 0x4:           /* SETHI */
1173 #define OPTIM
1174 #if defined(OPTIM)
1175                 if (rd) { // nop
1176 #endif
1177                     uint32_t value = GET_FIELD(insn, 10, 31);
1178                     gen_movl_imm_T0(value << 10);
1179                     gen_movl_T0_reg(rd);
1180 #if defined(OPTIM)
1181                 }
1182 #endif
1183                 break;
1184             case 0x0:           /* UNIMPL */
1185             default:
1186                 goto illegal_insn;
1187             }
1188             break;
1189         }
1190         break;
1191     case 1:
1192         /*CALL*/ {
1193             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1194
1195 #ifdef TARGET_SPARC64
1196             if (dc->pc == (uint32_t)dc->pc) {
1197                 gen_op_movl_T0_im(dc->pc);
1198             } else {
1199                 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1200             }
1201 #else
1202             gen_op_movl_T0_im(dc->pc);
1203 #endif
1204             gen_movl_T0_reg(15);
1205             target += dc->pc;
1206             gen_mov_pc_npc(dc);
1207             dc->npc = target;
1208         }
1209         goto jmp_insn;
1210     case 2:                     /* FPU & Logical Operations */
1211         {
1212             unsigned int xop = GET_FIELD(insn, 7, 12);
1213             if (xop == 0x3a) {  /* generate trap */
1214                 int cond;
1215
1216                 rs1 = GET_FIELD(insn, 13, 17);
1217                 gen_movl_reg_T0(rs1);
1218                 if (IS_IMM) {
1219                     rs2 = GET_FIELD(insn, 25, 31);
1220 #if defined(OPTIM)
1221                     if (rs2 != 0) {
1222 #endif
1223                         gen_movl_simm_T1(rs2);
1224                         gen_op_add_T1_T0();
1225 #if defined(OPTIM)
1226                     }
1227 #endif
1228                 } else {
1229                     rs2 = GET_FIELD(insn, 27, 31);
1230 #if defined(OPTIM)
1231                     if (rs2 != 0) {
1232 #endif
1233                         gen_movl_reg_T1(rs2);
1234                         gen_op_add_T1_T0();
1235 #if defined(OPTIM)
1236                     }
1237 #endif
1238                 }
1239                 cond = GET_FIELD(insn, 3, 6);
1240                 if (cond == 0x8) {
1241                     save_state(dc);
1242                     gen_op_trap_T0();
1243                 } else if (cond != 0) {
1244 #ifdef TARGET_SPARC64
1245                     /* V9 icc/xcc */
1246                     int cc = GET_FIELD_SP(insn, 11, 12);
1247                     flush_T2(dc);
1248                     save_state(dc);
1249                     if (cc == 0)
1250                         gen_cond[0][cond]();
1251                     else if (cc == 2)
1252                         gen_cond[1][cond]();
1253                     else
1254                         goto illegal_insn;
1255 #else
1256                     flush_T2(dc);
1257                     save_state(dc);
1258                     gen_cond[0][cond]();
1259 #endif
1260                     gen_op_trapcc_T0();
1261                 }
1262                 gen_op_next_insn();
1263                 tcg_gen_exit_tb(0);
1264                 dc->is_br = 1;
1265                 goto jmp_insn;
1266             } else if (xop == 0x28) {
1267                 rs1 = GET_FIELD(insn, 13, 17);
1268                 switch(rs1) {
1269                 case 0: /* rdy */
1270 #ifndef TARGET_SPARC64
1271                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1272                                        manual, rdy on the microSPARC
1273                                        II */
1274                 case 0x0f:          /* stbar in the SPARCv8 manual,
1275                                        rdy on the microSPARC II */
1276                 case 0x10 ... 0x1f: /* implementation-dependent in the
1277                                        SPARCv8 manual, rdy on the
1278                                        microSPARC II */
1279 #endif
1280                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1281                     gen_movl_T0_reg(rd);
1282                     break;
1283 #ifdef TARGET_SPARC64
1284                 case 0x2: /* V9 rdccr */
1285                     gen_op_rdccr();
1286                     gen_movl_T0_reg(rd);
1287                     break;
1288                 case 0x3: /* V9 rdasi */
1289                     gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1290                     gen_movl_T0_reg(rd);
1291                     break;
1292                 case 0x4: /* V9 rdtick */
1293                     gen_op_rdtick();
1294                     gen_movl_T0_reg(rd);
1295                     break;
1296                 case 0x5: /* V9 rdpc */
1297                     if (dc->pc == (uint32_t)dc->pc) {
1298                         gen_op_movl_T0_im(dc->pc);
1299                     } else {
1300                         gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1301                     }
1302                     gen_movl_T0_reg(rd);
1303                     break;
1304                 case 0x6: /* V9 rdfprs */
1305                     gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1306                     gen_movl_T0_reg(rd);
1307                     break;
1308                 case 0xf: /* V9 membar */
1309                     break; /* no effect */
1310                 case 0x13: /* Graphics Status */
1311                     if (gen_trap_ifnofpu(dc))
1312                         goto jmp_insn;
1313                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1314                     gen_movl_T0_reg(rd);
1315                     break;
1316                 case 0x17: /* Tick compare */
1317                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1318                     gen_movl_T0_reg(rd);
1319                     break;
1320                 case 0x18: /* System tick */
1321                     gen_op_rdstick();
1322                     gen_movl_T0_reg(rd);
1323                     break;
1324                 case 0x19: /* System tick compare */
1325                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1326                     gen_movl_T0_reg(rd);
1327                     break;
1328                 case 0x10: /* Performance Control */
1329                 case 0x11: /* Performance Instrumentation Counter */
1330                 case 0x12: /* Dispatch Control */
1331                 case 0x14: /* Softint set, WO */
1332                 case 0x15: /* Softint clear, WO */
1333                 case 0x16: /* Softint write */
1334 #endif
1335                 default:
1336                     goto illegal_insn;
1337                 }
1338 #if !defined(CONFIG_USER_ONLY)
1339             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1340 #ifndef TARGET_SPARC64
1341                 if (!supervisor(dc))
1342                     goto priv_insn;
1343                 gen_op_rdpsr();
1344 #else
1345                 if (!hypervisor(dc))
1346                     goto priv_insn;
1347                 rs1 = GET_FIELD(insn, 13, 17);
1348                 switch (rs1) {
1349                 case 0: // hpstate
1350                     // gen_op_rdhpstate();
1351                     break;
1352                 case 1: // htstate
1353                     // gen_op_rdhtstate();
1354                     break;
1355                 case 3: // hintp
1356                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1357                     break;
1358                 case 5: // htba
1359                     gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1360                     break;
1361                 case 6: // hver
1362                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1363                     break;
1364                 case 31: // hstick_cmpr
1365                     gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1366                     break;
1367                 default:
1368                     goto illegal_insn;
1369                 }
1370 #endif
1371                 gen_movl_T0_reg(rd);
1372                 break;
1373             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1374                 if (!supervisor(dc))
1375                     goto priv_insn;
1376 #ifdef TARGET_SPARC64
1377                 rs1 = GET_FIELD(insn, 13, 17);
1378                 switch (rs1) {
1379                 case 0: // tpc
1380                     gen_op_rdtpc();
1381                     break;
1382                 case 1: // tnpc
1383                     gen_op_rdtnpc();
1384                     break;
1385                 case 2: // tstate
1386                     gen_op_rdtstate();
1387                     break;
1388                 case 3: // tt
1389                     gen_op_rdtt();
1390                     break;
1391                 case 4: // tick
1392                     gen_op_rdtick();
1393                     break;
1394                 case 5: // tba
1395                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1396                     break;
1397                 case 6: // pstate
1398                     gen_op_rdpstate();
1399                     break;
1400                 case 7: // tl
1401                     gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1402                     break;
1403                 case 8: // pil
1404                     gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1405                     break;
1406                 case 9: // cwp
1407                     gen_op_rdcwp();
1408                     break;
1409                 case 10: // cansave
1410                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1411                     break;
1412                 case 11: // canrestore
1413                     gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1414                     break;
1415                 case 12: // cleanwin
1416                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1417                     break;
1418                 case 13: // otherwin
1419                     gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1420                     break;
1421                 case 14: // wstate
1422                     gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1423                     break;
1424                 case 16: // UA2005 gl
1425                     gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1426                     break;
1427                 case 26: // UA2005 strand status
1428                     if (!hypervisor(dc))
1429                         goto priv_insn;
1430                     gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1431                     break;
1432                 case 31: // ver
1433                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1434                     break;
1435                 case 15: // fq
1436                 default:
1437                     goto illegal_insn;
1438                 }
1439 #else
1440                 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1441 #endif
1442                 gen_movl_T0_reg(rd);
1443                 break;
1444             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1445 #ifdef TARGET_SPARC64
1446                 gen_op_flushw();
1447 #else
1448                 if (!supervisor(dc))
1449                     goto priv_insn;
1450                 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1451                 gen_movl_T0_reg(rd);
1452 #endif
1453                 break;
1454 #endif
1455             } else if (xop == 0x34) {   /* FPU Operations */
1456                 if (gen_trap_ifnofpu(dc))
1457                     goto jmp_insn;
1458                 gen_op_clear_ieee_excp_and_FTT();
1459                 rs1 = GET_FIELD(insn, 13, 17);
1460                 rs2 = GET_FIELD(insn, 27, 31);
1461                 xop = GET_FIELD(insn, 18, 26);
1462                 switch (xop) {
1463                     case 0x1: /* fmovs */
1464                         gen_op_load_fpr_FT0(rs2);
1465                         gen_op_store_FT0_fpr(rd);
1466                         break;
1467                     case 0x5: /* fnegs */
1468                         gen_op_load_fpr_FT1(rs2);
1469                         gen_op_fnegs();
1470                         gen_op_store_FT0_fpr(rd);
1471                         break;
1472                     case 0x9: /* fabss */
1473                         gen_op_load_fpr_FT1(rs2);
1474                         gen_op_fabss();
1475                         gen_op_store_FT0_fpr(rd);
1476                         break;
1477                     case 0x29: /* fsqrts */
1478                         gen_op_load_fpr_FT1(rs2);
1479                         gen_op_fsqrts();
1480                         gen_op_store_FT0_fpr(rd);
1481                         break;
1482                     case 0x2a: /* fsqrtd */
1483                         gen_op_load_fpr_DT1(DFPREG(rs2));
1484                         gen_op_fsqrtd();
1485                         gen_op_store_DT0_fpr(DFPREG(rd));
1486                         break;
1487                     case 0x2b: /* fsqrtq */
1488 #if defined(CONFIG_USER_ONLY)
1489                         gen_op_load_fpr_QT1(QFPREG(rs2));
1490                         gen_op_fsqrtq();
1491                         gen_op_store_QT0_fpr(QFPREG(rd));
1492                         break;
1493 #else
1494                         goto nfpu_insn;
1495 #endif
1496                     case 0x41:
1497                         gen_op_load_fpr_FT0(rs1);
1498                         gen_op_load_fpr_FT1(rs2);
1499                         gen_op_fadds();
1500                         gen_op_store_FT0_fpr(rd);
1501                         break;
1502                     case 0x42:
1503                         gen_op_load_fpr_DT0(DFPREG(rs1));
1504                         gen_op_load_fpr_DT1(DFPREG(rs2));
1505                         gen_op_faddd();
1506                         gen_op_store_DT0_fpr(DFPREG(rd));
1507                         break;
1508                     case 0x43: /* faddq */
1509 #if defined(CONFIG_USER_ONLY)
1510                         gen_op_load_fpr_QT0(QFPREG(rs1));
1511                         gen_op_load_fpr_QT1(QFPREG(rs2));
1512                         gen_op_faddq();
1513                         gen_op_store_QT0_fpr(QFPREG(rd));
1514                         break;
1515 #else
1516                         goto nfpu_insn;
1517 #endif
1518                     case 0x45:
1519                         gen_op_load_fpr_FT0(rs1);
1520                         gen_op_load_fpr_FT1(rs2);
1521                         gen_op_fsubs();
1522                         gen_op_store_FT0_fpr(rd);
1523                         break;
1524                     case 0x46:
1525                         gen_op_load_fpr_DT0(DFPREG(rs1));
1526                         gen_op_load_fpr_DT1(DFPREG(rs2));
1527                         gen_op_fsubd();
1528                         gen_op_store_DT0_fpr(DFPREG(rd));
1529                         break;
1530                     case 0x47: /* fsubq */
1531 #if defined(CONFIG_USER_ONLY)
1532                         gen_op_load_fpr_QT0(QFPREG(rs1));
1533                         gen_op_load_fpr_QT1(QFPREG(rs2));
1534                         gen_op_fsubq();
1535                         gen_op_store_QT0_fpr(QFPREG(rd));
1536                         break;
1537 #else
1538                         goto nfpu_insn;
1539 #endif
1540                     case 0x49:
1541                         gen_op_load_fpr_FT0(rs1);
1542                         gen_op_load_fpr_FT1(rs2);
1543                         gen_op_fmuls();
1544                         gen_op_store_FT0_fpr(rd);
1545                         break;
1546                     case 0x4a:
1547                         gen_op_load_fpr_DT0(DFPREG(rs1));
1548                         gen_op_load_fpr_DT1(DFPREG(rs2));
1549                         gen_op_fmuld();
1550                         gen_op_store_DT0_fpr(DFPREG(rd));
1551                         break;
1552                     case 0x4b: /* fmulq */
1553 #if defined(CONFIG_USER_ONLY)
1554                         gen_op_load_fpr_QT0(QFPREG(rs1));
1555                         gen_op_load_fpr_QT1(QFPREG(rs2));
1556                         gen_op_fmulq();
1557                         gen_op_store_QT0_fpr(QFPREG(rd));
1558                         break;
1559 #else
1560                         goto nfpu_insn;
1561 #endif
1562                     case 0x4d:
1563                         gen_op_load_fpr_FT0(rs1);
1564                         gen_op_load_fpr_FT1(rs2);
1565                         gen_op_fdivs();
1566                         gen_op_store_FT0_fpr(rd);
1567                         break;
1568                     case 0x4e:
1569                         gen_op_load_fpr_DT0(DFPREG(rs1));
1570                         gen_op_load_fpr_DT1(DFPREG(rs2));
1571                         gen_op_fdivd();
1572                         gen_op_store_DT0_fpr(DFPREG(rd));
1573                         break;
1574                     case 0x4f: /* fdivq */
1575 #if defined(CONFIG_USER_ONLY)
1576                         gen_op_load_fpr_QT0(QFPREG(rs1));
1577                         gen_op_load_fpr_QT1(QFPREG(rs2));
1578                         gen_op_fdivq();
1579                         gen_op_store_QT0_fpr(QFPREG(rd));
1580                         break;
1581 #else
1582                         goto nfpu_insn;
1583 #endif
1584                     case 0x69:
1585                         gen_op_load_fpr_FT0(rs1);
1586                         gen_op_load_fpr_FT1(rs2);
1587                         gen_op_fsmuld();
1588                         gen_op_store_DT0_fpr(DFPREG(rd));
1589                         break;
1590                     case 0x6e: /* fdmulq */
1591 #if defined(CONFIG_USER_ONLY)
1592                         gen_op_load_fpr_DT0(DFPREG(rs1));
1593                         gen_op_load_fpr_DT1(DFPREG(rs2));
1594                         gen_op_fdmulq();
1595                         gen_op_store_QT0_fpr(QFPREG(rd));
1596                         break;
1597 #else
1598                         goto nfpu_insn;
1599 #endif
1600                     case 0xc4:
1601                         gen_op_load_fpr_FT1(rs2);
1602                         gen_op_fitos();
1603                         gen_op_store_FT0_fpr(rd);
1604                         break;
1605                     case 0xc6:
1606                         gen_op_load_fpr_DT1(DFPREG(rs2));
1607                         gen_op_fdtos();
1608                         gen_op_store_FT0_fpr(rd);
1609                         break;
1610                     case 0xc7: /* fqtos */
1611 #if defined(CONFIG_USER_ONLY)
1612                         gen_op_load_fpr_QT1(QFPREG(rs2));
1613                         gen_op_fqtos();
1614                         gen_op_store_FT0_fpr(rd);
1615                         break;
1616 #else
1617                         goto nfpu_insn;
1618 #endif
1619                     case 0xc8:
1620                         gen_op_load_fpr_FT1(rs2);
1621                         gen_op_fitod();
1622                         gen_op_store_DT0_fpr(DFPREG(rd));
1623                         break;
1624                     case 0xc9:
1625                         gen_op_load_fpr_FT1(rs2);
1626                         gen_op_fstod();
1627                         gen_op_store_DT0_fpr(DFPREG(rd));
1628                         break;
1629                     case 0xcb: /* fqtod */
1630 #if defined(CONFIG_USER_ONLY)
1631                         gen_op_load_fpr_QT1(QFPREG(rs2));
1632                         gen_op_fqtod();
1633                         gen_op_store_DT0_fpr(DFPREG(rd));
1634                         break;
1635 #else
1636                         goto nfpu_insn;
1637 #endif
1638                     case 0xcc: /* fitoq */
1639 #if defined(CONFIG_USER_ONLY)
1640                         gen_op_load_fpr_FT1(rs2);
1641                         gen_op_fitoq();
1642                         gen_op_store_QT0_fpr(QFPREG(rd));
1643                         break;
1644 #else
1645                         goto nfpu_insn;
1646 #endif
1647                     case 0xcd: /* fstoq */
1648 #if defined(CONFIG_USER_ONLY)
1649                         gen_op_load_fpr_FT1(rs2);
1650                         gen_op_fstoq();
1651                         gen_op_store_QT0_fpr(QFPREG(rd));
1652                         break;
1653 #else
1654                         goto nfpu_insn;
1655 #endif
1656                     case 0xce: /* fdtoq */
1657 #if defined(CONFIG_USER_ONLY)
1658                         gen_op_load_fpr_DT1(DFPREG(rs2));
1659                         gen_op_fdtoq();
1660                         gen_op_store_QT0_fpr(QFPREG(rd));
1661                         break;
1662 #else
1663                         goto nfpu_insn;
1664 #endif
1665                     case 0xd1:
1666                         gen_op_load_fpr_FT1(rs2);
1667                         gen_op_fstoi();
1668                         gen_op_store_FT0_fpr(rd);
1669                         break;
1670                     case 0xd2:
1671                         gen_op_load_fpr_DT1(DFPREG(rs2));
1672                         gen_op_fdtoi();
1673                         gen_op_store_FT0_fpr(rd);
1674                         break;
1675                     case 0xd3: /* fqtoi */
1676 #if defined(CONFIG_USER_ONLY)
1677                         gen_op_load_fpr_QT1(QFPREG(rs2));
1678                         gen_op_fqtoi();
1679                         gen_op_store_FT0_fpr(rd);
1680                         break;
1681 #else
1682                         goto nfpu_insn;
1683 #endif
1684 #ifdef TARGET_SPARC64
1685                     case 0x2: /* V9 fmovd */
1686                         gen_op_load_fpr_DT0(DFPREG(rs2));
1687                         gen_op_store_DT0_fpr(DFPREG(rd));
1688                         break;
1689                     case 0x3: /* V9 fmovq */
1690 #if defined(CONFIG_USER_ONLY)
1691                         gen_op_load_fpr_QT0(QFPREG(rs2));
1692                         gen_op_store_QT0_fpr(QFPREG(rd));
1693                         break;
1694 #else
1695                         goto nfpu_insn;
1696 #endif
1697                     case 0x6: /* V9 fnegd */
1698                         gen_op_load_fpr_DT1(DFPREG(rs2));
1699                         gen_op_fnegd();
1700                         gen_op_store_DT0_fpr(DFPREG(rd));
1701                         break;
1702                     case 0x7: /* V9 fnegq */
1703 #if defined(CONFIG_USER_ONLY)
1704                         gen_op_load_fpr_QT1(QFPREG(rs2));
1705                         gen_op_fnegq();
1706                         gen_op_store_QT0_fpr(QFPREG(rd));
1707                         break;
1708 #else
1709                         goto nfpu_insn;
1710 #endif
1711                     case 0xa: /* V9 fabsd */
1712                         gen_op_load_fpr_DT1(DFPREG(rs2));
1713                         gen_op_fabsd();
1714                         gen_op_store_DT0_fpr(DFPREG(rd));
1715                         break;
1716                     case 0xb: /* V9 fabsq */
1717 #if defined(CONFIG_USER_ONLY)
1718                         gen_op_load_fpr_QT1(QFPREG(rs2));
1719                         gen_op_fabsq();
1720                         gen_op_store_QT0_fpr(QFPREG(rd));
1721                         break;
1722 #else
1723                         goto nfpu_insn;
1724 #endif
1725                     case 0x81: /* V9 fstox */
1726                         gen_op_load_fpr_FT1(rs2);
1727                         gen_op_fstox();
1728                         gen_op_store_DT0_fpr(DFPREG(rd));
1729                         break;
1730                     case 0x82: /* V9 fdtox */
1731                         gen_op_load_fpr_DT1(DFPREG(rs2));
1732                         gen_op_fdtox();
1733                         gen_op_store_DT0_fpr(DFPREG(rd));
1734                         break;
1735                     case 0x83: /* V9 fqtox */
1736 #if defined(CONFIG_USER_ONLY)
1737                         gen_op_load_fpr_QT1(QFPREG(rs2));
1738                         gen_op_fqtox();
1739                         gen_op_store_DT0_fpr(DFPREG(rd));
1740                         break;
1741 #else
1742                         goto nfpu_insn;
1743 #endif
1744                     case 0x84: /* V9 fxtos */
1745                         gen_op_load_fpr_DT1(DFPREG(rs2));
1746                         gen_op_fxtos();
1747                         gen_op_store_FT0_fpr(rd);
1748                         break;
1749                     case 0x88: /* V9 fxtod */
1750                         gen_op_load_fpr_DT1(DFPREG(rs2));
1751                         gen_op_fxtod();
1752                         gen_op_store_DT0_fpr(DFPREG(rd));
1753                         break;
1754                     case 0x8c: /* V9 fxtoq */
1755 #if defined(CONFIG_USER_ONLY)
1756                         gen_op_load_fpr_DT1(DFPREG(rs2));
1757                         gen_op_fxtoq();
1758                         gen_op_store_QT0_fpr(QFPREG(rd));
1759                         break;
1760 #else
1761                         goto nfpu_insn;
1762 #endif
1763 #endif
1764                     default:
1765                         goto illegal_insn;
1766                 }
1767             } else if (xop == 0x35) {   /* FPU Operations */
1768 #ifdef TARGET_SPARC64
1769                 int cond;
1770 #endif
1771                 if (gen_trap_ifnofpu(dc))
1772                     goto jmp_insn;
1773                 gen_op_clear_ieee_excp_and_FTT();
1774                 rs1 = GET_FIELD(insn, 13, 17);
1775                 rs2 = GET_FIELD(insn, 27, 31);
1776                 xop = GET_FIELD(insn, 18, 26);
1777 #ifdef TARGET_SPARC64
1778                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1779                     cond = GET_FIELD_SP(insn, 14, 17);
1780                     gen_op_load_fpr_FT0(rd);
1781                     gen_op_load_fpr_FT1(rs2);
1782                     rs1 = GET_FIELD(insn, 13, 17);
1783                     gen_movl_reg_T0(rs1);
1784                     flush_T2(dc);
1785                     gen_cond_reg(cond);
1786                     gen_op_fmovs_cc();
1787                     gen_op_store_FT0_fpr(rd);
1788                     break;
1789                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1790                     cond = GET_FIELD_SP(insn, 14, 17);
1791                     gen_op_load_fpr_DT0(DFPREG(rd));
1792                     gen_op_load_fpr_DT1(DFPREG(rs2));
1793                     flush_T2(dc);
1794                     rs1 = GET_FIELD(insn, 13, 17);
1795                     gen_movl_reg_T0(rs1);
1796                     gen_cond_reg(cond);
1797                     gen_op_fmovs_cc();
1798                     gen_op_store_DT0_fpr(DFPREG(rd));
1799                     break;
1800                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1801 #if defined(CONFIG_USER_ONLY)
1802                     cond = GET_FIELD_SP(insn, 14, 17);
1803                     gen_op_load_fpr_QT0(QFPREG(rd));
1804                     gen_op_load_fpr_QT1(QFPREG(rs2));
1805                     flush_T2(dc);
1806                     rs1 = GET_FIELD(insn, 13, 17);
1807                     gen_movl_reg_T0(rs1);
1808                     gen_cond_reg(cond);
1809                     gen_op_fmovq_cc();
1810                     gen_op_store_QT0_fpr(QFPREG(rd));
1811                     break;
1812 #else
1813                     goto nfpu_insn;
1814 #endif
1815                 }
1816 #endif
1817                 switch (xop) {
1818 #ifdef TARGET_SPARC64
1819                     case 0x001: /* V9 fmovscc %fcc0 */
1820                         cond = GET_FIELD_SP(insn, 14, 17);
1821                         gen_op_load_fpr_FT0(rd);
1822                         gen_op_load_fpr_FT1(rs2);
1823                         flush_T2(dc);
1824                         gen_fcond[0][cond]();
1825                         gen_op_fmovs_cc();
1826                         gen_op_store_FT0_fpr(rd);
1827                         break;
1828                     case 0x002: /* V9 fmovdcc %fcc0 */
1829                         cond = GET_FIELD_SP(insn, 14, 17);
1830                         gen_op_load_fpr_DT0(DFPREG(rd));
1831                         gen_op_load_fpr_DT1(DFPREG(rs2));
1832                         flush_T2(dc);
1833                         gen_fcond[0][cond]();
1834                         gen_op_fmovd_cc();
1835                         gen_op_store_DT0_fpr(DFPREG(rd));
1836                         break;
1837                     case 0x003: /* V9 fmovqcc %fcc0 */
1838 #if defined(CONFIG_USER_ONLY)
1839                         cond = GET_FIELD_SP(insn, 14, 17);
1840                         gen_op_load_fpr_QT0(QFPREG(rd));
1841                         gen_op_load_fpr_QT1(QFPREG(rs2));
1842                         flush_T2(dc);
1843                         gen_fcond[0][cond]();
1844                         gen_op_fmovq_cc();
1845                         gen_op_store_QT0_fpr(QFPREG(rd));
1846                         break;
1847 #else
1848                         goto nfpu_insn;
1849 #endif
1850                     case 0x041: /* V9 fmovscc %fcc1 */
1851                         cond = GET_FIELD_SP(insn, 14, 17);
1852                         gen_op_load_fpr_FT0(rd);
1853                         gen_op_load_fpr_FT1(rs2);
1854                         flush_T2(dc);
1855                         gen_fcond[1][cond]();
1856                         gen_op_fmovs_cc();
1857                         gen_op_store_FT0_fpr(rd);
1858                         break;
1859                     case 0x042: /* V9 fmovdcc %fcc1 */
1860                         cond = GET_FIELD_SP(insn, 14, 17);
1861                         gen_op_load_fpr_DT0(DFPREG(rd));
1862                         gen_op_load_fpr_DT1(DFPREG(rs2));
1863                         flush_T2(dc);
1864                         gen_fcond[1][cond]();
1865                         gen_op_fmovd_cc();
1866                         gen_op_store_DT0_fpr(DFPREG(rd));
1867                         break;
1868                     case 0x043: /* V9 fmovqcc %fcc1 */
1869 #if defined(CONFIG_USER_ONLY)
1870                         cond = GET_FIELD_SP(insn, 14, 17);
1871                         gen_op_load_fpr_QT0(QFPREG(rd));
1872                         gen_op_load_fpr_QT1(QFPREG(rs2));
1873                         flush_T2(dc);
1874                         gen_fcond[1][cond]();
1875                         gen_op_fmovq_cc();
1876                         gen_op_store_QT0_fpr(QFPREG(rd));
1877                         break;
1878 #else
1879                         goto nfpu_insn;
1880 #endif
1881                     case 0x081: /* V9 fmovscc %fcc2 */
1882                         cond = GET_FIELD_SP(insn, 14, 17);
1883                         gen_op_load_fpr_FT0(rd);
1884                         gen_op_load_fpr_FT1(rs2);
1885                         flush_T2(dc);
1886                         gen_fcond[2][cond]();
1887                         gen_op_fmovs_cc();
1888                         gen_op_store_FT0_fpr(rd);
1889                         break;
1890                     case 0x082: /* V9 fmovdcc %fcc2 */
1891                         cond = GET_FIELD_SP(insn, 14, 17);
1892                         gen_op_load_fpr_DT0(DFPREG(rd));
1893                         gen_op_load_fpr_DT1(DFPREG(rs2));
1894                         flush_T2(dc);
1895                         gen_fcond[2][cond]();
1896                         gen_op_fmovd_cc();
1897                         gen_op_store_DT0_fpr(DFPREG(rd));
1898                         break;
1899                     case 0x083: /* V9 fmovqcc %fcc2 */
1900 #if defined(CONFIG_USER_ONLY)
1901                         cond = GET_FIELD_SP(insn, 14, 17);
1902                         gen_op_load_fpr_QT0(rd);
1903                         gen_op_load_fpr_QT1(rs2);
1904                         flush_T2(dc);
1905                         gen_fcond[2][cond]();
1906                         gen_op_fmovq_cc();
1907                         gen_op_store_QT0_fpr(rd);
1908                         break;
1909 #else
1910                         goto nfpu_insn;
1911 #endif
1912                     case 0x0c1: /* V9 fmovscc %fcc3 */
1913                         cond = GET_FIELD_SP(insn, 14, 17);
1914                         gen_op_load_fpr_FT0(rd);
1915                         gen_op_load_fpr_FT1(rs2);
1916                         flush_T2(dc);
1917                         gen_fcond[3][cond]();
1918                         gen_op_fmovs_cc();
1919                         gen_op_store_FT0_fpr(rd);
1920                         break;
1921                     case 0x0c2: /* V9 fmovdcc %fcc3 */
1922                         cond = GET_FIELD_SP(insn, 14, 17);
1923                         gen_op_load_fpr_DT0(DFPREG(rd));
1924                         gen_op_load_fpr_DT1(DFPREG(rs2));
1925                         flush_T2(dc);
1926                         gen_fcond[3][cond]();
1927                         gen_op_fmovd_cc();
1928                         gen_op_store_DT0_fpr(DFPREG(rd));
1929                         break;
1930                     case 0x0c3: /* V9 fmovqcc %fcc3 */
1931 #if defined(CONFIG_USER_ONLY)
1932                         cond = GET_FIELD_SP(insn, 14, 17);
1933                         gen_op_load_fpr_QT0(QFPREG(rd));
1934                         gen_op_load_fpr_QT1(QFPREG(rs2));
1935                         flush_T2(dc);
1936                         gen_fcond[3][cond]();
1937                         gen_op_fmovq_cc();
1938                         gen_op_store_QT0_fpr(QFPREG(rd));
1939                         break;
1940 #else
1941                         goto nfpu_insn;
1942 #endif
1943                     case 0x101: /* V9 fmovscc %icc */
1944                         cond = GET_FIELD_SP(insn, 14, 17);
1945                         gen_op_load_fpr_FT0(rd);
1946                         gen_op_load_fpr_FT1(rs2);
1947                         flush_T2(dc);
1948                         gen_cond[0][cond]();
1949                         gen_op_fmovs_cc();
1950                         gen_op_store_FT0_fpr(rd);
1951                         break;
1952                     case 0x102: /* V9 fmovdcc %icc */
1953                         cond = GET_FIELD_SP(insn, 14, 17);
1954                         gen_op_load_fpr_DT0(DFPREG(rd));
1955                         gen_op_load_fpr_DT1(DFPREG(rs2));
1956                         flush_T2(dc);
1957                         gen_cond[0][cond]();
1958                         gen_op_fmovd_cc();
1959                         gen_op_store_DT0_fpr(DFPREG(rd));
1960                         break;
1961                     case 0x103: /* V9 fmovqcc %icc */
1962 #if defined(CONFIG_USER_ONLY)
1963                         cond = GET_FIELD_SP(insn, 14, 17);
1964                         gen_op_load_fpr_QT0(rd);
1965                         gen_op_load_fpr_QT1(rs2);
1966                         flush_T2(dc);
1967                         gen_cond[0][cond]();
1968                         gen_op_fmovq_cc();
1969                         gen_op_store_QT0_fpr(rd);
1970                         break;
1971 #else
1972                         goto nfpu_insn;
1973 #endif
1974                     case 0x181: /* V9 fmovscc %xcc */
1975                         cond = GET_FIELD_SP(insn, 14, 17);
1976                         gen_op_load_fpr_FT0(rd);
1977                         gen_op_load_fpr_FT1(rs2);
1978                         flush_T2(dc);
1979                         gen_cond[1][cond]();
1980                         gen_op_fmovs_cc();
1981                         gen_op_store_FT0_fpr(rd);
1982                         break;
1983                     case 0x182: /* V9 fmovdcc %xcc */
1984                         cond = GET_FIELD_SP(insn, 14, 17);
1985                         gen_op_load_fpr_DT0(DFPREG(rd));
1986                         gen_op_load_fpr_DT1(DFPREG(rs2));
1987                         flush_T2(dc);
1988                         gen_cond[1][cond]();
1989                         gen_op_fmovd_cc();
1990                         gen_op_store_DT0_fpr(DFPREG(rd));
1991                         break;
1992                     case 0x183: /* V9 fmovqcc %xcc */
1993 #if defined(CONFIG_USER_ONLY)
1994                         cond = GET_FIELD_SP(insn, 14, 17);
1995                         gen_op_load_fpr_QT0(rd);
1996                         gen_op_load_fpr_QT1(rs2);
1997                         flush_T2(dc);
1998                         gen_cond[1][cond]();
1999                         gen_op_fmovq_cc();
2000                         gen_op_store_QT0_fpr(rd);
2001                         break;
2002 #else
2003                         goto nfpu_insn;
2004 #endif
2005 #endif
2006                     case 0x51: /* fcmps, V9 %fcc */
2007                         gen_op_load_fpr_FT0(rs1);
2008                         gen_op_load_fpr_FT1(rs2);
2009 #ifdef TARGET_SPARC64
2010                         gen_fcmps[rd & 3]();
2011 #else
2012                         gen_op_fcmps();
2013 #endif
2014                         break;
2015                     case 0x52: /* fcmpd, V9 %fcc */
2016                         gen_op_load_fpr_DT0(DFPREG(rs1));
2017                         gen_op_load_fpr_DT1(DFPREG(rs2));
2018 #ifdef TARGET_SPARC64
2019                         gen_fcmpd[rd & 3]();
2020 #else
2021                         gen_op_fcmpd();
2022 #endif
2023                         break;
2024                     case 0x53: /* fcmpq, V9 %fcc */
2025 #if defined(CONFIG_USER_ONLY)
2026                         gen_op_load_fpr_QT0(QFPREG(rs1));
2027                         gen_op_load_fpr_QT1(QFPREG(rs2));
2028 #ifdef TARGET_SPARC64
2029                         gen_fcmpq[rd & 3]();
2030 #else
2031                         gen_op_fcmpq();
2032 #endif
2033                         break;
2034 #else /* !defined(CONFIG_USER_ONLY) */
2035                         goto nfpu_insn;
2036 #endif
2037                     case 0x55: /* fcmpes, V9 %fcc */
2038                         gen_op_load_fpr_FT0(rs1);
2039                         gen_op_load_fpr_FT1(rs2);
2040 #ifdef TARGET_SPARC64
2041                         gen_fcmpes[rd & 3]();
2042 #else
2043                         gen_op_fcmpes();
2044 #endif
2045                         break;
2046                     case 0x56: /* fcmped, V9 %fcc */
2047                         gen_op_load_fpr_DT0(DFPREG(rs1));
2048                         gen_op_load_fpr_DT1(DFPREG(rs2));
2049 #ifdef TARGET_SPARC64
2050                         gen_fcmped[rd & 3]();
2051 #else
2052                         gen_op_fcmped();
2053 #endif
2054                         break;
2055                     case 0x57: /* fcmpeq, V9 %fcc */
2056 #if defined(CONFIG_USER_ONLY)
2057                         gen_op_load_fpr_QT0(QFPREG(rs1));
2058                         gen_op_load_fpr_QT1(QFPREG(rs2));
2059 #ifdef TARGET_SPARC64
2060                         gen_fcmpeq[rd & 3]();
2061 #else
2062                         gen_op_fcmpeq();
2063 #endif
2064                         break;
2065 #else/* !defined(CONFIG_USER_ONLY) */
2066                         goto nfpu_insn;
2067 #endif
2068                     default:
2069                         goto illegal_insn;
2070                 }
2071 #if defined(OPTIM)
2072             } else if (xop == 0x2) {
2073                 // clr/mov shortcut
2074
2075                 rs1 = GET_FIELD(insn, 13, 17);
2076                 if (rs1 == 0) {
2077                     // or %g0, x, y -> mov T1, x; mov y, T1
2078                     if (IS_IMM) {       /* immediate */
2079                         rs2 = GET_FIELDs(insn, 19, 31);
2080                         gen_movl_simm_T1(rs2);
2081                     } else {            /* register */
2082                         rs2 = GET_FIELD(insn, 27, 31);
2083                         gen_movl_reg_T1(rs2);
2084                     }
2085                     gen_movl_T1_reg(rd);
2086                 } else {
2087                     gen_movl_reg_T0(rs1);
2088                     if (IS_IMM) {       /* immediate */
2089                         // or x, #0, y -> mov T1, x; mov y, T1
2090                         rs2 = GET_FIELDs(insn, 19, 31);
2091                         if (rs2 != 0) {
2092                             gen_movl_simm_T1(rs2);
2093                             gen_op_or_T1_T0();
2094                         }
2095                     } else {            /* register */
2096                         // or x, %g0, y -> mov T1, x; mov y, T1
2097                         rs2 = GET_FIELD(insn, 27, 31);
2098                         if (rs2 != 0) {
2099                             gen_movl_reg_T1(rs2);
2100                             gen_op_or_T1_T0();
2101                         }
2102                     }
2103                     gen_movl_T0_reg(rd);
2104                 }
2105 #endif
2106 #ifdef TARGET_SPARC64
2107             } else if (xop == 0x25) { /* sll, V9 sllx */
2108                 rs1 = GET_FIELD(insn, 13, 17);
2109                 gen_movl_reg_T0(rs1);
2110                 if (IS_IMM) {   /* immediate */
2111                     rs2 = GET_FIELDs(insn, 20, 31);
2112                     gen_movl_simm_T1(rs2);
2113                 } else {                /* register */
2114                     rs2 = GET_FIELD(insn, 27, 31);
2115                     gen_movl_reg_T1(rs2);
2116                 }
2117                 if (insn & (1 << 12))
2118                     gen_op_sllx();
2119                 else
2120                     gen_op_sll();
2121                 gen_movl_T0_reg(rd);
2122             } else if (xop == 0x26) { /* srl, V9 srlx */
2123                 rs1 = GET_FIELD(insn, 13, 17);
2124                 gen_movl_reg_T0(rs1);
2125                 if (IS_IMM) {   /* immediate */
2126                     rs2 = GET_FIELDs(insn, 20, 31);
2127                     gen_movl_simm_T1(rs2);
2128                 } else {                /* register */
2129                     rs2 = GET_FIELD(insn, 27, 31);
2130                     gen_movl_reg_T1(rs2);
2131                 }
2132                 if (insn & (1 << 12))
2133                     gen_op_srlx();
2134                 else
2135                     gen_op_srl();
2136                 gen_movl_T0_reg(rd);
2137             } else if (xop == 0x27) { /* sra, V9 srax */
2138                 rs1 = GET_FIELD(insn, 13, 17);
2139                 gen_movl_reg_T0(rs1);
2140                 if (IS_IMM) {   /* immediate */
2141                     rs2 = GET_FIELDs(insn, 20, 31);
2142                     gen_movl_simm_T1(rs2);
2143                 } else {                /* register */
2144                     rs2 = GET_FIELD(insn, 27, 31);
2145                     gen_movl_reg_T1(rs2);
2146                 }
2147                 if (insn & (1 << 12))
2148                     gen_op_srax();
2149                 else
2150                     gen_op_sra();
2151                 gen_movl_T0_reg(rd);
2152 #endif
2153             } else if (xop < 0x36) {
2154                 rs1 = GET_FIELD(insn, 13, 17);
2155                 gen_movl_reg_T0(rs1);
2156                 if (IS_IMM) {   /* immediate */
2157                     rs2 = GET_FIELDs(insn, 19, 31);
2158                     gen_movl_simm_T1(rs2);
2159                 } else {                /* register */
2160                     rs2 = GET_FIELD(insn, 27, 31);
2161                     gen_movl_reg_T1(rs2);
2162                 }
2163                 if (xop < 0x20) {
2164                     switch (xop & ~0x10) {
2165                     case 0x0:
2166                         if (xop & 0x10)
2167                             gen_op_add_T1_T0_cc();
2168                         else
2169                             gen_op_add_T1_T0();
2170                         break;
2171                     case 0x1:
2172                         gen_op_and_T1_T0();
2173                         if (xop & 0x10)
2174                             gen_op_logic_T0_cc();
2175                         break;
2176                     case 0x2:
2177                         gen_op_or_T1_T0();
2178                         if (xop & 0x10)
2179                             gen_op_logic_T0_cc();
2180                         break;
2181                     case 0x3:
2182                         gen_op_xor_T1_T0();
2183                         if (xop & 0x10)
2184                             gen_op_logic_T0_cc();
2185                         break;
2186                     case 0x4:
2187                         if (xop & 0x10)
2188                             gen_op_sub_T1_T0_cc();
2189                         else
2190                             gen_op_sub_T1_T0();
2191                         break;
2192                     case 0x5:
2193                         gen_op_andn_T1_T0();
2194                         if (xop & 0x10)
2195                             gen_op_logic_T0_cc();
2196                         break;
2197                     case 0x6:
2198                         gen_op_orn_T1_T0();
2199                         if (xop & 0x10)
2200                             gen_op_logic_T0_cc();
2201                         break;
2202                     case 0x7:
2203                         gen_op_xnor_T1_T0();
2204                         if (xop & 0x10)
2205                             gen_op_logic_T0_cc();
2206                         break;
2207                     case 0x8:
2208                         if (xop & 0x10)
2209                             gen_op_addx_T1_T0_cc();
2210                         else
2211                             gen_op_addx_T1_T0();
2212                         break;
2213 #ifdef TARGET_SPARC64
2214                     case 0x9: /* V9 mulx */
2215                         gen_op_mulx_T1_T0();
2216                         break;
2217 #endif
2218                     case 0xa:
2219                         gen_op_umul_T1_T0();
2220                         if (xop & 0x10)
2221                             gen_op_logic_T0_cc();
2222                         break;
2223                     case 0xb:
2224                         gen_op_smul_T1_T0();
2225                         if (xop & 0x10)
2226                             gen_op_logic_T0_cc();
2227                         break;
2228                     case 0xc:
2229                         if (xop & 0x10)
2230                             gen_op_subx_T1_T0_cc();
2231                         else
2232                             gen_op_subx_T1_T0();
2233                         break;
2234 #ifdef TARGET_SPARC64
2235                     case 0xd: /* V9 udivx */
2236                         gen_op_udivx_T1_T0();
2237                         break;
2238 #endif
2239                     case 0xe:
2240                         gen_op_udiv_T1_T0();
2241                         if (xop & 0x10)
2242                             gen_op_div_cc();
2243                         break;
2244                     case 0xf:
2245                         gen_op_sdiv_T1_T0();
2246                         if (xop & 0x10)
2247                             gen_op_div_cc();
2248                         break;
2249                     default:
2250                         goto illegal_insn;
2251                     }
2252                     gen_movl_T0_reg(rd);
2253                 } else {
2254                     switch (xop) {
2255                     case 0x20: /* taddcc */
2256                         gen_op_tadd_T1_T0_cc();
2257                         gen_movl_T0_reg(rd);
2258                         break;
2259                     case 0x21: /* tsubcc */
2260                         gen_op_tsub_T1_T0_cc();
2261                         gen_movl_T0_reg(rd);
2262                         break;
2263                     case 0x22: /* taddcctv */
2264                         save_state(dc);
2265                         gen_op_tadd_T1_T0_ccTV();
2266                         gen_movl_T0_reg(rd);
2267                         break;
2268                     case 0x23: /* tsubcctv */
2269                         save_state(dc);
2270                         gen_op_tsub_T1_T0_ccTV();
2271                         gen_movl_T0_reg(rd);
2272                         break;
2273                     case 0x24: /* mulscc */
2274                         gen_op_mulscc_T1_T0();
2275                         gen_movl_T0_reg(rd);
2276                         break;
2277 #ifndef TARGET_SPARC64
2278                     case 0x25:  /* sll */
2279                         gen_op_sll();
2280                         gen_movl_T0_reg(rd);
2281                         break;
2282                     case 0x26:  /* srl */
2283                         gen_op_srl();
2284                         gen_movl_T0_reg(rd);
2285                         break;
2286                     case 0x27:  /* sra */
2287                         gen_op_sra();
2288                         gen_movl_T0_reg(rd);
2289                         break;
2290 #endif
2291                     case 0x30:
2292                         {
2293                             switch(rd) {
2294                             case 0: /* wry */
2295                                 gen_op_xor_T1_T0();
2296                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
2297                                 break;
2298 #ifndef TARGET_SPARC64
2299                             case 0x01 ... 0x0f: /* undefined in the
2300                                                    SPARCv8 manual, nop
2301                                                    on the microSPARC
2302                                                    II */
2303                             case 0x10 ... 0x1f: /* implementation-dependent
2304                                                    in the SPARCv8
2305                                                    manual, nop on the
2306                                                    microSPARC II */
2307                                 break;
2308 #else
2309                             case 0x2: /* V9 wrccr */
2310                                 gen_op_xor_T1_T0();
2311                                 gen_op_wrccr();
2312                                 break;
2313                             case 0x3: /* V9 wrasi */
2314                                 gen_op_xor_T1_T0();
2315                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
2316                                 break;
2317                             case 0x6: /* V9 wrfprs */
2318                                 gen_op_xor_T1_T0();
2319                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
2320                                 save_state(dc);
2321                                 gen_op_next_insn();
2322                                 tcg_gen_exit_tb(0);
2323                                 dc->is_br = 1;
2324                                 break;
2325                             case 0xf: /* V9 sir, nop if user */
2326 #if !defined(CONFIG_USER_ONLY)
2327                                 if (supervisor(dc))
2328                                     gen_op_sir();
2329 #endif
2330                                 break;
2331                             case 0x13: /* Graphics Status */
2332                                 if (gen_trap_ifnofpu(dc))
2333                                     goto jmp_insn;
2334                                 gen_op_xor_T1_T0();
2335                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
2336                                 break;
2337                             case 0x17: /* Tick compare */
2338 #if !defined(CONFIG_USER_ONLY)
2339                                 if (!supervisor(dc))
2340                                     goto illegal_insn;
2341 #endif
2342                                 gen_op_xor_T1_T0();
2343                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2344                                 gen_op_wrtick_cmpr();
2345                                 break;
2346                             case 0x18: /* System tick */
2347 #if !defined(CONFIG_USER_ONLY)
2348                                 if (!supervisor(dc))
2349                                     goto illegal_insn;
2350 #endif
2351                                 gen_op_xor_T1_T0();
2352                                 gen_op_wrstick();
2353                                 break;
2354                             case 0x19: /* System tick compare */
2355 #if !defined(CONFIG_USER_ONLY)
2356                                 if (!supervisor(dc))
2357                                     goto illegal_insn;
2358 #endif
2359                                 gen_op_xor_T1_T0();
2360                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2361                                 gen_op_wrstick_cmpr();
2362                                 break;
2363
2364                             case 0x10: /* Performance Control */
2365                             case 0x11: /* Performance Instrumentation Counter */
2366                             case 0x12: /* Dispatch Control */
2367                             case 0x14: /* Softint set */
2368                             case 0x15: /* Softint clear */
2369                             case 0x16: /* Softint write */
2370 #endif
2371                             default:
2372                                 goto illegal_insn;
2373                             }
2374                         }
2375                         break;
2376 #if !defined(CONFIG_USER_ONLY)
2377                     case 0x31: /* wrpsr, V9 saved, restored */
2378                         {
2379                             if (!supervisor(dc))
2380                                 goto priv_insn;
2381 #ifdef TARGET_SPARC64
2382                             switch (rd) {
2383                             case 0:
2384                                 gen_op_saved();
2385                                 break;
2386                             case 1:
2387                                 gen_op_restored();
2388                                 break;
2389                             case 2: /* UA2005 allclean */
2390                             case 3: /* UA2005 otherw */
2391                             case 4: /* UA2005 normalw */
2392                             case 5: /* UA2005 invalw */
2393                                 // XXX
2394                             default:
2395                                 goto illegal_insn;
2396                             }
2397 #else
2398                             gen_op_xor_T1_T0();
2399                             gen_op_wrpsr();
2400                             save_state(dc);
2401                             gen_op_next_insn();
2402                             tcg_gen_exit_tb(0);
2403                             dc->is_br = 1;
2404 #endif
2405                         }
2406                         break;
2407                     case 0x32: /* wrwim, V9 wrpr */
2408                         {
2409                             if (!supervisor(dc))
2410                                 goto priv_insn;
2411                             gen_op_xor_T1_T0();
2412 #ifdef TARGET_SPARC64
2413                             switch (rd) {
2414                             case 0: // tpc
2415                                 gen_op_wrtpc();
2416                                 break;
2417                             case 1: // tnpc
2418                                 gen_op_wrtnpc();
2419                                 break;
2420                             case 2: // tstate
2421                                 gen_op_wrtstate();
2422                                 break;
2423                             case 3: // tt
2424                                 gen_op_wrtt();
2425                                 break;
2426                             case 4: // tick
2427                                 gen_op_wrtick();
2428                                 break;
2429                             case 5: // tba
2430                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2431                                 break;
2432                             case 6: // pstate
2433                                 gen_op_wrpstate();
2434                                 save_state(dc);
2435                                 gen_op_next_insn();
2436                                 tcg_gen_exit_tb(0);
2437                                 dc->is_br = 1;
2438                                 break;
2439                             case 7: // tl
2440                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2441                                 break;
2442                             case 8: // pil
2443                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2444                                 break;
2445                             case 9: // cwp
2446                                 gen_op_wrcwp();
2447                                 break;
2448                             case 10: // cansave
2449                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2450                                 break;
2451                             case 11: // canrestore
2452                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2453                                 break;
2454                             case 12: // cleanwin
2455                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2456                                 break;
2457                             case 13: // otherwin
2458                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2459                                 break;
2460                             case 14: // wstate
2461                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2462                                 break;
2463                             case 16: // UA2005 gl
2464                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2465                                 break;
2466                             case 26: // UA2005 strand status
2467                                 if (!hypervisor(dc))
2468                                     goto priv_insn;
2469                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2470                                 break;
2471                             default:
2472                                 goto illegal_insn;
2473                             }
2474 #else
2475                             gen_op_wrwim();
2476 #endif
2477                         }
2478                         break;
2479                     case 0x33: /* wrtbr, UA2005 wrhpr */
2480                         {
2481 #ifndef TARGET_SPARC64
2482                             if (!supervisor(dc))
2483                                 goto priv_insn;
2484                             gen_op_xor_T1_T0();
2485                             gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2486 #else
2487                             if (!hypervisor(dc))
2488                                 goto priv_insn;
2489                             gen_op_xor_T1_T0();
2490                             switch (rd) {
2491                             case 0: // hpstate
2492                                 // XXX gen_op_wrhpstate();
2493                                 save_state(dc);
2494                                 gen_op_next_insn();
2495                                 tcg_gen_exit_tb(0);
2496                                 dc->is_br = 1;
2497                                 break;
2498                             case 1: // htstate
2499                                 // XXX gen_op_wrhtstate();
2500                                 break;
2501                             case 3: // hintp
2502                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2503                                 break;
2504                             case 5: // htba
2505                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2506                                 break;
2507                             case 31: // hstick_cmpr
2508                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2509                                 gen_op_wrhstick_cmpr();
2510                                 break;
2511                             case 6: // hver readonly
2512                             default:
2513                                 goto illegal_insn;
2514                             }
2515 #endif
2516                         }
2517                         break;
2518 #endif
2519 #ifdef TARGET_SPARC64
2520                     case 0x2c: /* V9 movcc */
2521                         {
2522                             int cc = GET_FIELD_SP(insn, 11, 12);
2523                             int cond = GET_FIELD_SP(insn, 14, 17);
2524                             if (IS_IMM) {       /* immediate */
2525                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
2526                                 gen_movl_simm_T1(rs2);
2527                             }
2528                             else {
2529                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2530                                 gen_movl_reg_T1(rs2);
2531                             }
2532                             gen_movl_reg_T0(rd);
2533                             flush_T2(dc);
2534                             if (insn & (1 << 18)) {
2535                                 if (cc == 0)
2536                                     gen_cond[0][cond]();
2537                                 else if (cc == 2)
2538                                     gen_cond[1][cond]();
2539                                 else
2540                                     goto illegal_insn;
2541                             } else {
2542                                 gen_fcond[cc][cond]();
2543                             }
2544                             gen_op_mov_cc();
2545                             gen_movl_T0_reg(rd);
2546                             break;
2547                         }
2548                     case 0x2d: /* V9 sdivx */
2549                         gen_op_sdivx_T1_T0();
2550                         gen_movl_T0_reg(rd);
2551                         break;
2552                     case 0x2e: /* V9 popc */
2553                         {
2554                             if (IS_IMM) {       /* immediate */
2555                                 rs2 = GET_FIELD_SPs(insn, 0, 12);
2556                                 gen_movl_simm_T1(rs2);
2557                                 // XXX optimize: popc(constant)
2558                             }
2559                             else {
2560                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2561                                 gen_movl_reg_T1(rs2);
2562                             }
2563                             gen_op_popc();
2564                             gen_movl_T0_reg(rd);
2565                         }
2566                     case 0x2f: /* V9 movr */
2567                         {
2568                             int cond = GET_FIELD_SP(insn, 10, 12);
2569                             rs1 = GET_FIELD(insn, 13, 17);
2570                             flush_T2(dc);
2571                             gen_movl_reg_T0(rs1);
2572                             gen_cond_reg(cond);
2573                             if (IS_IMM) {       /* immediate */
2574                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
2575                                 gen_movl_simm_T1(rs2);
2576                             }
2577                             else {
2578                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2579                                 gen_movl_reg_T1(rs2);
2580                             }
2581                             gen_movl_reg_T0(rd);
2582                             gen_op_mov_cc();
2583                             gen_movl_T0_reg(rd);
2584                             break;
2585                         }
2586 #endif
2587                     default:
2588                         goto illegal_insn;
2589                     }
2590                 }
2591             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2592 #ifdef TARGET_SPARC64
2593                 int opf = GET_FIELD_SP(insn, 5, 13);
2594                 rs1 = GET_FIELD(insn, 13, 17);
2595                 rs2 = GET_FIELD(insn, 27, 31);
2596                 if (gen_trap_ifnofpu(dc))
2597                     goto jmp_insn;
2598
2599                 switch (opf) {
2600                 case 0x000: /* VIS I edge8cc */
2601                 case 0x001: /* VIS II edge8n */
2602                 case 0x002: /* VIS I edge8lcc */
2603                 case 0x003: /* VIS II edge8ln */
2604                 case 0x004: /* VIS I edge16cc */
2605                 case 0x005: /* VIS II edge16n */
2606                 case 0x006: /* VIS I edge16lcc */
2607                 case 0x007: /* VIS II edge16ln */
2608                 case 0x008: /* VIS I edge32cc */
2609                 case 0x009: /* VIS II edge32n */
2610                 case 0x00a: /* VIS I edge32lcc */
2611                 case 0x00b: /* VIS II edge32ln */
2612                     // XXX
2613                     goto illegal_insn;
2614                 case 0x010: /* VIS I array8 */
2615                     gen_movl_reg_T0(rs1);
2616                     gen_movl_reg_T1(rs2);
2617                     gen_op_array8();
2618                     gen_movl_T0_reg(rd);
2619                     break;
2620                 case 0x012: /* VIS I array16 */
2621                     gen_movl_reg_T0(rs1);
2622                     gen_movl_reg_T1(rs2);
2623                     gen_op_array16();
2624                     gen_movl_T0_reg(rd);
2625                     break;
2626                 case 0x014: /* VIS I array32 */
2627                     gen_movl_reg_T0(rs1);
2628                     gen_movl_reg_T1(rs2);
2629                     gen_op_array32();
2630                     gen_movl_T0_reg(rd);
2631                     break;
2632                 case 0x018: /* VIS I alignaddr */
2633                     gen_movl_reg_T0(rs1);
2634                     gen_movl_reg_T1(rs2);
2635                     gen_op_alignaddr();
2636                     gen_movl_T0_reg(rd);
2637                     break;
2638                 case 0x019: /* VIS II bmask */
2639                 case 0x01a: /* VIS I alignaddrl */
2640                     // XXX
2641                     goto illegal_insn;
2642                 case 0x020: /* VIS I fcmple16 */
2643                     gen_op_load_fpr_DT0(DFPREG(rs1));
2644                     gen_op_load_fpr_DT1(DFPREG(rs2));
2645                     gen_op_fcmple16();
2646                     gen_op_store_DT0_fpr(DFPREG(rd));
2647                     break;
2648                 case 0x022: /* VIS I fcmpne16 */
2649                     gen_op_load_fpr_DT0(DFPREG(rs1));
2650                     gen_op_load_fpr_DT1(DFPREG(rs2));
2651                     gen_op_fcmpne16();
2652                     gen_op_store_DT0_fpr(DFPREG(rd));
2653                     break;
2654                 case 0x024: /* VIS I fcmple32 */
2655                     gen_op_load_fpr_DT0(DFPREG(rs1));
2656                     gen_op_load_fpr_DT1(DFPREG(rs2));
2657                     gen_op_fcmple32();
2658                     gen_op_store_DT0_fpr(DFPREG(rd));
2659                     break;
2660                 case 0x026: /* VIS I fcmpne32 */
2661                     gen_op_load_fpr_DT0(DFPREG(rs1));
2662                     gen_op_load_fpr_DT1(DFPREG(rs2));
2663                     gen_op_fcmpne32();
2664                     gen_op_store_DT0_fpr(DFPREG(rd));
2665                     break;
2666                 case 0x028: /* VIS I fcmpgt16 */
2667                     gen_op_load_fpr_DT0(DFPREG(rs1));
2668                     gen_op_load_fpr_DT1(DFPREG(rs2));
2669                     gen_op_fcmpgt16();
2670                     gen_op_store_DT0_fpr(DFPREG(rd));
2671                     break;
2672                 case 0x02a: /* VIS I fcmpeq16 */
2673                     gen_op_load_fpr_DT0(DFPREG(rs1));
2674                     gen_op_load_fpr_DT1(DFPREG(rs2));
2675                     gen_op_fcmpeq16();
2676                     gen_op_store_DT0_fpr(DFPREG(rd));
2677                     break;
2678                 case 0x02c: /* VIS I fcmpgt32 */
2679                     gen_op_load_fpr_DT0(DFPREG(rs1));
2680                     gen_op_load_fpr_DT1(DFPREG(rs2));
2681                     gen_op_fcmpgt32();
2682                     gen_op_store_DT0_fpr(DFPREG(rd));
2683                     break;
2684                 case 0x02e: /* VIS I fcmpeq32 */
2685                     gen_op_load_fpr_DT0(DFPREG(rs1));
2686                     gen_op_load_fpr_DT1(DFPREG(rs2));
2687                     gen_op_fcmpeq32();
2688                     gen_op_store_DT0_fpr(DFPREG(rd));
2689                     break;
2690                 case 0x031: /* VIS I fmul8x16 */
2691                     gen_op_load_fpr_DT0(DFPREG(rs1));
2692                     gen_op_load_fpr_DT1(DFPREG(rs2));
2693                     gen_op_fmul8x16();
2694                     gen_op_store_DT0_fpr(DFPREG(rd));
2695                     break;
2696                 case 0x033: /* VIS I fmul8x16au */
2697                     gen_op_load_fpr_DT0(DFPREG(rs1));
2698                     gen_op_load_fpr_DT1(DFPREG(rs2));
2699                     gen_op_fmul8x16au();
2700                     gen_op_store_DT0_fpr(DFPREG(rd));
2701                     break;
2702                 case 0x035: /* VIS I fmul8x16al */
2703                     gen_op_load_fpr_DT0(DFPREG(rs1));
2704                     gen_op_load_fpr_DT1(DFPREG(rs2));
2705                     gen_op_fmul8x16al();
2706                     gen_op_store_DT0_fpr(DFPREG(rd));
2707                     break;
2708                 case 0x036: /* VIS I fmul8sux16 */
2709                     gen_op_load_fpr_DT0(DFPREG(rs1));
2710                     gen_op_load_fpr_DT1(DFPREG(rs2));
2711                     gen_op_fmul8sux16();
2712                     gen_op_store_DT0_fpr(DFPREG(rd));
2713                     break;
2714                 case 0x037: /* VIS I fmul8ulx16 */
2715                     gen_op_load_fpr_DT0(DFPREG(rs1));
2716                     gen_op_load_fpr_DT1(DFPREG(rs2));
2717                     gen_op_fmul8ulx16();
2718                     gen_op_store_DT0_fpr(DFPREG(rd));
2719                     break;
2720                 case 0x038: /* VIS I fmuld8sux16 */
2721                     gen_op_load_fpr_DT0(DFPREG(rs1));
2722                     gen_op_load_fpr_DT1(DFPREG(rs2));
2723                     gen_op_fmuld8sux16();
2724                     gen_op_store_DT0_fpr(DFPREG(rd));
2725                     break;
2726                 case 0x039: /* VIS I fmuld8ulx16 */
2727                     gen_op_load_fpr_DT0(DFPREG(rs1));
2728                     gen_op_load_fpr_DT1(DFPREG(rs2));
2729                     gen_op_fmuld8ulx16();
2730                     gen_op_store_DT0_fpr(DFPREG(rd));
2731                     break;
2732                 case 0x03a: /* VIS I fpack32 */
2733                 case 0x03b: /* VIS I fpack16 */
2734                 case 0x03d: /* VIS I fpackfix */
2735                 case 0x03e: /* VIS I pdist */
2736                     // XXX
2737                     goto illegal_insn;
2738                 case 0x048: /* VIS I faligndata */
2739                     gen_op_load_fpr_DT0(DFPREG(rs1));
2740                     gen_op_load_fpr_DT1(DFPREG(rs2));
2741                     gen_op_faligndata();
2742                     gen_op_store_DT0_fpr(DFPREG(rd));
2743                     break;
2744                 case 0x04b: /* VIS I fpmerge */
2745                     gen_op_load_fpr_DT0(DFPREG(rs1));
2746                     gen_op_load_fpr_DT1(DFPREG(rs2));
2747                     gen_op_fpmerge();
2748                     gen_op_store_DT0_fpr(DFPREG(rd));
2749                     break;
2750                 case 0x04c: /* VIS II bshuffle */
2751                     // XXX
2752                     goto illegal_insn;
2753                 case 0x04d: /* VIS I fexpand */
2754                     gen_op_load_fpr_DT0(DFPREG(rs1));
2755                     gen_op_load_fpr_DT1(DFPREG(rs2));
2756                     gen_op_fexpand();
2757                     gen_op_store_DT0_fpr(DFPREG(rd));
2758                     break;
2759                 case 0x050: /* VIS I fpadd16 */
2760                     gen_op_load_fpr_DT0(DFPREG(rs1));
2761                     gen_op_load_fpr_DT1(DFPREG(rs2));
2762                     gen_op_fpadd16();
2763                     gen_op_store_DT0_fpr(DFPREG(rd));
2764                     break;
2765                 case 0x051: /* VIS I fpadd16s */
2766                     gen_op_load_fpr_FT0(rs1);
2767                     gen_op_load_fpr_FT1(rs2);
2768                     gen_op_fpadd16s();
2769                     gen_op_store_FT0_fpr(rd);
2770                     break;
2771                 case 0x052: /* VIS I fpadd32 */
2772                     gen_op_load_fpr_DT0(DFPREG(rs1));
2773                     gen_op_load_fpr_DT1(DFPREG(rs2));
2774                     gen_op_fpadd32();
2775                     gen_op_store_DT0_fpr(DFPREG(rd));
2776                     break;
2777                 case 0x053: /* VIS I fpadd32s */
2778                     gen_op_load_fpr_FT0(rs1);
2779                     gen_op_load_fpr_FT1(rs2);
2780                     gen_op_fpadd32s();
2781                     gen_op_store_FT0_fpr(rd);
2782                     break;
2783                 case 0x054: /* VIS I fpsub16 */
2784                     gen_op_load_fpr_DT0(DFPREG(rs1));
2785                     gen_op_load_fpr_DT1(DFPREG(rs2));
2786                     gen_op_fpsub16();
2787                     gen_op_store_DT0_fpr(DFPREG(rd));
2788                     break;
2789                 case 0x055: /* VIS I fpsub16s */
2790                     gen_op_load_fpr_FT0(rs1);
2791                     gen_op_load_fpr_FT1(rs2);
2792                     gen_op_fpsub16s();
2793                     gen_op_store_FT0_fpr(rd);
2794                     break;
2795                 case 0x056: /* VIS I fpsub32 */
2796                     gen_op_load_fpr_DT0(DFPREG(rs1));
2797                     gen_op_load_fpr_DT1(DFPREG(rs2));
2798                     gen_op_fpadd32();
2799                     gen_op_store_DT0_fpr(DFPREG(rd));
2800                     break;
2801                 case 0x057: /* VIS I fpsub32s */
2802                     gen_op_load_fpr_FT0(rs1);
2803                     gen_op_load_fpr_FT1(rs2);
2804                     gen_op_fpsub32s();
2805                     gen_op_store_FT0_fpr(rd);
2806                     break;
2807                 case 0x060: /* VIS I fzero */
2808                     gen_op_movl_DT0_0();
2809                     gen_op_store_DT0_fpr(DFPREG(rd));
2810                     break;
2811                 case 0x061: /* VIS I fzeros */
2812                     gen_op_movl_FT0_0();
2813                     gen_op_store_FT0_fpr(rd);
2814                     break;
2815                 case 0x062: /* VIS I fnor */
2816                     gen_op_load_fpr_DT0(DFPREG(rs1));
2817                     gen_op_load_fpr_DT1(DFPREG(rs2));
2818                     gen_op_fnor();
2819                     gen_op_store_DT0_fpr(DFPREG(rd));
2820                     break;
2821                 case 0x063: /* VIS I fnors */
2822                     gen_op_load_fpr_FT0(rs1);
2823                     gen_op_load_fpr_FT1(rs2);
2824                     gen_op_fnors();
2825                     gen_op_store_FT0_fpr(rd);
2826                     break;
2827                 case 0x064: /* VIS I fandnot2 */
2828                     gen_op_load_fpr_DT1(DFPREG(rs1));
2829                     gen_op_load_fpr_DT0(DFPREG(rs2));
2830                     gen_op_fandnot();
2831                     gen_op_store_DT0_fpr(DFPREG(rd));
2832                     break;
2833                 case 0x065: /* VIS I fandnot2s */
2834                     gen_op_load_fpr_FT1(rs1);
2835                     gen_op_load_fpr_FT0(rs2);
2836                     gen_op_fandnots();
2837                     gen_op_store_FT0_fpr(rd);
2838                     break;
2839                 case 0x066: /* VIS I fnot2 */
2840                     gen_op_load_fpr_DT1(DFPREG(rs2));
2841                     gen_op_fnot();
2842                     gen_op_store_DT0_fpr(DFPREG(rd));
2843                     break;
2844                 case 0x067: /* VIS I fnot2s */
2845                     gen_op_load_fpr_FT1(rs2);
2846                     gen_op_fnot();
2847                     gen_op_store_FT0_fpr(rd);
2848                     break;
2849                 case 0x068: /* VIS I fandnot1 */
2850                     gen_op_load_fpr_DT0(DFPREG(rs1));
2851                     gen_op_load_fpr_DT1(DFPREG(rs2));
2852                     gen_op_fandnot();
2853                     gen_op_store_DT0_fpr(DFPREG(rd));
2854                     break;
2855                 case 0x069: /* VIS I fandnot1s */
2856                     gen_op_load_fpr_FT0(rs1);
2857                     gen_op_load_fpr_FT1(rs2);
2858                     gen_op_fandnots();
2859                     gen_op_store_FT0_fpr(rd);
2860                     break;
2861                 case 0x06a: /* VIS I fnot1 */
2862                     gen_op_load_fpr_DT1(DFPREG(rs1));
2863                     gen_op_fnot();
2864                     gen_op_store_DT0_fpr(DFPREG(rd));
2865                     break;
2866                 case 0x06b: /* VIS I fnot1s */
2867                     gen_op_load_fpr_FT1(rs1);
2868                     gen_op_fnot();
2869                     gen_op_store_FT0_fpr(rd);
2870                     break;
2871                 case 0x06c: /* VIS I fxor */
2872                     gen_op_load_fpr_DT0(DFPREG(rs1));
2873                     gen_op_load_fpr_DT1(DFPREG(rs2));
2874                     gen_op_fxor();
2875                     gen_op_store_DT0_fpr(DFPREG(rd));
2876                     break;
2877                 case 0x06d: /* VIS I fxors */
2878                     gen_op_load_fpr_FT0(rs1);
2879                     gen_op_load_fpr_FT1(rs2);
2880                     gen_op_fxors();
2881                     gen_op_store_FT0_fpr(rd);
2882                     break;
2883                 case 0x06e: /* VIS I fnand */
2884                     gen_op_load_fpr_DT0(DFPREG(rs1));
2885                     gen_op_load_fpr_DT1(DFPREG(rs2));
2886                     gen_op_fnand();
2887                     gen_op_store_DT0_fpr(DFPREG(rd));
2888                     break;
2889                 case 0x06f: /* VIS I fnands */
2890                     gen_op_load_fpr_FT0(rs1);
2891                     gen_op_load_fpr_FT1(rs2);
2892                     gen_op_fnands();
2893                     gen_op_store_FT0_fpr(rd);
2894                     break;
2895                 case 0x070: /* VIS I fand */
2896                     gen_op_load_fpr_DT0(DFPREG(rs1));
2897                     gen_op_load_fpr_DT1(DFPREG(rs2));
2898                     gen_op_fand();
2899                     gen_op_store_DT0_fpr(DFPREG(rd));
2900                     break;
2901                 case 0x071: /* VIS I fands */
2902                     gen_op_load_fpr_FT0(rs1);
2903                     gen_op_load_fpr_FT1(rs2);
2904                     gen_op_fands();
2905                     gen_op_store_FT0_fpr(rd);
2906                     break;
2907                 case 0x072: /* VIS I fxnor */
2908                     gen_op_load_fpr_DT0(DFPREG(rs1));
2909                     gen_op_load_fpr_DT1(DFPREG(rs2));
2910                     gen_op_fxnor();
2911                     gen_op_store_DT0_fpr(DFPREG(rd));
2912                     break;
2913                 case 0x073: /* VIS I fxnors */
2914                     gen_op_load_fpr_FT0(rs1);
2915                     gen_op_load_fpr_FT1(rs2);
2916                     gen_op_fxnors();
2917                     gen_op_store_FT0_fpr(rd);
2918                     break;
2919                 case 0x074: /* VIS I fsrc1 */
2920                     gen_op_load_fpr_DT0(DFPREG(rs1));
2921                     gen_op_store_DT0_fpr(DFPREG(rd));
2922                     break;
2923                 case 0x075: /* VIS I fsrc1s */
2924                     gen_op_load_fpr_FT0(rs1);
2925                     gen_op_store_FT0_fpr(rd);
2926                     break;
2927                 case 0x076: /* VIS I fornot2 */
2928                     gen_op_load_fpr_DT1(DFPREG(rs1));
2929                     gen_op_load_fpr_DT0(DFPREG(rs2));
2930                     gen_op_fornot();
2931                     gen_op_store_DT0_fpr(DFPREG(rd));
2932                     break;
2933                 case 0x077: /* VIS I fornot2s */
2934                     gen_op_load_fpr_FT1(rs1);
2935                     gen_op_load_fpr_FT0(rs2);
2936                     gen_op_fornots();
2937                     gen_op_store_FT0_fpr(rd);
2938                     break;
2939                 case 0x078: /* VIS I fsrc2 */
2940                     gen_op_load_fpr_DT0(DFPREG(rs2));
2941                     gen_op_store_DT0_fpr(DFPREG(rd));
2942                     break;
2943                 case 0x079: /* VIS I fsrc2s */
2944                     gen_op_load_fpr_FT0(rs2);
2945                     gen_op_store_FT0_fpr(rd);
2946                     break;
2947                 case 0x07a: /* VIS I fornot1 */
2948                     gen_op_load_fpr_DT0(DFPREG(rs1));
2949                     gen_op_load_fpr_DT1(DFPREG(rs2));
2950                     gen_op_fornot();
2951                     gen_op_store_DT0_fpr(DFPREG(rd));
2952                     break;
2953                 case 0x07b: /* VIS I fornot1s */
2954                     gen_op_load_fpr_FT0(rs1);
2955                     gen_op_load_fpr_FT1(rs2);
2956                     gen_op_fornots();
2957                     gen_op_store_FT0_fpr(rd);
2958                     break;
2959                 case 0x07c: /* VIS I for */
2960                     gen_op_load_fpr_DT0(DFPREG(rs1));
2961                     gen_op_load_fpr_DT1(DFPREG(rs2));
2962                     gen_op_for();
2963                     gen_op_store_DT0_fpr(DFPREG(rd));
2964                     break;
2965                 case 0x07d: /* VIS I fors */
2966                     gen_op_load_fpr_FT0(rs1);
2967                     gen_op_load_fpr_FT1(rs2);
2968                     gen_op_fors();
2969                     gen_op_store_FT0_fpr(rd);
2970                     break;
2971                 case 0x07e: /* VIS I fone */
2972                     gen_op_movl_DT0_1();
2973                     gen_op_store_DT0_fpr(DFPREG(rd));
2974                     break;
2975                 case 0x07f: /* VIS I fones */
2976                     gen_op_movl_FT0_1();
2977                     gen_op_store_FT0_fpr(rd);
2978                     break;
2979                 case 0x080: /* VIS I shutdown */
2980                 case 0x081: /* VIS II siam */
2981                     // XXX
2982                     goto illegal_insn;
2983                 default:
2984                     goto illegal_insn;
2985                 }
2986 #else
2987                 goto ncp_insn;
2988 #endif
2989             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2990 #ifdef TARGET_SPARC64
2991                 goto illegal_insn;
2992 #else
2993                 goto ncp_insn;
2994 #endif
2995 #ifdef TARGET_SPARC64
2996             } else if (xop == 0x39) { /* V9 return */
2997                 rs1 = GET_FIELD(insn, 13, 17);
2998                 save_state(dc);
2999                 gen_movl_reg_T0(rs1);
3000                 if (IS_IMM) {   /* immediate */
3001                     rs2 = GET_FIELDs(insn, 19, 31);
3002 #if defined(OPTIM)
3003                     if (rs2) {
3004 #endif
3005                         gen_movl_simm_T1(rs2);
3006                         gen_op_add_T1_T0();
3007 #if defined(OPTIM)
3008                     }
3009 #endif
3010                 } else {                /* register */
3011                     rs2 = GET_FIELD(insn, 27, 31);
3012 #if defined(OPTIM)
3013                     if (rs2) {
3014 #endif
3015                         gen_movl_reg_T1(rs2);
3016                         gen_op_add_T1_T0();
3017 #if defined(OPTIM)
3018                     }
3019 #endif
3020                 }
3021                 gen_op_restore();
3022                 gen_mov_pc_npc(dc);
3023                 gen_op_check_align_T0_3();
3024                 gen_op_movl_npc_T0();
3025                 dc->npc = DYNAMIC_PC;
3026                 goto jmp_insn;
3027 #endif
3028             } else {
3029                 rs1 = GET_FIELD(insn, 13, 17);
3030                 gen_movl_reg_T0(rs1);
3031                 if (IS_IMM) {   /* immediate */
3032                     rs2 = GET_FIELDs(insn, 19, 31);
3033 #if defined(OPTIM)
3034                     if (rs2) {
3035 #endif
3036                         gen_movl_simm_T1(rs2);
3037                         gen_op_add_T1_T0();
3038 #if defined(OPTIM)
3039                     }
3040 #endif
3041                 } else {                /* register */
3042                     rs2 = GET_FIELD(insn, 27, 31);
3043 #if defined(OPTIM)
3044                     if (rs2) {
3045 #endif
3046                         gen_movl_reg_T1(rs2);
3047                         gen_op_add_T1_T0();
3048 #if defined(OPTIM)
3049                     }
3050 #endif
3051                 }
3052                 switch (xop) {
3053                 case 0x38:      /* jmpl */
3054                     {
3055                         if (rd != 0) {
3056 #ifdef TARGET_SPARC64
3057                             if (dc->pc == (uint32_t)dc->pc) {
3058                                 gen_op_movl_T1_im(dc->pc);
3059                             } else {
3060                                 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
3061                             }
3062 #else
3063                             gen_op_movl_T1_im(dc->pc);
3064 #endif
3065                             gen_movl_T1_reg(rd);
3066                         }
3067                         gen_mov_pc_npc(dc);
3068                         gen_op_check_align_T0_3();
3069                         gen_op_movl_npc_T0();
3070                         dc->npc = DYNAMIC_PC;
3071                     }
3072                     goto jmp_insn;
3073 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3074                 case 0x39:      /* rett, V9 return */
3075                     {
3076                         if (!supervisor(dc))
3077                             goto priv_insn;
3078                         gen_mov_pc_npc(dc);
3079                         gen_op_check_align_T0_3();
3080                         gen_op_movl_npc_T0();
3081                         dc->npc = DYNAMIC_PC;
3082                         gen_op_rett();
3083                     }
3084                     goto jmp_insn;
3085 #endif
3086                 case 0x3b: /* flush */
3087                     gen_op_flush_T0();
3088                     break;
3089                 case 0x3c:      /* save */
3090                     save_state(dc);
3091                     gen_op_save();
3092                     gen_movl_T0_reg(rd);
3093                     break;
3094                 case 0x3d:      /* restore */
3095                     save_state(dc);
3096                     gen_op_restore();
3097                     gen_movl_T0_reg(rd);
3098                     break;
3099 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
3100                 case 0x3e:      /* V9 done/retry */
3101                     {
3102                         switch (rd) {
3103                         case 0:
3104                             if (!supervisor(dc))
3105                                 goto priv_insn;
3106                             dc->npc = DYNAMIC_PC;
3107                             dc->pc = DYNAMIC_PC;
3108                             gen_op_done();
3109                             goto jmp_insn;
3110                         case 1:
3111                             if (!supervisor(dc))
3112                                 goto priv_insn;
3113                             dc->npc = DYNAMIC_PC;
3114                             dc->pc = DYNAMIC_PC;
3115                             gen_op_retry();
3116                             goto jmp_insn;
3117                         default:
3118                             goto illegal_insn;
3119                         }
3120                     }
3121                     break;
3122 #endif
3123                 default:
3124                     goto illegal_insn;
3125                 }
3126             }
3127             break;
3128         }
3129         break;
3130     case 3:                     /* load/store instructions */
3131         {
3132             unsigned int xop = GET_FIELD(insn, 7, 12);
3133             rs1 = GET_FIELD(insn, 13, 17);
3134             save_state(dc);
3135             gen_movl_reg_T0(rs1);
3136             if (xop == 0x3c || xop == 0x3e)
3137             {
3138                 rs2 = GET_FIELD(insn, 27, 31);
3139                 gen_movl_reg_T1(rs2);
3140             }
3141             else if (IS_IMM) {       /* immediate */
3142                 rs2 = GET_FIELDs(insn, 19, 31);
3143 #if defined(OPTIM)
3144                 if (rs2 != 0) {
3145 #endif
3146                     gen_movl_simm_T1(rs2);
3147                     gen_op_add_T1_T0();
3148 #if defined(OPTIM)
3149                 }
3150 #endif
3151             } else {            /* register */
3152                 rs2 = GET_FIELD(insn, 27, 31);
3153 #if defined(OPTIM)
3154                 if (rs2 != 0) {
3155 #endif
3156                     gen_movl_reg_T1(rs2);
3157                     gen_op_add_T1_T0();
3158 #if defined(OPTIM)
3159                 }
3160 #endif
3161             }
3162             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
3163                 (xop > 0x17 && xop <= 0x1d ) ||
3164                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
3165                 switch (xop) {
3166                 case 0x0:       /* load word */
3167                     gen_op_check_align_T0_3();
3168 #ifndef TARGET_SPARC64
3169                     gen_op_ldst(ld);
3170 #else
3171                     gen_op_ldst(lduw);
3172 #endif
3173                     break;
3174                 case 0x1:       /* load unsigned byte */
3175                     gen_op_ldst(ldub);
3176                     break;
3177                 case 0x2:       /* load unsigned halfword */
3178                     gen_op_check_align_T0_1();
3179                     gen_op_ldst(lduh);
3180                     break;
3181                 case 0x3:       /* load double word */
3182                     if (rd & 1)
3183                         goto illegal_insn;
3184                     gen_op_check_align_T0_7();
3185                     gen_op_ldst(ldd);
3186                     gen_movl_T0_reg(rd + 1);
3187                     break;
3188                 case 0x9:       /* load signed byte */
3189                     gen_op_ldst(ldsb);
3190                     break;
3191                 case 0xa:       /* load signed halfword */
3192                     gen_op_check_align_T0_1();
3193                     gen_op_ldst(ldsh);
3194                     break;
3195                 case 0xd:       /* ldstub -- XXX: should be atomically */
3196                     gen_op_ldst(ldstub);
3197                     break;
3198                 case 0x0f:      /* swap register with memory. Also atomically */
3199                     gen_op_check_align_T0_3();
3200                     gen_movl_reg_T1(rd);
3201                     gen_op_ldst(swap);
3202                     break;
3203 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3204                 case 0x10:      /* load word alternate */
3205 #ifndef TARGET_SPARC64
3206                     if (IS_IMM)
3207                         goto illegal_insn;
3208                     if (!supervisor(dc))
3209                         goto priv_insn;
3210 #endif
3211                     gen_op_check_align_T0_3();
3212                     gen_ld_asi(insn, 4, 0);
3213                     break;
3214                 case 0x11:      /* load unsigned byte alternate */
3215 #ifndef TARGET_SPARC64
3216                     if (IS_IMM)
3217                         goto illegal_insn;
3218                     if (!supervisor(dc))
3219                         goto priv_insn;
3220 #endif
3221                     gen_ld_asi(insn, 1, 0);
3222                     break;
3223                 case 0x12:      /* load unsigned halfword alternate */
3224 #ifndef TARGET_SPARC64
3225                     if (IS_IMM)
3226                         goto illegal_insn;
3227                     if (!supervisor(dc))
3228                         goto priv_insn;
3229 #endif
3230                     gen_op_check_align_T0_1();
3231                     gen_ld_asi(insn, 2, 0);
3232                     break;
3233                 case 0x13:      /* load double word alternate */
3234 #ifndef TARGET_SPARC64
3235                     if (IS_IMM)
3236                         goto illegal_insn;
3237                     if (!supervisor(dc))
3238                         goto priv_insn;
3239 #endif
3240                     if (rd & 1)
3241                         goto illegal_insn;
3242                     gen_op_check_align_T0_7();
3243                     gen_ldda_asi(insn);
3244                     gen_movl_T0_reg(rd + 1);
3245                     break;
3246                 case 0x19:      /* load signed byte alternate */
3247 #ifndef TARGET_SPARC64
3248                     if (IS_IMM)
3249                         goto illegal_insn;
3250                     if (!supervisor(dc))
3251                         goto priv_insn;
3252 #endif
3253                     gen_ld_asi(insn, 1, 1);
3254                     break;
3255                 case 0x1a:      /* load signed halfword alternate */
3256 #ifndef TARGET_SPARC64
3257                     if (IS_IMM)
3258                         goto illegal_insn;
3259                     if (!supervisor(dc))
3260                         goto priv_insn;
3261 #endif
3262                     gen_op_check_align_T0_1();
3263                     gen_ld_asi(insn, 2, 1);
3264                     break;
3265                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
3266 #ifndef TARGET_SPARC64
3267                     if (IS_IMM)
3268                         goto illegal_insn;
3269                     if (!supervisor(dc))
3270                         goto priv_insn;
3271 #endif
3272                     gen_ldstub_asi(insn);
3273                     break;
3274                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
3275 #ifndef TARGET_SPARC64
3276                     if (IS_IMM)
3277                         goto illegal_insn;
3278                     if (!supervisor(dc))
3279                         goto priv_insn;
3280 #endif
3281                     gen_op_check_align_T0_3();
3282                     gen_movl_reg_T1(rd);
3283                     gen_swap_asi(insn);
3284                     break;
3285
3286 #ifndef TARGET_SPARC64
3287                 case 0x30: /* ldc */
3288                 case 0x31: /* ldcsr */
3289                 case 0x33: /* lddc */
3290                     goto ncp_insn;
3291 #endif
3292 #endif
3293 #ifdef TARGET_SPARC64
3294                 case 0x08: /* V9 ldsw */
3295                     gen_op_check_align_T0_3();
3296                     gen_op_ldst(ldsw);
3297                     break;
3298                 case 0x0b: /* V9 ldx */
3299                     gen_op_check_align_T0_7();
3300                     gen_op_ldst(ldx);
3301                     break;
3302                 case 0x18: /* V9 ldswa */
3303                     gen_op_check_align_T0_3();
3304                     gen_ld_asi(insn, 4, 1);
3305                     break;
3306                 case 0x1b: /* V9 ldxa */
3307                     gen_op_check_align_T0_7();
3308                     gen_ld_asi(insn, 8, 0);
3309                     break;
3310                 case 0x2d: /* V9 prefetch, no effect */
3311                     goto skip_move;
3312                 case 0x30: /* V9 ldfa */
3313                     gen_op_check_align_T0_3();
3314                     gen_ldf_asi(insn, 4, rd);
3315                     goto skip_move;
3316                 case 0x33: /* V9 lddfa */
3317                     gen_op_check_align_T0_3();
3318                     gen_ldf_asi(insn, 8, DFPREG(rd));
3319                     goto skip_move;
3320                 case 0x3d: /* V9 prefetcha, no effect */
3321                     goto skip_move;
3322                 case 0x32: /* V9 ldqfa */
3323 #if defined(CONFIG_USER_ONLY)
3324                     gen_op_check_align_T0_3();
3325                     gen_ldf_asi(insn, 16, QFPREG(rd));
3326                     goto skip_move;
3327 #else
3328                     goto nfpu_insn;
3329 #endif
3330 #endif
3331                 default:
3332                     goto illegal_insn;
3333                 }
3334                 gen_movl_T1_reg(rd);
3335 #ifdef TARGET_SPARC64
3336             skip_move: ;
3337 #endif
3338             } else if (xop >= 0x20 && xop < 0x24) {
3339                 if (gen_trap_ifnofpu(dc))
3340                     goto jmp_insn;
3341                 switch (xop) {
3342                 case 0x20:      /* load fpreg */
3343                     gen_op_check_align_T0_3();
3344                     gen_op_ldst(ldf);
3345                     gen_op_store_FT0_fpr(rd);
3346                     break;
3347                 case 0x21:      /* load fsr */
3348                     gen_op_check_align_T0_3();
3349                     gen_op_ldst(ldf);
3350                     gen_op_ldfsr();
3351                     break;
3352                 case 0x22:      /* load quad fpreg */
3353 #if defined(CONFIG_USER_ONLY)
3354                     gen_op_check_align_T0_7();
3355                     gen_op_ldst(ldqf);
3356                     gen_op_store_QT0_fpr(QFPREG(rd));
3357                     break;
3358 #else
3359                     goto nfpu_insn;
3360 #endif
3361                 case 0x23:      /* load double fpreg */
3362                     gen_op_check_align_T0_7();
3363                     gen_op_ldst(lddf);
3364                     gen_op_store_DT0_fpr(DFPREG(rd));
3365                     break;
3366                 default:
3367                     goto illegal_insn;
3368                 }
3369             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3370                        xop == 0xe || xop == 0x1e) {
3371                 gen_movl_reg_T1(rd);
3372                 switch (xop) {
3373                 case 0x4:
3374                     gen_op_check_align_T0_3();
3375                     gen_op_ldst(st);
3376                     break;
3377                 case 0x5:
3378                     gen_op_ldst(stb);
3379                     break;
3380                 case 0x6:
3381                     gen_op_check_align_T0_1();
3382                     gen_op_ldst(sth);
3383                     break;
3384                 case 0x7:
3385                     if (rd & 1)
3386                         goto illegal_insn;
3387                     gen_op_check_align_T0_7();
3388                     flush_T2(dc);
3389                     gen_movl_reg_T2(rd + 1);
3390                     gen_op_ldst(std);
3391                     break;
3392 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3393                 case 0x14:
3394 #ifndef TARGET_SPARC64
3395                     if (IS_IMM)
3396                         goto illegal_insn;
3397                     if (!supervisor(dc))
3398                         goto priv_insn;
3399 #endif
3400                     gen_op_check_align_T0_3();
3401                     gen_st_asi(insn, 4);
3402                     break;
3403                 case 0x15:
3404 #ifndef TARGET_SPARC64
3405                     if (IS_IMM)
3406                         goto illegal_insn;
3407                     if (!supervisor(dc))
3408                         goto priv_insn;
3409 #endif
3410                     gen_st_asi(insn, 1);
3411                     break;
3412                 case 0x16:
3413 #ifndef TARGET_SPARC64
3414                     if (IS_IMM)
3415                         goto illegal_insn;
3416                     if (!supervisor(dc))
3417                         goto priv_insn;
3418 #endif
3419                     gen_op_check_align_T0_1();
3420                     gen_st_asi(insn, 2);
3421                     break;
3422                 case 0x17:
3423 #ifndef TARGET_SPARC64
3424                     if (IS_IMM)
3425                         goto illegal_insn;
3426                     if (!supervisor(dc))
3427                         goto priv_insn;
3428 #endif
3429                     if (rd & 1)
3430                         goto illegal_insn;
3431                     gen_op_check_align_T0_7();
3432                     flush_T2(dc);
3433                     gen_movl_reg_T2(rd + 1);
3434                     gen_stda_asi(insn);
3435                     break;
3436 #endif
3437 #ifdef TARGET_SPARC64
3438                 case 0x0e: /* V9 stx */
3439                     gen_op_check_align_T0_7();
3440                     gen_op_ldst(stx);
3441                     break;
3442                 case 0x1e: /* V9 stxa */
3443                     gen_op_check_align_T0_7();
3444                     gen_st_asi(insn, 8);
3445                     break;
3446 #endif
3447                 default:
3448                     goto illegal_insn;
3449                 }
3450             } else if (xop > 0x23 && xop < 0x28) {
3451                 if (gen_trap_ifnofpu(dc))
3452                     goto jmp_insn;
3453                 switch (xop) {
3454                 case 0x24:
3455                     gen_op_check_align_T0_3();
3456                     gen_op_load_fpr_FT0(rd);
3457                     gen_op_ldst(stf);
3458                     break;
3459                 case 0x25: /* stfsr, V9 stxfsr */
3460 #ifdef CONFIG_USER_ONLY
3461                     gen_op_check_align_T0_3();
3462 #endif
3463                     gen_op_stfsr();
3464                     gen_op_ldst(stf);
3465                     break;
3466                 case 0x26:
3467 #ifdef TARGET_SPARC64
3468 #if defined(CONFIG_USER_ONLY)
3469                     /* V9 stqf, store quad fpreg */
3470                     gen_op_check_align_T0_7();
3471                     gen_op_load_fpr_QT0(QFPREG(rd));
3472                     gen_op_ldst(stqf);
3473                     break;
3474 #else
3475                     goto nfpu_insn;
3476 #endif
3477 #else /* !TARGET_SPARC64 */
3478                     /* stdfq, store floating point queue */
3479 #if defined(CONFIG_USER_ONLY)
3480                     goto illegal_insn;
3481 #else
3482                     if (!supervisor(dc))
3483                         goto priv_insn;
3484                     if (gen_trap_ifnofpu(dc))
3485                         goto jmp_insn;
3486                     goto nfq_insn;
3487 #endif
3488 #endif
3489                 case 0x27:
3490                     gen_op_check_align_T0_7();
3491                     gen_op_load_fpr_DT0(DFPREG(rd));
3492                     gen_op_ldst(stdf);
3493                     break;
3494                 default:
3495                     goto illegal_insn;
3496                 }
3497             } else if (xop > 0x33 && xop < 0x3f) {
3498                 switch (xop) {
3499 #ifdef TARGET_SPARC64
3500                 case 0x34: /* V9 stfa */
3501                     gen_op_check_align_T0_3();
3502                     gen_op_load_fpr_FT0(rd);
3503                     gen_stf_asi(insn, 4, rd);
3504                     break;
3505                 case 0x36: /* V9 stqfa */
3506 #if defined(CONFIG_USER_ONLY)
3507                     gen_op_check_align_T0_7();
3508                     gen_op_load_fpr_QT0(QFPREG(rd));
3509                     gen_stf_asi(insn, 16, QFPREG(rd));
3510                     break;
3511 #else
3512                     goto nfpu_insn;
3513 #endif
3514                 case 0x37: /* V9 stdfa */
3515                     gen_op_check_align_T0_3();
3516                     gen_op_load_fpr_DT0(DFPREG(rd));
3517                     gen_stf_asi(insn, 8, DFPREG(rd));
3518                     break;
3519                 case 0x3c: /* V9 casa */
3520                     gen_op_check_align_T0_3();
3521                     flush_T2(dc);
3522                     gen_movl_reg_T2(rd);
3523                     gen_cas_asi(insn);
3524                     gen_movl_T1_reg(rd);
3525                     break;
3526                 case 0x3e: /* V9 casxa */
3527                     gen_op_check_align_T0_7();
3528                     flush_T2(dc);
3529                     gen_movl_reg_T2(rd);
3530                     gen_casx_asi(insn);
3531                     gen_movl_T1_reg(rd);
3532                     break;
3533 #else
3534                 case 0x34: /* stc */
3535                 case 0x35: /* stcsr */
3536                 case 0x36: /* stdcq */
3537                 case 0x37: /* stdc */
3538                     goto ncp_insn;
3539 #endif
3540                 default:
3541                     goto illegal_insn;
3542                 }
3543             }
3544             else
3545                 goto illegal_insn;
3546         }
3547         break;
3548     }
3549     /* default case for non jump instructions */
3550     if (dc->npc == DYNAMIC_PC) {
3551         dc->pc = DYNAMIC_PC;
3552         gen_op_next_insn();
3553     } else if (dc->npc == JUMP_PC) {
3554         /* we can do a static jump */
3555         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
3556         dc->is_br = 1;
3557     } else {
3558         dc->pc = dc->npc;
3559         dc->npc = dc->npc + 4;
3560     }
3561  jmp_insn:
3562     return;
3563  illegal_insn:
3564     save_state(dc);
3565     gen_op_exception(TT_ILL_INSN);
3566     dc->is_br = 1;
3567     return;
3568 #if !defined(CONFIG_USER_ONLY)
3569  priv_insn:
3570     save_state(dc);
3571     gen_op_exception(TT_PRIV_INSN);
3572     dc->is_br = 1;
3573     return;
3574  nfpu_insn:
3575     save_state(dc);
3576     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3577     dc->is_br = 1;
3578     return;
3579 #ifndef TARGET_SPARC64
3580  nfq_insn:
3581     save_state(dc);
3582     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3583     dc->is_br = 1;
3584     return;
3585 #endif
3586 #endif
3587 #ifndef TARGET_SPARC64
3588  ncp_insn:
3589     save_state(dc);
3590     gen_op_exception(TT_NCP_INSN);
3591     dc->is_br = 1;
3592     return;
3593 #endif
3594 }
3595
3596 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3597                                                  int spc, CPUSPARCState *env)
3598 {
3599     target_ulong pc_start, last_pc;
3600     uint16_t *gen_opc_end;
3601     DisasContext dc1, *dc = &dc1;
3602     int j, lj = -1;
3603
3604     memset(dc, 0, sizeof(DisasContext));
3605     dc->tb = tb;
3606     pc_start = tb->pc;
3607     dc->pc = pc_start;
3608     last_pc = dc->pc;
3609     dc->npc = (target_ulong) tb->cs_base;
3610     dc->mem_idx = cpu_mmu_index(env);
3611     dc->fpu_enabled = cpu_fpu_enabled(env);
3612     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3613
3614     do {
3615         if (env->nb_breakpoints > 0) {
3616             for(j = 0; j < env->nb_breakpoints; j++) {
3617                 if (env->breakpoints[j] == dc->pc) {
3618                     if (dc->pc != pc_start)
3619                         save_state(dc);
3620                     gen_op_debug();
3621                     tcg_gen_exit_tb(0);
3622                     dc->is_br = 1;
3623                     goto exit_gen_loop;
3624                 }
3625             }
3626         }
3627         if (spc) {
3628             if (loglevel > 0)
3629                 fprintf(logfile, "Search PC...\n");
3630             j = gen_opc_ptr - gen_opc_buf;
3631             if (lj < j) {
3632                 lj++;
3633                 while (lj < j)
3634                     gen_opc_instr_start[lj++] = 0;
3635                 gen_opc_pc[lj] = dc->pc;
3636                 gen_opc_npc[lj] = dc->npc;
3637                 gen_opc_instr_start[lj] = 1;
3638             }
3639         }
3640         last_pc = dc->pc;
3641         disas_sparc_insn(dc);
3642
3643         if (dc->is_br)
3644             break;
3645         /* if the next PC is different, we abort now */
3646         if (dc->pc != (last_pc + 4))
3647             break;
3648         /* if we reach a page boundary, we stop generation so that the
3649            PC of a TT_TFAULT exception is always in the right page */
3650         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3651             break;
3652         /* if single step mode, we generate only one instruction and
3653            generate an exception */
3654         if (env->singlestep_enabled) {
3655             gen_jmp_im(dc->pc);
3656             tcg_gen_exit_tb(0);
3657             break;
3658         }
3659     } while ((gen_opc_ptr < gen_opc_end) &&
3660              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
3661
3662  exit_gen_loop:
3663     if (!dc->is_br) {
3664         if (dc->pc != DYNAMIC_PC &&
3665             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3666             /* static PC and NPC: we can use direct chaining */
3667             gen_branch(dc, dc->pc, dc->npc);
3668         } else {
3669             if (dc->pc != DYNAMIC_PC)
3670                 gen_jmp_im(dc->pc);
3671             save_npc(dc);
3672             tcg_gen_exit_tb(0);
3673         }
3674     }
3675     *gen_opc_ptr = INDEX_op_end;
3676     if (spc) {
3677         j = gen_opc_ptr - gen_opc_buf;
3678         lj++;
3679         while (lj <= j)
3680             gen_opc_instr_start[lj++] = 0;
3681 #if 0
3682         if (loglevel > 0) {
3683             page_dump(logfile);
3684         }
3685 #endif
3686         gen_opc_jump_pc[0] = dc->jump_pc[0];
3687         gen_opc_jump_pc[1] = dc->jump_pc[1];
3688     } else {
3689         tb->size = last_pc + 4 - pc_start;
3690     }
3691 #ifdef DEBUG_DISAS
3692     if (loglevel & CPU_LOG_TB_IN_ASM) {
3693         fprintf(logfile, "--------------\n");
3694         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3695         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3696         fprintf(logfile, "\n");
3697     }
3698 #endif
3699     return 0;
3700 }
3701
3702 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
3703 {
3704     return gen_intermediate_code_internal(tb, 0, env);
3705 }
3706
3707 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
3708 {
3709     return gen_intermediate_code_internal(tb, 1, env);
3710 }
3711
3712 void cpu_reset(CPUSPARCState *env)
3713 {
3714     tlb_flush(env, 1);
3715     env->cwp = 0;
3716     env->wim = 1;
3717     env->regwptr = env->regbase + (env->cwp * 16);
3718 #if defined(CONFIG_USER_ONLY)
3719     env->user_mode_only = 1;
3720 #ifdef TARGET_SPARC64
3721     env->cleanwin = NWINDOWS - 2;
3722     env->cansave = NWINDOWS - 2;
3723     env->pstate = PS_RMO | PS_PEF | PS_IE;
3724     env->asi = 0x82; // Primary no-fault
3725 #endif
3726 #else
3727     env->psret = 0;
3728     env->psrs = 1;
3729     env->psrps = 1;
3730 #ifdef TARGET_SPARC64
3731     env->pstate = PS_PRIV;
3732     env->hpstate = HS_PRIV;
3733     env->pc = 0x1fff0000000ULL;
3734 #else
3735     env->pc = 0;
3736     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3737     env->mmuregs[0] |= env->mmu_bm;
3738 #endif
3739     env->npc = env->pc + 4;
3740 #endif
3741 }
3742
3743 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
3744 {
3745     CPUSPARCState *env;
3746     const sparc_def_t *def;
3747
3748     def = cpu_sparc_find_by_name(cpu_model);
3749     if (!def)
3750         return NULL;
3751
3752     env = qemu_mallocz(sizeof(CPUSPARCState));
3753     if (!env)
3754         return NULL;
3755     cpu_exec_init(env);
3756     env->cpu_model_str = cpu_model;
3757     env->version = def->iu_version;
3758     env->fsr = def->fpu_version;
3759 #if !defined(TARGET_SPARC64)
3760     env->mmu_bm = def->mmu_bm;
3761     env->mmuregs[0] |= def->mmu_version;
3762     cpu_sparc_set_id(env, 0);
3763 #endif
3764     cpu_reset(env);
3765
3766     return env;
3767 }
3768
3769 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
3770 {
3771 #if !defined(TARGET_SPARC64)
3772     env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
3773 #endif
3774 }
3775
3776 static const sparc_def_t sparc_defs[] = {
3777 #ifdef TARGET_SPARC64
3778     {
3779         .name = "Fujitsu Sparc64",
3780         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
3781                        | (MAXTL << 8) | (NWINDOWS - 1)),
3782         .fpu_version = 0x00000000,
3783         .mmu_version = 0,
3784     },
3785     {
3786         .name = "Fujitsu Sparc64 III",
3787         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
3788                        | (MAXTL << 8) | (NWINDOWS - 1)),
3789         .fpu_version = 0x00000000,
3790         .mmu_version = 0,
3791     },
3792     {
3793         .name = "Fujitsu Sparc64 IV",
3794         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
3795                        | (MAXTL << 8) | (NWINDOWS - 1)),
3796         .fpu_version = 0x00000000,
3797         .mmu_version = 0,
3798     },
3799     {
3800         .name = "Fujitsu Sparc64 V",
3801         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
3802                        | (MAXTL << 8) | (NWINDOWS - 1)),
3803         .fpu_version = 0x00000000,
3804         .mmu_version = 0,
3805     },
3806     {
3807         .name = "TI UltraSparc I",
3808         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
3809                        | (MAXTL << 8) | (NWINDOWS - 1)),
3810         .fpu_version = 0x00000000,
3811         .mmu_version = 0,
3812     },
3813     {
3814         .name = "TI UltraSparc II",
3815         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
3816                        | (MAXTL << 8) | (NWINDOWS - 1)),
3817         .fpu_version = 0x00000000,
3818         .mmu_version = 0,
3819     },
3820     {
3821         .name = "TI UltraSparc IIi",
3822         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
3823                        | (MAXTL << 8) | (NWINDOWS - 1)),
3824         .fpu_version = 0x00000000,
3825         .mmu_version = 0,
3826     },
3827     {
3828         .name = "TI UltraSparc IIe",
3829         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
3830                        | (MAXTL << 8) | (NWINDOWS - 1)),
3831         .fpu_version = 0x00000000,
3832         .mmu_version = 0,
3833     },
3834     {
3835         .name = "Sun UltraSparc III",
3836         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
3837                        | (MAXTL << 8) | (NWINDOWS - 1)),
3838         .fpu_version = 0x00000000,
3839         .mmu_version = 0,
3840     },
3841     {
3842         .name = "Sun UltraSparc III Cu",
3843         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
3844                        | (MAXTL << 8) | (NWINDOWS - 1)),
3845         .fpu_version = 0x00000000,
3846         .mmu_version = 0,
3847     },
3848     {
3849         .name = "Sun UltraSparc IIIi",
3850         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
3851                        | (MAXTL << 8) | (NWINDOWS - 1)),
3852         .fpu_version = 0x00000000,
3853         .mmu_version = 0,
3854     },
3855     {
3856         .name = "Sun UltraSparc IV",
3857         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
3858                        | (MAXTL << 8) | (NWINDOWS - 1)),
3859         .fpu_version = 0x00000000,
3860         .mmu_version = 0,
3861     },
3862     {
3863         .name = "Sun UltraSparc IV+",
3864         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
3865                        | (MAXTL << 8) | (NWINDOWS - 1)),
3866         .fpu_version = 0x00000000,
3867         .mmu_version = 0,
3868     },
3869     {
3870         .name = "Sun UltraSparc IIIi+",
3871         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
3872                        | (MAXTL << 8) | (NWINDOWS - 1)),
3873         .fpu_version = 0x00000000,
3874         .mmu_version = 0,
3875     },
3876     {
3877         .name = "NEC UltraSparc I",
3878         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
3879                        | (MAXTL << 8) | (NWINDOWS - 1)),
3880         .fpu_version = 0x00000000,
3881         .mmu_version = 0,
3882     },
3883 #else
3884     {
3885         .name = "Fujitsu MB86900",
3886         .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
3887         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3888         .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
3889         .mmu_bm = 0x00004000,
3890     },
3891     {
3892         .name = "Fujitsu MB86904",
3893         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3894         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3895         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3896         .mmu_bm = 0x00004000,
3897     },
3898     {
3899         .name = "Fujitsu MB86907",
3900         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3901         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3902         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3903         .mmu_bm = 0x00004000,
3904     },
3905     {
3906         .name = "LSI L64811",
3907         .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
3908         .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
3909         .mmu_version = 0x10 << 24,
3910         .mmu_bm = 0x00004000,
3911     },
3912     {
3913         .name = "Cypress CY7C601",
3914         .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
3915         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
3916         .mmu_version = 0x10 << 24,
3917         .mmu_bm = 0x00004000,
3918     },
3919     {
3920         .name = "Cypress CY7C611",
3921         .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
3922         .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
3923         .mmu_version = 0x10 << 24,
3924         .mmu_bm = 0x00004000,
3925     },
3926     {
3927         .name = "TI SuperSparc II",
3928         .iu_version = 0x40000000,
3929         .fpu_version = 0 << 17,
3930         .mmu_version = 0x04000000,
3931         .mmu_bm = 0x00002000,
3932     },
3933     {
3934         .name = "TI MicroSparc I",
3935         .iu_version = 0x41000000,
3936         .fpu_version = 4 << 17,
3937         .mmu_version = 0x41000000,
3938         .mmu_bm = 0x00004000,
3939     },
3940     {
3941         .name = "TI MicroSparc II",
3942         .iu_version = 0x42000000,
3943         .fpu_version = 4 << 17,
3944         .mmu_version = 0x02000000,
3945         .mmu_bm = 0x00004000,
3946     },
3947     {
3948         .name = "TI MicroSparc IIep",
3949         .iu_version = 0x42000000,
3950         .fpu_version = 4 << 17,
3951         .mmu_version = 0x04000000,
3952         .mmu_bm = 0x00004000,
3953     },
3954     {
3955         .name = "TI SuperSparc 51",
3956         .iu_version = 0x43000000,
3957         .fpu_version = 0 << 17,
3958         .mmu_version = 0x04000000,
3959         .mmu_bm = 0x00002000,
3960     },
3961     {
3962         .name = "TI SuperSparc 61",
3963         .iu_version = 0x44000000,
3964         .fpu_version = 0 << 17,
3965         .mmu_version = 0x04000000,
3966         .mmu_bm = 0x00002000,
3967     },
3968     {
3969         .name = "Ross RT625",
3970         .iu_version = 0x1e000000,
3971         .fpu_version = 1 << 17,
3972         .mmu_version = 0x1e000000,
3973         .mmu_bm = 0x00004000,
3974     },
3975     {
3976         .name = "Ross RT620",
3977         .iu_version = 0x1f000000,
3978         .fpu_version = 1 << 17,
3979         .mmu_version = 0x1f000000,
3980         .mmu_bm = 0x00004000,
3981     },
3982     {
3983         .name = "BIT B5010",
3984         .iu_version = 0x20000000,
3985         .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
3986         .mmu_version = 0x20000000,
3987         .mmu_bm = 0x00004000,
3988     },
3989     {
3990         .name = "Matsushita MN10501",
3991         .iu_version = 0x50000000,
3992         .fpu_version = 0 << 17,
3993         .mmu_version = 0x50000000,
3994         .mmu_bm = 0x00004000,
3995     },
3996     {
3997         .name = "Weitek W8601",
3998         .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
3999         .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
4000         .mmu_version = 0x10 << 24,
4001         .mmu_bm = 0x00004000,
4002     },
4003     {
4004         .name = "LEON2",
4005         .iu_version = 0xf2000000,
4006         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4007         .mmu_version = 0xf2000000,
4008         .mmu_bm = 0x00004000,
4009     },
4010     {
4011         .name = "LEON3",
4012         .iu_version = 0xf3000000,
4013         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4014         .mmu_version = 0xf3000000,
4015         .mmu_bm = 0x00004000,
4016     },
4017 #endif
4018 };
4019
4020 static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
4021 {
4022     unsigned int i;
4023
4024     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4025         if (strcasecmp(name, sparc_defs[i].name) == 0) {
4026             return &sparc_defs[i];
4027         }
4028     }
4029     return NULL;
4030 }
4031
4032 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
4033 {
4034     unsigned int i;
4035
4036     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4037         (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
4038                        sparc_defs[i].name,
4039                        sparc_defs[i].iu_version,
4040                        sparc_defs[i].fpu_version,
4041                        sparc_defs[i].mmu_version);
4042     }
4043 }
4044
4045 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
4046
4047 void cpu_dump_state(CPUState *env, FILE *f,
4048                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
4049                     int flags)
4050 {
4051     int i, x;
4052
4053     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
4054     cpu_fprintf(f, "General Registers:\n");
4055     for (i = 0; i < 4; i++)
4056         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
4057     cpu_fprintf(f, "\n");
4058     for (; i < 8; i++)
4059         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
4060     cpu_fprintf(f, "\nCurrent Register Window:\n");
4061     for (x = 0; x < 3; x++) {
4062         for (i = 0; i < 4; i++)
4063             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4064                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
4065                     env->regwptr[i + x * 8]);
4066         cpu_fprintf(f, "\n");
4067         for (; i < 8; i++)
4068             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4069                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
4070                     env->regwptr[i + x * 8]);
4071         cpu_fprintf(f, "\n");
4072     }
4073     cpu_fprintf(f, "\nFloating Point Registers:\n");
4074     for (i = 0; i < 32; i++) {
4075         if ((i & 3) == 0)
4076             cpu_fprintf(f, "%%f%02d:", i);
4077         cpu_fprintf(f, " %016lf", env->fpr[i]);
4078         if ((i & 3) == 3)
4079             cpu_fprintf(f, "\n");
4080     }
4081 #ifdef TARGET_SPARC64
4082     cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
4083                 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
4084     cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
4085                 env->cansave, env->canrestore, env->otherwin, env->wstate,
4086                 env->cleanwin, NWINDOWS - 1 - env->cwp);
4087 #else
4088     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
4089             GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
4090             GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
4091             env->psrs?'S':'-', env->psrps?'P':'-',
4092             env->psret?'E':'-', env->wim);
4093 #endif
4094     cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
4095 }
4096
4097 #if defined(CONFIG_USER_ONLY)
4098 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
4099 {
4100     return addr;
4101 }
4102
4103 #else
4104 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
4105                                  int *access_index, target_ulong address, int rw,
4106                                  int mmu_idx);
4107
4108 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
4109 {
4110     target_phys_addr_t phys_addr;
4111     int prot, access_index;
4112
4113     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
4114         if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
4115             return -1;
4116     if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
4117         return -1;
4118     return phys_addr;
4119 }
4120 #endif
4121
4122 void helper_flush(target_ulong addr)
4123 {
4124     addr &= ~7;
4125     tb_invalidate_page_range(addr, addr + 8);
4126 }