5 void OPPROTO do_fabss(void)
10 void OPPROTO do_fsqrts(void)
15 void OPPROTO do_fsqrtd(void)
20 void OPPROTO do_fcmps (void)
22 if (isnan(FT0) || isnan(FT1)) {
23 T0 = FSR_FCC1 | FSR_FCC0;
24 } else if (FT0 < FT1) {
26 } else if (FT0 > FT1) {
34 void OPPROTO do_fcmpd (void)
36 if (isnan(DT0) || isnan(DT1)) {
37 T0 = FSR_FCC1 | FSR_FCC0;
38 } else if (DT0 < DT1) {
40 } else if (DT0 > DT1) {
48 void OPPROTO helper_ld_asi(int asi, int size, int sign)
51 case 3: /* MMU probe */
54 case 4: /* read MMU regs */
56 int temp, reg = (T0 >> 8) & 0xf;
58 temp = env->mmuregs[reg];
59 if (reg == 3 || reg == 4) /* Fault status, addr cleared on read*/
60 env->mmuregs[reg] = 0;
64 case 0x20 ... 0x2f: /* MMU passthrough */
68 cpu_physical_memory_read(T0, (void *) &temp, size);
79 void OPPROTO helper_st_asi(int asi, int size, int sign)
82 case 3: /* MMU flush */
84 case 4: /* write MMU regs */
86 int reg = (T0 >> 8) & 0xf;
88 env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
89 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
91 env->mmuregs[reg] = T1;
94 case 0x20 ... 0x2f: /* MMU passthrough */
99 cpu_physical_memory_write(T0, (void *) &temp, size);
108 void do_ldd_raw(uint32_t addr)
110 T1 = ldl_raw((void *) addr);
111 T0 = ldl_raw((void *) (addr + 4));
114 #if !defined(CONFIG_USER_ONLY)
115 void do_ldd_user(uint32_t addr)
117 T1 = ldl_user((void *) addr);
118 T0 = ldl_user((void *) (addr + 4));
120 void do_ldd_kernel(uint32_t addr)
122 T1 = ldl_kernel((void *) addr);
123 T0 = ldl_kernel((void *) (addr + 4));
128 void OPPROTO helper_rett()
132 cwp = (env->cwp + 1) & (NWINDOWS - 1);
133 if (env->wim & (1 << cwp)) {
134 raise_exception(TT_WIN_UNF);
137 env->psrs = env->psrps;
140 void helper_ldfsr(void)
142 switch (env->fsr & FSR_RD_MASK) {
144 fesetround(FE_TONEAREST);
147 fesetround(FE_TOWARDZERO);
150 fesetround(FE_UPWARD);
153 fesetround(FE_DOWNWARD);