2 * PowerPC CPU initialization for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DEBUG_IRQ
33 const unsigned char *name;
43 void (*init_proc)(CPUPPCState *env);
46 /* For user-mode emulation, we don't emulate any IRQ controller */
47 #if defined(CONFIG_USER_ONLY)
48 #define PPC_IRQ_INIT_FN(name) \
49 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
53 #define PPC_IRQ_INIT_FN(name) \
54 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
63 * do nothing but store/retrieve spr value
65 #ifdef PPC_DUMP_SPR_ACCESSES
66 static void spr_read_generic (void *opaque, int sprn)
68 gen_op_load_dump_spr(sprn);
71 static void spr_write_generic (void *opaque, int sprn)
73 gen_op_store_dump_spr(sprn);
76 static void spr_read_generic (void *opaque, int sprn)
78 gen_op_load_spr(sprn);
81 static void spr_write_generic (void *opaque, int sprn)
83 gen_op_store_spr(sprn);
87 #if !defined(CONFIG_USER_ONLY)
88 static void spr_write_clear (void *opaque, int sprn)
90 gen_op_mask_spr(sprn);
94 /* SPR common to all PowerPC */
96 static void spr_read_xer (void *opaque, int sprn)
101 static void spr_write_xer (void *opaque, int sprn)
107 static void spr_read_lr (void *opaque, int sprn)
112 static void spr_write_lr (void *opaque, int sprn)
118 static void spr_read_ctr (void *opaque, int sprn)
123 static void spr_write_ctr (void *opaque, int sprn)
128 /* User read access to SPR */
134 static void spr_read_ureg (void *opaque, int sprn)
136 gen_op_load_spr(sprn + 0x10);
139 /* SPR common to all non-embedded PowerPC */
141 #if !defined(CONFIG_USER_ONLY)
142 static void spr_read_decr (void *opaque, int sprn)
147 static void spr_write_decr (void *opaque, int sprn)
153 /* SPR common to all non-embedded PowerPC, except 601 */
155 static void spr_read_tbl (void *opaque, int sprn)
160 static void spr_read_tbu (void *opaque, int sprn)
165 __attribute__ (( unused ))
166 static void spr_read_atbl (void *opaque, int sprn)
171 __attribute__ (( unused ))
172 static void spr_read_atbu (void *opaque, int sprn)
177 #if !defined(CONFIG_USER_ONLY)
178 static void spr_write_tbl (void *opaque, int sprn)
183 static void spr_write_tbu (void *opaque, int sprn)
188 __attribute__ (( unused ))
189 static void spr_write_atbl (void *opaque, int sprn)
194 __attribute__ (( unused ))
195 static void spr_write_atbu (void *opaque, int sprn)
201 #if !defined(CONFIG_USER_ONLY)
202 /* IBAT0U...IBAT0U */
203 /* IBAT0L...IBAT7L */
204 static void spr_read_ibat (void *opaque, int sprn)
206 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
209 static void spr_read_ibat_h (void *opaque, int sprn)
211 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
214 static void spr_write_ibatu (void *opaque, int sprn)
216 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
219 static void spr_write_ibatu_h (void *opaque, int sprn)
221 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
224 static void spr_write_ibatl (void *opaque, int sprn)
226 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
229 static void spr_write_ibatl_h (void *opaque, int sprn)
231 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
234 /* DBAT0U...DBAT7U */
235 /* DBAT0L...DBAT7L */
236 static void spr_read_dbat (void *opaque, int sprn)
238 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
241 static void spr_read_dbat_h (void *opaque, int sprn)
243 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
246 static void spr_write_dbatu (void *opaque, int sprn)
248 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
251 static void spr_write_dbatu_h (void *opaque, int sprn)
253 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
256 static void spr_write_dbatl (void *opaque, int sprn)
258 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
261 static void spr_write_dbatl_h (void *opaque, int sprn)
263 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
267 static void spr_read_sdr1 (void *opaque, int sprn)
272 static void spr_write_sdr1 (void *opaque, int sprn)
277 /* 64 bits PowerPC specific SPRs */
279 /* Currently unused */
280 #if 0 && defined(TARGET_PPC64)
281 static void spr_read_asr (void *opaque, int sprn)
286 static void spr_write_asr (void *opaque, int sprn)
288 DisasContext *ctx = opaque;
295 /* PowerPC 601 specific registers */
297 static void spr_read_601_rtcl (void *opaque, int sprn)
299 gen_op_load_601_rtcl();
302 static void spr_read_601_rtcu (void *opaque, int sprn)
304 gen_op_load_601_rtcu();
307 #if !defined(CONFIG_USER_ONLY)
308 static void spr_write_601_rtcu (void *opaque, int sprn)
310 gen_op_store_601_rtcu();
313 static void spr_write_601_rtcl (void *opaque, int sprn)
315 gen_op_store_601_rtcl();
320 #if !defined(CONFIG_USER_ONLY)
321 static void spr_read_601_ubat (void *opaque, int sprn)
323 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
326 static void spr_write_601_ubatu (void *opaque, int sprn)
328 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
331 static void spr_write_601_ubatl (void *opaque, int sprn)
333 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
337 /* PowerPC 40x specific registers */
338 #if !defined(CONFIG_USER_ONLY)
339 static void spr_read_40x_pit (void *opaque, int sprn)
341 gen_op_load_40x_pit();
344 static void spr_write_40x_pit (void *opaque, int sprn)
346 gen_op_store_40x_pit();
349 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
351 DisasContext *ctx = opaque;
353 gen_op_store_40x_dbcr0();
354 /* We must stop translation as we may have rebooted */
358 static void spr_write_40x_sler (void *opaque, int sprn)
360 gen_op_store_40x_sler();
363 static void spr_write_booke_tcr (void *opaque, int sprn)
365 gen_op_store_booke_tcr();
368 static void spr_write_booke_tsr (void *opaque, int sprn)
370 gen_op_store_booke_tsr();
374 /* PowerPC 403 specific registers */
375 /* PBL1 / PBU1 / PBL2 / PBU2 */
376 #if !defined(CONFIG_USER_ONLY)
377 static void spr_read_403_pbr (void *opaque, int sprn)
379 gen_op_load_403_pb(sprn - SPR_403_PBL1);
382 static void spr_write_403_pbr (void *opaque, int sprn)
384 gen_op_store_403_pb(sprn - SPR_403_PBL1);
387 static void spr_write_pir (void *opaque, int sprn)
393 #if defined(CONFIG_USER_ONLY)
394 #define spr_register(env, num, name, uea_read, uea_write, \
395 oea_read, oea_write, initial_value) \
397 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
399 static inline void _spr_register (CPUPPCState *env, int num,
400 const unsigned char *name,
401 void (*uea_read)(void *opaque, int sprn),
402 void (*uea_write)(void *opaque, int sprn),
403 target_ulong initial_value)
405 static inline void spr_register (CPUPPCState *env, int num,
406 const unsigned char *name,
407 void (*uea_read)(void *opaque, int sprn),
408 void (*uea_write)(void *opaque, int sprn),
409 void (*oea_read)(void *opaque, int sprn),
410 void (*oea_write)(void *opaque, int sprn),
411 target_ulong initial_value)
416 spr = &env->spr_cb[num];
417 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
418 #if !defined(CONFIG_USER_ONLY)
419 spr->oea_read != NULL || spr->oea_write != NULL ||
421 spr->uea_read != NULL || spr->uea_write != NULL) {
422 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
425 #if defined(PPC_DEBUG_SPR)
426 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
430 spr->uea_read = uea_read;
431 spr->uea_write = uea_write;
432 #if !defined(CONFIG_USER_ONLY)
433 spr->oea_read = oea_read;
434 spr->oea_write = oea_write;
436 env->spr[num] = initial_value;
439 /* Generic PowerPC SPRs */
440 static void gen_spr_generic (CPUPPCState *env)
442 /* Integer processing */
443 spr_register(env, SPR_XER, "XER",
444 &spr_read_xer, &spr_write_xer,
445 &spr_read_xer, &spr_write_xer,
448 spr_register(env, SPR_LR, "LR",
449 &spr_read_lr, &spr_write_lr,
450 &spr_read_lr, &spr_write_lr,
452 spr_register(env, SPR_CTR, "CTR",
453 &spr_read_ctr, &spr_write_ctr,
454 &spr_read_ctr, &spr_write_ctr,
456 /* Interrupt processing */
457 spr_register(env, SPR_SRR0, "SRR0",
458 SPR_NOACCESS, SPR_NOACCESS,
459 &spr_read_generic, &spr_write_generic,
461 spr_register(env, SPR_SRR1, "SRR1",
462 SPR_NOACCESS, SPR_NOACCESS,
463 &spr_read_generic, &spr_write_generic,
465 /* Processor control */
466 spr_register(env, SPR_SPRG0, "SPRG0",
467 SPR_NOACCESS, SPR_NOACCESS,
468 &spr_read_generic, &spr_write_generic,
470 spr_register(env, SPR_SPRG1, "SPRG1",
471 SPR_NOACCESS, SPR_NOACCESS,
472 &spr_read_generic, &spr_write_generic,
474 spr_register(env, SPR_SPRG2, "SPRG2",
475 SPR_NOACCESS, SPR_NOACCESS,
476 &spr_read_generic, &spr_write_generic,
478 spr_register(env, SPR_SPRG3, "SPRG3",
479 SPR_NOACCESS, SPR_NOACCESS,
480 &spr_read_generic, &spr_write_generic,
484 /* SPR common to all non-embedded PowerPC, including 601 */
485 static void gen_spr_ne_601 (CPUPPCState *env)
487 /* Exception processing */
488 spr_register(env, SPR_DSISR, "DSISR",
489 SPR_NOACCESS, SPR_NOACCESS,
490 &spr_read_generic, &spr_write_generic,
492 spr_register(env, SPR_DAR, "DAR",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
497 spr_register(env, SPR_DECR, "DECR",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_decr, &spr_write_decr,
501 /* Memory management */
502 spr_register(env, SPR_SDR1, "SDR1",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_sdr1, &spr_write_sdr1,
509 static void gen_low_BATs (CPUPPCState *env)
511 spr_register(env, SPR_IBAT0U, "IBAT0U",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_ibat, &spr_write_ibatu,
515 spr_register(env, SPR_IBAT0L, "IBAT0L",
516 SPR_NOACCESS, SPR_NOACCESS,
517 &spr_read_ibat, &spr_write_ibatl,
519 spr_register(env, SPR_IBAT1U, "IBAT1U",
520 SPR_NOACCESS, SPR_NOACCESS,
521 &spr_read_ibat, &spr_write_ibatu,
523 spr_register(env, SPR_IBAT1L, "IBAT1L",
524 SPR_NOACCESS, SPR_NOACCESS,
525 &spr_read_ibat, &spr_write_ibatl,
527 spr_register(env, SPR_IBAT2U, "IBAT2U",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_ibat, &spr_write_ibatu,
531 spr_register(env, SPR_IBAT2L, "IBAT2L",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_ibat, &spr_write_ibatl,
535 spr_register(env, SPR_IBAT3U, "IBAT3U",
536 SPR_NOACCESS, SPR_NOACCESS,
537 &spr_read_ibat, &spr_write_ibatu,
539 spr_register(env, SPR_IBAT3L, "IBAT3L",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_ibat, &spr_write_ibatl,
543 spr_register(env, SPR_DBAT0U, "DBAT0U",
544 SPR_NOACCESS, SPR_NOACCESS,
545 &spr_read_dbat, &spr_write_dbatu,
547 spr_register(env, SPR_DBAT0L, "DBAT0L",
548 SPR_NOACCESS, SPR_NOACCESS,
549 &spr_read_dbat, &spr_write_dbatl,
551 spr_register(env, SPR_DBAT1U, "DBAT1U",
552 SPR_NOACCESS, SPR_NOACCESS,
553 &spr_read_dbat, &spr_write_dbatu,
555 spr_register(env, SPR_DBAT1L, "DBAT1L",
556 SPR_NOACCESS, SPR_NOACCESS,
557 &spr_read_dbat, &spr_write_dbatl,
559 spr_register(env, SPR_DBAT2U, "DBAT2U",
560 SPR_NOACCESS, SPR_NOACCESS,
561 &spr_read_dbat, &spr_write_dbatu,
563 spr_register(env, SPR_DBAT2L, "DBAT2L",
564 SPR_NOACCESS, SPR_NOACCESS,
565 &spr_read_dbat, &spr_write_dbatl,
567 spr_register(env, SPR_DBAT3U, "DBAT3U",
568 SPR_NOACCESS, SPR_NOACCESS,
569 &spr_read_dbat, &spr_write_dbatu,
571 spr_register(env, SPR_DBAT3L, "DBAT3L",
572 SPR_NOACCESS, SPR_NOACCESS,
573 &spr_read_dbat, &spr_write_dbatl,
579 static void gen_high_BATs (CPUPPCState *env)
581 spr_register(env, SPR_IBAT4U, "IBAT4U",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_ibat_h, &spr_write_ibatu_h,
585 spr_register(env, SPR_IBAT4L, "IBAT4L",
586 SPR_NOACCESS, SPR_NOACCESS,
587 &spr_read_ibat_h, &spr_write_ibatl_h,
589 spr_register(env, SPR_IBAT5U, "IBAT5U",
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_ibat_h, &spr_write_ibatu_h,
593 spr_register(env, SPR_IBAT5L, "IBAT5L",
594 SPR_NOACCESS, SPR_NOACCESS,
595 &spr_read_ibat_h, &spr_write_ibatl_h,
597 spr_register(env, SPR_IBAT6U, "IBAT6U",
598 SPR_NOACCESS, SPR_NOACCESS,
599 &spr_read_ibat_h, &spr_write_ibatu_h,
601 spr_register(env, SPR_IBAT6L, "IBAT6L",
602 SPR_NOACCESS, SPR_NOACCESS,
603 &spr_read_ibat_h, &spr_write_ibatl_h,
605 spr_register(env, SPR_IBAT7U, "IBAT7U",
606 SPR_NOACCESS, SPR_NOACCESS,
607 &spr_read_ibat_h, &spr_write_ibatu_h,
609 spr_register(env, SPR_IBAT7L, "IBAT7L",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_ibat_h, &spr_write_ibatl_h,
613 spr_register(env, SPR_DBAT4U, "DBAT4U",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_dbat_h, &spr_write_dbatu_h,
617 spr_register(env, SPR_DBAT4L, "DBAT4L",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_dbat_h, &spr_write_dbatl_h,
621 spr_register(env, SPR_DBAT5U, "DBAT5U",
622 SPR_NOACCESS, SPR_NOACCESS,
623 &spr_read_dbat_h, &spr_write_dbatu_h,
625 spr_register(env, SPR_DBAT5L, "DBAT5L",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_dbat_h, &spr_write_dbatl_h,
629 spr_register(env, SPR_DBAT6U, "DBAT6U",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_dbat_h, &spr_write_dbatu_h,
633 spr_register(env, SPR_DBAT6L, "DBAT6L",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_dbat_h, &spr_write_dbatl_h,
637 spr_register(env, SPR_DBAT7U, "DBAT7U",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_dbat_h, &spr_write_dbatu_h,
641 spr_register(env, SPR_DBAT7L, "DBAT7L",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_dbat_h, &spr_write_dbatl_h,
648 /* Generic PowerPC time base */
649 static void gen_tbl (CPUPPCState *env)
651 spr_register(env, SPR_VTBL, "TBL",
652 &spr_read_tbl, SPR_NOACCESS,
653 &spr_read_tbl, SPR_NOACCESS,
655 spr_register(env, SPR_TBL, "TBL",
656 SPR_NOACCESS, SPR_NOACCESS,
657 SPR_NOACCESS, &spr_write_tbl,
659 spr_register(env, SPR_VTBU, "TBU",
660 &spr_read_tbu, SPR_NOACCESS,
661 &spr_read_tbu, SPR_NOACCESS,
663 spr_register(env, SPR_TBU, "TBU",
664 SPR_NOACCESS, SPR_NOACCESS,
665 SPR_NOACCESS, &spr_write_tbu,
669 /* Softare table search registers */
670 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
672 env->nb_tlb = nb_tlbs;
673 env->nb_ways = nb_ways;
675 spr_register(env, SPR_DMISS, "DMISS",
676 SPR_NOACCESS, SPR_NOACCESS,
677 &spr_read_generic, SPR_NOACCESS,
679 spr_register(env, SPR_DCMP, "DCMP",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_generic, SPR_NOACCESS,
683 spr_register(env, SPR_HASH1, "HASH1",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_generic, SPR_NOACCESS,
687 spr_register(env, SPR_HASH2, "HASH2",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_generic, SPR_NOACCESS,
691 spr_register(env, SPR_IMISS, "IMISS",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_generic, SPR_NOACCESS,
695 spr_register(env, SPR_ICMP, "ICMP",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, SPR_NOACCESS,
699 spr_register(env, SPR_RPA, "RPA",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
705 /* SPR common to MPC755 and G2 */
706 static void gen_spr_G2_755 (CPUPPCState *env)
709 spr_register(env, SPR_SPRG4, "SPRG4",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
713 spr_register(env, SPR_SPRG5, "SPRG5",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_generic, &spr_write_generic,
717 spr_register(env, SPR_SPRG6, "SPRG6",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, &spr_write_generic,
721 spr_register(env, SPR_SPRG7, "SPRG7",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, &spr_write_generic,
725 /* External access control */
726 /* XXX : not implemented */
727 spr_register(env, SPR_EAR, "EAR",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_generic, &spr_write_generic,
733 /* SPR common to all 7xx PowerPC implementations */
734 static void gen_spr_7xx (CPUPPCState *env)
737 /* XXX : not implemented */
738 spr_register(env, SPR_DABR, "DABR",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
742 /* XXX : not implemented */
743 spr_register(env, SPR_IABR, "IABR",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_generic, &spr_write_generic,
747 /* Cache management */
748 /* XXX : not implemented */
749 spr_register(env, SPR_ICTC, "ICTC",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_generic, &spr_write_generic,
753 /* XXX : not implemented */
754 spr_register(env, SPR_L2CR, "L2CR",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_generic, &spr_write_generic,
758 /* Performance monitors */
759 /* XXX : not implemented */
760 spr_register(env, SPR_MMCR0, "MMCR0",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_generic, &spr_write_generic,
764 /* XXX : not implemented */
765 spr_register(env, SPR_MMCR1, "MMCR1",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_generic,
769 /* XXX : not implemented */
770 spr_register(env, SPR_PMC1, "PMC1",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_generic,
774 /* XXX : not implemented */
775 spr_register(env, SPR_PMC2, "PMC2",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
779 /* XXX : not implemented */
780 spr_register(env, SPR_PMC3, "PMC3",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_generic,
784 /* XXX : not implemented */
785 spr_register(env, SPR_PMC4, "PMC4",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
789 /* XXX : not implemented */
790 spr_register(env, SPR_SIAR, "SIAR",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_generic, SPR_NOACCESS,
794 spr_register(env, SPR_UMMCR0, "UMMCR0",
795 &spr_read_ureg, SPR_NOACCESS,
796 &spr_read_ureg, SPR_NOACCESS,
798 spr_register(env, SPR_UMMCR1, "UMMCR1",
799 &spr_read_ureg, SPR_NOACCESS,
800 &spr_read_ureg, SPR_NOACCESS,
802 spr_register(env, SPR_UPMC1, "UPMC1",
803 &spr_read_ureg, SPR_NOACCESS,
804 &spr_read_ureg, SPR_NOACCESS,
806 spr_register(env, SPR_UPMC2, "UPMC2",
807 &spr_read_ureg, SPR_NOACCESS,
808 &spr_read_ureg, SPR_NOACCESS,
810 spr_register(env, SPR_UPMC3, "UPMC3",
811 &spr_read_ureg, SPR_NOACCESS,
812 &spr_read_ureg, SPR_NOACCESS,
814 spr_register(env, SPR_UPMC4, "UPMC4",
815 &spr_read_ureg, SPR_NOACCESS,
816 &spr_read_ureg, SPR_NOACCESS,
818 spr_register(env, SPR_USIAR, "USIAR",
819 &spr_read_ureg, SPR_NOACCESS,
820 &spr_read_ureg, SPR_NOACCESS,
822 /* External access control */
823 /* XXX : not implemented */
824 spr_register(env, SPR_EAR, "EAR",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
830 static void gen_spr_thrm (CPUPPCState *env)
832 /* Thermal management */
833 /* XXX : not implemented */
834 spr_register(env, SPR_THRM1, "THRM1",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, &spr_write_generic,
838 /* XXX : not implemented */
839 spr_register(env, SPR_THRM2, "THRM2",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_generic, &spr_write_generic,
843 /* XXX : not implemented */
844 spr_register(env, SPR_THRM3, "THRM3",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_generic, &spr_write_generic,
850 /* SPR specific to PowerPC 604 implementation */
851 static void gen_spr_604 (CPUPPCState *env)
853 /* Processor identification */
854 spr_register(env, SPR_PIR, "PIR",
855 SPR_NOACCESS, SPR_NOACCESS,
856 &spr_read_generic, &spr_write_pir,
859 /* XXX : not implemented */
860 spr_register(env, SPR_IABR, "IABR",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, &spr_write_generic,
864 /* XXX : not implemented */
865 spr_register(env, SPR_DABR, "DABR",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, &spr_write_generic,
869 /* Performance counters */
870 /* XXX : not implemented */
871 spr_register(env, SPR_MMCR0, "MMCR0",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
875 /* XXX : not implemented */
876 spr_register(env, SPR_MMCR1, "MMCR1",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, &spr_write_generic,
880 /* XXX : not implemented */
881 spr_register(env, SPR_PMC1, "PMC1",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, &spr_write_generic,
885 /* XXX : not implemented */
886 spr_register(env, SPR_PMC2, "PMC2",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, &spr_write_generic,
890 /* XXX : not implemented */
891 spr_register(env, SPR_PMC3, "PMC3",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
895 /* XXX : not implemented */
896 spr_register(env, SPR_PMC4, "PMC4",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
900 /* XXX : not implemented */
901 spr_register(env, SPR_SIAR, "SIAR",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, SPR_NOACCESS,
905 /* XXX : not implemented */
906 spr_register(env, SPR_SDA, "SDA",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, SPR_NOACCESS,
910 /* External access control */
911 /* XXX : not implemented */
912 spr_register(env, SPR_EAR, "EAR",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
918 /* SPR specific to PowerPC 603 implementation */
919 static void gen_spr_603 (CPUPPCState *env)
921 /* External access control */
922 /* XXX : not implemented */
923 spr_register(env, SPR_EAR, "EAR",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
929 /* SPR specific to PowerPC G2 implementation */
930 static void gen_spr_G2 (CPUPPCState *env)
932 /* Memory base address */
934 spr_register(env, SPR_MBAR, "MBAR",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
938 /* System version register */
940 spr_register(env, SPR_SVR, "SVR",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, SPR_NOACCESS,
944 /* Exception processing */
945 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
949 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
954 /* XXX : not implemented */
955 spr_register(env, SPR_DABR, "DABR",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
959 /* XXX : not implemented */
960 spr_register(env, SPR_DABR2, "DABR2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
964 /* XXX : not implemented */
965 spr_register(env, SPR_IABR, "IABR",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
969 /* XXX : not implemented */
970 spr_register(env, SPR_IABR2, "IABR2",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
974 /* XXX : not implemented */
975 spr_register(env, SPR_IBCR, "IBCR",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, &spr_write_generic,
979 /* XXX : not implemented */
980 spr_register(env, SPR_DBCR, "DBCR",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
986 /* SPR specific to PowerPC 602 implementation */
987 static void gen_spr_602 (CPUPPCState *env)
990 /* XXX : not implemented */
991 spr_register(env, SPR_SER, "SER",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
995 /* XXX : not implemented */
996 spr_register(env, SPR_SEBR, "SEBR",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_ESASRR, "ESASRR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1005 /* Floating point status */
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_SP, "SP",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1011 /* XXX : not implemented */
1012 spr_register(env, SPR_LT, "LT",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1016 /* Watchdog timer */
1017 /* XXX : not implemented */
1018 spr_register(env, SPR_TCR, "TCR",
1019 SPR_NOACCESS, SPR_NOACCESS,
1020 &spr_read_generic, &spr_write_generic,
1022 /* Interrupt base */
1023 spr_register(env, SPR_IBR, "IBR",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_generic,
1027 /* XXX : not implemented */
1028 spr_register(env, SPR_IABR, "IABR",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, &spr_write_generic,
1034 /* SPR specific to PowerPC 601 implementation */
1035 static void gen_spr_601 (CPUPPCState *env)
1037 /* Multiplication/division register */
1039 spr_register(env, SPR_MQ, "MQ",
1040 &spr_read_generic, &spr_write_generic,
1041 &spr_read_generic, &spr_write_generic,
1044 spr_register(env, SPR_601_RTCU, "RTCU",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 SPR_NOACCESS, &spr_write_601_rtcu,
1048 spr_register(env, SPR_601_VRTCU, "RTCU",
1049 &spr_read_601_rtcu, SPR_NOACCESS,
1050 &spr_read_601_rtcu, SPR_NOACCESS,
1052 spr_register(env, SPR_601_RTCL, "RTCL",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 SPR_NOACCESS, &spr_write_601_rtcl,
1056 spr_register(env, SPR_601_VRTCL, "RTCL",
1057 &spr_read_601_rtcl, SPR_NOACCESS,
1058 &spr_read_601_rtcl, SPR_NOACCESS,
1062 spr_register(env, SPR_601_UDECR, "UDECR",
1063 &spr_read_decr, SPR_NOACCESS,
1064 &spr_read_decr, SPR_NOACCESS,
1067 /* External access control */
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_EAR, "EAR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1073 /* Memory management */
1074 spr_register(env, SPR_IBAT0U, "IBAT0U",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_601_ubat, &spr_write_601_ubatu,
1078 spr_register(env, SPR_IBAT0L, "IBAT0L",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_601_ubat, &spr_write_601_ubatl,
1082 spr_register(env, SPR_IBAT1U, "IBAT1U",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_601_ubat, &spr_write_601_ubatu,
1086 spr_register(env, SPR_IBAT1L, "IBAT1L",
1087 SPR_NOACCESS, SPR_NOACCESS,
1088 &spr_read_601_ubat, &spr_write_601_ubatl,
1090 spr_register(env, SPR_IBAT2U, "IBAT2U",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_601_ubat, &spr_write_601_ubatu,
1094 spr_register(env, SPR_IBAT2L, "IBAT2L",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_601_ubat, &spr_write_601_ubatl,
1098 spr_register(env, SPR_IBAT3U, "IBAT3U",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_601_ubat, &spr_write_601_ubatu,
1102 spr_register(env, SPR_IBAT3L, "IBAT3L",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_601_ubat, &spr_write_601_ubatl,
1109 static void gen_spr_74xx (CPUPPCState *env)
1111 /* Processor identification */
1112 spr_register(env, SPR_PIR, "PIR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_pir,
1116 /* XXX : not implemented */
1117 spr_register(env, SPR_MMCR2, "MMCR2",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1121 spr_register(env, SPR_UMMCR2, "UMMCR2",
1122 &spr_read_ureg, SPR_NOACCESS,
1123 &spr_read_ureg, SPR_NOACCESS,
1125 /* XXX: not implemented */
1126 spr_register(env, SPR_BAMR, "BAMR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1130 spr_register(env, SPR_UBAMR, "UBAMR",
1131 &spr_read_ureg, SPR_NOACCESS,
1132 &spr_read_ureg, SPR_NOACCESS,
1134 spr_register(env, SPR_MSSCR0, "MSSCR0",
1135 SPR_NOACCESS, SPR_NOACCESS,
1136 &spr_read_generic, &spr_write_generic,
1138 /* Hardware implementation registers */
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_HID0, "HID0",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_HID1, "HID1",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_generic,
1150 spr_register(env, SPR_VRSAVE, "VRSAVE",
1151 &spr_read_generic, &spr_write_generic,
1152 &spr_read_generic, &spr_write_generic,
1157 static void gen_l3_ctrl (CPUPPCState *env)
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_L3CR, "L3CR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1166 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_generic,
1171 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1176 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1181 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1186 spr_register(env, SPR_L3OHCR, "L3OHCR",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1191 spr_register(env, SPR_L3PM, "L3PM",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1199 static void gen_74xx_soft_tlb (CPUPPCState *env)
1202 spr_register(env, SPR_PTEHI, "PTEHI",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1206 spr_register(env, SPR_PTELO, "PTELO",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1210 spr_register(env, SPR_TLBMISS, "TLBMISS",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_generic,
1217 /* PowerPC BookE SPR */
1218 static void gen_spr_BookE (CPUPPCState *env)
1220 /* Processor identification */
1221 spr_register(env, SPR_BOOKE_PIR, "PIR",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_pir,
1225 /* Interrupt processing */
1226 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1230 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1235 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1239 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1245 /* XXX : not implemented */
1246 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_generic, &spr_write_generic,
1250 /* XXX : not implemented */
1251 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1255 /* XXX : not implemented */
1256 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, &spr_write_generic,
1260 /* XXX : not implemented */
1261 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1262 SPR_NOACCESS, SPR_NOACCESS,
1263 &spr_read_generic, &spr_write_generic,
1265 /* XXX : not implemented */
1266 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1270 /* XXX : not implemented */
1271 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_generic, &spr_write_generic,
1275 /* XXX : not implemented */
1276 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1280 /* XXX : not implemented */
1281 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1285 /* XXX : not implemented */
1286 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_generic,
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1300 /* XXX : not implemented */
1301 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_clear,
1305 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1309 spr_register(env, SPR_BOOKE_ESR, "ESR",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1313 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1314 SPR_NOACCESS, SPR_NOACCESS,
1315 &spr_read_generic, &spr_write_generic,
1317 /* Exception vectors */
1318 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1322 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, &spr_write_generic,
1326 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1330 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1334 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1338 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1342 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1346 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1350 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1354 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1358 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1362 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1366 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1370 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1374 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1378 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1383 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1387 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1391 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1395 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1396 SPR_NOACCESS, SPR_NOACCESS,
1397 &spr_read_generic, &spr_write_generic,
1399 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1403 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1408 spr_register(env, SPR_BOOKE_PID, "PID",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1412 spr_register(env, SPR_BOOKE_TCR, "TCR",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_booke_tcr,
1416 spr_register(env, SPR_BOOKE_TSR, "TSR",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_booke_tsr,
1421 spr_register(env, SPR_DECR, "DECR",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_decr, &spr_write_decr,
1425 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 SPR_NOACCESS, &spr_write_generic,
1430 spr_register(env, SPR_USPRG0, "USPRG0",
1431 &spr_read_generic, &spr_write_generic,
1432 &spr_read_generic, &spr_write_generic,
1434 spr_register(env, SPR_SPRG4, "SPRG4",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1438 spr_register(env, SPR_USPRG4, "USPRG4",
1439 &spr_read_ureg, SPR_NOACCESS,
1440 &spr_read_ureg, SPR_NOACCESS,
1442 spr_register(env, SPR_SPRG5, "SPRG5",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_generic, &spr_write_generic,
1446 spr_register(env, SPR_USPRG5, "USPRG5",
1447 &spr_read_ureg, SPR_NOACCESS,
1448 &spr_read_ureg, SPR_NOACCESS,
1450 spr_register(env, SPR_SPRG6, "SPRG6",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1454 spr_register(env, SPR_USPRG6, "USPRG6",
1455 &spr_read_ureg, SPR_NOACCESS,
1456 &spr_read_ureg, SPR_NOACCESS,
1458 spr_register(env, SPR_SPRG7, "SPRG7",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1462 spr_register(env, SPR_USPRG7, "USPRG7",
1463 &spr_read_ureg, SPR_NOACCESS,
1464 &spr_read_ureg, SPR_NOACCESS,
1468 /* FSL storage control registers */
1470 static void gen_spr_BookE_FSL (CPUPPCState *env)
1472 /* TLB assist registers */
1473 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1477 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1481 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1485 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1489 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1493 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1497 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1501 if (env->nb_pids > 1) {
1502 spr_register(env, SPR_BOOKE_PID1, "PID1",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1507 if (env->nb_pids > 2) {
1508 spr_register(env, SPR_BOOKE_PID2, "PID2",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1513 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, SPR_NOACCESS,
1516 0x00000000); /* TOFIX */
1517 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_generic,
1520 0x00000000); /* TOFIX */
1521 switch (env->nb_ways) {
1523 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, SPR_NOACCESS,
1526 0x00000000); /* TOFIX */
1529 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, SPR_NOACCESS,
1532 0x00000000); /* TOFIX */
1535 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, SPR_NOACCESS,
1538 0x00000000); /* TOFIX */
1541 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, SPR_NOACCESS,
1544 0x00000000); /* TOFIX */
1553 /* SPR specific to PowerPC 440 implementation */
1554 static void gen_spr_440 (CPUPPCState *env)
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_440_DNV0, "DNV0",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_440_DNV1, "DNV1",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_440_DNV2, "DNV2",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1572 /* XXX : not implemented */
1573 spr_register(env, SPR_440_DNV3, "DNV3",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1577 /* XXX : not implemented */
1578 spr_register(env, SPR_440_DTV0, "DTV0",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1582 /* XXX : not implemented */
1583 spr_register(env, SPR_440_DTV1, "DTV1",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1587 /* XXX : not implemented */
1588 spr_register(env, SPR_440_DTV2, "DTV2",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1592 /* XXX : not implemented */
1593 spr_register(env, SPR_440_DTV3, "DTV3",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1597 /* XXX : not implemented */
1598 spr_register(env, SPR_440_DVLIM, "DVLIM",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_440_INV0, "INV0",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1607 /* XXX : not implemented */
1608 spr_register(env, SPR_440_INV1, "INV1",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1612 /* XXX : not implemented */
1613 spr_register(env, SPR_440_INV2, "INV2",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic,
1617 /* XXX : not implemented */
1618 spr_register(env, SPR_440_INV3, "INV3",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_generic,
1622 /* XXX : not implemented */
1623 spr_register(env, SPR_440_ITV0, "ITV0",
1624 SPR_NOACCESS, SPR_NOACCESS,
1625 &spr_read_generic, &spr_write_generic,
1627 /* XXX : not implemented */
1628 spr_register(env, SPR_440_ITV1, "ITV1",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1632 /* XXX : not implemented */
1633 spr_register(env, SPR_440_ITV2, "ITV2",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1637 /* XXX : not implemented */
1638 spr_register(env, SPR_440_ITV3, "ITV3",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1642 /* XXX : not implemented */
1643 spr_register(env, SPR_440_IVLIM, "IVLIM",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1648 /* XXX : not implemented */
1649 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1650 SPR_NOACCESS, SPR_NOACCESS,
1651 &spr_read_generic, SPR_NOACCESS,
1653 /* XXX : not implemented */
1654 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, SPR_NOACCESS,
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, SPR_NOACCESS,
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, SPR_NOACCESS,
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, SPR_NOACCESS,
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_440_DBDR, "DBDR",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_generic,
1678 /* Processor control */
1679 spr_register(env, SPR_4xx_CCR0, "CCR0",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1683 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, SPR_NOACCESS,
1687 /* Storage control */
1688 spr_register(env, SPR_440_MMUCR, "MMUCR",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1694 /* SPR shared between PowerPC 40x implementations */
1695 static void gen_spr_40x (CPUPPCState *env)
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_40x_DCCR, "DCCR",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_40x_ICCR, "ICCR",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, SPR_NOACCESS,
1714 spr_register(env, SPR_40x_DEAR, "DEAR",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1718 spr_register(env, SPR_40x_ESR, "ESR",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1722 spr_register(env, SPR_40x_EVPR, "EVPR",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, &spr_write_generic,
1726 spr_register(env, SPR_40x_SRR2, "SRR2",
1727 &spr_read_generic, &spr_write_generic,
1728 &spr_read_generic, &spr_write_generic,
1730 spr_register(env, SPR_40x_SRR3, "SRR3",
1731 &spr_read_generic, &spr_write_generic,
1732 &spr_read_generic, &spr_write_generic,
1735 spr_register(env, SPR_40x_PIT, "PIT",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_40x_pit, &spr_write_40x_pit,
1739 spr_register(env, SPR_40x_TCR, "TCR",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_booke_tcr,
1743 spr_register(env, SPR_40x_TSR, "TSR",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_booke_tsr,
1749 /* SPR specific to PowerPC 405 implementation */
1750 static void gen_spr_405 (CPUPPCState *env)
1753 spr_register(env, SPR_40x_PID, "PID",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1757 spr_register(env, SPR_4xx_CCR0, "CCR0",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1761 /* Debug interface */
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_40x_dbcr0,
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_405_DBCR1, "DBCR1",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_40x_DBSR, "DBSR",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_clear,
1776 /* Last reset was system reset */
1778 /* XXX : not implemented */
1779 spr_register(env, SPR_40x_DAC1, "DAC1",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1783 spr_register(env, SPR_40x_DAC2, "DAC2",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1787 /* XXX : not implemented */
1788 spr_register(env, SPR_405_DVC1, "DVC1",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1792 /* XXX : not implemented */
1793 spr_register(env, SPR_405_DVC2, "DVC2",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1797 /* XXX : not implemented */
1798 spr_register(env, SPR_40x_IAC1, "IAC1",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1802 spr_register(env, SPR_40x_IAC2, "IAC2",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1806 /* XXX : not implemented */
1807 spr_register(env, SPR_405_IAC3, "IAC3",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_405_IAC4, "IAC4",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1816 /* Storage control */
1817 spr_register(env, SPR_405_SLER, "SLER",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_40x_sler,
1821 spr_register(env, SPR_40x_ZPR, "ZPR",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, &spr_write_generic,
1825 /* XXX : not implemented */
1826 spr_register(env, SPR_405_SU0R, "SU0R",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1831 spr_register(env, SPR_USPRG0, "USPRG0",
1832 &spr_read_ureg, SPR_NOACCESS,
1833 &spr_read_ureg, SPR_NOACCESS,
1835 spr_register(env, SPR_SPRG4, "SPRG4",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, &spr_write_generic,
1839 spr_register(env, SPR_USPRG4, "USPRG4",
1840 &spr_read_ureg, SPR_NOACCESS,
1841 &spr_read_ureg, SPR_NOACCESS,
1843 spr_register(env, SPR_SPRG5, "SPRG5",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 spr_read_generic, &spr_write_generic,
1847 spr_register(env, SPR_USPRG5, "USPRG5",
1848 &spr_read_ureg, SPR_NOACCESS,
1849 &spr_read_ureg, SPR_NOACCESS,
1851 spr_register(env, SPR_SPRG6, "SPRG6",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 spr_read_generic, &spr_write_generic,
1855 spr_register(env, SPR_USPRG6, "USPRG6",
1856 &spr_read_ureg, SPR_NOACCESS,
1857 &spr_read_ureg, SPR_NOACCESS,
1859 spr_register(env, SPR_SPRG7, "SPRG7",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 spr_read_generic, &spr_write_generic,
1863 spr_register(env, SPR_USPRG7, "USPRG7",
1864 &spr_read_ureg, SPR_NOACCESS,
1865 &spr_read_ureg, SPR_NOACCESS,
1869 /* SPR shared between PowerPC 401 & 403 implementations */
1870 static void gen_spr_401_403 (CPUPPCState *env)
1873 spr_register(env, SPR_403_VTBL, "TBL",
1874 &spr_read_tbl, SPR_NOACCESS,
1875 &spr_read_tbl, SPR_NOACCESS,
1877 spr_register(env, SPR_403_TBL, "TBL",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 SPR_NOACCESS, &spr_write_tbl,
1881 spr_register(env, SPR_403_VTBU, "TBU",
1882 &spr_read_tbu, SPR_NOACCESS,
1883 &spr_read_tbu, SPR_NOACCESS,
1885 spr_register(env, SPR_403_TBU, "TBU",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 SPR_NOACCESS, &spr_write_tbu,
1890 /* XXX: not implemented */
1891 spr_register(env, SPR_403_CDBCR, "CDBCR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1897 /* SPR specific to PowerPC 401 implementation */
1898 static void gen_spr_401 (CPUPPCState *env)
1900 /* Debug interface */
1901 /* XXX : not implemented */
1902 spr_register(env, SPR_40x_DBCR0, "DBCR",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_40x_dbcr0,
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_40x_DBSR, "DBSR",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_clear,
1910 /* Last reset was system reset */
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_40x_DAC1, "DAC",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1917 /* XXX : not implemented */
1918 spr_register(env, SPR_40x_IAC1, "IAC",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1922 /* Storage control */
1923 spr_register(env, SPR_405_SLER, "SLER",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_40x_sler,
1929 static void gen_spr_401x2 (CPUPPCState *env)
1932 spr_register(env, SPR_40x_PID, "PID",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_generic,
1936 spr_register(env, SPR_40x_ZPR, "ZPR",
1937 SPR_NOACCESS, SPR_NOACCESS,
1938 &spr_read_generic, &spr_write_generic,
1942 /* SPR specific to PowerPC 403 implementation */
1943 static void gen_spr_403 (CPUPPCState *env)
1945 /* Debug interface */
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_40x_dbcr0,
1951 /* XXX : not implemented */
1952 spr_register(env, SPR_40x_DBSR, "DBSR",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_clear,
1955 /* Last reset was system reset */
1957 /* XXX : not implemented */
1958 spr_register(env, SPR_40x_DAC1, "DAC1",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1962 spr_register(env, SPR_40x_DAC2, "DAC2",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1966 /* XXX : not implemented */
1967 spr_register(env, SPR_40x_IAC1, "IAC1",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 &spr_read_generic, &spr_write_generic,
1971 spr_register(env, SPR_40x_IAC2, "IAC2",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 &spr_read_generic, &spr_write_generic,
1977 static void gen_spr_403_real (CPUPPCState *env)
1979 spr_register(env, SPR_403_PBL1, "PBL1",
1980 SPR_NOACCESS, SPR_NOACCESS,
1981 &spr_read_403_pbr, &spr_write_403_pbr,
1983 spr_register(env, SPR_403_PBU1, "PBU1",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_403_pbr, &spr_write_403_pbr,
1987 spr_register(env, SPR_403_PBL2, "PBL2",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_403_pbr, &spr_write_403_pbr,
1991 spr_register(env, SPR_403_PBU2, "PBU2",
1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_403_pbr, &spr_write_403_pbr,
1997 static void gen_spr_403_mmu (CPUPPCState *env)
2000 spr_register(env, SPR_40x_PID, "PID",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2004 spr_register(env, SPR_40x_ZPR, "ZPR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2010 /* SPR specific to PowerPC compression coprocessor extension */
2011 static void gen_spr_compress (CPUPPCState *env)
2013 spr_register(env, SPR_401_SKR, "SKR",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2019 #if defined (TARGET_PPC64)
2021 /* SPR specific to PowerPC 620 */
2022 static void gen_spr_620 (CPUPPCState *env)
2024 spr_register(env, SPR_620_PMR0, "PMR0",
2025 SPR_NOACCESS, SPR_NOACCESS,
2026 &spr_read_generic, &spr_write_generic,
2028 spr_register(env, SPR_620_PMR1, "PMR1",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, &spr_write_generic,
2032 spr_register(env, SPR_620_PMR2, "PMR2",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 &spr_read_generic, &spr_write_generic,
2036 spr_register(env, SPR_620_PMR3, "PMR3",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_generic,
2040 spr_register(env, SPR_620_PMR4, "PMR4",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2044 spr_register(env, SPR_620_PMR5, "PMR5",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2048 spr_register(env, SPR_620_PMR6, "PMR6",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, &spr_write_generic,
2052 spr_register(env, SPR_620_PMR7, "PMR7",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_generic,
2056 spr_register(env, SPR_620_PMR8, "PMR8",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_generic,
2060 spr_register(env, SPR_620_PMR9, "PMR9",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2064 spr_register(env, SPR_620_PMRA, "PMR10",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2068 spr_register(env, SPR_620_PMRB, "PMR11",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2072 spr_register(env, SPR_620_PMRC, "PMR12",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2076 spr_register(env, SPR_620_PMRD, "PMR13",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2080 spr_register(env, SPR_620_PMRE, "PMR14",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2084 spr_register(env, SPR_620_PMRF, "PMR15",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2088 spr_register(env, SPR_620_HID8, "HID8",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2092 spr_register(env, SPR_620_HID9, "HID9",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2098 #endif /* defined (TARGET_PPC64) */
2102 * AMR => SPR 29 (Power 2.04)
2103 * CTRL => SPR 136 (Power 2.04)
2104 * CTRL => SPR 152 (Power 2.04)
2105 * SCOMC => SPR 276 (64 bits ?)
2106 * SCOMD => SPR 277 (64 bits ?)
2107 * ASR => SPR 280 (64 bits)
2108 * TBU40 => SPR 286 (Power 2.04 hypv)
2109 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2110 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2111 * HDSISR => SPR 306 (Power 2.04 hypv)
2112 * HDAR => SPR 307 (Power 2.04 hypv)
2113 * PURR => SPR 309 (Power 2.04 hypv)
2114 * HDEC => SPR 310 (Power 2.04 hypv)
2115 * HIOR => SPR 311 (hypv)
2116 * RMOR => SPR 312 (970)
2117 * HRMOR => SPR 313 (Power 2.04 hypv)
2118 * HSRR0 => SPR 314 (Power 2.04 hypv)
2119 * HSRR1 => SPR 315 (Power 2.04 hypv)
2120 * LPCR => SPR 316 (970)
2121 * LPIDR => SPR 317 (970)
2122 * SPEFSCR => SPR 512 (Power 2.04 emb)
2123 * ATBL => SPR 526 (Power 2.04 emb)
2124 * ATBU => SPR 527 (Power 2.04 emb)
2125 * EPR => SPR 702 (Power 2.04 emb)
2126 * perf => 768-783 (Power 2.04)
2127 * perf => 784-799 (Power 2.04)
2128 * PPR => SPR 896 (Power 2.04)
2129 * EPLC => SPR 947 (Power 2.04 emb)
2130 * EPSC => SPR 948 (Power 2.04 emb)
2131 * DABRX => 1015 (Power 2.04 hypv)
2132 * FPECR => SPR 1022 (?)
2133 * ... and more (thermal management, performance counters, ...)
2136 /*****************************************************************************/
2137 /* Exception vectors models */
2138 static void init_excp_4xx_real (CPUPPCState *env)
2140 #if !defined(CONFIG_USER_ONLY)
2141 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2142 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2143 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2144 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2145 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2146 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2147 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2148 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2149 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2150 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2154 static void init_excp_4xx_softmmu (CPUPPCState *env)
2156 #if !defined(CONFIG_USER_ONLY)
2157 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2158 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2159 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2160 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2161 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2162 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2163 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2164 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2165 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2166 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2167 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2168 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2169 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2170 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2174 static void init_excp_BookE (CPUPPCState *env)
2176 #if !defined(CONFIG_USER_ONLY)
2177 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2178 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2179 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2180 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2181 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2182 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2183 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2184 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2185 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2186 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2187 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2188 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2189 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2190 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2191 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2192 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2193 env->excp_prefix = 0x00000000;
2194 env->ivor_mask = 0x0000FFE0;
2195 env->ivpr_mask = 0xFFFF0000;
2199 static void init_excp_601 (CPUPPCState *env)
2201 #if !defined(CONFIG_USER_ONLY)
2202 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2203 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2204 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2205 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2206 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2207 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2208 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2209 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2210 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2211 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2212 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2213 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2214 env->excp_prefix = 0xFFF00000;
2218 static void init_excp_602 (CPUPPCState *env)
2220 #if !defined(CONFIG_USER_ONLY)
2221 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2222 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2223 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2224 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2225 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2226 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2227 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2228 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2229 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2230 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2231 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2232 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2233 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2234 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2235 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2236 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2237 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2238 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2239 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2240 env->excp_prefix = 0xFFF00000;
2244 static void init_excp_603 (CPUPPCState *env)
2246 #if !defined(CONFIG_USER_ONLY)
2247 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2248 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2249 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2250 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2251 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2252 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2253 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2254 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2255 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2256 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2257 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2258 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2259 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2260 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2261 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2262 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2266 static void init_excp_G2 (CPUPPCState *env)
2268 #if !defined(CONFIG_USER_ONLY)
2269 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2270 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2271 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2272 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2273 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2274 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2275 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2276 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2277 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2278 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2279 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2280 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2281 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2282 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2283 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2284 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2285 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2289 static void init_excp_604 (CPUPPCState *env)
2291 #if !defined(CONFIG_USER_ONLY)
2292 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2293 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2294 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2295 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2296 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2297 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2298 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2299 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2300 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2301 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2302 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2303 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2304 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2305 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2310 static void init_excp_620 (CPUPPCState *env)
2312 #if !defined(CONFIG_USER_ONLY)
2313 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2314 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2315 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2316 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2317 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2318 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2319 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2320 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2321 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2322 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2323 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2324 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2325 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2326 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2327 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2330 #endif /* defined (TODO) */
2332 static void init_excp_7x0 (CPUPPCState *env)
2334 #if !defined(CONFIG_USER_ONLY)
2335 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2336 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2337 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2338 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2339 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2340 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2341 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2342 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2343 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2344 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2345 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2346 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2348 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2352 static void init_excp_750FX (CPUPPCState *env)
2354 #if !defined(CONFIG_USER_ONLY)
2355 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2356 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2357 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2358 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2359 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2360 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2361 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2362 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2363 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2364 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2365 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2366 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2367 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2368 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2369 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2373 static void init_excp_7400 (CPUPPCState *env)
2375 #if !defined(CONFIG_USER_ONLY)
2376 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2377 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2378 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2379 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2380 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2381 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2382 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2383 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2384 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2385 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2386 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2387 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2388 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2389 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2390 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2391 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2392 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2397 static void init_excp_7450 (CPUPPCState *env)
2399 #if !defined(CONFIG_USER_ONLY)
2400 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2401 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2402 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2403 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2404 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2405 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2406 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2407 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2408 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2409 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2410 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2411 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2412 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2413 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2414 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2415 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2416 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2417 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2418 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2421 #endif /* defined (TODO) */
2423 #if defined (TARGET_PPC64)
2424 static void init_excp_970 (CPUPPCState *env)
2426 #if !defined(CONFIG_USER_ONLY)
2427 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2428 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2429 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2430 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2431 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2432 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2433 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2434 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2435 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2436 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2437 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2438 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2439 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2441 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2442 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2443 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2444 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2445 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2446 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2447 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2448 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2453 /*****************************************************************************/
2454 /* PowerPC implementations definitions */
2456 /* PowerPC 40x instruction set */
2457 #define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
2460 #define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | \
2461 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2462 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2463 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
2464 #define POWERPC_MMU_401 (POWERPC_MMU_REAL_4xx)
2465 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
2466 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
2467 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
2469 static void init_proc_401 (CPUPPCState *env)
2472 gen_spr_401_403(env);
2474 /* Bus access control */
2475 spr_register(env, SPR_40x_SGR, "SGR",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_40x_DCWR, "DCWR",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2484 init_excp_4xx_real(env);
2485 /* XXX: TODO: allocate internal IRQ controller */
2489 #define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | \
2490 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2491 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2492 PPC_CACHE_DCBA | PPC_MFTB | \
2493 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2494 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
2495 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
2496 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
2497 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
2498 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
2500 static void init_proc_401x2 (CPUPPCState *env)
2503 gen_spr_401_403(env);
2505 gen_spr_compress(env);
2506 /* Bus access control */
2507 spr_register(env, SPR_40x_SGR, "SGR",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_40x_DCWR, "DCWR",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2516 /* Memory management */
2520 init_excp_4xx_softmmu(env);
2521 /* XXX: TODO: allocate internal IRQ controller */
2526 #define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | \
2527 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2528 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2529 PPC_CACHE_DCBA | PPC_MFTB | \
2530 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2531 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
2532 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
2533 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
2534 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
2535 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
2537 static void init_proc_401x3 (CPUPPCState *env)
2539 init_excp_4xx_softmmu(env);
2544 #define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | \
2545 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2546 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2548 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2549 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
2550 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
2551 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
2552 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2553 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
2555 static void init_proc_IOP480 (CPUPPCState *env)
2558 gen_spr_401_403(env);
2560 gen_spr_compress(env);
2561 /* Bus access control */
2562 spr_register(env, SPR_40x_SGR, "SGR",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_40x_DCWR, "DCWR",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2571 /* Memory management */
2575 init_excp_4xx_softmmu(env);
2576 /* XXX: TODO: allocate internal IRQ controller */
2580 #define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | \
2581 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2582 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2583 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2584 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
2585 #define POWERPC_MMU_403 (POWERPC_MMU_REAL_4xx)
2586 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
2587 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
2588 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
2590 static void init_proc_403 (CPUPPCState *env)
2593 gen_spr_401_403(env);
2595 gen_spr_403_real(env);
2596 init_excp_4xx_real(env);
2597 /* XXX: TODO: allocate internal IRQ controller */
2600 /* PowerPC 403 GCX */
2601 #define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | \
2602 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2603 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2604 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2605 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
2606 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
2607 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
2608 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2609 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
2611 static void init_proc_403GCX (CPUPPCState *env)
2614 gen_spr_401_403(env);
2616 gen_spr_403_real(env);
2617 gen_spr_403_mmu(env);
2618 /* Bus access control */
2619 spr_register(env, SPR_40x_SGR, "SGR",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_40x_DCWR, "DCWR",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2628 /* Memory management */
2632 init_excp_4xx_softmmu(env);
2633 /* XXX: TODO: allocate internal IRQ controller */
2637 #define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_MFTB | \
2638 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2639 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2640 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
2642 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
2643 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
2644 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
2645 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
2646 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
2648 static void init_proc_405 (CPUPPCState *env)
2654 /* Bus access control */
2655 spr_register(env, SPR_40x_SGR, "SGR",
2656 SPR_NOACCESS, SPR_NOACCESS,
2657 &spr_read_generic, &spr_write_generic,
2659 /* XXX : not implemented */
2660 spr_register(env, SPR_40x_DCWR, "DCWR",
2661 SPR_NOACCESS, SPR_NOACCESS,
2662 &spr_read_generic, &spr_write_generic,
2664 /* Memory management */
2668 init_excp_4xx_softmmu(env);
2669 /* Allocate hardware IRQ controller */
2670 ppc405_irq_init(env);
2673 /* PowerPC 440 EP */
2674 #define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | \
2675 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2676 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2677 PPC_440_SPEC | PPC_RFMCI)
2678 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
2679 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
2680 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
2681 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
2682 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
2684 static void init_proc_440EP (CPUPPCState *env)
2690 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2691 SPR_NOACCESS, SPR_NOACCESS,
2692 &spr_read_generic, &spr_write_generic,
2694 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2695 SPR_NOACCESS, SPR_NOACCESS,
2696 &spr_read_generic, &spr_write_generic,
2698 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2699 SPR_NOACCESS, SPR_NOACCESS,
2700 &spr_read_generic, &spr_write_generic,
2702 spr_register(env, SPR_440_CCR1, "CCR1",
2703 SPR_NOACCESS, SPR_NOACCESS,
2704 &spr_read_generic, &spr_write_generic,
2706 /* Memory management */
2710 init_excp_BookE(env);
2711 /* XXX: TODO: allocate internal IRQ controller */
2714 /* PowerPC 440 GP */
2715 #define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | \
2716 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2717 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2718 PPC_405_MAC | PPC_440_SPEC)
2719 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
2720 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
2721 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
2722 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
2723 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
2725 static void init_proc_440GP (CPUPPCState *env)
2731 /* Memory management */
2735 init_excp_BookE(env);
2736 /* XXX: TODO: allocate internal IRQ controller */
2741 #define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | \
2742 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2743 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2745 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
2746 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
2747 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
2748 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
2749 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
2751 static void init_proc_440x4 (CPUPPCState *env)
2757 /* Memory management */
2761 init_excp_BookE(env);
2762 /* XXX: TODO: allocate internal IRQ controller */
2767 #define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | \
2768 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2769 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
2770 PPC_440_SPEC | PPC_RFMCI)
2771 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
2772 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
2773 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
2774 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
2775 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
2777 static void init_proc_440x5 (CPUPPCState *env)
2783 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2784 SPR_NOACCESS, SPR_NOACCESS,
2785 &spr_read_generic, &spr_write_generic,
2787 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2788 SPR_NOACCESS, SPR_NOACCESS,
2789 &spr_read_generic, &spr_write_generic,
2791 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2792 SPR_NOACCESS, SPR_NOACCESS,
2793 &spr_read_generic, &spr_write_generic,
2795 spr_register(env, SPR_440_CCR1, "CCR1",
2796 SPR_NOACCESS, SPR_NOACCESS,
2797 &spr_read_generic, &spr_write_generic,
2799 /* Memory management */
2803 init_excp_BookE(env);
2804 /* XXX: TODO: allocate internal IRQ controller */
2807 /* PowerPC 460 (guessed) */
2809 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2810 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2811 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2812 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2813 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2814 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
2815 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
2816 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
2817 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
2819 static void init_proc_460 (CPUPPCState *env)
2825 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2826 SPR_NOACCESS, SPR_NOACCESS,
2827 &spr_read_generic, &spr_write_generic,
2829 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2830 SPR_NOACCESS, SPR_NOACCESS,
2831 &spr_read_generic, &spr_write_generic,
2833 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2834 SPR_NOACCESS, SPR_NOACCESS,
2835 &spr_read_generic, &spr_write_generic,
2837 spr_register(env, SPR_440_CCR1, "CCR1",
2838 SPR_NOACCESS, SPR_NOACCESS,
2839 &spr_read_generic, &spr_write_generic,
2841 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2842 &spr_read_generic, &spr_write_generic,
2843 &spr_read_generic, &spr_write_generic,
2845 /* Memory management */
2849 init_excp_BookE(env);
2850 /* XXX: TODO: allocate internal IRQ controller */
2854 /* PowerPC 460F (guessed) */
2856 #define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | \
2857 PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
2858 PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
2859 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
2860 PPC_FLOAT_STFIWX | \
2861 PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON | \
2862 PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2863 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
2864 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
2865 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
2866 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
2867 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
2869 static void init_proc_460F (CPUPPCState *env)
2875 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2876 SPR_NOACCESS, SPR_NOACCESS,
2877 &spr_read_generic, &spr_write_generic,
2879 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2880 SPR_NOACCESS, SPR_NOACCESS,
2881 &spr_read_generic, &spr_write_generic,
2883 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2884 SPR_NOACCESS, SPR_NOACCESS,
2885 &spr_read_generic, &spr_write_generic,
2887 spr_register(env, SPR_440_CCR1, "CCR1",
2888 SPR_NOACCESS, SPR_NOACCESS,
2889 &spr_read_generic, &spr_write_generic,
2891 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2892 &spr_read_generic, &spr_write_generic,
2893 &spr_read_generic, &spr_write_generic,
2895 /* Memory management */
2899 init_excp_BookE(env);
2900 /* XXX: TODO: allocate internal IRQ controller */
2904 /* Generic BookE PowerPC */
2906 #define POWERPC_INSNS_BookE (POWERPC_INSNS_EMB | \
2907 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2909 PPC_FLOAT | PPC_FLOAT_FSQRT | \
2910 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2911 PPC_FLOAT_FSEL | PPC_FLOAT_STFIW | \
2913 #define POWERPC_MSRM_BookE (0x000000000006D630ULL)
2914 #define POWERPC_MMU_BookE (POWERPC_MMU_BOOKE)
2915 #define POWERPC_EXCP_BookE (POWERPC_EXCP_BOOKE)
2916 #define POWERPC_INPUT_BookE (PPC_FLAGS_INPUT_BookE)
2917 #define POWERPC_BFDM_BookE (bfd_mach_ppc_403)
2919 static void init_proc_BookE (CPUPPCState *env)
2921 init_excp_BookE(env);
2935 #define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | \
2936 PPC_MEM_EIEIO | PPC_MEM_TLBSYNC | \
2938 PPC_BOOKE | PPC_E500_VECTOR)
2939 #define POWERPC_MMU_e500 (POWERPC_MMU_SOFT_4xx)
2940 #define POWERPC_EXCP_e500 (POWERPC_EXCP_40x)
2941 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
2942 #define POWERPC_BFDM_e500 (bfd_mach_ppc_403)
2944 static void init_proc_e500 (CPUPPCState *env)
2949 /* Memory management */
2950 gen_spr_BookE_FSL(env);
2954 init_excp_BookE(env);
2955 /* XXX: TODO: allocate internal IRQ controller */
2963 /* Non-embedded PowerPC */
2964 /* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
2965 #define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
2966 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
2967 /* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
2968 #define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
2969 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
2970 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
2971 PPC_MEM_TLBSYNC | PPC_MFTB)
2973 /* POWER : same as 601, without mfmsr, mfsr */
2975 #define POWERPC_INSNS_POWER (XXX_TODO)
2976 /* POWER RSC (from RAD6000) */
2977 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
2981 #define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
2982 #define POWERPC_MSRM_601 (0x000000000000FE70ULL)
2983 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
2984 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
2985 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
2986 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
2988 static void init_proc_601 (CPUPPCState *env)
2990 gen_spr_ne_601(env);
2992 /* Hardware implementation registers */
2993 /* XXX : not implemented */
2994 spr_register(env, SPR_HID0, "HID0",
2995 SPR_NOACCESS, SPR_NOACCESS,
2996 &spr_read_generic, &spr_write_generic,
2998 /* XXX : not implemented */
2999 spr_register(env, SPR_HID1, "HID1",
3000 SPR_NOACCESS, SPR_NOACCESS,
3001 &spr_read_generic, &spr_write_generic,
3003 /* XXX : not implemented */
3004 spr_register(env, SPR_601_HID2, "HID2",
3005 SPR_NOACCESS, SPR_NOACCESS,
3006 &spr_read_generic, &spr_write_generic,
3008 /* XXX : not implemented */
3009 spr_register(env, SPR_601_HID5, "HID5",
3010 SPR_NOACCESS, SPR_NOACCESS,
3011 &spr_read_generic, &spr_write_generic,
3013 /* XXX : not implemented */
3014 spr_register(env, SPR_601_HID15, "HID15",
3015 SPR_NOACCESS, SPR_NOACCESS,
3016 &spr_read_generic, &spr_write_generic,
3018 /* Memory management */
3024 /* XXX: TODO: allocate internal IRQ controller */
3028 #define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
3029 PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
3030 PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
3031 PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
3032 #define POWERPC_MSRM_602 (0x000000000033FF73ULL)
3033 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
3034 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
3035 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
3036 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
3038 static void init_proc_602 (CPUPPCState *env)
3040 gen_spr_ne_601(env);
3044 /* hardware implementation registers */
3045 /* XXX : not implemented */
3046 spr_register(env, SPR_HID0, "HID0",
3047 SPR_NOACCESS, SPR_NOACCESS,
3048 &spr_read_generic, &spr_write_generic,
3050 /* XXX : not implemented */
3051 spr_register(env, SPR_HID1, "HID1",
3052 SPR_NOACCESS, SPR_NOACCESS,
3053 &spr_read_generic, &spr_write_generic,
3055 /* Memory management */
3057 gen_6xx_7xx_soft_tlb(env, 64, 2);
3059 /* Allocate hardware IRQ controller */
3060 ppc6xx_irq_init(env);
3064 #define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3065 #define POWERPC_MSRM_603 (0x000000000001FF73ULL)
3066 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
3067 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
3068 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
3069 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
3071 static void init_proc_603 (CPUPPCState *env)
3073 gen_spr_ne_601(env);
3077 /* hardware implementation registers */
3078 /* XXX : not implemented */
3079 spr_register(env, SPR_HID0, "HID0",
3080 SPR_NOACCESS, SPR_NOACCESS,
3081 &spr_read_generic, &spr_write_generic,
3083 /* XXX : not implemented */
3084 spr_register(env, SPR_HID1, "HID1",
3085 SPR_NOACCESS, SPR_NOACCESS,
3086 &spr_read_generic, &spr_write_generic,
3088 /* Memory management */
3090 gen_6xx_7xx_soft_tlb(env, 64, 2);
3092 /* Allocate hardware IRQ controller */
3093 ppc6xx_irq_init(env);
3097 #define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3098 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
3099 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
3100 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
3101 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
3102 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
3104 static void init_proc_603E (CPUPPCState *env)
3106 gen_spr_ne_601(env);
3110 /* hardware implementation registers */
3111 /* XXX : not implemented */
3112 spr_register(env, SPR_HID0, "HID0",
3113 SPR_NOACCESS, SPR_NOACCESS,
3114 &spr_read_generic, &spr_write_generic,
3116 /* XXX : not implemented */
3117 spr_register(env, SPR_HID1, "HID1",
3118 SPR_NOACCESS, SPR_NOACCESS,
3119 &spr_read_generic, &spr_write_generic,
3121 /* XXX : not implemented */
3122 spr_register(env, SPR_IABR, "IABR",
3123 SPR_NOACCESS, SPR_NOACCESS,
3124 &spr_read_generic, &spr_write_generic,
3126 /* Memory management */
3128 gen_6xx_7xx_soft_tlb(env, 64, 2);
3130 /* Allocate hardware IRQ controller */
3131 ppc6xx_irq_init(env);
3135 #define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3136 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3137 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3138 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3139 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3140 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3142 static void init_proc_G2 (CPUPPCState *env)
3144 gen_spr_ne_601(env);
3145 gen_spr_G2_755(env);
3149 /* Hardware implementation register */
3150 /* XXX : not implemented */
3151 spr_register(env, SPR_HID0, "HID0",
3152 SPR_NOACCESS, SPR_NOACCESS,
3153 &spr_read_generic, &spr_write_generic,
3155 /* XXX : not implemented */
3156 spr_register(env, SPR_HID1, "HID1",
3157 SPR_NOACCESS, SPR_NOACCESS,
3158 &spr_read_generic, &spr_write_generic,
3160 /* XXX : not implemented */
3161 spr_register(env, SPR_HID2, "HID2",
3162 SPR_NOACCESS, SPR_NOACCESS,
3163 &spr_read_generic, &spr_write_generic,
3165 /* Memory management */
3168 gen_6xx_7xx_soft_tlb(env, 64, 2);
3170 /* Allocate hardware IRQ controller */
3171 ppc6xx_irq_init(env);
3175 #define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3176 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3177 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3178 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3179 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3180 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3182 static void init_proc_G2LE (CPUPPCState *env)
3184 gen_spr_ne_601(env);
3185 gen_spr_G2_755(env);
3189 /* Hardware implementation register */
3190 /* XXX : not implemented */
3191 spr_register(env, SPR_HID0, "HID0",
3192 SPR_NOACCESS, SPR_NOACCESS,
3193 &spr_read_generic, &spr_write_generic,
3195 /* XXX : not implemented */
3196 spr_register(env, SPR_HID1, "HID1",
3197 SPR_NOACCESS, SPR_NOACCESS,
3198 &spr_read_generic, &spr_write_generic,
3200 /* XXX : not implemented */
3201 spr_register(env, SPR_HID2, "HID2",
3202 SPR_NOACCESS, SPR_NOACCESS,
3203 &spr_read_generic, &spr_write_generic,
3205 /* Memory management */
3208 gen_6xx_7xx_soft_tlb(env, 64, 2);
3210 /* Allocate hardware IRQ controller */
3211 ppc6xx_irq_init(env);
3215 #define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3216 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
3217 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
3218 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
3219 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
3220 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
3222 static void init_proc_604 (CPUPPCState *env)
3224 gen_spr_ne_601(env);
3228 /* Hardware implementation registers */
3229 /* XXX : not implemented */
3230 spr_register(env, SPR_HID0, "HID0",
3231 SPR_NOACCESS, SPR_NOACCESS,
3232 &spr_read_generic, &spr_write_generic,
3234 /* XXX : not implemented */
3235 spr_register(env, SPR_HID1, "HID1",
3236 SPR_NOACCESS, SPR_NOACCESS,
3237 &spr_read_generic, &spr_write_generic,
3239 /* Memory management */
3242 /* Allocate hardware IRQ controller */
3243 ppc6xx_irq_init(env);
3246 /* PowerPC 740/750 (aka G3) */
3247 #define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
3248 #define POWERPC_MSRM_7x0 (0x000000000007FF77ULL)
3249 #define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
3250 //#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
3251 #define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
3252 #define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
3254 static void init_proc_7x0 (CPUPPCState *env)
3256 gen_spr_ne_601(env);
3260 /* Thermal management */
3262 /* Hardware implementation registers */
3263 /* XXX : not implemented */
3264 spr_register(env, SPR_HID0, "HID0",
3265 SPR_NOACCESS, SPR_NOACCESS,
3266 &spr_read_generic, &spr_write_generic,
3268 /* XXX : not implemented */
3269 spr_register(env, SPR_HID1, "HID1",
3270 SPR_NOACCESS, SPR_NOACCESS,
3271 &spr_read_generic, &spr_write_generic,
3273 /* Memory management */
3276 /* Allocate hardware IRQ controller */
3277 ppc6xx_irq_init(env);
3280 /* PowerPC 750FX/GX */
3281 #define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
3282 #define POWERPC_MSRM_750fx (0x000000000007FF77ULL)
3283 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
3284 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
3285 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
3286 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
3288 static void init_proc_750fx (CPUPPCState *env)
3290 gen_spr_ne_601(env);
3294 /* Thermal management */
3296 /* Hardware implementation registers */
3297 /* XXX : not implemented */
3298 spr_register(env, SPR_HID0, "HID0",
3299 SPR_NOACCESS, SPR_NOACCESS,
3300 &spr_read_generic, &spr_write_generic,
3302 /* XXX : not implemented */
3303 spr_register(env, SPR_HID1, "HID1",
3304 SPR_NOACCESS, SPR_NOACCESS,
3305 &spr_read_generic, &spr_write_generic,
3307 /* XXX : not implemented */
3308 spr_register(env, SPR_750_HID2, "HID2",
3309 SPR_NOACCESS, SPR_NOACCESS,
3310 &spr_read_generic, &spr_write_generic,
3312 /* Memory management */
3314 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3316 init_excp_750FX(env);
3317 /* Allocate hardware IRQ controller */
3318 ppc6xx_irq_init(env);
3321 /* PowerPC 745/755 */
3322 #define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3323 #define POWERPC_MSRM_7x5 (0x000000000007FF77ULL)
3324 #define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
3325 //#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
3326 #define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
3327 #define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
3329 static void init_proc_7x5 (CPUPPCState *env)
3331 gen_spr_ne_601(env);
3332 gen_spr_G2_755(env);
3335 /* L2 cache control */
3336 /* XXX : not implemented */
3337 spr_register(env, SPR_ICTC, "ICTC",
3338 SPR_NOACCESS, SPR_NOACCESS,
3339 &spr_read_generic, &spr_write_generic,
3341 /* XXX : not implemented */
3342 spr_register(env, SPR_L2PMCR, "L2PMCR",
3343 SPR_NOACCESS, SPR_NOACCESS,
3344 &spr_read_generic, &spr_write_generic,
3346 /* Hardware implementation registers */
3347 /* XXX : not implemented */
3348 spr_register(env, SPR_HID0, "HID0",
3349 SPR_NOACCESS, SPR_NOACCESS,
3350 &spr_read_generic, &spr_write_generic,
3352 /* XXX : not implemented */
3353 spr_register(env, SPR_HID1, "HID1",
3354 SPR_NOACCESS, SPR_NOACCESS,
3355 &spr_read_generic, &spr_write_generic,
3357 /* XXX : not implemented */
3358 spr_register(env, SPR_HID2, "HID2",
3359 SPR_NOACCESS, SPR_NOACCESS,
3360 &spr_read_generic, &spr_write_generic,
3362 /* Memory management */
3365 gen_6xx_7xx_soft_tlb(env, 64, 2);
3366 /* Allocate hardware IRQ controller */
3367 ppc6xx_irq_init(env);
3370 /* PowerPC 7400 (aka G4) */
3371 #define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3372 PPC_EXTERN | PPC_MEM_TLBIA | \
3374 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
3375 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
3376 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
3377 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
3378 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
3380 static void init_proc_7400 (CPUPPCState *env)
3382 gen_spr_ne_601(env);
3386 /* 74xx specific SPR */
3388 /* Thermal management */
3390 /* Memory management */
3392 init_excp_7400(env);
3393 /* Allocate hardware IRQ controller */
3394 ppc6xx_irq_init(env);
3397 /* PowerPC 7410 (aka G4) */
3398 #define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3399 PPC_EXTERN | PPC_MEM_TLBIA | \
3401 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
3402 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
3403 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
3404 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
3405 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
3407 static void init_proc_7410 (CPUPPCState *env)
3409 gen_spr_ne_601(env);
3413 /* 74xx specific SPR */
3415 /* Thermal management */
3418 /* XXX : not implemented */
3419 spr_register(env, SPR_L2PMCR, "L2PMCR",
3420 SPR_NOACCESS, SPR_NOACCESS,
3421 &spr_read_generic, &spr_write_generic,
3424 /* XXX : not implemented */
3425 spr_register(env, SPR_LDSTDB, "LDSTDB",
3426 SPR_NOACCESS, SPR_NOACCESS,
3427 &spr_read_generic, &spr_write_generic,
3429 /* Memory management */
3431 init_excp_7400(env);
3432 /* Allocate hardware IRQ controller */
3433 ppc6xx_irq_init(env);
3436 /* PowerPC 7440 (aka G4) */
3438 #define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3439 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3441 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
3442 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
3443 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
3444 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
3445 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
3447 static void init_proc_7440 (CPUPPCState *env)
3449 gen_spr_ne_601(env);
3453 /* 74xx specific SPR */
3456 /* XXX : not implemented */
3457 spr_register(env, SPR_LDSTCR, "LDSTCR",
3458 SPR_NOACCESS, SPR_NOACCESS,
3459 &spr_read_generic, &spr_write_generic,
3462 /* XXX : not implemented */
3463 spr_register(env, SPR_ICTRL, "ICTRL",
3464 SPR_NOACCESS, SPR_NOACCESS,
3465 &spr_read_generic, &spr_write_generic,
3468 spr_register(env, SPR_MSSSR0, "MSSSR0",
3469 SPR_NOACCESS, SPR_NOACCESS,
3470 &spr_read_generic, &spr_write_generic,
3473 /* XXX : not implemented */
3474 spr_register(env, SPR_PMC5, "PMC5",
3475 SPR_NOACCESS, SPR_NOACCESS,
3476 &spr_read_generic, &spr_write_generic,
3478 spr_register(env, SPR_UPMC5, "UPMC5",
3479 &spr_read_ureg, SPR_NOACCESS,
3480 &spr_read_ureg, SPR_NOACCESS,
3482 spr_register(env, SPR_PMC6, "PMC6",
3483 SPR_NOACCESS, SPR_NOACCESS,
3484 &spr_read_generic, &spr_write_generic,
3486 spr_register(env, SPR_UPMC6, "UPMC6",
3487 &spr_read_ureg, SPR_NOACCESS,
3488 &spr_read_ureg, SPR_NOACCESS,
3490 /* Memory management */
3492 gen_74xx_soft_tlb(env);
3493 /* Allocate hardware IRQ controller */
3494 ppc6xx_irq_init(env);
3498 /* PowerPC 7450 (aka G4) */
3500 #define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3501 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3503 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
3504 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
3505 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
3506 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
3507 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
3509 static void init_proc_7450 (CPUPPCState *env)
3511 gen_spr_ne_601(env);
3515 /* 74xx specific SPR */
3517 /* Level 3 cache control */
3520 /* XXX : not implemented */
3521 spr_register(env, SPR_LDSTCR, "LDSTCR",
3522 SPR_NOACCESS, SPR_NOACCESS,
3523 &spr_read_generic, &spr_write_generic,
3526 /* XXX : not implemented */
3527 spr_register(env, SPR_ICTRL, "ICTRL",
3528 SPR_NOACCESS, SPR_NOACCESS,
3529 &spr_read_generic, &spr_write_generic,
3532 spr_register(env, SPR_MSSSR0, "MSSSR0",
3533 SPR_NOACCESS, SPR_NOACCESS,
3534 &spr_read_generic, &spr_write_generic,
3537 /* XXX : not implemented */
3538 spr_register(env, SPR_PMC5, "PMC5",
3539 SPR_NOACCESS, SPR_NOACCESS,
3540 &spr_read_generic, &spr_write_generic,
3542 spr_register(env, SPR_UPMC5, "UPMC5",
3543 &spr_read_ureg, SPR_NOACCESS,
3544 &spr_read_ureg, SPR_NOACCESS,
3546 spr_register(env, SPR_PMC6, "PMC6",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, &spr_write_generic,
3550 spr_register(env, SPR_UPMC6, "UPMC6",
3551 &spr_read_ureg, SPR_NOACCESS,
3552 &spr_read_ureg, SPR_NOACCESS,
3554 /* Memory management */
3556 gen_74xx_soft_tlb(env);
3557 init_excp_7450(env);
3558 /* Allocate hardware IRQ controller */
3559 ppc6xx_irq_init(env);
3563 /* PowerPC 7445 (aka G4) */
3565 #define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3566 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3568 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
3569 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
3570 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
3571 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
3572 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
3574 static void init_proc_7445 (CPUPPCState *env)
3576 gen_spr_ne_601(env);
3580 /* 74xx specific SPR */
3583 /* XXX : not implemented */
3584 spr_register(env, SPR_LDSTCR, "LDSTCR",
3585 SPR_NOACCESS, SPR_NOACCESS,
3586 &spr_read_generic, &spr_write_generic,
3589 /* XXX : not implemented */
3590 spr_register(env, SPR_ICTRL, "ICTRL",
3591 SPR_NOACCESS, SPR_NOACCESS,
3592 &spr_read_generic, &spr_write_generic,
3595 spr_register(env, SPR_MSSSR0, "MSSSR0",
3596 SPR_NOACCESS, SPR_NOACCESS,
3597 &spr_read_generic, &spr_write_generic,
3600 /* XXX : not implemented */
3601 spr_register(env, SPR_PMC5, "PMC5",
3602 SPR_NOACCESS, SPR_NOACCESS,
3603 &spr_read_generic, &spr_write_generic,
3605 spr_register(env, SPR_UPMC5, "UPMC5",
3606 &spr_read_ureg, SPR_NOACCESS,
3607 &spr_read_ureg, SPR_NOACCESS,
3609 spr_register(env, SPR_PMC6, "PMC6",
3610 SPR_NOACCESS, SPR_NOACCESS,
3611 &spr_read_generic, &spr_write_generic,
3613 spr_register(env, SPR_UPMC6, "UPMC6",
3614 &spr_read_ureg, SPR_NOACCESS,
3615 &spr_read_ureg, SPR_NOACCESS,
3618 spr_register(env, SPR_SPRG4, "SPRG4",
3619 SPR_NOACCESS, SPR_NOACCESS,
3620 &spr_read_generic, &spr_write_generic,
3622 spr_register(env, SPR_USPRG4, "USPRG4",
3623 &spr_read_ureg, SPR_NOACCESS,
3624 &spr_read_ureg, SPR_NOACCESS,
3626 spr_register(env, SPR_SPRG5, "SPRG5",
3627 SPR_NOACCESS, SPR_NOACCESS,
3628 &spr_read_generic, &spr_write_generic,
3630 spr_register(env, SPR_USPRG5, "USPRG5",
3631 &spr_read_ureg, SPR_NOACCESS,
3632 &spr_read_ureg, SPR_NOACCESS,
3634 spr_register(env, SPR_SPRG6, "SPRG6",
3635 SPR_NOACCESS, SPR_NOACCESS,
3636 &spr_read_generic, &spr_write_generic,
3638 spr_register(env, SPR_USPRG6, "USPRG6",
3639 &spr_read_ureg, SPR_NOACCESS,
3640 &spr_read_ureg, SPR_NOACCESS,
3642 spr_register(env, SPR_SPRG7, "SPRG7",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3646 spr_register(env, SPR_USPRG7, "USPRG7",
3647 &spr_read_ureg, SPR_NOACCESS,
3648 &spr_read_ureg, SPR_NOACCESS,
3650 /* Memory management */
3653 gen_74xx_soft_tlb(env);
3654 init_excp_7450(env);
3655 /* Allocate hardware IRQ controller */
3656 ppc6xx_irq_init(env);
3660 /* PowerPC 7455 (aka G4) */
3662 #define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
3663 PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
3665 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
3666 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
3667 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
3668 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
3669 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
3671 static void init_proc_7455 (CPUPPCState *env)
3673 gen_spr_ne_601(env);
3677 /* 74xx specific SPR */
3679 /* Level 3 cache control */
3682 /* XXX : not implemented */
3683 spr_register(env, SPR_LDSTCR, "LDSTCR",
3684 SPR_NOACCESS, SPR_NOACCESS,
3685 &spr_read_generic, &spr_write_generic,
3688 /* XXX : not implemented */
3689 spr_register(env, SPR_ICTRL, "ICTRL",
3690 SPR_NOACCESS, SPR_NOACCESS,
3691 &spr_read_generic, &spr_write_generic,
3694 spr_register(env, SPR_MSSSR0, "MSSSR0",
3695 SPR_NOACCESS, SPR_NOACCESS,
3696 &spr_read_generic, &spr_write_generic,
3699 /* XXX : not implemented */
3700 spr_register(env, SPR_PMC5, "PMC5",
3701 SPR_NOACCESS, SPR_NOACCESS,
3702 &spr_read_generic, &spr_write_generic,
3704 spr_register(env, SPR_UPMC5, "UPMC5",
3705 &spr_read_ureg, SPR_NOACCESS,
3706 &spr_read_ureg, SPR_NOACCESS,
3708 spr_register(env, SPR_PMC6, "PMC6",
3709 SPR_NOACCESS, SPR_NOACCESS,
3710 &spr_read_generic, &spr_write_generic,
3712 spr_register(env, SPR_UPMC6, "UPMC6",
3713 &spr_read_ureg, SPR_NOACCESS,
3714 &spr_read_ureg, SPR_NOACCESS,
3717 spr_register(env, SPR_SPRG4, "SPRG4",
3718 SPR_NOACCESS, SPR_NOACCESS,
3719 &spr_read_generic, &spr_write_generic,
3721 spr_register(env, SPR_USPRG4, "USPRG4",
3722 &spr_read_ureg, SPR_NOACCESS,
3723 &spr_read_ureg, SPR_NOACCESS,
3725 spr_register(env, SPR_SPRG5, "SPRG5",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3729 spr_register(env, SPR_USPRG5, "USPRG5",
3730 &spr_read_ureg, SPR_NOACCESS,
3731 &spr_read_ureg, SPR_NOACCESS,
3733 spr_register(env, SPR_SPRG6, "SPRG6",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3737 spr_register(env, SPR_USPRG6, "USPRG6",
3738 &spr_read_ureg, SPR_NOACCESS,
3739 &spr_read_ureg, SPR_NOACCESS,
3741 spr_register(env, SPR_SPRG7, "SPRG7",
3742 SPR_NOACCESS, SPR_NOACCESS,
3743 &spr_read_generic, &spr_write_generic,
3745 spr_register(env, SPR_USPRG7, "USPRG7",
3746 &spr_read_ureg, SPR_NOACCESS,
3747 &spr_read_ureg, SPR_NOACCESS,
3749 /* Memory management */
3752 gen_74xx_soft_tlb(env);
3753 init_excp_7450(env);
3754 /* Allocate hardware IRQ controller */
3755 ppc6xx_irq_init(env);
3759 #if defined (TARGET_PPC64)
3761 #define POWERPC_INSNS_970 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3762 PPC_64B | PPC_ALTIVEC | \
3763 PPC_64_BRIDGE | PPC_SLBI)
3764 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
3765 #define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE)
3766 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
3767 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
3768 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
3770 static void init_proc_970 (CPUPPCState *env)
3772 gen_spr_ne_601(env);
3776 /* Hardware implementation registers */
3777 /* XXX : not implemented */
3778 spr_register(env, SPR_HID0, "HID0",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3782 /* XXX : not implemented */
3783 spr_register(env, SPR_HID1, "HID1",
3784 SPR_NOACCESS, SPR_NOACCESS,
3785 &spr_read_generic, &spr_write_generic,
3787 /* XXX : not implemented */
3788 spr_register(env, SPR_750_HID2, "HID2",
3789 SPR_NOACCESS, SPR_NOACCESS,
3790 &spr_read_generic, &spr_write_generic,
3792 /* Memory management */
3793 /* XXX: not correct */
3799 /* Allocate hardware IRQ controller */
3800 ppc970_irq_init(env);
3803 /* PowerPC 970FX (aka G5) */
3804 #define POWERPC_INSNS_970FX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3805 PPC_64B | PPC_ALTIVEC | \
3806 PPC_64_BRIDGE | PPC_SLBI)
3807 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
3808 #define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE)
3809 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
3810 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
3811 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
3813 static void init_proc_970FX (CPUPPCState *env)
3815 gen_spr_ne_601(env);
3819 /* Hardware implementation registers */
3820 /* XXX : not implemented */
3821 spr_register(env, SPR_HID0, "HID0",
3822 SPR_NOACCESS, SPR_NOACCESS,
3823 &spr_read_generic, &spr_write_generic,
3825 /* XXX : not implemented */
3826 spr_register(env, SPR_HID1, "HID1",
3827 SPR_NOACCESS, SPR_NOACCESS,
3828 &spr_read_generic, &spr_write_generic,
3830 /* XXX : not implemented */
3831 spr_register(env, SPR_750_HID2, "HID2",
3832 SPR_NOACCESS, SPR_NOACCESS,
3833 &spr_read_generic, &spr_write_generic,
3835 /* Memory management */
3836 /* XXX: not correct */
3842 /* Allocate hardware IRQ controller */
3843 ppc970_irq_init(env);
3846 /* PowerPC 970 GX */
3847 #define POWERPC_INSNS_970GX (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3848 PPC_64B | PPC_ALTIVEC | \
3849 PPC_64_BRIDGE | PPC_SLBI)
3850 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
3851 #define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE)
3852 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
3853 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
3854 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
3856 static void init_proc_970GX (CPUPPCState *env)
3858 gen_spr_ne_601(env);
3862 /* Hardware implementation registers */
3863 /* XXX : not implemented */
3864 spr_register(env, SPR_HID0, "HID0",
3865 SPR_NOACCESS, SPR_NOACCESS,
3866 &spr_read_generic, &spr_write_generic,
3868 /* XXX : not implemented */
3869 spr_register(env, SPR_HID1, "HID1",
3870 SPR_NOACCESS, SPR_NOACCESS,
3871 &spr_read_generic, &spr_write_generic,
3873 /* XXX : not implemented */
3874 spr_register(env, SPR_750_HID2, "HID2",
3875 SPR_NOACCESS, SPR_NOACCESS,
3876 &spr_read_generic, &spr_write_generic,
3878 /* Memory management */
3879 /* XXX: not correct */
3885 /* Allocate hardware IRQ controller */
3886 ppc970_irq_init(env);
3891 #define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
3893 #define POWERPC_MSRM_620 (0x800000000005FF73ULL)
3894 #define POWERPC_MMU_620 (POWERPC_MMU_64B)
3895 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
3896 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_970)
3897 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
3899 static void init_proc_620 (CPUPPCState *env)
3901 gen_spr_ne_601(env);
3905 /* Hardware implementation registers */
3906 /* XXX : not implemented */
3907 spr_register(env, SPR_HID0, "HID0",
3908 SPR_NOACCESS, SPR_NOACCESS,
3909 &spr_read_generic, &spr_write_generic,
3911 /* Memory management */
3915 /* XXX: TODO: initialize internal interrupt controller */
3918 #endif /* defined (TARGET_PPC64) */
3920 /* Default 32 bits PowerPC target will be 604 */
3921 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
3922 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
3923 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
3924 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
3925 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
3926 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
3927 #define init_proc_PPC32 init_proc_604
3928 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
3930 /* Default 64 bits PowerPC target will be 970 FX */
3931 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
3932 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
3933 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
3934 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
3935 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
3936 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
3937 #define init_proc_PPC64 init_proc_970FX
3938 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
3940 /* Default PowerPC target will be PowerPC 32 */
3941 #if defined (TARGET_PPC64) && 0 // XXX: TODO
3942 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
3943 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
3944 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
3945 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
3946 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
3947 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
3948 #define init_proc_DEFAULT init_proc_PPC64
3949 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
3951 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
3952 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
3953 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
3954 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
3955 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
3956 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
3957 #define init_proc_DEFAULT init_proc_PPC32
3958 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
3961 /*****************************************************************************/
3962 /* PVR definitions for most known PowerPC */
3964 /* PowerPC 401 family */
3965 /* Generic PowerPC 401 */
3966 #define CPU_POWERPC_401 CPU_POWERPC_401G2
3967 /* PowerPC 401 cores */
3968 CPU_POWERPC_401A1 = 0x00210000,
3969 CPU_POWERPC_401B2 = 0x00220000,
3971 CPU_POWERPC_401B3 = xxx,
3973 CPU_POWERPC_401C2 = 0x00230000,
3974 CPU_POWERPC_401D2 = 0x00240000,
3975 CPU_POWERPC_401E2 = 0x00250000,
3976 CPU_POWERPC_401F2 = 0x00260000,
3977 CPU_POWERPC_401G2 = 0x00270000,
3978 /* PowerPC 401 microcontrolers */
3980 CPU_POWERPC_401GF = xxx,
3982 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
3983 /* IBM Processor for Network Resources */
3984 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
3986 CPU_POWERPC_XIPCHIP = xxx,
3988 /* PowerPC 403 family */
3989 /* Generic PowerPC 403 */
3990 #define CPU_POWERPC_403 CPU_POWERPC_403GC
3991 /* PowerPC 403 microcontrollers */
3992 CPU_POWERPC_403GA = 0x00200011,
3993 CPU_POWERPC_403GB = 0x00200100,
3994 CPU_POWERPC_403GC = 0x00200200,
3995 CPU_POWERPC_403GCX = 0x00201400,
3997 CPU_POWERPC_403GP = xxx,
3999 /* PowerPC 405 family */
4000 /* Generic PowerPC 405 */
4001 #define CPU_POWERPC_405 CPU_POWERPC_405D4
4002 /* PowerPC 405 cores */
4004 CPU_POWERPC_405A3 = xxx,
4007 CPU_POWERPC_405A4 = xxx,
4010 CPU_POWERPC_405B3 = xxx,
4013 CPU_POWERPC_405B4 = xxx,
4016 CPU_POWERPC_405C3 = xxx,
4019 CPU_POWERPC_405C4 = xxx,
4021 CPU_POWERPC_405D2 = 0x20010000,
4023 CPU_POWERPC_405D3 = xxx,
4025 CPU_POWERPC_405D4 = 0x41810000,
4027 CPU_POWERPC_405D5 = xxx,
4030 CPU_POWERPC_405E4 = xxx,
4033 CPU_POWERPC_405F4 = xxx,
4036 CPU_POWERPC_405F5 = xxx,
4039 CPU_POWERPC_405F6 = xxx,
4041 /* PowerPC 405 microcontrolers */
4042 /* XXX: missing 0x200108a0 */
4043 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
4044 CPU_POWERPC_405CRa = 0x40110041,
4045 CPU_POWERPC_405CRb = 0x401100C5,
4046 CPU_POWERPC_405CRc = 0x40110145,
4047 CPU_POWERPC_405EP = 0x51210950,
4049 CPU_POWERPC_405EXr = xxx,
4051 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
4053 CPU_POWERPC_405FX = xxx,
4055 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
4056 CPU_POWERPC_405GPa = 0x40110000,
4057 CPU_POWERPC_405GPb = 0x40110040,
4058 CPU_POWERPC_405GPc = 0x40110082,
4059 CPU_POWERPC_405GPd = 0x401100C4,
4060 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
4061 CPU_POWERPC_405GPR = 0x50910951,
4063 CPU_POWERPC_405H = xxx,
4066 CPU_POWERPC_405L = xxx,
4068 CPU_POWERPC_405LP = 0x41F10000,
4070 CPU_POWERPC_405PM = xxx,
4073 CPU_POWERPC_405PS = xxx,
4076 CPU_POWERPC_405S = xxx,
4078 /* IBM network processors */
4079 CPU_POWERPC_NPE405H = 0x414100C0,
4080 CPU_POWERPC_NPE405H2 = 0x41410140,
4081 CPU_POWERPC_NPE405L = 0x416100C0,
4082 CPU_POWERPC_NPE4GS3 = 0x40B10000,
4084 CPU_POWERPC_NPCxx1 = xxx,
4087 CPU_POWERPC_NPR161 = xxx,
4090 CPU_POWERPC_LC77700 = xxx,
4092 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4094 CPU_POWERPC_STB01000 = xxx,
4097 CPU_POWERPC_STB01010 = xxx,
4100 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
4102 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
4104 CPU_POWERPC_STB043 = xxx,
4107 CPU_POWERPC_STB045 = xxx,
4109 CPU_POWERPC_STB04 = 0x41810000,
4110 CPU_POWERPC_STB25 = 0x51510950,
4112 CPU_POWERPC_STB130 = xxx,
4115 CPU_POWERPC_X2VP4 = 0x20010820,
4116 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
4117 CPU_POWERPC_X2VP20 = 0x20010860,
4118 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
4120 CPU_POWERPC_ZL10310 = xxx,
4123 CPU_POWERPC_ZL10311 = xxx,
4126 CPU_POWERPC_ZL10320 = xxx,
4129 CPU_POWERPC_ZL10321 = xxx,
4131 /* PowerPC 440 family */
4132 /* Generic PowerPC 440 */
4133 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
4134 /* PowerPC 440 cores */
4136 CPU_POWERPC_440A4 = xxx,
4139 CPU_POWERPC_440A5 = xxx,
4142 CPU_POWERPC_440B4 = xxx,
4145 CPU_POWERPC_440F5 = xxx,
4148 CPU_POWERPC_440G5 = xxx,
4151 CPU_POWERPC_440H4 = xxx,
4154 CPU_POWERPC_440H6 = xxx,
4156 /* PowerPC 440 microcontrolers */
4157 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
4158 CPU_POWERPC_440EPa = 0x42221850,
4159 CPU_POWERPC_440EPb = 0x422218D3,
4160 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
4161 CPU_POWERPC_440GPb = 0x40120440,
4162 CPU_POWERPC_440GPc = 0x40120481,
4163 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
4164 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
4165 CPU_POWERPC_440GRX = 0x200008D0,
4166 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
4167 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
4168 CPU_POWERPC_440GXa = 0x51B21850,
4169 CPU_POWERPC_440GXb = 0x51B21851,
4170 CPU_POWERPC_440GXc = 0x51B21892,
4171 CPU_POWERPC_440GXf = 0x51B21894,
4173 CPU_POWERPC_440S = xxx,
4175 CPU_POWERPC_440SP = 0x53221850,
4176 CPU_POWERPC_440SP2 = 0x53221891,
4177 CPU_POWERPC_440SPE = 0x53421890,
4178 /* PowerPC 460 family */
4180 /* Generic PowerPC 464 */
4181 #define CPU_POWERPC_464 CPU_POWERPC_464H90
4183 /* PowerPC 464 microcontrolers */
4185 CPU_POWERPC_464H90 = xxx,
4188 CPU_POWERPC_464H90FP = xxx,
4190 /* Freescale embedded PowerPC cores */
4192 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
4194 CPU_POWERPC_e200z0 = xxx,
4197 CPU_POWERPC_e200z3 = xxx,
4199 CPU_POWERPC_e200z5 = 0x81000000,
4200 CPU_POWERPC_e200z6 = 0x81120000,
4202 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
4203 CPU_POWERPC_e300c1 = 0x00830000,
4204 CPU_POWERPC_e300c2 = 0x00840000,
4205 CPU_POWERPC_e300c3 = 0x00850000,
4207 #define CPU_POWERPC_e500 CPU_POWERPC_e500_v22
4208 CPU_POWERPC_e500_v11 = 0x80200010,
4209 CPU_POWERPC_e500_v12 = 0x80200020,
4210 CPU_POWERPC_e500_v21 = 0x80210010,
4211 CPU_POWERPC_e500_v22 = 0x80210020,
4213 CPU_POWERPC_e500mc = xxx,
4216 CPU_POWERPC_e600 = 0x80040010,
4217 /* PowerPC MPC 5xx cores */
4218 CPU_POWERPC_5xx = 0x00020020,
4219 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4220 CPU_POWERPC_8xx = 0x00500000,
4221 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4222 CPU_POWERPC_82xx_HIP3 = 0x00810101,
4223 CPU_POWERPC_82xx_HIP4 = 0x80811014,
4224 CPU_POWERPC_827x = 0x80822013,
4225 /* PowerPC 6xx cores */
4226 CPU_POWERPC_601 = 0x00010001,
4227 CPU_POWERPC_601a = 0x00010002,
4228 CPU_POWERPC_602 = 0x00050100,
4229 CPU_POWERPC_603 = 0x00030100,
4230 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
4231 CPU_POWERPC_603E_v11 = 0x00060101,
4232 CPU_POWERPC_603E_v12 = 0x00060102,
4233 CPU_POWERPC_603E_v13 = 0x00060103,
4234 CPU_POWERPC_603E_v14 = 0x00060104,
4235 CPU_POWERPC_603E_v22 = 0x00060202,
4236 CPU_POWERPC_603E_v3 = 0x00060300,
4237 CPU_POWERPC_603E_v4 = 0x00060400,
4238 CPU_POWERPC_603E_v41 = 0x00060401,
4239 CPU_POWERPC_603E7t = 0x00071201,
4240 CPU_POWERPC_603E7v = 0x00070100,
4241 CPU_POWERPC_603E7v1 = 0x00070101,
4242 CPU_POWERPC_603E7v2 = 0x00070201,
4243 CPU_POWERPC_603E7 = 0x00070200,
4244 CPU_POWERPC_603P = 0x00070000,
4245 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
4246 CPU_POWERPC_G2 = 0x00810011,
4247 #if 0 // Linux pretends the MSB is zero...
4248 CPU_POWERPC_G2H4 = 0x80811010,
4249 CPU_POWERPC_G2gp = 0x80821010,
4250 CPU_POWERPC_G2ls = 0x90810010,
4251 CPU_POWERPC_G2LE = 0x80820010,
4252 CPU_POWERPC_G2LEgp = 0x80822010,
4253 CPU_POWERPC_G2LEls = 0xA0822010,
4255 CPU_POWERPC_G2H4 = 0x00811010,
4256 CPU_POWERPC_G2gp = 0x00821010,
4257 CPU_POWERPC_G2ls = 0x10810010,
4258 CPU_POWERPC_G2LE = 0x00820010,
4259 CPU_POWERPC_G2LEgp = 0x00822010,
4260 CPU_POWERPC_G2LEls = 0x20822010,
4262 CPU_POWERPC_604 = 0x00040103,
4263 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
4264 CPU_POWERPC_604E_v10 = 0x00090100, /* Also 2110 & 2120 */
4265 CPU_POWERPC_604E_v22 = 0x00090202,
4266 CPU_POWERPC_604E_v24 = 0x00090204,
4267 CPU_POWERPC_604R = 0x000a0101, /* Also 0x00093102 */
4269 CPU_POWERPC_604EV = xxx,
4271 /* PowerPC 740/750 cores (aka G3) */
4272 /* XXX: missing 0x00084202 */
4273 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
4274 CPU_POWERPC_7x0_v20 = 0x00080200,
4275 CPU_POWERPC_7x0_v21 = 0x00080201,
4276 CPU_POWERPC_7x0_v22 = 0x00080202,
4277 CPU_POWERPC_7x0_v30 = 0x00080300,
4278 CPU_POWERPC_7x0_v31 = 0x00080301,
4279 CPU_POWERPC_740E = 0x00080100,
4280 CPU_POWERPC_7x0P = 0x10080000,
4281 /* XXX: missing 0x00087010 (CL ?) */
4282 CPU_POWERPC_750CL = 0x00087200,
4283 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
4284 CPU_POWERPC_750CX_v21 = 0x00082201,
4285 CPU_POWERPC_750CX_v22 = 0x00082202,
4286 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
4287 CPU_POWERPC_750CXE_v21 = 0x00082211,
4288 CPU_POWERPC_750CXE_v22 = 0x00082212,
4289 CPU_POWERPC_750CXE_v23 = 0x00082213,
4290 CPU_POWERPC_750CXE_v24 = 0x00082214,
4291 CPU_POWERPC_750CXE_v24b = 0x00083214,
4292 CPU_POWERPC_750CXE_v31 = 0x00083211,
4293 CPU_POWERPC_750CXE_v31b = 0x00083311,
4294 CPU_POWERPC_750CXR = 0x00083410,
4295 CPU_POWERPC_750E = 0x00080200,
4296 CPU_POWERPC_750FL = 0x700A0203,
4297 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
4298 CPU_POWERPC_750FX_v10 = 0x70000100,
4299 CPU_POWERPC_750FX_v20 = 0x70000200,
4300 CPU_POWERPC_750FX_v21 = 0x70000201,
4301 CPU_POWERPC_750FX_v22 = 0x70000202,
4302 CPU_POWERPC_750FX_v23 = 0x70000203,
4303 CPU_POWERPC_750GL = 0x70020102,
4304 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
4305 CPU_POWERPC_750GX_v10 = 0x70020100,
4306 CPU_POWERPC_750GX_v11 = 0x70020101,
4307 CPU_POWERPC_750GX_v12 = 0x70020102,
4308 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
4309 CPU_POWERPC_750L_v22 = 0x00088202,
4310 CPU_POWERPC_750L_v30 = 0x00088300,
4311 CPU_POWERPC_750L_v32 = 0x00088302,
4312 /* PowerPC 745/755 cores */
4313 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
4314 CPU_POWERPC_7x5_v10 = 0x00083100,
4315 CPU_POWERPC_7x5_v11 = 0x00083101,
4316 CPU_POWERPC_7x5_v20 = 0x00083200,
4317 CPU_POWERPC_7x5_v21 = 0x00083201,
4318 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
4319 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
4320 CPU_POWERPC_7x5_v24 = 0x00083204,
4321 CPU_POWERPC_7x5_v25 = 0x00083205,
4322 CPU_POWERPC_7x5_v26 = 0x00083206,
4323 CPU_POWERPC_7x5_v27 = 0x00083207,
4324 CPU_POWERPC_7x5_v28 = 0x00083208,
4326 CPU_POWERPC_7x5P = xxx,
4328 /* PowerPC 74xx cores (aka G4) */
4329 /* XXX: missing 0x000C1101 */
4330 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
4331 CPU_POWERPC_7400_v10 = 0x000C0100,
4332 CPU_POWERPC_7400_v11 = 0x000C0101,
4333 CPU_POWERPC_7400_v20 = 0x000C0200,
4334 CPU_POWERPC_7400_v22 = 0x000C0202,
4335 CPU_POWERPC_7400_v26 = 0x000C0206,
4336 CPU_POWERPC_7400_v27 = 0x000C0207,
4337 CPU_POWERPC_7400_v28 = 0x000C0208,
4338 CPU_POWERPC_7400_v29 = 0x000C0209,
4339 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
4340 CPU_POWERPC_7410_v10 = 0x800C1100,
4341 CPU_POWERPC_7410_v11 = 0x800C1101,
4342 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
4343 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
4344 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
4345 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
4346 CPU_POWERPC_7448_v10 = 0x80040100,
4347 CPU_POWERPC_7448_v11 = 0x80040101,
4348 CPU_POWERPC_7448_v20 = 0x80040200,
4349 CPU_POWERPC_7448_v21 = 0x80040201,
4350 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
4351 CPU_POWERPC_7450_v10 = 0x80000100,
4352 CPU_POWERPC_7450_v11 = 0x80000101,
4353 CPU_POWERPC_7450_v12 = 0x80000102,
4354 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
4355 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4356 CPU_POWERPC_74x1 = 0x80000203,
4357 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
4358 /* XXX: missing 0x80010200 */
4359 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
4360 CPU_POWERPC_74x5_v10 = 0x80010100,
4361 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
4362 CPU_POWERPC_74x5_v32 = 0x80010302,
4363 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
4364 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
4365 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
4366 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
4367 CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
4368 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
4369 /* 64 bits PowerPC */
4370 CPU_POWERPC_620 = 0x00140000,
4371 CPU_POWERPC_630 = 0x00400000,
4372 CPU_POWERPC_631 = 0x00410104,
4373 CPU_POWERPC_POWER4 = 0x00350000,
4374 CPU_POWERPC_POWER4P = 0x00380000,
4375 CPU_POWERPC_POWER5 = 0x003A0203,
4376 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
4377 CPU_POWERPC_POWER5P = 0x003B0000,
4378 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
4379 CPU_POWERPC_POWER6 = 0x003E0000,
4380 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 running POWER5 mode */
4381 CPU_POWERPC_POWER6A = 0x0F000002,
4382 CPU_POWERPC_970 = 0x00390202,
4383 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
4384 CPU_POWERPC_970FX_v10 = 0x00391100,
4385 CPU_POWERPC_970FX_v20 = 0x003C0200,
4386 CPU_POWERPC_970FX_v21 = 0x003C0201,
4387 CPU_POWERPC_970FX_v30 = 0x003C0300,
4388 CPU_POWERPC_970FX_v31 = 0x003C0301,
4389 CPU_POWERPC_970GX = 0x00450000,
4390 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
4391 CPU_POWERPC_970MP_v10 = 0x00440100,
4392 CPU_POWERPC_970MP_v11 = 0x00440101,
4393 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
4394 CPU_POWERPC_CELL_v10 = 0x00700100,
4395 CPU_POWERPC_CELL_v20 = 0x00700400,
4396 CPU_POWERPC_CELL_v30 = 0x00700500,
4397 CPU_POWERPC_CELL_v31 = 0x00700501,
4398 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
4399 CPU_POWERPC_RS64 = 0x00330000,
4400 CPU_POWERPC_RS64II = 0x00340000,
4401 CPU_POWERPC_RS64III = 0x00360000,
4402 CPU_POWERPC_RS64IV = 0x00370000,
4403 /* Original POWER */
4404 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4405 * POWER2 (RIOS2) & RSC2 (P2SC) here
4408 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4411 CPU_POWER2 = xxx, /* 0x40000 ? */
4414 CPU_POWERPC_PA6T = 0x00900000,
4417 /* System version register (used on MPC 8xxx) */
4419 PPC_SVR_8540 = 0x80300000,
4420 PPC_SVR_8541E = 0x807A0010,
4421 PPC_SVR_8543v10 = 0x80320010,
4422 PPC_SVR_8543v11 = 0x80320011,
4423 PPC_SVR_8543v20 = 0x80320020,
4424 PPC_SVR_8543Ev10 = 0x803A0010,
4425 PPC_SVR_8543Ev11 = 0x803A0011,
4426 PPC_SVR_8543Ev20 = 0x803A0020,
4427 PPC_SVR_8545 = 0x80310220,
4428 PPC_SVR_8545E = 0x80390220,
4429 PPC_SVR_8547E = 0x80390120,
4430 PPC_SCR_8548v10 = 0x80310010,
4431 PPC_SCR_8548v11 = 0x80310011,
4432 PPC_SCR_8548v20 = 0x80310020,
4433 PPC_SVR_8548Ev10 = 0x80390010,
4434 PPC_SVR_8548Ev11 = 0x80390011,
4435 PPC_SVR_8548Ev20 = 0x80390020,
4436 PPC_SVR_8555E = 0x80790010,
4437 PPC_SVR_8560v10 = 0x80700010,
4438 PPC_SVR_8560v20 = 0x80700020,
4441 /*****************************************************************************/
4442 /* PowerPC CPU definitions */
4443 #define POWERPC_DEF(_name, _pvr, _pvr_mask, _type) \
4447 .pvr_mask = _pvr_mask, \
4448 .insns_flags = glue(POWERPC_INSNS_,_type), \
4449 .msr_mask = glue(POWERPC_MSRM_,_type), \
4450 .mmu_model = glue(POWERPC_MMU_,_type), \
4451 .excp_model = glue(POWERPC_EXCP_,_type), \
4452 .bus_model = glue(POWERPC_INPUT_,_type), \
4453 .bfd_mach = glue(POWERPC_BFDM_,_type), \
4454 .init_proc = &glue(init_proc_,_type), \
4457 static ppc_def_t ppc_defs[] = {
4458 /* Embedded PowerPC */
4459 /* PowerPC 401 family */
4460 /* Generic PowerPC 401 */
4461 POWERPC_DEF("401", CPU_POWERPC_401, 0xFFFF0000, 401),
4462 /* PowerPC 401 cores */
4464 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 0xFFFFFFFF, 401),
4466 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 0xFFFFFFFF, 401x2),
4469 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 0xFFFFFFFF, 401x3),
4472 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 0xFFFFFFFF, 401x2),
4474 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 0xFFFFFFFF, 401x2),
4476 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 0xFFFFFFFF, 401x2),
4478 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 0xFFFFFFFF, 401x2),
4480 /* XXX: to be checked */
4481 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 0xFFFFFFFF, 401x2),
4482 /* PowerPC 401 microcontrolers */
4485 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 0xFFFFFFFF, 401),
4487 /* IOP480 (401 microcontroler) */
4488 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, 0xFFFFFFFF, IOP480),
4489 /* IBM Processor for Network Resources */
4490 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 0xFFFFFFFF, 401),
4492 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 0xFFFFFFFF, 401),
4494 /* PowerPC 403 family */
4495 /* Generic PowerPC 403 */
4496 POWERPC_DEF("403", CPU_POWERPC_403, 0xFFFF0000, 403),
4497 /* PowerPC 403 microcontrolers */
4498 /* PowerPC 403 GA */
4499 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 0xFFFFFFFF, 403),
4500 /* PowerPC 403 GB */
4501 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 0xFFFFFFFF, 403),
4502 /* PowerPC 403 GC */
4503 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 0xFFFFFFFF, 403),
4504 /* PowerPC 403 GCX */
4505 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 0xFFFFFFFF, 403GCX),
4507 /* PowerPC 403 GP */
4508 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 0xFFFFFFFF, 403),
4510 /* PowerPC 405 family */
4511 /* Generic PowerPC 405 */
4512 POWERPC_DEF("405", CPU_POWERPC_405, 0xFFFF0000, 405),
4513 /* PowerPC 405 cores */
4515 /* PowerPC 405 A3 */
4516 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 0xFFFFFFFF, 405),
4519 /* PowerPC 405 A4 */
4520 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 0xFFFFFFFF, 405),
4523 /* PowerPC 405 B3 */
4524 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 0xFFFFFFFF, 405),
4527 /* PowerPC 405 B4 */
4528 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 0xFFFFFFFF, 405),
4531 /* PowerPC 405 C3 */
4532 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 0xFFFFFFFF, 405),
4535 /* PowerPC 405 C4 */
4536 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 0xFFFFFFFF, 405),
4538 /* PowerPC 405 D2 */
4539 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 0xFFFFFFFF, 405),
4541 /* PowerPC 405 D3 */
4542 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 0xFFFFFFFF, 405),
4544 /* PowerPC 405 D4 */
4545 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 0xFFFFFFFF, 405),
4547 /* PowerPC 405 D5 */
4548 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 0xFFFFFFFF, 405),
4551 /* PowerPC 405 E4 */
4552 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 0xFFFFFFFF, 405),
4555 /* PowerPC 405 F4 */
4556 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 0xFFFFFFFF, 405),
4559 /* PowerPC 405 F5 */
4560 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 0xFFFFFFFF, 405),
4563 /* PowerPC 405 F6 */
4564 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 0xFFFFFFFF, 405),
4566 /* PowerPC 405 microcontrolers */
4567 /* PowerPC 405 CR */
4568 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 0xFFFFFFFF, 405),
4569 /* PowerPC 405 CRa */
4570 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 0xFFFFFFFF, 405),
4571 /* PowerPC 405 CRb */
4572 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 0xFFFFFFFF, 405),
4573 /* PowerPC 405 CRc */
4574 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 0xFFFFFFFF, 405),
4575 /* PowerPC 405 EP */
4576 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 0xFFFFFFFF, 405),
4578 /* PowerPC 405 EXr */
4579 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 0xFFFFFFFF, 405),
4581 /* PowerPC 405 EZ */
4582 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 0xFFFFFFFF, 405),
4584 /* PowerPC 405 FX */
4585 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 0xFFFFFFFF, 405),
4587 /* PowerPC 405 GP */
4588 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 0xFFFFFFFF, 405),
4589 /* PowerPC 405 GPa */
4590 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 0xFFFFFFFF, 405),
4591 /* PowerPC 405 GPb */
4592 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 0xFFFFFFFF, 405),
4593 /* PowerPC 405 GPc */
4594 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 0xFFFFFFFF, 405),
4595 /* PowerPC 405 GPd */
4596 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 0xFFFFFFFF, 405),
4597 /* PowerPC 405 GPe */
4598 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 0xFFFFFFFF, 405),
4599 /* PowerPC 405 GPR */
4600 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 0xFFFFFFFF, 405),
4603 POWERPC_DEF("405H", CPU_POWERPC_405H, 0xFFFFFFFF, 405),
4607 POWERPC_DEF("405L", CPU_POWERPC_405L, 0xFFFFFFFF, 405),
4609 /* PowerPC 405 LP */
4610 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 0xFFFFFFFF, 405),
4612 /* PowerPC 405 PM */
4613 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 0xFFFFFFFF, 405),
4616 /* PowerPC 405 PS */
4617 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 0xFFFFFFFF, 405),
4621 POWERPC_DEF("405S", CPU_POWERPC_405S, 0xFFFFFFFF, 405),
4624 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 0xFFFFFFFF, 405),
4626 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 0xFFFFFFFF, 405),
4628 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 0xFFFFFFFF, 405),
4630 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 0xFFFFFFFF, 405),
4632 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 0xFFFFFFFF, 405),
4635 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 0xFFFFFFFF, 405),
4638 /* PowerPC LC77700 (Sanyo) */
4639 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 0xFFFFFFFF, 405),
4641 /* PowerPC 401/403/405 based set-top-box microcontrolers */
4644 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 0xFFFFFFFF, 401x2),
4648 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 0xFFFFFFFF, 401x2),
4652 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 0xFFFFFFFF, 401x3),
4655 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 0xFFFFFFFF, 405),
4658 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 0xFFFFFFFF, 405),
4662 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 0xFFFFFFFF, 405),
4665 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 0xFFFF0000, 405),
4667 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 0xFFFFFFFF, 405),
4670 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 0xFFFFFFFF, 405),
4672 /* Xilinx PowerPC 405 cores */
4673 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 0xFFFFFFFF, 405),
4674 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 0xFFFFFFFF, 405),
4675 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 0xFFFFFFFF, 405),
4676 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 0xFFFFFFFF, 405),
4678 /* Zarlink ZL10310 */
4679 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 0xFFFFFFFF, 405),
4682 /* Zarlink ZL10311 */
4683 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 0xFFFFFFFF, 405),
4686 /* Zarlink ZL10320 */
4687 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 0xFFFFFFFF, 405),
4690 /* Zarlink ZL10321 */
4691 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 0xFFFFFFFF, 405),
4693 /* PowerPC 440 family */
4694 /* Generic PowerPC 440 */
4695 POWERPC_DEF("440", CPU_POWERPC_440, 0xFFFFFFFF, 440GP),
4696 /* PowerPC 440 cores */
4698 /* PowerPC 440 A4 */
4699 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 0xFFFFFFFF, 440x4),
4702 /* PowerPC 440 A5 */
4703 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 0xFFFFFFFF, 440x5),
4706 /* PowerPC 440 B4 */
4707 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 0xFFFFFFFF, 440x4),
4710 /* PowerPC 440 G4 */
4711 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 0xFFFFFFFF, 440x4),
4714 /* PowerPC 440 F5 */
4715 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 0xFFFFFFFF, 440x5),
4718 /* PowerPC 440 G5 */
4719 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 0xFFFFFFFF, 440x5),
4723 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 0xFFFFFFFF, 440x4),
4727 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 0xFFFFFFFF, 440Gx5),
4729 /* PowerPC 440 microcontrolers */
4730 /* PowerPC 440 EP */
4731 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 0xFFFFFFFF, 440EP),
4732 /* PowerPC 440 EPa */
4733 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 0xFFFFFFFF, 440EP),
4734 /* PowerPC 440 EPb */
4735 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 0xFFFFFFFF, 440EP),
4736 /* PowerPC 440 EPX */
4737 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 0xFFFFFFFF, 440EP),
4738 /* PowerPC 440 GP */
4739 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 0xFFFFFFFF, 440GP),
4740 /* PowerPC 440 GPb */
4741 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 0xFFFFFFFF, 440GP),
4742 /* PowerPC 440 GPc */
4743 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 0xFFFFFFFF, 440GP),
4744 /* PowerPC 440 GR */
4745 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 0xFFFFFFFF, 440x5),
4746 /* PowerPC 440 GRa */
4747 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 0xFFFFFFFF, 440x5),
4748 /* PowerPC 440 GRX */
4749 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 0xFFFFFFFF, 440x5),
4750 /* PowerPC 440 GX */
4751 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 0xFFFFFFFF, 440EP),
4752 /* PowerPC 440 GXa */
4753 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 0xFFFFFFFF, 440EP),
4754 /* PowerPC 440 GXb */
4755 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 0xFFFFFFFF, 440EP),
4756 /* PowerPC 440 GXc */
4757 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 0xFFFFFFFF, 440EP),
4758 /* PowerPC 440 GXf */
4759 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 0xFFFFFFFF, 440EP),
4762 POWERPC_DEF("440S", CPU_POWERPC_440S, 0xFFFFFFFF, 440),
4764 /* PowerPC 440 SP */
4765 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 0xFFFFFFFF, 440EP),
4766 /* PowerPC 440 SP2 */
4767 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 0xFFFFFFFF, 440EP),
4768 /* PowerPC 440 SPE */
4769 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 0xFFFFFFFF, 440EP),
4770 /* PowerPC 460 family */
4772 /* Generic PowerPC 464 */
4773 POWERPC_DEF("464", CPU_POWERPC_464, 0xFFFFFFFF, 460),
4775 /* PowerPC 464 microcontrolers */
4777 /* PowerPC 464H90 */
4778 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 0xFFFFFFFF, 460),
4781 /* PowerPC 464H90F */
4782 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 0xFFFFFFFF, 460F),
4784 /* Freescale embedded PowerPC cores */
4787 /* Generic PowerPC e200 core */
4788 POWERPC_DEF("e200", CPU_POWERPC_e200, 0xFFFFFFFF, e200),
4791 /* PowerPC e200z5 core */
4792 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, 0xFFFFFFFF, e200),
4795 /* PowerPC e200z6 core */
4796 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, 0xFFFFFFFF, e200),
4800 /* Generic PowerPC e300 core */
4801 POWERPC_DEF("e300", CPU_POWERPC_e300, 0xFFFFFFFF, e300),
4804 /* PowerPC e300c1 core */
4805 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, 0xFFFFFFFF, e300),
4808 /* PowerPC e300c2 core */
4809 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, 0xFFFFFFFF, e300),
4812 /* PowerPC e300c3 core */
4813 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, 0xFFFFFFFF, e300),
4817 /* PowerPC e500 core */
4818 POWERPC_DEF("e500", CPU_POWERPC_e500, 0xFFFFFFFF, e500),
4821 /* PowerPC e500 v1.1 core */
4822 POWERPC_DEF("e500v1.1", CPU_POWERPC_e500_v11, 0xFFFFFFFF, e500),
4825 /* PowerPC e500 v1.2 core */
4826 POWERPC_DEF("e500v1.2", CPU_POWERPC_e500_v12, 0xFFFFFFFF, e500),
4829 /* PowerPC e500 v2.1 core */
4830 POWERPC_DEF("e500v2.1", CPU_POWERPC_e500_v21, 0xFFFFFFFF, e500),
4833 /* PowerPC e500 v2.2 core */
4834 POWERPC_DEF("e500v2.2", CPU_POWERPC_e500_v22, 0xFFFFFFFF, e500),
4838 /* PowerPC e600 core */
4839 POWERPC_DEF("e600", CPU_POWERPC_e600, 0xFFFFFFFF, e600),
4841 /* PowerPC MPC 5xx cores */
4843 /* PowerPC MPC 5xx */
4844 POWERPC_DEF("mpc5xx", CPU_POWERPC_5xx, 0xFFFFFFFF, 5xx),
4846 /* PowerPC MPC 8xx cores */
4848 /* PowerPC MPC 8xx */
4849 POWERPC_DEF("mpc8xx", CPU_POWERPC_8xx, 0xFFFFFFFF, 8xx),
4851 /* PowerPC MPC 8xxx cores */
4853 /* PowerPC MPC 82xx HIP3 */
4854 POWERPC_DEF("mpc82xxhip3", CPU_POWERPC_82xx_HIP3, 0xFFFFFFFF, 82xx),
4857 /* PowerPC MPC 82xx HIP4 */
4858 POWERPC_DEF("mpc82xxhip4", CPU_POWERPC_82xx_HIP4, 0xFFFFFFFF, 82xx),
4861 /* PowerPC MPC 827x */
4862 POWERPC_DEF("mpc827x", CPU_POWERPC_827x, 0xFFFFFFFF, 827x),
4865 /* 32 bits "classic" PowerPC */
4866 /* PowerPC 6xx family */
4868 POWERPC_DEF("601", CPU_POWERPC_601, 0xFFFFFFFF, 601),
4870 POWERPC_DEF("601a", CPU_POWERPC_601a, 0xFFFFFFFF, 601),
4872 POWERPC_DEF("602", CPU_POWERPC_602, 0xFFFFFFFF, 602),
4874 POWERPC_DEF("603", CPU_POWERPC_603, 0xFFFFFFFF, 603),
4875 /* Code name for PowerPC 603 */
4876 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 0xFFFFFFFF, 603),
4878 POWERPC_DEF("603e", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
4879 /* Code name for PowerPC 603e */
4880 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 0xFFFFFFFF, 603E),
4881 /* PowerPC 603e v1.1 */
4882 POWERPC_DEF("603e1.1", CPU_POWERPC_603E_v11, 0xFFFFFFFF, 603E),
4883 /* PowerPC 603e v1.2 */
4884 POWERPC_DEF("603e1.2", CPU_POWERPC_603E_v12, 0xFFFFFFFF, 603E),
4885 /* PowerPC 603e v1.3 */
4886 POWERPC_DEF("603e1.3", CPU_POWERPC_603E_v13, 0xFFFFFFFF, 603E),
4887 /* PowerPC 603e v1.4 */
4888 POWERPC_DEF("603e1.4", CPU_POWERPC_603E_v14, 0xFFFFFFFF, 603E),
4889 /* PowerPC 603e v2.2 */
4890 POWERPC_DEF("603e2.2", CPU_POWERPC_603E_v22, 0xFFFFFFFF, 603E),
4891 /* PowerPC 603e v3 */
4892 POWERPC_DEF("603e3", CPU_POWERPC_603E_v3, 0xFFFFFFFF, 603E),
4893 /* PowerPC 603e v4 */
4894 POWERPC_DEF("603e4", CPU_POWERPC_603E_v4, 0xFFFFFFFF, 603E),
4895 /* PowerPC 603e v4.1 */
4896 POWERPC_DEF("603e4.1", CPU_POWERPC_603E_v41, 0xFFFFFFFF, 603E),
4898 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 0xFFFFFFFF, 603E),
4899 /* PowerPC 603e7t */
4900 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 0xFFFFFFFF, 603E),
4901 /* PowerPC 603e7v */
4902 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
4903 /* Code name for PowerPC 603ev */
4904 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 0xFFFFFFFF, 603E),
4905 /* PowerPC 603e7v1 */
4906 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 0xFFFFFFFF, 603E),
4907 /* PowerPC 603e7v2 */
4908 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 0xFFFFFFFF, 603E),
4911 POWERPC_DEF("603p", CPU_POWERPC_603P, 0xFFFFFFFF, 603),
4913 POWERPC_DEF("603r", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
4914 /* Code name for PowerPC 603r */
4915 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 0xFFFFFFFF, 603E),
4916 /* PowerPC G2 core */
4917 POWERPC_DEF("G2", CPU_POWERPC_G2, 0xFFFFFFFF, G2),
4919 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, 0xFFFFFFFF, G2),
4921 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, 0xFFFFFFFF, G2),
4923 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, 0xFFFFFFFF, G2),
4925 /* Same as G2, with little-endian mode support */
4926 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, 0xFFFFFFFF, G2LE),
4927 /* PowerPC G2LE GP */
4928 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, 0xFFFFFFFF, G2LE),
4929 /* PowerPC G2LE LS */
4930 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, 0xFFFFFFFF, G2LE),
4932 POWERPC_DEF("604", CPU_POWERPC_604, 0xFFFFFFFF, 604),
4934 POWERPC_DEF("604e", CPU_POWERPC_604E, 0xFFFFFFFF, 604),
4935 /* PowerPC 604e v1.0 */
4936 POWERPC_DEF("604e1.0", CPU_POWERPC_604E_v10, 0xFFFFFFFF, 604),
4937 /* PowerPC 604e v2.2 */
4938 POWERPC_DEF("604e2.2", CPU_POWERPC_604E_v22, 0xFFFFFFFF, 604),
4939 /* PowerPC 604e v2.4 */
4940 POWERPC_DEF("604e2.4", CPU_POWERPC_604E_v24, 0xFFFFFFFF, 604),
4942 POWERPC_DEF("604r", CPU_POWERPC_604R, 0xFFFFFFFF, 604),
4945 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 0xFFFFFFFF, 604),
4947 /* PowerPC 7xx family */
4948 /* Generic PowerPC 740 (G3) */
4949 POWERPC_DEF("740", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4950 /* Generic PowerPC 750 (G3) */
4951 POWERPC_DEF("750", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4952 /* Code name for generic PowerPC 740/750 (G3) */
4953 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4954 /* PowerPC 740/750 is also known as G3 */
4955 POWERPC_DEF("G3", CPU_POWERPC_7x0, 0xFFFFFFFF, 7x0),
4956 /* PowerPC 740 v2.0 (G3) */
4957 POWERPC_DEF("740v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
4958 /* PowerPC 750 v2.0 (G3) */
4959 POWERPC_DEF("750v2.0", CPU_POWERPC_7x0_v20, 0xFFFFFFFF, 7x0),
4960 /* PowerPC 740 v2.1 (G3) */
4961 POWERPC_DEF("740v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
4962 /* PowerPC 750 v2.1 (G3) */
4963 POWERPC_DEF("750v2.1", CPU_POWERPC_7x0_v21, 0xFFFFFFFF, 7x0),
4964 /* PowerPC 740 v2.2 (G3) */
4965 POWERPC_DEF("740v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
4966 /* PowerPC 750 v2.2 (G3) */
4967 POWERPC_DEF("750v2.2", CPU_POWERPC_7x0_v22, 0xFFFFFFFF, 7x0),
4968 /* PowerPC 740 v3.0 (G3) */
4969 POWERPC_DEF("740v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
4970 /* PowerPC 750 v3.0 (G3) */
4971 POWERPC_DEF("750v3.0", CPU_POWERPC_7x0_v30, 0xFFFFFFFF, 7x0),
4972 /* PowerPC 740 v3.1 (G3) */
4973 POWERPC_DEF("740v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
4974 /* PowerPC 750 v3.1 (G3) */
4975 POWERPC_DEF("750v3.1", CPU_POWERPC_7x0_v31, 0xFFFFFFFF, 7x0),
4976 /* PowerPC 740E (G3) */
4977 POWERPC_DEF("740e", CPU_POWERPC_740E, 0xFFFFFFFF, 7x0),
4978 /* PowerPC 740P (G3) */
4979 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
4980 /* PowerPC 750P (G3) */
4981 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
4982 /* Code name for PowerPC 740P/750P (G3) */
4983 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 0xFFFFFFFF, 7x0),
4984 /* PowerPC 750CL (G3 embedded) */
4985 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 0xFFFFFFFF, 7x0),
4986 /* PowerPC 750CX (G3 embedded) */
4987 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 0xFFFFFFFF, 7x0),
4988 /* PowerPC 750CX v2.1 (G3 embedded) */
4989 POWERPC_DEF("750cx2.1", CPU_POWERPC_750CX_v21, 0xFFFFFFFF, 7x0),
4990 /* PowerPC 750CX v2.2 (G3 embedded) */
4991 POWERPC_DEF("750cx2.2", CPU_POWERPC_750CX_v22, 0xFFFFFFFF, 7x0),
4992 /* PowerPC 750CXe (G3 embedded) */
4993 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 0xFFFFFFFF, 7x0),
4994 /* PowerPC 750CXe v2.1 (G3 embedded) */
4995 POWERPC_DEF("750cxe21", CPU_POWERPC_750CXE_v21, 0xFFFFFFFF, 7x0),
4996 /* PowerPC 750CXe v2.2 (G3 embedded) */
4997 POWERPC_DEF("750cxe22", CPU_POWERPC_750CXE_v22, 0xFFFFFFFF, 7x0),
4998 /* PowerPC 750CXe v2.3 (G3 embedded) */
4999 POWERPC_DEF("750cxe23", CPU_POWERPC_750CXE_v23, 0xFFFFFFFF, 7x0),
5000 /* PowerPC 750CXe v2.4 (G3 embedded) */
5001 POWERPC_DEF("750cxe24", CPU_POWERPC_750CXE_v24, 0xFFFFFFFF, 7x0),
5002 /* PowerPC 750CXe v2.4b (G3 embedded) */
5003 POWERPC_DEF("750cxe24b", CPU_POWERPC_750CXE_v24b, 0xFFFFFFFF, 7x0),
5004 /* PowerPC 750CXe v3.1 (G3 embedded) */
5005 POWERPC_DEF("750cxe31", CPU_POWERPC_750CXE_v31, 0xFFFFFFFF, 7x0),
5006 /* PowerPC 750CXe v3.1b (G3 embedded) */
5007 POWERPC_DEF("750cxe3.1b", CPU_POWERPC_750CXE_v31b, 0xFFFFFFFF, 7x0),
5008 /* PowerPC 750CXr (G3 embedded) */
5009 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 0xFFFFFFFF, 7x0),
5010 /* PowerPC 750E (G3) */
5011 POWERPC_DEF("750e", CPU_POWERPC_750E, 0xFFFFFFFF, 7x0),
5012 /* PowerPC 750FL (G3 embedded) */
5013 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 0xFFFFFFFF, 750fx),
5014 /* PowerPC 750FX (G3 embedded) */
5015 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 0xFFFFFFFF, 750fx),
5016 /* PowerPC 750FX v1.0 (G3 embedded) */
5017 POWERPC_DEF("750fx1.0", CPU_POWERPC_750FX_v10, 0xFFFFFFFF, 750fx),
5018 /* PowerPC 750FX v2.0 (G3 embedded) */
5019 POWERPC_DEF("750fx2.0", CPU_POWERPC_750FX_v20, 0xFFFFFFFF, 750fx),
5020 /* PowerPC 750FX v2.1 (G3 embedded) */
5021 POWERPC_DEF("750fx2.1", CPU_POWERPC_750FX_v21, 0xFFFFFFFF, 750fx),
5022 /* PowerPC 750FX v2.2 (G3 embedded) */
5023 POWERPC_DEF("750fx2.2", CPU_POWERPC_750FX_v22, 0xFFFFFFFF, 750fx),
5024 /* PowerPC 750FX v2.3 (G3 embedded) */
5025 POWERPC_DEF("750fx2.3", CPU_POWERPC_750FX_v23, 0xFFFFFFFF, 750fx),
5026 /* PowerPC 750GL (G3 embedded) */
5027 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 0xFFFFFFFF, 750fx),
5028 /* PowerPC 750GX (G3 embedded) */
5029 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 0xFFFFFFFF, 750fx),
5030 /* PowerPC 750GX v1.0 (G3 embedded) */
5031 POWERPC_DEF("750gx1.0", CPU_POWERPC_750GX_v10, 0xFFFFFFFF, 750fx),
5032 /* PowerPC 750GX v1.1 (G3 embedded) */
5033 POWERPC_DEF("750gx1.1", CPU_POWERPC_750GX_v11, 0xFFFFFFFF, 750fx),
5034 /* PowerPC 750GX v1.2 (G3 embedded) */
5035 POWERPC_DEF("750gx1.2", CPU_POWERPC_750GX_v12, 0xFFFFFFFF, 750fx),
5036 /* PowerPC 750L (G3 embedded) */
5037 POWERPC_DEF("750l", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5038 /* Code name for PowerPC 750L (G3 embedded) */
5039 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 0xFFFFFFFF, 7x0),
5040 /* PowerPC 750L v2.2 (G3 embedded) */
5041 POWERPC_DEF("750l2.2", CPU_POWERPC_750L_v22, 0xFFFFFFFF, 7x0),
5042 /* PowerPC 750L v3.0 (G3 embedded) */
5043 POWERPC_DEF("750l3.0", CPU_POWERPC_750L_v30, 0xFFFFFFFF, 7x0),
5044 /* PowerPC 750L v3.2 (G3 embedded) */
5045 POWERPC_DEF("750l3.2", CPU_POWERPC_750L_v32, 0xFFFFFFFF, 7x0),
5046 /* Generic PowerPC 745 */
5047 POWERPC_DEF("745", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5048 /* Generic PowerPC 755 */
5049 POWERPC_DEF("755", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5050 /* Code name for PowerPC 745/755 */
5051 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 0xFFFFFFFF, 7x5),
5052 /* PowerPC 745 v1.0 */
5053 POWERPC_DEF("745v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5054 /* PowerPC 755 v1.0 */
5055 POWERPC_DEF("755v1.0", CPU_POWERPC_7x5_v10, 0xFFFFFFFF, 7x5),
5056 /* PowerPC 745 v1.1 */
5057 POWERPC_DEF("745v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5058 /* PowerPC 755 v1.1 */
5059 POWERPC_DEF("755v1.1", CPU_POWERPC_7x5_v11, 0xFFFFFFFF, 7x5),
5060 /* PowerPC 745 v2.0 */
5061 POWERPC_DEF("745v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5062 /* PowerPC 755 v2.0 */
5063 POWERPC_DEF("755v2.0", CPU_POWERPC_7x5_v20, 0xFFFFFFFF, 7x5),
5064 /* PowerPC 745 v2.1 */
5065 POWERPC_DEF("745v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5066 /* PowerPC 755 v2.1 */
5067 POWERPC_DEF("755v2.1", CPU_POWERPC_7x5_v21, 0xFFFFFFFF, 7x5),
5068 /* PowerPC 745 v2.2 */
5069 POWERPC_DEF("745v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5070 /* PowerPC 755 v2.2 */
5071 POWERPC_DEF("755v2.2", CPU_POWERPC_7x5_v22, 0xFFFFFFFF, 7x5),
5072 /* PowerPC 745 v2.3 */
5073 POWERPC_DEF("745v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5074 /* PowerPC 755 v2.3 */
5075 POWERPC_DEF("755v2.3", CPU_POWERPC_7x5_v23, 0xFFFFFFFF, 7x5),
5076 /* PowerPC 745 v2.4 */
5077 POWERPC_DEF("745v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5078 /* PowerPC 755 v2.4 */
5079 POWERPC_DEF("755v2.4", CPU_POWERPC_7x5_v24, 0xFFFFFFFF, 7x5),
5080 /* PowerPC 745 v2.5 */
5081 POWERPC_DEF("745v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5082 /* PowerPC 755 v2.5 */
5083 POWERPC_DEF("755v2.5", CPU_POWERPC_7x5_v25, 0xFFFFFFFF, 7x5),
5084 /* PowerPC 745 v2.6 */
5085 POWERPC_DEF("745v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5086 /* PowerPC 755 v2.6 */
5087 POWERPC_DEF("755v2.6", CPU_POWERPC_7x5_v26, 0xFFFFFFFF, 7x5),
5088 /* PowerPC 745 v2.7 */
5089 POWERPC_DEF("745v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5090 /* PowerPC 755 v2.7 */
5091 POWERPC_DEF("755v2.7", CPU_POWERPC_7x5_v27, 0xFFFFFFFF, 7x5),
5092 /* PowerPC 745 v2.8 */
5093 POWERPC_DEF("745v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5094 /* PowerPC 755 v2.8 */
5095 POWERPC_DEF("755v2.8", CPU_POWERPC_7x5_v28, 0xFFFFFFFF, 7x5),
5097 /* PowerPC 745P (G3) */
5098 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5099 /* PowerPC 755P (G3) */
5100 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 0xFFFFFFFF, 7x5),
5102 /* PowerPC 74xx family */
5103 /* PowerPC 7400 (G4) */
5104 POWERPC_DEF("7400", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5105 /* Code name for PowerPC 7400 */
5106 POWERPC_DEF("Max", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5107 /* PowerPC 74xx is also well known as G4 */
5108 POWERPC_DEF("G4", CPU_POWERPC_7400, 0xFFFFFFFF, 7400),
5109 /* PowerPC 7400 v1.0 (G4) */
5110 POWERPC_DEF("7400v1.0", CPU_POWERPC_7400_v10, 0xFFFFFFFF, 7400),
5111 /* PowerPC 7400 v1.1 (G4) */
5112 POWERPC_DEF("7400v1.1", CPU_POWERPC_7400_v11, 0xFFFFFFFF, 7400),
5113 /* PowerPC 7400 v2.0 (G4) */
5114 POWERPC_DEF("7400v2.0", CPU_POWERPC_7400_v20, 0xFFFFFFFF, 7400),
5115 /* PowerPC 7400 v2.2 (G4) */
5116 POWERPC_DEF("7400v2.2", CPU_POWERPC_7400_v22, 0xFFFFFFFF, 7400),
5117 /* PowerPC 7400 v2.6 (G4) */
5118 POWERPC_DEF("7400v2.6", CPU_POWERPC_7400_v26, 0xFFFFFFFF, 7400),
5119 /* PowerPC 7400 v2.7 (G4) */
5120 POWERPC_DEF("7400v2.7", CPU_POWERPC_7400_v27, 0xFFFFFFFF, 7400),
5121 /* PowerPC 7400 v2.8 (G4) */
5122 POWERPC_DEF("7400v2.8", CPU_POWERPC_7400_v28, 0xFFFFFFFF, 7400),
5123 /* PowerPC 7400 v2.9 (G4) */
5124 POWERPC_DEF("7400v2.9", CPU_POWERPC_7400_v29, 0xFFFFFFFF, 7400),
5125 /* PowerPC 7410 (G4) */
5126 POWERPC_DEF("7410", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5127 /* Code name for PowerPC 7410 */
5128 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 0xFFFFFFFF, 7410),
5129 /* PowerPC 7410 v1.0 (G4) */
5130 POWERPC_DEF("7410v1.0", CPU_POWERPC_7410_v10, 0xFFFFFFFF, 7410),
5131 /* PowerPC 7410 v1.1 (G4) */
5132 POWERPC_DEF("7410v1.1", CPU_POWERPC_7410_v11, 0xFFFFFFFF, 7410),
5133 /* PowerPC 7410 v1.2 (G4) */
5134 POWERPC_DEF("7410v1.2", CPU_POWERPC_7410_v12, 0xFFFFFFFF, 7410),
5135 /* PowerPC 7410 v1.3 (G4) */
5136 POWERPC_DEF("7410v1.3", CPU_POWERPC_7410_v13, 0xFFFFFFFF, 7410),
5137 /* PowerPC 7410 v1.4 (G4) */
5138 POWERPC_DEF("7410v1.4", CPU_POWERPC_7410_v14, 0xFFFFFFFF, 7410),
5139 /* PowerPC 7448 (G4) */
5140 POWERPC_DEF("7448", CPU_POWERPC_7448, 0xFFFFFFFF, 7400),
5141 /* PowerPC 7448 v1.0 (G4) */
5142 POWERPC_DEF("7448v1.0", CPU_POWERPC_7448_v10, 0xFFFFFFFF, 7400),
5143 /* PowerPC 7448 v1.1 (G4) */
5144 POWERPC_DEF("7448v1.1", CPU_POWERPC_7448_v11, 0xFFFFFFFF, 7400),
5145 /* PowerPC 7448 v2.0 (G4) */
5146 POWERPC_DEF("7448v2.0", CPU_POWERPC_7448_v20, 0xFFFFFFFF, 7400),
5147 /* PowerPC 7448 v2.1 (G4) */
5148 POWERPC_DEF("7448v2.1", CPU_POWERPC_7448_v21, 0xFFFFFFFF, 7400),
5150 /* PowerPC 7450 (G4) */
5151 POWERPC_DEF("7450", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5152 /* Code name for PowerPC 7450 */
5153 POWERPC_DEF("Vger", CPU_POWERPC_7450, 0xFFFFFFFF, 7450),
5156 /* PowerPC 7450 v1.0 (G4) */
5157 POWERPC_DEF("7450v1.0", CPU_POWERPC_7450_v10, 0xFFFFFFFF, 7450),
5160 /* PowerPC 7450 v1.1 (G4) */
5161 POWERPC_DEF("7450v1.1", CPU_POWERPC_7450_v11, 0xFFFFFFFF, 7450),
5164 /* PowerPC 7450 v1.2 (G4) */
5165 POWERPC_DEF("7450v1.2", CPU_POWERPC_7450_v12, 0xFFFFFFFF, 7450),
5168 /* PowerPC 7450 v2.0 (G4) */
5169 POWERPC_DEF("7450v2.0", CPU_POWERPC_7450_v20, 0xFFFFFFFF, 7450),
5172 /* PowerPC 7450 v2.1 (G4) */
5173 POWERPC_DEF("7450v2.1", CPU_POWERPC_7450_v21, 0xFFFFFFFF, 7450),
5176 /* PowerPC 7441 (G4) */
5177 POWERPC_DEF("7441", CPU_POWERPC_74x1, 0xFFFFFFFF, 7440),
5178 /* PowerPC 7451 (G4) */
5179 POWERPC_DEF("7451", CPU_POWERPC_74x1, 0xFFFFFFFF, 7450),
5182 /* PowerPC 7441g (G4) */
5183 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7440),
5184 /* PowerPC 7451g (G4) */
5185 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 0xFFFFFFFF, 7450),
5188 /* PowerPC 7445 (G4) */
5189 POWERPC_DEF("7445", CPU_POWERPC_74x5, 0xFFFFFFFF, 7445),
5190 /* PowerPC 7455 (G4) */
5191 POWERPC_DEF("7455", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5192 /* Code name for PowerPC 7445/7455 */
5193 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 0xFFFFFFFF, 7455),
5196 /* PowerPC 7445 v1.0 (G4) */
5197 POWERPC_DEF("7445v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7445),
5198 /* PowerPC 7455 v1.0 (G4) */
5199 POWERPC_DEF("7455v1.0", CPU_POWERPC_74x5_v10, 0xFFFFFFFF, 7455),
5202 /* PowerPC 7445 v2.1 (G4) */
5203 POWERPC_DEF("7445v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7445),
5204 /* PowerPC 7455 v2.1 (G4) */
5205 POWERPC_DEF("7455v2.1", CPU_POWERPC_74x5_v21, 0xFFFFFFFF, 7455),
5208 /* PowerPC 7445 v3.2 (G4) */
5209 POWERPC_DEF("7445v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7445),
5210 /* PowerPC 7455 v3.2 (G4) */
5211 POWERPC_DEF("7455v3.2", CPU_POWERPC_74x5_v32, 0xFFFFFFFF, 7455),
5214 /* PowerPC 7445 v3.3 (G4) */
5215 POWERPC_DEF("7445v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7445),
5216 /* PowerPC 7455 v3.3 (G4) */
5217 POWERPC_DEF("7455v3.3", CPU_POWERPC_74x5_v33, 0xFFFFFFFF, 7455),
5220 /* PowerPC 7445 v3.4 (G4) */
5221 POWERPC_DEF("7445v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7445),
5222 /* PowerPC 7455 v3.4 (G4) */
5223 POWERPC_DEF("7455v3.4", CPU_POWERPC_74x5_v34, 0xFFFFFFFF, 7455),
5226 /* PowerPC 7447 (G4) */
5227 POWERPC_DEF("7447", CPU_POWERPC_74x7, 0xFFFFFFFF, 7445),
5228 /* PowerPC 7457 (G4) */
5229 POWERPC_DEF("7457", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5230 /* Code name for PowerPC 7447/7457 */
5231 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 0xFFFFFFFF, 7455),
5234 /* PowerPC 7447 v1.0 (G4) */
5235 POWERPC_DEF("7447v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7445),
5236 /* PowerPC 7457 v1.0 (G4) */
5237 POWERPC_DEF("7457v1.0", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5238 /* Code name for PowerPC 7447A/7457A */
5239 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 0xFFFFFFFF, 7455),
5242 /* PowerPC 7447 v1.1 (G4) */
5243 POWERPC_DEF("7447v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7445),
5244 /* PowerPC 7457 v1.1 (G4) */
5245 POWERPC_DEF("7457v1.1", CPU_POWERPC_74x7_v11, 0xFFFFFFFF, 7455),
5248 /* PowerPC 7447 v1.2 (G4) */
5249 POWERPC_DEF("7447v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7445),
5250 /* PowerPC 7457 v1.2 (G4) */
5251 POWERPC_DEF("7457v1.2", CPU_POWERPC_74x7_v12, 0xFFFFFFFF, 7455),
5253 /* 64 bits PowerPC */
5254 #if defined (TARGET_PPC64)
5257 POWERPC_DEF("620", CPU_POWERPC_620, 0xFFFFFFFF, 620),
5260 /* PowerPC 630 (POWER3) */
5261 POWERPC_DEF("630", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5262 POWERPC_DEF("POWER3", CPU_POWERPC_630, 0xFFFFFFFF, 630),
5265 /* PowerPC 631 (Power 3+) */
5266 POWERPC_DEF("631", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5267 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 0xFFFFFFFF, 631),
5271 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, 0xFFFFFFFF, POWER4),
5275 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, 0xFFFFFFFF, POWER4P),
5279 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, 0xFFFFFFFF, POWER5),
5281 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, 0xFFFFFFFF, POWER5),
5285 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, 0xFFFFFFFF, POWER5P),
5287 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, 0xFFFFFFFF, POWER5P),
5291 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, 0xFFFFFFFF, POWER6),
5292 /* POWER6 running in POWER5 mode */
5293 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, 0xFFFFFFFF, POWER5),
5295 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, 0xFFFFFFFF, POWER6),
5298 POWERPC_DEF("970", CPU_POWERPC_970, 0xFFFFFFFF, 970),
5299 /* PowerPC 970FX (G5) */
5300 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 0xFFFFFFFF, 970FX),
5301 /* PowerPC 970FX v1.0 (G5) */
5302 POWERPC_DEF("970fx1.0", CPU_POWERPC_970FX_v10, 0xFFFFFFFF, 970FX),
5303 /* PowerPC 970FX v2.0 (G5) */
5304 POWERPC_DEF("970fx2.0", CPU_POWERPC_970FX_v20, 0xFFFFFFFF, 970FX),
5305 /* PowerPC 970FX v2.1 (G5) */
5306 POWERPC_DEF("970fx2.1", CPU_POWERPC_970FX_v21, 0xFFFFFFFF, 970FX),
5307 /* PowerPC 970FX v3.0 (G5) */
5308 POWERPC_DEF("970fx3.0", CPU_POWERPC_970FX_v30, 0xFFFFFFFF, 970FX),
5309 /* PowerPC 970FX v3.1 (G5) */
5310 POWERPC_DEF("970fx3.1", CPU_POWERPC_970FX_v31, 0xFFFFFFFF, 970FX),
5311 /* PowerPC 970GX (G5) */
5312 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 0xFFFFFFFF, 970GX),
5314 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 0xFFFFFFFF, 970),
5315 /* PowerPC 970MP v1.0 */
5316 POWERPC_DEF("970mp1.0", CPU_POWERPC_970MP_v10, 0xFFFFFFFF, 970),
5317 /* PowerPC 970MP v1.1 */
5318 POWERPC_DEF("970mp1.1", CPU_POWERPC_970MP_v11, 0xFFFFFFFF, 970),
5321 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 0xFFFFFFFF, 970),
5324 /* PowerPC Cell v1.0 */
5325 POWERPC_DEF("Cell1.0", CPU_POWERPC_CELL_v10, 0xFFFFFFFF, 970),
5328 /* PowerPC Cell v2.0 */
5329 POWERPC_DEF("Cell2.0", CPU_POWERPC_CELL_v20, 0xFFFFFFFF, 970),
5332 /* PowerPC Cell v3.0 */
5333 POWERPC_DEF("Cell3.0", CPU_POWERPC_CELL_v30, 0xFFFFFFFF, 970),
5336 /* PowerPC Cell v3.1 */
5337 POWERPC_DEF("Cell3.1", CPU_POWERPC_CELL_v31, 0xFFFFFFFF, 970),
5340 /* PowerPC Cell v3.2 */
5341 POWERPC_DEF("Cell3.2", CPU_POWERPC_CELL_v32, 0xFFFFFFFF, 970),
5344 /* RS64 (Apache/A35) */
5345 /* This one seems to support the whole POWER2 instruction set
5346 * and the PowerPC 64 one.
5348 /* What about A10 & A30 ? */
5349 POWERPC_DEF("RS64", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5350 POWERPC_DEF("Apache", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5351 POWERPC_DEF("A35", CPU_POWERPC_RS64, 0xFFFFFFFF, RS64),
5354 /* RS64-II (NorthStar/A50) */
5355 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5356 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5357 POWERPC_DEF("A50", CPU_POWERPC_RS64II, 0xFFFFFFFF, RS64),
5360 /* RS64-III (Pulsar) */
5361 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5362 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, 0xFFFFFFFF, RS64),
5365 /* RS64-IV (IceStar/IStar/SStar) */
5366 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5367 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5368 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5369 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, 0xFFFFFFFF, RS64),
5371 #endif /* defined (TARGET_PPC64) */
5374 /* Original POWER */
5375 POWERPC_DEF("POWER", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5376 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5377 POWERPC_DEF("RSC", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5378 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5379 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, 0xFFFFFFFF, POWER),
5383 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5384 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5385 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, 0xFFFFFFFF, POWER),
5390 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, 0xFFFFFFFF, PA6T),
5392 /* Generic PowerPCs */
5393 #if defined (TARGET_PPC64)
5395 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, 0xFFFFFFFF, PPC64),
5398 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, 0xFFFFFFFF, PPC32),
5399 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5401 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, 0xFFFFFFFF, DEFAULT),
5404 /*****************************************************************************/
5405 /* Generic CPU instanciation routine */
5406 static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5408 #if !defined(CONFIG_USER_ONLY)
5411 env->irq_inputs = NULL;
5412 /* Set all exception vectors to an invalid address */
5413 for (i = 0; i < POWERPC_EXCP_NB; i++)
5414 env->excp_vectors[i] = (target_ulong)(-1ULL);
5415 env->excp_prefix = 0x00000000;
5416 env->ivor_mask = 0x00000000;
5417 env->ivpr_mask = 0x00000000;
5419 /* Default MMU definitions */
5423 /* Register SPR common to all PowerPC implementations */
5424 gen_spr_generic(env);
5425 spr_register(env, SPR_PVR, "PVR",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, SPR_NOACCESS,
5429 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5430 (*def->init_proc)(env);
5431 /* Allocate TLBs buffer when needed */
5432 if (env->nb_tlb != 0) {
5433 int nb_tlb = env->nb_tlb;
5434 if (env->id_tlbs != 0)
5436 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
5437 /* Pre-compute some useful values */
5438 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5440 #if !defined(CONFIG_USER_ONLY)
5441 if (env->irq_inputs == NULL) {
5442 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5443 " Attempt Qemu to crash very soon !\n");
5448 #if defined(PPC_DUMP_CPU)
5449 static void dump_ppc_sprs (CPUPPCState *env)
5452 #if !defined(CONFIG_USER_ONLY)
5458 printf("Special purpose registers:\n");
5459 for (i = 0; i < 32; i++) {
5460 for (j = 0; j < 32; j++) {
5462 spr = &env->spr_cb[n];
5463 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
5464 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
5465 #if !defined(CONFIG_USER_ONLY)
5466 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
5467 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
5468 if (sw || sr || uw || ur) {
5469 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
5470 (i << 5) | j, (i << 5) | j, spr->name,
5471 sw ? 'w' : '-', sr ? 'r' : '-',
5472 uw ? 'w' : '-', ur ? 'r' : '-');
5476 printf("SPR: %4d (%03x) %-8s u%c%c\n",
5477 (i << 5) | j, (i << 5) | j, spr->name,
5478 uw ? 'w' : '-', ur ? 'r' : '-');
5488 /*****************************************************************************/
5492 int fflush (FILE *stream);
5496 PPC_DIRECT = 0, /* Opcode routine */
5497 PPC_INDIRECT = 1, /* Indirect opcode table */
5500 static inline int is_indirect_opcode (void *handler)
5502 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
5505 static inline opc_handler_t **ind_table(void *handler)
5507 return (opc_handler_t **)((unsigned long)handler & ~3);
5510 /* Instruction table creation */
5511 /* Opcodes tables creation */
5512 static void fill_new_table (opc_handler_t **table, int len)
5516 for (i = 0; i < len; i++)
5517 table[i] = &invalid_handler;
5520 static int create_new_table (opc_handler_t **table, unsigned char idx)
5522 opc_handler_t **tmp;
5524 tmp = malloc(0x20 * sizeof(opc_handler_t));
5527 fill_new_table(tmp, 0x20);
5528 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
5533 static int insert_in_table (opc_handler_t **table, unsigned char idx,
5534 opc_handler_t *handler)
5536 if (table[idx] != &invalid_handler)
5538 table[idx] = handler;
5543 static int register_direct_insn (opc_handler_t **ppc_opcodes,
5544 unsigned char idx, opc_handler_t *handler)
5546 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
5547 printf("*** ERROR: opcode %02x already assigned in main "
5548 "opcode table\n", idx);
5555 static int register_ind_in_table (opc_handler_t **table,
5556 unsigned char idx1, unsigned char idx2,
5557 opc_handler_t *handler)
5559 if (table[idx1] == &invalid_handler) {
5560 if (create_new_table(table, idx1) < 0) {
5561 printf("*** ERROR: unable to create indirect table "
5562 "idx=%02x\n", idx1);
5566 if (!is_indirect_opcode(table[idx1])) {
5567 printf("*** ERROR: idx %02x already assigned to a direct "
5572 if (handler != NULL &&
5573 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
5574 printf("*** ERROR: opcode %02x already assigned in "
5575 "opcode table %02x\n", idx2, idx1);
5582 static int register_ind_insn (opc_handler_t **ppc_opcodes,
5583 unsigned char idx1, unsigned char idx2,
5584 opc_handler_t *handler)
5588 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
5593 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
5594 unsigned char idx1, unsigned char idx2,
5595 unsigned char idx3, opc_handler_t *handler)
5597 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
5598 printf("*** ERROR: unable to join indirect table idx "
5599 "[%02x-%02x]\n", idx1, idx2);
5602 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
5604 printf("*** ERROR: unable to insert opcode "
5605 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
5612 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
5614 if (insn->opc2 != 0xFF) {
5615 if (insn->opc3 != 0xFF) {
5616 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
5617 insn->opc3, &insn->handler) < 0)
5620 if (register_ind_insn(ppc_opcodes, insn->opc1,
5621 insn->opc2, &insn->handler) < 0)
5625 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
5632 static int test_opcode_table (opc_handler_t **table, int len)
5636 for (i = 0, count = 0; i < len; i++) {
5637 /* Consistency fixup */
5638 if (table[i] == NULL)
5639 table[i] = &invalid_handler;
5640 if (table[i] != &invalid_handler) {
5641 if (is_indirect_opcode(table[i])) {
5642 tmp = test_opcode_table(ind_table(table[i]), 0x20);
5645 table[i] = &invalid_handler;
5658 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
5660 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
5661 printf("*** WARNING: no opcode defined !\n");
5664 /*****************************************************************************/
5665 static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
5667 opcode_t *opc, *start, *end;
5669 fill_new_table(env->opcodes, 0x40);
5670 if (&opc_start < &opc_end) {
5677 for (opc = start + 1; opc != end; opc++) {
5678 if ((opc->handler.type & def->insns_flags) != 0) {
5679 if (register_insn(env->opcodes, opc) < 0) {
5680 printf("*** ERROR initializing PowerPC instruction "
5681 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
5687 fix_opcode_tables(env->opcodes);
5694 #if defined(PPC_DUMP_CPU)
5695 static int dump_ppc_insns (CPUPPCState *env)
5697 opc_handler_t **table, *handler;
5698 uint8_t opc1, opc2, opc3;
5700 printf("Instructions set:\n");
5701 /* opc1 is 6 bits long */
5702 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
5703 table = env->opcodes;
5704 handler = table[opc1];
5705 if (is_indirect_opcode(handler)) {
5706 /* opc2 is 5 bits long */
5707 for (opc2 = 0; opc2 < 0x20; opc2++) {
5708 table = env->opcodes;
5709 handler = env->opcodes[opc1];
5710 table = ind_table(handler);
5711 handler = table[opc2];
5712 if (is_indirect_opcode(handler)) {
5713 table = ind_table(handler);
5714 /* opc3 is 5 bits long */
5715 for (opc3 = 0; opc3 < 0x20; opc3++) {
5716 handler = table[opc3];
5717 if (handler->handler != &gen_invalid) {
5718 printf("INSN: %02x %02x %02x (%02d %04d) : %s\n",
5719 opc1, opc2, opc3, opc1, (opc3 << 5) | opc2,
5724 if (handler->handler != &gen_invalid) {
5725 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
5726 opc1, opc2, opc1, opc2, handler->oname);
5731 if (handler->handler != &gen_invalid) {
5732 printf("INSN: %02x -- -- (%02d ----) : %s\n",
5733 opc1, opc1, handler->oname);
5740 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
5742 env->msr_mask = def->msr_mask;
5743 env->mmu_model = def->mmu_model;
5744 env->excp_model = def->excp_model;
5745 env->bus_model = def->bus_model;
5746 env->bfd_mach = def->bfd_mach;
5747 if (create_ppc_opcodes(env, def) < 0)
5749 init_ppc_proc(env, def);
5750 #if defined(PPC_DUMP_CPU)
5752 const unsigned char *mmu_model, *excp_model, *bus_model;
5753 switch (env->mmu_model) {
5754 case POWERPC_MMU_32B:
5755 mmu_model = "PowerPC 32";
5757 case POWERPC_MMU_64B:
5758 mmu_model = "PowerPC 64";
5760 case POWERPC_MMU_601:
5761 mmu_model = "PowerPC 601";
5763 case POWERPC_MMU_SOFT_6xx:
5764 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
5766 case POWERPC_MMU_SOFT_74xx:
5767 mmu_model = "PowerPC 74xx with software driven TLBs";
5769 case POWERPC_MMU_SOFT_4xx:
5770 mmu_model = "PowerPC 4xx with software driven TLBs";
5772 case POWERPC_MMU_SOFT_4xx_Z:
5773 mmu_model = "PowerPC 4xx with software driven TLBs "
5774 "and zones protections";
5776 case POWERPC_MMU_REAL_4xx:
5777 mmu_model = "PowerPC 4xx real mode only";
5779 case POWERPC_MMU_BOOKE:
5780 mmu_model = "PowerPC BookE";
5782 case POWERPC_MMU_BOOKE_FSL:
5783 mmu_model = "PowerPC BookE FSL";
5785 case POWERPC_MMU_64BRIDGE:
5786 mmu_model = "PowerPC 64 bridge";
5789 mmu_model = "Unknown or invalid";
5792 switch (env->excp_model) {
5793 case POWERPC_EXCP_STD:
5794 excp_model = "PowerPC";
5796 case POWERPC_EXCP_40x:
5797 excp_model = "PowerPC 40x";
5799 case POWERPC_EXCP_601:
5800 excp_model = "PowerPC 601";
5802 case POWERPC_EXCP_602:
5803 excp_model = "PowerPC 602";
5805 case POWERPC_EXCP_603:
5806 excp_model = "PowerPC 603";
5808 case POWERPC_EXCP_603E:
5809 excp_model = "PowerPC 603e";
5811 case POWERPC_EXCP_604:
5812 excp_model = "PowerPC 604";
5814 case POWERPC_EXCP_7x0:
5815 excp_model = "PowerPC 740/750";
5817 case POWERPC_EXCP_7x5:
5818 excp_model = "PowerPC 745/755";
5820 case POWERPC_EXCP_74xx:
5821 excp_model = "PowerPC 74xx";
5823 case POWERPC_EXCP_970:
5824 excp_model = "PowerPC 970";
5826 case POWERPC_EXCP_BOOKE:
5827 excp_model = "PowerPC BookE";
5830 excp_model = "Unknown or invalid";
5833 switch (env->bus_model) {
5834 case PPC_FLAGS_INPUT_6xx:
5835 bus_model = "PowerPC 6xx";
5837 case PPC_FLAGS_INPUT_BookE:
5838 bus_model = "PowerPC BookE";
5840 case PPC_FLAGS_INPUT_405:
5841 bus_model = "PowerPC 405";
5843 case PPC_FLAGS_INPUT_970:
5844 bus_model = "PowerPC 970";
5846 case PPC_FLAGS_INPUT_401:
5847 bus_model = "PowerPC 401/403";
5850 bus_model = "Unknown or invalid";
5853 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
5854 " MMU model : %s\n",
5855 def->name, def->pvr, def->msr_mask, mmu_model);
5856 if (env->tlb != NULL) {
5857 printf(" %d %s TLB in %d ways\n",
5858 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
5861 printf(" Exceptions model : %s\n"
5862 " Bus model : %s\n",
5863 excp_model, bus_model);
5865 dump_ppc_insns(env);
5873 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
5879 for (i = 0; strcmp(ppc_defs[i].name, "default") != 0; i++) {
5880 if (strcasecmp(name, ppc_defs[i].name) == 0) {
5881 *def = &ppc_defs[i];
5890 int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
5896 for (i = 0; ppc_defs[i].name != NULL; i++) {
5897 if ((pvr & ppc_defs[i].pvr_mask) ==
5898 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
5899 *def = &ppc_defs[i];
5908 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5912 for (i = 0; ; i++) {
5913 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
5914 ppc_defs[i].name, ppc_defs[i].pvr);
5915 if (strcmp(ppc_defs[i].name, "default") == 0)