vcs.maemo.org Git - qemu/blob - target-ppc/translate.c

   1 /*
   2  *  PowerPC emulation for qemu: main translation routines.
   3  *
   4  *  Copyright (c) 2003-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25
  26 #include "cpu.h"
  27 #include "exec-all.h"
  28 #include "disas.h"
  29
  30 //#define DO_SINGLE_STEP
  31 //#define PPC_DEBUG_DISAS
  32
  33 #ifdef USE_DIRECT_JUMP
  34 #define TBPARAM(x)
  35 #else
  36 #define TBPARAM(x) (long)(x)
  37 #endif
  38
  39 enum {
  40 #define DEF(s, n, copy_size) INDEX_op_ ## s,
  41 #include "opc.h"
  42 #undef DEF
  43     NB_OPS,
  44 };
  45
  46 static uint16_t *gen_opc_ptr;
  47 static uint32_t *gen_opparam_ptr;
  48
  49 #include "gen-op.h"
  50
  51 #define GEN8(func, NAME) \
  52 static GenOpFunc *NAME ## _table [8] = {                                      \
  53 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
  54 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
  55 };                                                                            \
  56 static inline void func(int n)                                                \
  57 {                                                                             \
  58     NAME ## _table[n]();                                                      \
  59 }
  60
  61 #define GEN16(func, NAME)                                                     \
  62 static GenOpFunc *NAME ## _table [16] = {                                     \
  63 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
  64 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
  65 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
  66 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
  67 };                                                                            \
  68 static inline void func(int n)                                                \
  69 {                                                                             \
  70     NAME ## _table[n]();                                                      \
  71 }
  72
  73 #define GEN32(func, NAME) \
  74 static GenOpFunc *NAME ## _table [32] = {                                     \
  75 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
  76 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
  77 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
  78 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
  79 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
  80 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
  81 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
  82 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
  83 };                                                                            \
  84 static inline void func(int n)                                                \
  85 {                                                                             \
  86     NAME ## _table[n]();                                                      \
  87 }
  88
  89 /* Condition register moves */
  90 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
  91 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
  92 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
  93 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
  94
  95 /* Floating point condition and status register moves */
  96 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
  97 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
  98 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
  99 static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
 100     &gen_op_store_T0_fpscri_fpscr0,
 101     &gen_op_store_T0_fpscri_fpscr1,
 102     &gen_op_store_T0_fpscri_fpscr2,
 103     &gen_op_store_T0_fpscri_fpscr3,
 104     &gen_op_store_T0_fpscri_fpscr4,
 105     &gen_op_store_T0_fpscri_fpscr5,
 106     &gen_op_store_T0_fpscri_fpscr6,
 107     &gen_op_store_T0_fpscri_fpscr7,
 108 };
 109 static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
 110 {
 111     (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
 112 }
 113
 114 /* Segment register moves */
 115 GEN16(gen_op_load_sr, gen_op_load_sr);
 116 GEN16(gen_op_store_sr, gen_op_store_sr);
 117
 118 /* General purpose registers moves */
 119 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
 120 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
 121 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
 122
 123 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
 124 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
 125 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
 126
 127 /* floating point registers moves */
 128 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
 129 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
 130 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
 131 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
 132 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
 133 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
 134
 135 static uint8_t  spr_access[1024 / 2];
 136
 137 /* internal defines */
 138 typedef struct DisasContext {
 139     struct TranslationBlock *tb;
 140     target_ulong nip;
 141     uint32_t opcode;
 142     uint32_t exception;
 143     /* Routine used to access memory */
 144     int mem_idx;
 145     /* Translation flags */
 146 #if !defined(CONFIG_USER_ONLY)
 147     int supervisor;
 148 #endif
 149     int fpu_enabled;
 150     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
 151 } DisasContext;
 152
 153 struct opc_handler_t {
 154     /* invalid bits */
 155     uint32_t inval;
 156     /* instruction type */
 157     uint32_t type;
 158     /* handler */
 159     void (*handler)(DisasContext *ctx);
 160 };
 161
 162 #define RET_EXCP(ctx, excp, error)                                            \
 163 do {                                                                          \
 164     if ((ctx)->exception == EXCP_NONE) {                                      \
 165         gen_op_update_nip((ctx)->nip);                                        \
 166     }                                                                         \
 167     gen_op_raise_exception_err((excp), (error));                              \
 168     ctx->exception = (excp);                                                  \
 169 } while (0)
 170
 171 #define RET_INVAL(ctx)                                                        \
 172 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
 173
 174 #define RET_PRIVOPC(ctx)                                                      \
 175 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
 176
 177 #define RET_PRIVREG(ctx)                                                      \
 178 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
 179
 180 #define RET_MTMSR(ctx)                                                        \
 181 RET_EXCP((ctx), EXCP_MTMSR, 0)
 182
 183 static inline void RET_STOP (DisasContext *ctx)
 184 {
 185     RET_EXCP(ctx, EXCP_MTMSR, 0);
 186 }
 187
 188 static inline void RET_CHG_FLOW (DisasContext *ctx)
 189 {
 190     gen_op_raise_exception_err(EXCP_MTMSR, 0);
 191     ctx->exception = EXCP_MTMSR;
 192 }
 193
 194 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
 195 static void gen_##name (DisasContext *ctx);                                   \
 196 GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
 197 static void gen_##name (DisasContext *ctx)
 198
 199 typedef struct opcode_t {
 200     unsigned char opc1, opc2, opc3;
 201 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
 202     unsigned char pad[5];
 203 #else
 204     unsigned char pad[1];
 205 #endif
 206     opc_handler_t handler;
 207     const unsigned char *oname;
 208 } opcode_t;
 209
 210 /***                           Instruction decoding                        ***/
 211 #define EXTRACT_HELPER(name, shift, nb)                                       \
 212 static inline uint32_t name (uint32_t opcode)                                 \
 213 {                                                                             \
 214     return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
 215 }
 216
 217 #define EXTRACT_SHELPER(name, shift, nb)                                      \
 218 static inline int32_t name (uint32_t opcode)                                  \
 219 {                                                                             \
 220     return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
 221 }
 222
 223 /* Opcode part 1 */
 224 EXTRACT_HELPER(opc1, 26, 6);
 225 /* Opcode part 2 */
 226 EXTRACT_HELPER(opc2, 1, 5);
 227 /* Opcode part 3 */
 228 EXTRACT_HELPER(opc3, 6, 5);
 229 /* Update Cr0 flags */
 230 EXTRACT_HELPER(Rc, 0, 1);
 231 /* Destination */
 232 EXTRACT_HELPER(rD, 21, 5);
 233 /* Source */
 234 EXTRACT_HELPER(rS, 21, 5);
 235 /* First operand */
 236 EXTRACT_HELPER(rA, 16, 5);
 237 /* Second operand */
 238 EXTRACT_HELPER(rB, 11, 5);
 239 /* Third operand */
 240 EXTRACT_HELPER(rC, 6, 5);
 241 /***                               Get CRn                                 ***/
 242 EXTRACT_HELPER(crfD, 23, 3);
 243 EXTRACT_HELPER(crfS, 18, 3);
 244 EXTRACT_HELPER(crbD, 21, 5);
 245 EXTRACT_HELPER(crbA, 16, 5);
 246 EXTRACT_HELPER(crbB, 11, 5);
 247 /* SPR / TBL */
 248 EXTRACT_HELPER(_SPR, 11, 10);
 249 static inline uint32_t SPR (uint32_t opcode)
 250 {
 251     uint32_t sprn = _SPR(opcode);
 252
 253     return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
 254 }
 255 /***                              Get constants                            ***/
 256 EXTRACT_HELPER(IMM, 12, 8);
 257 /* 16 bits signed immediate value */
 258 EXTRACT_SHELPER(SIMM, 0, 16);
 259 /* 16 bits unsigned immediate value */
 260 EXTRACT_HELPER(UIMM, 0, 16);
 261 /* Bit count */
 262 EXTRACT_HELPER(NB, 11, 5);
 263 /* Shift count */
 264 EXTRACT_HELPER(SH, 11, 5);
 265 /* Mask start */
 266 EXTRACT_HELPER(MB, 6, 5);
 267 /* Mask end */
 268 EXTRACT_HELPER(ME, 1, 5);
 269 /* Trap operand */
 270 EXTRACT_HELPER(TO, 21, 5);
 271
 272 EXTRACT_HELPER(CRM, 12, 8);
 273 EXTRACT_HELPER(FM, 17, 8);
 274 EXTRACT_HELPER(SR, 16, 4);
 275 EXTRACT_HELPER(FPIMM, 20, 4);
 276
 277 /***                            Jump target decoding                       ***/
 278 /* Displacement */
 279 EXTRACT_SHELPER(d, 0, 16);
 280 /* Immediate address */
 281 static inline uint32_t LI (uint32_t opcode)
 282 {
 283     return (opcode >> 0) & 0x03FFFFFC;
 284 }
 285
 286 static inline uint32_t BD (uint32_t opcode)
 287 {
 288     return (opcode >> 0) & 0xFFFC;
 289 }
 290
 291 EXTRACT_HELPER(BO, 21, 5);
 292 EXTRACT_HELPER(BI, 16, 5);
 293 /* Absolute/relative address */
 294 EXTRACT_HELPER(AA, 1, 1);
 295 /* Link */
 296 EXTRACT_HELPER(LK, 0, 1);
 297
 298 /* Create a mask between <start> and <end> bits */
 299 static inline uint32_t MASK (uint32_t start, uint32_t end)
 300 {
 301     uint32_t ret;
 302
 303     ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
 304     if (start > end)
 305         return ~ret;
 306
 307     return ret;
 308 }
 309
 310 #if HOST_LONG_BITS == 64
 311 #define OPC_ALIGN 8
 312 #else
 313 #define OPC_ALIGN 4
 314 #endif
 315 #if defined(__APPLE__)
 316 #define OPCODES_SECTION \
 317     __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
 318 #else
 319 #define OPCODES_SECTION \
 320     __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
 321 #endif
 322
 323 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
 324 OPCODES_SECTION opcode_t opc_##name = {                                       \
 325     .opc1 = op1,                                                              \
 326     .opc2 = op2,                                                              \
 327     .opc3 = op3,                                                              \
 328     .pad  = { 0, },                                                           \
 329     .handler = {                                                              \
 330         .inval   = invl,                                                      \
 331         .type = _typ,                                                         \
 332         .handler = &gen_##name,                                               \
 333     },                                                                        \
 334     .oname = stringify(name),                                                 \
 335 }
 336
 337 #define GEN_OPCODE_MARK(name)                                                 \
 338 OPCODES_SECTION opcode_t opc_##name = {                                       \
 339     .opc1 = 0xFF,                                                             \
 340     .opc2 = 0xFF,                                                             \
 341     .opc3 = 0xFF,                                                             \
 342     .pad  = { 0, },                                                           \
 343     .handler = {                                                              \
 344         .inval   = 0x00000000,                                                \
 345         .type = 0x00,                                                         \
 346         .handler = NULL,                                                      \
 347     },                                                                        \
 348     .oname = stringify(name),                                                 \
 349 }
 350
 351 /* Start opcode list */
 352 GEN_OPCODE_MARK(start);
 353
 354 /* Invalid instruction */
 355 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
 356 {
 357     RET_INVAL(ctx);
 358 }
 359
 360 static opc_handler_t invalid_handler = {
 361     .inval   = 0xFFFFFFFF,
 362     .type    = PPC_NONE,
 363     .handler = gen_invalid,
 364 };
 365
 366 /***                           Integer arithmetic                          ***/
 367 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval)                       \
 368 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
 369 {                                                                             \
 370     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
 371     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
 372     gen_op_##name();                                                          \
 373     if (Rc(ctx->opcode) != 0)                                                 \
 374         gen_op_set_Rc0();                                                     \
 375     gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
 376 }
 377
 378 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval)                     \
 379 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER)                       \
 380 {                                                                             \
 381     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
 382     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
 383     gen_op_##name();                                                          \
 384     if (Rc(ctx->opcode) != 0)                                                 \
 385         gen_op_set_Rc0();                                                     \
 386     gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
 387 }
 388
 389 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3)                              \
 390 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
 391 {                                                                             \
 392     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
 393     gen_op_##name();                                                          \
 394     if (Rc(ctx->opcode) != 0)                                                 \
 395         gen_op_set_Rc0();                                                     \
 396     gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
 397 }
 398 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3)                            \
 399 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER)                  \
 400 {                                                                             \
 401     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
 402     gen_op_##name();                                                          \
 403     if (Rc(ctx->opcode) != 0)                                                 \
 404         gen_op_set_Rc0();                                                     \
 405     gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
 406 }
 407
 408 /* Two operands arithmetic functions */
 409 #define GEN_INT_ARITH2(name, opc1, opc2, opc3)                                \
 410 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000)                          \
 411 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
 412
 413 /* Two operands arithmetic functions with no overflow allowed */
 414 #define GEN_INT_ARITHN(name, opc1, opc2, opc3)                                \
 415 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
 416
 417 /* One operand arithmetic functions */
 418 #define GEN_INT_ARITH1(name, opc1, opc2, opc3)                                \
 419 __GEN_INT_ARITH1(name, opc1, opc2, opc3)                                      \
 420 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
 421
 422 /* add    add.    addo    addo.    */
 423 GEN_INT_ARITH2 (add,    0x1F, 0x0A, 0x08);
 424 /* addc   addc.   addco   addco.   */
 425 GEN_INT_ARITH2 (addc,   0x1F, 0x0A, 0x00);
 426 /* adde   adde.   addeo   addeo.   */
 427 GEN_INT_ARITH2 (adde,   0x1F, 0x0A, 0x04);
 428 /* addme  addme.  addmeo  addmeo.  */
 429 GEN_INT_ARITH1 (addme,  0x1F, 0x0A, 0x07);
 430 /* addze  addze.  addzeo  addzeo.  */
 431 GEN_INT_ARITH1 (addze,  0x1F, 0x0A, 0x06);
 432 /* divw   divw.   divwo   divwo.   */
 433 GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F);
 434 /* divwu  divwu.  divwuo  divwuo.  */
 435 GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E);
 436 /* mulhw  mulhw.                   */
 437 GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02);
 438 /* mulhwu mulhwu.                  */
 439 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
 440 /* mullw  mullw.  mullwo  mullwo.  */
 441 GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07);
 442 /* neg    neg.    nego    nego.    */
 443 GEN_INT_ARITH1 (neg,    0x1F, 0x08, 0x03);
 444 /* subf   subf.   subfo   subfo.   */
 445 GEN_INT_ARITH2 (subf,   0x1F, 0x08, 0x01);
 446 /* subfc  subfc.  subfco  subfco.  */
 447 GEN_INT_ARITH2 (subfc,  0x1F, 0x08, 0x00);
 448 /* subfe  subfe.  subfeo  subfeo.  */
 449 GEN_INT_ARITH2 (subfe,  0x1F, 0x08, 0x04);
 450 /* subfme subfme. subfmeo subfmeo. */
 451 GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
 452 /* subfze subfze. subfzeo subfzeo. */
 453 GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
 454 /* addi */
 455 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 456 {
 457     int32_t simm = SIMM(ctx->opcode);
 458
 459     if (rA(ctx->opcode) == 0) {
 460         gen_op_set_T0(simm);
 461     } else {
 462         gen_op_load_gpr_T0(rA(ctx->opcode));
 463         gen_op_addi(simm);
 464     }
 465     gen_op_store_T0_gpr(rD(ctx->opcode));
 466 }
 467 /* addic */
 468 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 469 {
 470     gen_op_load_gpr_T0(rA(ctx->opcode));
 471     gen_op_addic(SIMM(ctx->opcode));
 472     gen_op_store_T0_gpr(rD(ctx->opcode));
 473 }
 474 /* addic. */
 475 GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 476 {
 477     gen_op_load_gpr_T0(rA(ctx->opcode));
 478     gen_op_addic(SIMM(ctx->opcode));
 479     gen_op_set_Rc0();
 480     gen_op_store_T0_gpr(rD(ctx->opcode));
 481 }
 482 /* addis */
 483 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 484 {
 485     int32_t simm = SIMM(ctx->opcode);
 486
 487     if (rA(ctx->opcode) == 0) {
 488         gen_op_set_T0(simm << 16);
 489     } else {
 490         gen_op_load_gpr_T0(rA(ctx->opcode));
 491         gen_op_addi(simm << 16);
 492     }
 493     gen_op_store_T0_gpr(rD(ctx->opcode));
 494 }
 495 /* mulli */
 496 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 497 {
 498     gen_op_load_gpr_T0(rA(ctx->opcode));
 499     gen_op_mulli(SIMM(ctx->opcode));
 500     gen_op_store_T0_gpr(rD(ctx->opcode));
 501 }
 502 /* subfic */
 503 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 504 {
 505     gen_op_load_gpr_T0(rA(ctx->opcode));
 506     gen_op_subfic(SIMM(ctx->opcode));
 507     gen_op_store_T0_gpr(rD(ctx->opcode));
 508 }
 509
 510 /***                           Integer comparison                          ***/
 511 #define GEN_CMP(name, opc)                                                    \
 512 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER)                   \
 513 {                                                                             \
 514     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
 515     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
 516     gen_op_##name();                                                          \
 517     gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
 518 }
 519
 520 /* cmp */
 521 GEN_CMP(cmp, 0x00);
 522 /* cmpi */
 523 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
 524 {
 525     gen_op_load_gpr_T0(rA(ctx->opcode));
 526     gen_op_cmpi(SIMM(ctx->opcode));
 527     gen_op_store_T0_crf(crfD(ctx->opcode));
 528 }
 529 /* cmpl */
 530 GEN_CMP(cmpl, 0x01);
 531 /* cmpli */
 532 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
 533 {
 534     gen_op_load_gpr_T0(rA(ctx->opcode));
 535     gen_op_cmpli(UIMM(ctx->opcode));
 536     gen_op_store_T0_crf(crfD(ctx->opcode));
 537 }
 538
 539 /***                            Integer logical                            ***/
 540 #define __GEN_LOGICAL2(name, opc2, opc3)                                      \
 541 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER)                  \
 542 {                                                                             \
 543     gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
 544     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
 545     gen_op_##name();                                                          \
 546     if (Rc(ctx->opcode) != 0)                                                 \
 547         gen_op_set_Rc0();                                                     \
 548     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
 549 }
 550 #define GEN_LOGICAL2(name, opc)                                               \
 551 __GEN_LOGICAL2(name, 0x1C, opc)
 552
 553 #define GEN_LOGICAL1(name, opc)                                               \
 554 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER)                   \
 555 {                                                                             \
 556     gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
 557     gen_op_##name();                                                          \
 558     if (Rc(ctx->opcode) != 0)                                                 \
 559         gen_op_set_Rc0();                                                     \
 560     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
 561 }
 562
 563 /* and & and. */
 564 GEN_LOGICAL2(and, 0x00);
 565 /* andc & andc. */
 566 GEN_LOGICAL2(andc, 0x01);
 567 /* andi. */
 568 GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 569 {
 570     gen_op_load_gpr_T0(rS(ctx->opcode));
 571     gen_op_andi_(UIMM(ctx->opcode));
 572     gen_op_set_Rc0();
 573     gen_op_store_T0_gpr(rA(ctx->opcode));
 574 }
 575 /* andis. */
 576 GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 577 {
 578     gen_op_load_gpr_T0(rS(ctx->opcode));
 579     gen_op_andi_(UIMM(ctx->opcode) << 16);
 580     gen_op_set_Rc0();
 581     gen_op_store_T0_gpr(rA(ctx->opcode));
 582 }
 583
 584 /* cntlzw */
 585 GEN_LOGICAL1(cntlzw, 0x00);
 586 /* eqv & eqv. */
 587 GEN_LOGICAL2(eqv, 0x08);
 588 /* extsb & extsb. */
 589 GEN_LOGICAL1(extsb, 0x1D);
 590 /* extsh & extsh. */
 591 GEN_LOGICAL1(extsh, 0x1C);
 592 /* nand & nand. */
 593 GEN_LOGICAL2(nand, 0x0E);
 594 /* nor & nor. */
 595 GEN_LOGICAL2(nor, 0x03);
 596
 597 /* or & or. */
 598 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
 599 {
 600     gen_op_load_gpr_T0(rS(ctx->opcode));
 601     /* Optimisation for mr case */
 602     if (rS(ctx->opcode) != rB(ctx->opcode)) {
 603         gen_op_load_gpr_T1(rB(ctx->opcode));
 604         gen_op_or();
 605     }
 606     if (Rc(ctx->opcode) != 0)
 607         gen_op_set_Rc0();
 608     gen_op_store_T0_gpr(rA(ctx->opcode));
 609 }
 610
 611 /* orc & orc. */
 612 GEN_LOGICAL2(orc, 0x0C);
 613 /* xor & xor. */
 614 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
 615 {
 616     gen_op_load_gpr_T0(rS(ctx->opcode));
 617     /* Optimisation for "set to zero" case */
 618     if (rS(ctx->opcode) != rB(ctx->opcode)) {
 619         gen_op_load_gpr_T1(rB(ctx->opcode));
 620         gen_op_xor();
 621     } else {
 622         gen_op_set_T0(0);
 623     }
 624     if (Rc(ctx->opcode) != 0)
 625         gen_op_set_Rc0();
 626     gen_op_store_T0_gpr(rA(ctx->opcode));
 627 }
 628 /* ori */
 629 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 630 {
 631     uint32_t uimm = UIMM(ctx->opcode);
 632
 633     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
 634         /* NOP */
 635         return;
 636         }
 637         gen_op_load_gpr_T0(rS(ctx->opcode));
 638     if (uimm != 0)
 639         gen_op_ori(uimm);
 640         gen_op_store_T0_gpr(rA(ctx->opcode));
 641 }
 642 /* oris */
 643 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 644 {
 645     uint32_t uimm = UIMM(ctx->opcode);
 646
 647     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
 648         /* NOP */
 649         return;
 650         }
 651         gen_op_load_gpr_T0(rS(ctx->opcode));
 652     if (uimm != 0)
 653         gen_op_ori(uimm << 16);
 654         gen_op_store_T0_gpr(rA(ctx->opcode));
 655 }
 656 /* xori */
 657 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 658 {
 659     uint32_t uimm = UIMM(ctx->opcode);
 660
 661     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
 662         /* NOP */
 663         return;
 664     }
 665     gen_op_load_gpr_T0(rS(ctx->opcode));
 666     if (uimm != 0)
 667     gen_op_xori(uimm);
 668     gen_op_store_T0_gpr(rA(ctx->opcode));
 669 }
 670
 671 /* xoris */
 672 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 673 {
 674     uint32_t uimm = UIMM(ctx->opcode);
 675
 676     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
 677         /* NOP */
 678         return;
 679     }
 680     gen_op_load_gpr_T0(rS(ctx->opcode));
 681     if (uimm != 0)
 682     gen_op_xori(uimm << 16);
 683     gen_op_store_T0_gpr(rA(ctx->opcode));
 684 }
 685
 686 /***                             Integer rotate                            ***/
 687 /* rlwimi & rlwimi. */
 688 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 689 {
 690     uint32_t mb, me;
 691
 692     mb = MB(ctx->opcode);
 693     me = ME(ctx->opcode);
 694     gen_op_load_gpr_T0(rS(ctx->opcode));
 695     gen_op_load_gpr_T1(rA(ctx->opcode));
 696     gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
 697     if (Rc(ctx->opcode) != 0)
 698         gen_op_set_Rc0();
 699     gen_op_store_T0_gpr(rA(ctx->opcode));
 700 }
 701 /* rlwinm & rlwinm. */
 702 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 703 {
 704     uint32_t mb, me, sh;
 705
 706     sh = SH(ctx->opcode);
 707     mb = MB(ctx->opcode);
 708     me = ME(ctx->opcode);
 709     gen_op_load_gpr_T0(rS(ctx->opcode));
 710 #if 1 // TRY
 711     if (sh == 0) {
 712         gen_op_andi_(MASK(mb, me));
 713         goto store;
 714     }
 715 #endif
 716     if (mb == 0) {
 717         if (me == 31) {
 718             gen_op_rotlwi(sh);
 719             goto store;
 720 #if 0
 721         } else if (me == (31 - sh)) {
 722             gen_op_slwi(sh);
 723             goto store;
 724 #endif
 725         }
 726     } else if (me == 31) {
 727 #if 0
 728         if (sh == (32 - mb)) {
 729             gen_op_srwi(mb);
 730             goto store;
 731         }
 732 #endif
 733     }
 734     gen_op_rlwinm(sh, MASK(mb, me));
 735 store:
 736     if (Rc(ctx->opcode) != 0)
 737         gen_op_set_Rc0();
 738     gen_op_store_T0_gpr(rA(ctx->opcode));
 739 }
 740 /* rlwnm & rlwnm. */
 741 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 742 {
 743     uint32_t mb, me;
 744
 745     mb = MB(ctx->opcode);
 746     me = ME(ctx->opcode);
 747     gen_op_load_gpr_T0(rS(ctx->opcode));
 748     gen_op_load_gpr_T1(rB(ctx->opcode));
 749     if (mb == 0 && me == 31) {
 750         gen_op_rotl();
 751     } else
 752     {
 753         gen_op_rlwnm(MASK(mb, me));
 754     }
 755     if (Rc(ctx->opcode) != 0)
 756         gen_op_set_Rc0();
 757     gen_op_store_T0_gpr(rA(ctx->opcode));
 758 }
 759
 760 /***                             Integer shift                             ***/
 761 /* slw & slw. */
 762 __GEN_LOGICAL2(slw, 0x18, 0x00);
 763 /* sraw & sraw. */
 764 __GEN_LOGICAL2(sraw, 0x18, 0x18);
 765 /* srawi & srawi. */
 766 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
 767 {
 768     gen_op_load_gpr_T0(rS(ctx->opcode));
 769     if (SH(ctx->opcode) != 0)
 770     gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
 771     if (Rc(ctx->opcode) != 0)
 772         gen_op_set_Rc0();
 773     gen_op_store_T0_gpr(rA(ctx->opcode));
 774 }
 775 /* srw & srw. */
 776 __GEN_LOGICAL2(srw, 0x18, 0x10);
 777
 778 /***                       Floating-Point arithmetic                       ***/
 779 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat)                           \
 780 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT)                   \
 781 {                                                                             \
 782     if (!ctx->fpu_enabled) {                                                  \
 783         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
 784         return;                                                               \
 785     }                                                                         \
 786     gen_op_reset_scrfx();                                                     \
 787     gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
 788     gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
 789     gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
 790     gen_op_f##op();                                                           \
 791     if (isfloat) {                                                            \
 792         gen_op_frsp();                                                        \
 793     }                                                                         \
 794     gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
 795     if (Rc(ctx->opcode))                                                      \
 796         gen_op_set_Rc1();                                                     \
 797 }
 798
 799 #define GEN_FLOAT_ACB(name, op2)                                              \
 800 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0);                                     \
 801 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
 802
 803 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat)                     \
 804 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
 805 {                                                                             \
 806     if (!ctx->fpu_enabled) {                                                  \
 807         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
 808         return;                                                               \
 809     }                                                                         \
 810     gen_op_reset_scrfx();                                                     \
 811     gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
 812     gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
 813     gen_op_f##op();                                                           \
 814     if (isfloat) {                                                            \
 815         gen_op_frsp();                                                        \
 816     }                                                                         \
 817     gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
 818     if (Rc(ctx->opcode))                                                      \
 819         gen_op_set_Rc1();                                                     \
 820 }
 821 #define GEN_FLOAT_AB(name, op2, inval)                                        \
 822 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0);                               \
 823 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
 824
 825 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat)                     \
 826 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
 827 {                                                                             \
 828     if (!ctx->fpu_enabled) {                                                  \
 829         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
 830         return;                                                               \
 831     }                                                                         \
 832     gen_op_reset_scrfx();                                                     \
 833     gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
 834     gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
 835     gen_op_f##op();                                                           \
 836     if (isfloat) {                                                            \
 837         gen_op_frsp();                                                        \
 838     }                                                                         \
 839     gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
 840     if (Rc(ctx->opcode))                                                      \
 841         gen_op_set_Rc1();                                                     \
 842 }
 843 #define GEN_FLOAT_AC(name, op2, inval)                                        \
 844 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0);                               \
 845 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
 846
 847 #define GEN_FLOAT_B(name, op2, op3)                                           \
 848 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT)                   \
 849 {                                                                             \
 850     if (!ctx->fpu_enabled) {                                                  \
 851         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
 852         return;                                                               \
 853     }                                                                         \
 854     gen_op_reset_scrfx();                                                     \
 855     gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
 856     gen_op_f##name();                                                         \
 857     gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
 858     if (Rc(ctx->opcode))                                                      \
 859         gen_op_set_Rc1();                                                     \
 860 }
 861
 862 #define GEN_FLOAT_BS(name, op1, op2)                                          \
 863 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT)                   \
 864 {                                                                             \
 865     if (!ctx->fpu_enabled) {                                                  \
 866         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
 867         return;                                                               \
 868     }                                                                         \
 869     gen_op_reset_scrfx();                                                     \
 870     gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
 871     gen_op_f##name();                                                         \
 872     gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
 873     if (Rc(ctx->opcode))                                                      \
 874         gen_op_set_Rc1();                                                     \
 875 }
 876
 877 /* fadd - fadds */
 878 GEN_FLOAT_AB(add, 0x15, 0x000007C0);
 879 /* fdiv - fdivs */
 880 GEN_FLOAT_AB(div, 0x12, 0x000007C0);
 881 /* fmul - fmuls */
 882 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
 883
 884 /* fres */
 885 GEN_FLOAT_BS(res, 0x3B, 0x18);
 886
 887 /* frsqrte */
 888 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
 889
 890 /* fsel */
 891 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
 892 /* fsub - fsubs */
 893 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
 894 /* Optional: */
 895 /* fsqrt */
 896 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
 897 {
 898     if (!ctx->fpu_enabled) {
 899         RET_EXCP(ctx, EXCP_NO_FP, 0);
 900         return;
 901     }
 902     gen_op_reset_scrfx();
 903     gen_op_load_fpr_FT0(rB(ctx->opcode));
 904     gen_op_fsqrt();
 905     gen_op_store_FT0_fpr(rD(ctx->opcode));
 906     if (Rc(ctx->opcode))
 907         gen_op_set_Rc1();
 908 }
 909
 910 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
 911 {
 912     if (!ctx->fpu_enabled) {
 913         RET_EXCP(ctx, EXCP_NO_FP, 0);
 914         return;
 915     }
 916     gen_op_reset_scrfx();
 917     gen_op_load_fpr_FT0(rB(ctx->opcode));
 918     gen_op_fsqrt();
 919     gen_op_frsp();
 920     gen_op_store_FT0_fpr(rD(ctx->opcode));
 921     if (Rc(ctx->opcode))
 922         gen_op_set_Rc1();
 923 }
 924
 925 /***                     Floating-Point multiply-and-add                   ***/
 926 /* fmadd - fmadds */
 927 GEN_FLOAT_ACB(madd, 0x1D);
 928 /* fmsub - fmsubs */
 929 GEN_FLOAT_ACB(msub, 0x1C);
 930 /* fnmadd - fnmadds */
 931 GEN_FLOAT_ACB(nmadd, 0x1F);
 932 /* fnmsub - fnmsubs */
 933 GEN_FLOAT_ACB(nmsub, 0x1E);
 934
 935 /***                     Floating-Point round & convert                    ***/
 936 /* fctiw */
 937 GEN_FLOAT_B(ctiw, 0x0E, 0x00);
 938 /* fctiwz */
 939 GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
 940 /* frsp */
 941 GEN_FLOAT_B(rsp, 0x0C, 0x00);
 942
 943 /***                         Floating-Point compare                        ***/
 944 /* fcmpo */
 945 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
 946 {
 947     if (!ctx->fpu_enabled) {
 948         RET_EXCP(ctx, EXCP_NO_FP, 0);
 949         return;
 950     }
 951     gen_op_reset_scrfx();
 952     gen_op_load_fpr_FT0(rA(ctx->opcode));
 953     gen_op_load_fpr_FT1(rB(ctx->opcode));
 954     gen_op_fcmpo();
 955     gen_op_store_T0_crf(crfD(ctx->opcode));
 956 }
 957
 958 /* fcmpu */
 959 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
 960 {
 961     if (!ctx->fpu_enabled) {
 962         RET_EXCP(ctx, EXCP_NO_FP, 0);
 963         return;
 964     }
 965     gen_op_reset_scrfx();
 966     gen_op_load_fpr_FT0(rA(ctx->opcode));
 967     gen_op_load_fpr_FT1(rB(ctx->opcode));
 968     gen_op_fcmpu();
 969     gen_op_store_T0_crf(crfD(ctx->opcode));
 970 }
 971
 972 /***                         Floating-point move                           ***/
 973 /* fabs */
 974 GEN_FLOAT_B(abs, 0x08, 0x08);
 975
 976 /* fmr  - fmr. */
 977 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
 978 {
 979     if (!ctx->fpu_enabled) {
 980         RET_EXCP(ctx, EXCP_NO_FP, 0);
 981         return;
 982     }
 983     gen_op_reset_scrfx();
 984     gen_op_load_fpr_FT0(rB(ctx->opcode));
 985     gen_op_store_FT0_fpr(rD(ctx->opcode));
 986     if (Rc(ctx->opcode))
 987         gen_op_set_Rc1();
 988 }
 989
 990 /* fnabs */
 991 GEN_FLOAT_B(nabs, 0x08, 0x04);
 992 /* fneg */
 993 GEN_FLOAT_B(neg, 0x08, 0x01);
 994
 995 /***                  Floating-Point status & ctrl register                ***/
 996 /* mcrfs */
 997 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
 998 {
 999     if (!ctx->fpu_enabled) {
1000         RET_EXCP(ctx, EXCP_NO_FP, 0);
1001         return;
1002     }
1003     gen_op_load_fpscr_T0(crfS(ctx->opcode));
1004     gen_op_store_T0_crf(crfD(ctx->opcode));
1005     gen_op_clear_fpscr(crfS(ctx->opcode));
1006 }
1007
1008 /* mffs */
1009 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1010 {
1011     if (!ctx->fpu_enabled) {
1012         RET_EXCP(ctx, EXCP_NO_FP, 0);
1013         return;
1014     }
1015     gen_op_load_fpscr();
1016     gen_op_store_FT0_fpr(rD(ctx->opcode));
1017     if (Rc(ctx->opcode))
1018         gen_op_set_Rc1();
1019 }
1020
1021 /* mtfsb0 */
1022 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1023 {
1024     uint8_t crb;
1025
1026     if (!ctx->fpu_enabled) {
1027         RET_EXCP(ctx, EXCP_NO_FP, 0);
1028         return;
1029     }
1030     crb = crbD(ctx->opcode) >> 2;
1031     gen_op_load_fpscr_T0(crb);
1032     gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1033     gen_op_store_T0_fpscr(crb);
1034     if (Rc(ctx->opcode))
1035         gen_op_set_Rc1();
1036 }
1037
1038 /* mtfsb1 */
1039 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1040 {
1041     uint8_t crb;
1042
1043     if (!ctx->fpu_enabled) {
1044         RET_EXCP(ctx, EXCP_NO_FP, 0);
1045         return;
1046     }
1047     crb = crbD(ctx->opcode) >> 2;
1048     gen_op_load_fpscr_T0(crb);
1049     gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1050     gen_op_store_T0_fpscr(crb);
1051     if (Rc(ctx->opcode))
1052         gen_op_set_Rc1();
1053 }
1054
1055 /* mtfsf */
1056 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1057 {
1058     if (!ctx->fpu_enabled) {
1059         RET_EXCP(ctx, EXCP_NO_FP, 0);
1060         return;
1061     }
1062     gen_op_load_fpr_FT0(rB(ctx->opcode));
1063     gen_op_store_fpscr(FM(ctx->opcode));
1064     if (Rc(ctx->opcode))
1065         gen_op_set_Rc1();
1066 }
1067
1068 /* mtfsfi */
1069 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1070 {
1071     if (!ctx->fpu_enabled) {
1072         RET_EXCP(ctx, EXCP_NO_FP, 0);
1073         return;
1074     }
1075     gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1076     if (Rc(ctx->opcode))
1077         gen_op_set_Rc1();
1078 }
1079
1080 /***                             Integer load                              ***/
1081 #define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
1082 #if defined(CONFIG_USER_ONLY)
1083 #define OP_LD_TABLE(width)                                                    \
1084 static GenOpFunc *gen_op_l##width[] = {                                       \
1085     &gen_op_l##width##_raw,                                                   \
1086     &gen_op_l##width##_le_raw,                                                \
1087 };
1088 #define OP_ST_TABLE(width)                                                    \
1089 static GenOpFunc *gen_op_st##width[] = {                                      \
1090     &gen_op_st##width##_raw,                                                  \
1091     &gen_op_st##width##_le_raw,                                               \
1092 };
1093 /* Byte access routine are endian safe */
1094 #define gen_op_stb_le_raw gen_op_stb_raw
1095 #define gen_op_lbz_le_raw gen_op_lbz_raw
1096 #else
1097 #define OP_LD_TABLE(width)                                                    \
1098 static GenOpFunc *gen_op_l##width[] = {                                       \
1099     &gen_op_l##width##_user,                                                  \
1100     &gen_op_l##width##_le_user,                                               \
1101     &gen_op_l##width##_kernel,                                                \
1102     &gen_op_l##width##_le_kernel,                                             \
1103 };
1104 #define OP_ST_TABLE(width)                                                    \
1105 static GenOpFunc *gen_op_st##width[] = {                                      \
1106     &gen_op_st##width##_user,                                                 \
1107     &gen_op_st##width##_le_user,                                              \
1108     &gen_op_st##width##_kernel,                                               \
1109     &gen_op_st##width##_le_kernel,                                            \
1110 };
1111 /* Byte access routine are endian safe */
1112 #define gen_op_stb_le_user gen_op_stb_user
1113 #define gen_op_lbz_le_user gen_op_lbz_user
1114 #define gen_op_stb_le_kernel gen_op_stb_kernel
1115 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
1116 #endif
1117
1118 #define GEN_LD(width, opc)                                                    \
1119 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)               \
1120 {                                                                             \
1121     uint32_t simm = SIMM(ctx->opcode);                                        \
1122     if (rA(ctx->opcode) == 0) {                                               \
1123         gen_op_set_T0(simm);                                                  \
1124     } else {                                                                  \
1125         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1126         if (simm != 0)                                                        \
1127             gen_op_addi(simm);                                                \
1128     }                                                                         \
1129     op_ldst(l##width);                                                        \
1130     gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1131 }
1132
1133 #define GEN_LDU(width, opc)                                                   \
1134 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)            \
1135 {                                                                             \
1136     uint32_t simm = SIMM(ctx->opcode);                                        \
1137     if (rA(ctx->opcode) == 0 ||                                               \
1138         rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1139         RET_INVAL(ctx);                                                       \
1140         return;                                                               \
1141     }                                                                         \
1142     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1143     if (simm != 0)                                                            \
1144         gen_op_addi(simm);                                                    \
1145     op_ldst(l##width);                                                        \
1146     gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1147     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1148 }
1149
1150 #define GEN_LDUX(width, opc)                                                  \
1151 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)           \
1152 {                                                                             \
1153     if (rA(ctx->opcode) == 0 ||                                               \
1154         rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1155         RET_INVAL(ctx);                                                       \
1156         return;                                                               \
1157     }                                                                         \
1158     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1159     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1160     gen_op_add();                                                             \
1161     op_ldst(l##width);                                                        \
1162     gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1163     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1164 }
1165
1166 #define GEN_LDX(width, opc2, opc3)                                            \
1167 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)           \
1168 {                                                                             \
1169     if (rA(ctx->opcode) == 0) {                                               \
1170         gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1171     } else {                                                                  \
1172         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1173         gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1174         gen_op_add();                                                         \
1175     }                                                                         \
1176     op_ldst(l##width);                                                        \
1177     gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
1178 }
1179
1180 #define GEN_LDS(width, op)                                                    \
1181 OP_LD_TABLE(width);                                                           \
1182 GEN_LD(width, op | 0x20);                                                     \
1183 GEN_LDU(width, op | 0x21);                                                    \
1184 GEN_LDUX(width, op | 0x01);                                                   \
1185 GEN_LDX(width, 0x17, op | 0x00)
1186
1187 /* lbz lbzu lbzux lbzx */
1188 GEN_LDS(bz, 0x02);
1189 /* lha lhau lhaux lhax */
1190 GEN_LDS(ha, 0x0A);
1191 /* lhz lhzu lhzux lhzx */
1192 GEN_LDS(hz, 0x08);
1193 /* lwz lwzu lwzux lwzx */
1194 GEN_LDS(wz, 0x00);
1195
1196 /***                              Integer store                            ***/
1197 #define GEN_ST(width, opc)                                                    \
1198 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)              \
1199 {                                                                             \
1200     uint32_t simm = SIMM(ctx->opcode);                                        \
1201     if (rA(ctx->opcode) == 0) {                                               \
1202         gen_op_set_T0(simm);                                                  \
1203     } else {                                                                  \
1204         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1205         if (simm != 0)                                                        \
1206             gen_op_addi(simm);                                                \
1207     }                                                                         \
1208     gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1209     op_ldst(st##width);                                                       \
1210 }
1211
1212 #define GEN_STU(width, opc)                                                   \
1213 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)           \
1214 {                                                                             \
1215     uint32_t simm = SIMM(ctx->opcode);                                        \
1216     if (rA(ctx->opcode) == 0) {                                               \
1217         RET_INVAL(ctx);                                                       \
1218         return;                                                               \
1219     }                                                                         \
1220     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1221     if (simm != 0)                                                            \
1222         gen_op_addi(simm);                                                    \
1223     gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1224     op_ldst(st##width);                                                       \
1225     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1226 }
1227
1228 #define GEN_STUX(width, opc)                                                  \
1229 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER)          \
1230 {                                                                             \
1231     if (rA(ctx->opcode) == 0) {                                               \
1232         RET_INVAL(ctx);                                                       \
1233         return;                                                               \
1234     }                                                                         \
1235     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1236     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1237     gen_op_add();                                                             \
1238     gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1239     op_ldst(st##width);                                                       \
1240     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1241 }
1242
1243 #define GEN_STX(width, opc2, opc3)                                            \
1244 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER)          \
1245 {                                                                             \
1246     if (rA(ctx->opcode) == 0) {                                               \
1247         gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1248     } else {                                                                  \
1249         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1250         gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1251         gen_op_add();                                                         \
1252     }                                                                         \
1253     gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
1254     op_ldst(st##width);                                                       \
1255 }
1256
1257 #define GEN_STS(width, op)                                                    \
1258 OP_ST_TABLE(width);                                                           \
1259 GEN_ST(width, op | 0x20);                                                     \
1260 GEN_STU(width, op | 0x21);                                                    \
1261 GEN_STUX(width, op | 0x01);                                                   \
1262 GEN_STX(width, 0x17, op | 0x00)
1263
1264 /* stb stbu stbux stbx */
1265 GEN_STS(b, 0x06);
1266 /* sth sthu sthux sthx */
1267 GEN_STS(h, 0x0C);
1268 /* stw stwu stwux stwx */
1269 GEN_STS(w, 0x04);
1270
1271 /***                Integer load and store with byte reverse               ***/
1272 /* lhbrx */
1273 OP_LD_TABLE(hbr);
1274 GEN_LDX(hbr, 0x16, 0x18);
1275 /* lwbrx */
1276 OP_LD_TABLE(wbr);
1277 GEN_LDX(wbr, 0x16, 0x10);
1278 /* sthbrx */
1279 OP_ST_TABLE(hbr);
1280 GEN_STX(hbr, 0x16, 0x1C);
1281 /* stwbrx */
1282 OP_ST_TABLE(wbr);
1283 GEN_STX(wbr, 0x16, 0x14);
1284
1285 /***                    Integer load and store multiple                    ***/
1286 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1287 #if defined(CONFIG_USER_ONLY)
1288 static GenOpFunc1 *gen_op_lmw[] = {
1289     &gen_op_lmw_raw,
1290     &gen_op_lmw_le_raw,
1291 };
1292 static GenOpFunc1 *gen_op_stmw[] = {
1293     &gen_op_stmw_raw,
1294     &gen_op_stmw_le_raw,
1295 };
1296 #else
1297 static GenOpFunc1 *gen_op_lmw[] = {
1298     &gen_op_lmw_user,
1299     &gen_op_lmw_le_user,
1300     &gen_op_lmw_kernel,
1301     &gen_op_lmw_le_kernel,
1302 };
1303 static GenOpFunc1 *gen_op_stmw[] = {
1304     &gen_op_stmw_user,
1305     &gen_op_stmw_le_user,
1306     &gen_op_stmw_kernel,
1307     &gen_op_stmw_le_kernel,
1308 };
1309 #endif
1310
1311 /* lmw */
1312 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1313 {
1314     int simm = SIMM(ctx->opcode);
1315
1316     if (rA(ctx->opcode) == 0) {
1317         gen_op_set_T0(simm);
1318     } else {
1319         gen_op_load_gpr_T0(rA(ctx->opcode));
1320         if (simm != 0)
1321             gen_op_addi(simm);
1322     }
1323     op_ldstm(lmw, rD(ctx->opcode));
1324 }
1325
1326 /* stmw */
1327 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1328 {
1329     int simm = SIMM(ctx->opcode);
1330
1331     if (rA(ctx->opcode) == 0) {
1332         gen_op_set_T0(simm);
1333     } else {
1334         gen_op_load_gpr_T0(rA(ctx->opcode));
1335         if (simm != 0)
1336             gen_op_addi(simm);
1337     }
1338     op_ldstm(stmw, rS(ctx->opcode));
1339 }
1340
1341 /***                    Integer load and store strings                     ***/
1342 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1343 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1344 #if defined(CONFIG_USER_ONLY)
1345 static GenOpFunc1 *gen_op_lswi[] = {
1346     &gen_op_lswi_raw,
1347     &gen_op_lswi_le_raw,
1348 };
1349 static GenOpFunc3 *gen_op_lswx[] = {
1350     &gen_op_lswx_raw,
1351     &gen_op_lswx_le_raw,
1352 };
1353 static GenOpFunc1 *gen_op_stsw[] = {
1354     &gen_op_stsw_raw,
1355     &gen_op_stsw_le_raw,
1356 };
1357 #else
1358 static GenOpFunc1 *gen_op_lswi[] = {
1359     &gen_op_lswi_user,
1360     &gen_op_lswi_le_user,
1361     &gen_op_lswi_kernel,
1362     &gen_op_lswi_le_kernel,
1363 };
1364 static GenOpFunc3 *gen_op_lswx[] = {
1365     &gen_op_lswx_user,
1366     &gen_op_lswx_le_user,
1367     &gen_op_lswx_kernel,
1368     &gen_op_lswx_le_kernel,
1369 };
1370 static GenOpFunc1 *gen_op_stsw[] = {
1371     &gen_op_stsw_user,
1372     &gen_op_stsw_le_user,
1373     &gen_op_stsw_kernel,
1374     &gen_op_stsw_le_kernel,
1375 };
1376 #endif
1377
1378 /* lswi */
1379 /* PowerPC32 specification says we must generate an exception if
1380  * rA is in the range of registers to be loaded.
1381  * In an other hand, IBM says this is valid, but rA won't be loaded.
1382  * For now, I'll follow the spec...
1383  */
1384 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1385 {
1386     int nb = NB(ctx->opcode);
1387     int start = rD(ctx->opcode);
1388     int ra = rA(ctx->opcode);
1389     int nr;
1390
1391     if (nb == 0)
1392         nb = 32;
1393     nr = nb / 4;
1394     if (((start + nr) > 32  && start <= ra && (start + nr - 32) > ra) ||
1395         ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1396         RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1397         return;
1398     }
1399     if (ra == 0) {
1400         gen_op_set_T0(0);
1401     } else {
1402         gen_op_load_gpr_T0(ra);
1403     }
1404     gen_op_set_T1(nb);
1405     /* NIP cannot be restored if the memory exception comes from an helper */
1406     gen_op_update_nip((ctx)->nip - 4);
1407     op_ldsts(lswi, start);
1408 }
1409
1410 /* lswx */
1411 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1412 {
1413     int ra = rA(ctx->opcode);
1414     int rb = rB(ctx->opcode);
1415
1416     if (ra == 0) {
1417         gen_op_load_gpr_T0(rb);
1418         ra = rb;
1419     } else {
1420         gen_op_load_gpr_T0(ra);
1421         gen_op_load_gpr_T1(rb);
1422         gen_op_add();
1423     }
1424     gen_op_load_xer_bc();
1425     /* NIP cannot be restored if the memory exception comes from an helper */
1426     gen_op_update_nip((ctx)->nip - 4);
1427     op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1428 }
1429
1430 /* stswi */
1431 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1432 {
1433     int nb = NB(ctx->opcode);
1434
1435     if (rA(ctx->opcode) == 0) {
1436         gen_op_set_T0(0);
1437     } else {
1438         gen_op_load_gpr_T0(rA(ctx->opcode));
1439     }
1440     if (nb == 0)
1441         nb = 32;
1442     gen_op_set_T1(nb);
1443     /* NIP cannot be restored if the memory exception comes from an helper */
1444     gen_op_update_nip((ctx)->nip - 4);
1445     op_ldsts(stsw, rS(ctx->opcode));
1446 }
1447
1448 /* stswx */
1449 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1450 {
1451     int ra = rA(ctx->opcode);
1452
1453     if (ra == 0) {
1454         gen_op_load_gpr_T0(rB(ctx->opcode));
1455         ra = rB(ctx->opcode);
1456     } else {
1457         gen_op_load_gpr_T0(ra);
1458         gen_op_load_gpr_T1(rB(ctx->opcode));
1459         gen_op_add();
1460     }
1461     gen_op_load_xer_bc();
1462     /* NIP cannot be restored if the memory exception comes from an helper */
1463     gen_op_update_nip((ctx)->nip - 4);
1464     op_ldsts(stsw, rS(ctx->opcode));
1465 }
1466
1467 /***                        Memory synchronisation                         ***/
1468 /* eieio */
1469 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1470 {
1471 }
1472
1473 /* isync */
1474 GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1475 {
1476 }
1477
1478 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1479 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1480 #if defined(CONFIG_USER_ONLY)
1481 static GenOpFunc *gen_op_lwarx[] = {
1482     &gen_op_lwarx_raw,
1483     &gen_op_lwarx_le_raw,
1484 };
1485 static GenOpFunc *gen_op_stwcx[] = {
1486     &gen_op_stwcx_raw,
1487     &gen_op_stwcx_le_raw,
1488 };
1489 #else
1490 static GenOpFunc *gen_op_lwarx[] = {
1491     &gen_op_lwarx_user,
1492     &gen_op_lwarx_le_user,
1493     &gen_op_lwarx_kernel,
1494     &gen_op_lwarx_le_kernel,
1495 };
1496 static GenOpFunc *gen_op_stwcx[] = {
1497     &gen_op_stwcx_user,
1498     &gen_op_stwcx_le_user,
1499     &gen_op_stwcx_kernel,
1500     &gen_op_stwcx_le_kernel,
1501 };
1502 #endif
1503
1504 /* lwarx */
1505 GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1506 {
1507     if (rA(ctx->opcode) == 0) {
1508         gen_op_load_gpr_T0(rB(ctx->opcode));
1509     } else {
1510         gen_op_load_gpr_T0(rA(ctx->opcode));
1511         gen_op_load_gpr_T1(rB(ctx->opcode));
1512         gen_op_add();
1513     }
1514     op_lwarx();
1515     gen_op_store_T1_gpr(rD(ctx->opcode));
1516 }
1517
1518 /* stwcx. */
1519 GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1520 {
1521         if (rA(ctx->opcode) == 0) {
1522             gen_op_load_gpr_T0(rB(ctx->opcode));
1523         } else {
1524             gen_op_load_gpr_T0(rA(ctx->opcode));
1525             gen_op_load_gpr_T1(rB(ctx->opcode));
1526         gen_op_add();
1527         }
1528     gen_op_load_gpr_T1(rS(ctx->opcode));
1529     op_stwcx();
1530 }
1531
1532 /* sync */
1533 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1534 {
1535 }
1536
1537 /***                         Floating-point load                           ***/
1538 #define GEN_LDF(width, opc)                                                   \
1539 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                 \
1540 {                                                                             \
1541     uint32_t simm = SIMM(ctx->opcode);                                        \
1542     if (!ctx->fpu_enabled) {                                                  \
1543         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1544         return;                                                               \
1545     }                                                                         \
1546     if (rA(ctx->opcode) == 0) {                                               \
1547         gen_op_set_T0(simm);                                                  \
1548     } else {                                                                  \
1549         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1550         if (simm != 0)                                                        \
1551             gen_op_addi(simm);                                                \
1552     }                                                                         \
1553     op_ldst(l##width);                                                        \
1554     gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1555 }
1556
1557 #define GEN_LDUF(width, opc)                                                  \
1558 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)              \
1559 {                                                                             \
1560     uint32_t simm = SIMM(ctx->opcode);                                        \
1561     if (!ctx->fpu_enabled) {                                                  \
1562         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1563         return;                                                               \
1564     }                                                                         \
1565     if (rA(ctx->opcode) == 0 ||                                               \
1566         rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1567         RET_INVAL(ctx);                                                       \
1568         return;                                                               \
1569     }                                                                         \
1570     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1571     if (simm != 0)                                                            \
1572         gen_op_addi(simm);                                                    \
1573     op_ldst(l##width);                                                        \
1574     gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1575     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1576 }
1577
1578 #define GEN_LDUXF(width, opc)                                                 \
1579 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)             \
1580 {                                                                             \
1581     if (!ctx->fpu_enabled) {                                                  \
1582         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1583         return;                                                               \
1584     }                                                                         \
1585     if (rA(ctx->opcode) == 0 ||                                               \
1586         rA(ctx->opcode) == rD(ctx->opcode)) {                                 \
1587         RET_INVAL(ctx);                                                       \
1588         return;                                                               \
1589     }                                                                         \
1590     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1591     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1592     gen_op_add();                                                             \
1593     op_ldst(l##width);                                                        \
1594     gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1595     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1596 }
1597
1598 #define GEN_LDXF(width, opc2, opc3)                                           \
1599 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)             \
1600 {                                                                             \
1601     if (!ctx->fpu_enabled) {                                                  \
1602         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1603         return;                                                               \
1604     }                                                                         \
1605     if (rA(ctx->opcode) == 0) {                                               \
1606         gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1607     } else {                                                                  \
1608         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1609         gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1610         gen_op_add();                                                         \
1611     }                                                                         \
1612     op_ldst(l##width);                                                        \
1613     gen_op_store_FT1_fpr(rD(ctx->opcode));                                    \
1614 }
1615
1616 #define GEN_LDFS(width, op)                                                   \
1617 OP_LD_TABLE(width);                                                           \
1618 GEN_LDF(width, op | 0x20);                                                    \
1619 GEN_LDUF(width, op | 0x21);                                                   \
1620 GEN_LDUXF(width, op | 0x01);                                                  \
1621 GEN_LDXF(width, 0x17, op | 0x00)
1622
1623 /* lfd lfdu lfdux lfdx */
1624 GEN_LDFS(fd, 0x12);
1625 /* lfs lfsu lfsux lfsx */
1626 GEN_LDFS(fs, 0x10);
1627
1628 /***                         Floating-point store                          ***/
1629 #define GEN_STF(width, opc)                                                   \
1630 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                \
1631 {                                                                             \
1632     uint32_t simm = SIMM(ctx->opcode);                                        \
1633     if (!ctx->fpu_enabled) {                                                  \
1634         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1635         return;                                                               \
1636     }                                                                         \
1637     if (rA(ctx->opcode) == 0) {                                               \
1638         gen_op_set_T0(simm);                                                  \
1639     } else {                                                                  \
1640         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1641         if (simm != 0)                                                        \
1642             gen_op_addi(simm);                                                \
1643     }                                                                         \
1644     gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1645     op_ldst(st##width);                                                       \
1646 }
1647
1648 #define GEN_STUF(width, opc)                                                  \
1649 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)             \
1650 {                                                                             \
1651     uint32_t simm = SIMM(ctx->opcode);                                        \
1652     if (!ctx->fpu_enabled) {                                                  \
1653         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1654         return;                                                               \
1655     }                                                                         \
1656     if (rA(ctx->opcode) == 0) {                                               \
1657         RET_INVAL(ctx);                                                       \
1658         return;                                                               \
1659     }                                                                         \
1660     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1661     if (simm != 0)                                                            \
1662         gen_op_addi(simm);                                                    \
1663     gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1664     op_ldst(st##width);                                                       \
1665     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1666 }
1667
1668 #define GEN_STUXF(width, opc)                                                 \
1669 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)            \
1670 {                                                                             \
1671     if (!ctx->fpu_enabled) {                                                  \
1672         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1673         return;                                                               \
1674     }                                                                         \
1675     if (rA(ctx->opcode) == 0) {                                               \
1676         RET_INVAL(ctx);                                                       \
1677         return;                                                               \
1678     }                                                                         \
1679     gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1680     gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1681     gen_op_add();                                                             \
1682     gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1683     op_ldst(st##width);                                                       \
1684     gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1685 }
1686
1687 #define GEN_STXF(width, opc2, opc3)                                           \
1688 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)            \
1689 {                                                                             \
1690     if (!ctx->fpu_enabled) {                                                  \
1691         RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1692         return;                                                               \
1693     }                                                                         \
1694     if (rA(ctx->opcode) == 0) {                                               \
1695         gen_op_load_gpr_T0(rB(ctx->opcode));                                  \
1696     } else {                                                                  \
1697         gen_op_load_gpr_T0(rA(ctx->opcode));                                  \
1698         gen_op_load_gpr_T1(rB(ctx->opcode));                                  \
1699         gen_op_add();                                                         \
1700     }                                                                         \
1701     gen_op_load_fpr_FT1(rS(ctx->opcode));                                     \
1702     op_ldst(st##width);                                                       \
1703 }
1704
1705 #define GEN_STFS(width, op)                                                   \
1706 OP_ST_TABLE(width);                                                           \
1707 GEN_STF(width, op | 0x20);                                                    \
1708 GEN_STUF(width, op | 0x21);                                                   \
1709 GEN_STUXF(width, op | 0x01);                                                  \
1710 GEN_STXF(width, 0x17, op | 0x00)
1711
1712 /* stfd stfdu stfdux stfdx */
1713 GEN_STFS(fd, 0x16);
1714 /* stfs stfsu stfsux stfsx */
1715 GEN_STFS(fs, 0x14);
1716
1717 /* Optional: */
1718 /* stfiwx */
1719 GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1720 {
1721     if (!ctx->fpu_enabled) {
1722         RET_EXCP(ctx, EXCP_NO_FP, 0);
1723         return;
1724     }
1725     RET_INVAL(ctx);
1726 }
1727
1728 /***                                Branch                                 ***/
1729
1730 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1731 {
1732     TranslationBlock *tb;
1733     tb = ctx->tb;
1734     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1735         if (n == 0)
1736             gen_op_goto_tb0(TBPARAM(tb));
1737         else
1738             gen_op_goto_tb1(TBPARAM(tb));
1739         gen_op_set_T1(dest);
1740         gen_op_b_T1();
1741         gen_op_set_T0((long)tb + n);
1742         gen_op_exit_tb();
1743     } else {
1744         gen_op_set_T1(dest);
1745         gen_op_b_T1();
1746         gen_op_set_T0(0);
1747         gen_op_exit_tb();
1748     }
1749 }
1750
1751 /* b ba bl bla */
1752 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1753 {
1754     uint32_t li, target;
1755
1756     /* sign extend LI */
1757     li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1758
1759     if (AA(ctx->opcode) == 0)
1760         target = ctx->nip + li - 4;
1761     else
1762         target = li;
1763     if (LK(ctx->opcode)) {
1764         gen_op_setlr(ctx->nip);
1765     }
1766     gen_goto_tb(ctx, 0, target);
1767     ctx->exception = EXCP_BRANCH;
1768 }
1769
1770 #define BCOND_IM  0
1771 #define BCOND_LR  1
1772 #define BCOND_CTR 2
1773
1774 static inline void gen_bcond(DisasContext *ctx, int type)
1775 {
1776     uint32_t target = 0;
1777     uint32_t bo = BO(ctx->opcode);
1778     uint32_t bi = BI(ctx->opcode);
1779     uint32_t mask;
1780     uint32_t li;
1781
1782     if ((bo & 0x4) == 0)
1783         gen_op_dec_ctr();
1784     switch(type) {
1785     case BCOND_IM:
1786         li = (int32_t)((int16_t)(BD(ctx->opcode)));
1787         if (AA(ctx->opcode) == 0) {
1788             target = ctx->nip + li - 4;
1789         } else {
1790             target = li;
1791         }
1792         break;
1793     case BCOND_CTR:
1794         gen_op_movl_T1_ctr();
1795         break;
1796     default:
1797     case BCOND_LR:
1798         gen_op_movl_T1_lr();
1799         break;
1800     }
1801     if (LK(ctx->opcode)) {
1802         gen_op_setlr(ctx->nip);
1803     }
1804     if (bo & 0x10) {
1805         /* No CR condition */
1806         switch (bo & 0x6) {
1807         case 0:
1808             gen_op_test_ctr();
1809             break;
1810         case 2:
1811             gen_op_test_ctrz();
1812             break;
1813         default:
1814         case 4:
1815         case 6:
1816             if (type == BCOND_IM) {
1817                 gen_goto_tb(ctx, 0, target);
1818             } else {
1819                 gen_op_b_T1();
1820             }
1821             goto no_test;
1822         }
1823     } else {
1824         mask = 1 << (3 - (bi & 0x03));
1825         gen_op_load_crf_T0(bi >> 2);
1826         if (bo & 0x8) {
1827             switch (bo & 0x6) {
1828             case 0:
1829                 gen_op_test_ctr_true(mask);
1830                 break;
1831             case 2:
1832                 gen_op_test_ctrz_true(mask);
1833                 break;
1834             default:
1835             case 4:
1836             case 6:
1837                 gen_op_test_true(mask);
1838                 break;
1839             }
1840         } else {
1841             switch (bo & 0x6) {
1842             case 0:
1843                 gen_op_test_ctr_false(mask);
1844                 break;
1845             case 2:
1846                 gen_op_test_ctrz_false(mask);
1847                 break;
1848             default:
1849             case 4:
1850             case 6:
1851                 gen_op_test_false(mask);
1852                 break;
1853             }
1854         }
1855     }
1856     if (type == BCOND_IM) {
1857         int l1 = gen_new_label();
1858         gen_op_jz_T0(l1);
1859         gen_goto_tb(ctx, 0, target);
1860         gen_set_label(l1);
1861         gen_goto_tb(ctx, 1, ctx->nip);
1862     } else {
1863         gen_op_btest_T1(ctx->nip);
1864     }
1865  no_test:
1866     ctx->exception = EXCP_BRANCH;
1867 }
1868
1869 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1870 {
1871     gen_bcond(ctx, BCOND_IM);
1872 }
1873
1874 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1875 {
1876     gen_bcond(ctx, BCOND_CTR);
1877 }
1878
1879 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1880 {
1881     gen_bcond(ctx, BCOND_LR);
1882 }
1883
1884 /***                      Condition register logical                       ***/
1885 #define GEN_CRLOGIC(op, opc)                                                  \
1886 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
1887 {                                                                             \
1888     gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
1889     gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03));                         \
1890     gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
1891     gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03));                         \
1892     gen_op_##op();                                                            \
1893     gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
1894     gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))),                \
1895                      3 - (crbD(ctx->opcode) & 0x03));                         \
1896     gen_op_store_T1_crf(crbD(ctx->opcode) >> 2);                              \
1897 }
1898
1899 /* crand */
1900 GEN_CRLOGIC(and, 0x08)
1901 /* crandc */
1902 GEN_CRLOGIC(andc, 0x04)
1903 /* creqv */
1904 GEN_CRLOGIC(eqv, 0x09)
1905 /* crnand */
1906 GEN_CRLOGIC(nand, 0x07)
1907 /* crnor */
1908 GEN_CRLOGIC(nor, 0x01)
1909 /* cror */
1910 GEN_CRLOGIC(or, 0x0E)
1911 /* crorc */
1912 GEN_CRLOGIC(orc, 0x0D)
1913 /* crxor */
1914 GEN_CRLOGIC(xor, 0x06)
1915 /* mcrf */
1916 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1917 {
1918     gen_op_load_crf_T0(crfS(ctx->opcode));
1919     gen_op_store_T0_crf(crfD(ctx->opcode));
1920 }
1921
1922 /***                           System linkage                              ***/
1923 /* rfi (supervisor only) */
1924 GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1925 {
1926 #if defined(CONFIG_USER_ONLY)
1927     RET_PRIVOPC(ctx);
1928 #else
1929     /* Restore CPU state */
1930     if (!ctx->supervisor) {
1931         RET_PRIVOPC(ctx);
1932         return;
1933     }
1934     gen_op_rfi();
1935     RET_CHG_FLOW(ctx);
1936 #endif
1937 }
1938
1939 /* sc */
1940 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1941 {
1942 #if defined(CONFIG_USER_ONLY)
1943     RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1944 #else
1945     RET_EXCP(ctx, EXCP_SYSCALL, 0);
1946 #endif
1947 }
1948
1949 /***                                Trap                                   ***/
1950 /* tw */
1951 GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1952 {
1953     gen_op_load_gpr_T0(rA(ctx->opcode));
1954     gen_op_load_gpr_T1(rB(ctx->opcode));
1955     gen_op_tw(TO(ctx->opcode));
1956 }
1957
1958 /* twi */
1959 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1960 {
1961     gen_op_load_gpr_T0(rA(ctx->opcode));
1962 #if 0
1963     printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1964            SIMM(ctx->opcode), TO(ctx->opcode));
1965 #endif
1966     gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1967 }
1968
1969 /***                          Processor control                            ***/
1970 static inline int check_spr_access (int spr, int rw, int supervisor)
1971 {
1972     uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1973
1974 #if 0
1975     if (spr != LR && spr != CTR) {
1976     if (loglevel > 0) {
1977         fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1978                 SPR_ENCODE(spr), supervisor, rw, rights,
1979                 (rights >> ((2 * supervisor) + rw)) & 1);
1980     } else {
1981         printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1982                SPR_ENCODE(spr), supervisor, rw, rights,
1983                (rights >> ((2 * supervisor) + rw)) & 1);
1984     }
1985     }
1986 #endif
1987     if (rights == 0)
1988         return -1;
1989     rights = rights >> (2 * supervisor);
1990     rights = rights >> rw;
1991
1992     return rights & 1;
1993 }
1994
1995 /* mcrxr */
1996 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1997 {
1998     gen_op_load_xer_cr();
1999     gen_op_store_T0_crf(crfD(ctx->opcode));
2000     gen_op_clear_xer_cr();
2001 }
2002
2003 /* mfcr */
2004 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
2005 {
2006     gen_op_load_cr();
2007     gen_op_store_T0_gpr(rD(ctx->opcode));
2008 }
2009
2010 /* mfmsr */
2011 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
2012 {
2013 #if defined(CONFIG_USER_ONLY)
2014     RET_PRIVREG(ctx);
2015 #else
2016     if (!ctx->supervisor) {
2017         RET_PRIVREG(ctx);
2018         return;
2019     }
2020     gen_op_load_msr();
2021     gen_op_store_T0_gpr(rD(ctx->opcode));
2022 #endif
2023 }
2024
2025 #if 0
2026 #define SPR_NOACCESS ((void *)(-1))
2027 #else
2028 static void spr_noaccess (void *opaque, int sprn)
2029 {
2030     sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
2031     printf("ERROR: try to access SPR %d !\n", sprn);
2032 }
2033 #define SPR_NOACCESS (&spr_noaccess)
2034 #endif
2035
2036 /* mfspr */
2037 static inline void gen_op_mfspr (DisasContext *ctx)
2038 {
2039     void (*read_cb)(void *opaque, int sprn);
2040     uint32_t sprn = SPR(ctx->opcode);
2041
2042 #if !defined(CONFIG_USER_ONLY)
2043     if (ctx->supervisor)
2044         read_cb = ctx->spr_cb[sprn].oea_read;
2045     else
2046 #endif
2047         read_cb = ctx->spr_cb[sprn].uea_read;
2048     if (read_cb != NULL) {
2049         if (read_cb != SPR_NOACCESS) {
2050             (*read_cb)(ctx, sprn);
2051             gen_op_store_T0_gpr(rD(ctx->opcode));
2052         } else {
2053             /* Privilege exception */
2054             printf("Trying to read priviledged spr %d %03x\n", sprn, sprn);
2055         RET_PRIVREG(ctx);
2056         }
2057     } else {
2058         /* Not defined */
2059         printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
2060         RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2061     }
2062 }
2063
2064 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
2065 {
2066     gen_op_mfspr(ctx);
2067     }
2068
2069 /* mftb */
2070 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB)
2071 {
2072     gen_op_mfspr(ctx);
2073 }
2074
2075 /* mtcrf */
2076 /* The mask should be 0x00100801, but Mac OS X 10.4 use an alternate form */
2077 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
2078 {
2079     gen_op_load_gpr_T0(rS(ctx->opcode));
2080     gen_op_store_cr(CRM(ctx->opcode));
2081 }
2082
2083 /* mtmsr */
2084 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2085 {
2086 #if defined(CONFIG_USER_ONLY)
2087     RET_PRIVREG(ctx);
2088 #else
2089     if (!ctx->supervisor) {
2090         RET_PRIVREG(ctx);
2091         return;
2092     }
2093     gen_op_load_gpr_T0(rS(ctx->opcode));
2094     gen_op_store_msr();
2095     /* Must stop the translation as machine state (may have) changed */
2096     RET_MTMSR(ctx);
2097 #endif
2098 }
2099
2100 /* mtspr */
2101 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2102 {
2103     void (*write_cb)(void *opaque, int sprn);
2104     uint32_t sprn = SPR(ctx->opcode);
2105
2106 #if !defined(CONFIG_USER_ONLY)
2107     if (ctx->supervisor)
2108         write_cb = ctx->spr_cb[sprn].oea_write;
2109     else
2110 #endif
2111         write_cb = ctx->spr_cb[sprn].uea_write;
2112     if (write_cb != NULL) {
2113         if (write_cb != SPR_NOACCESS) {
2114             gen_op_load_gpr_T0(rS(ctx->opcode));
2115             (*write_cb)(ctx, sprn);
2116         } else {
2117             /* Privilege exception */
2118             printf("Trying to write priviledged spr %d %03x\n", sprn, sprn);
2119         RET_PRIVREG(ctx);
2120     }
2121     } else {
2122         /* Not defined */
2123         printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
2124         RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2125     }
2126 }
2127
2128 /***                         Cache management                              ***/
2129 /* For now, all those will be implemented as nop:
2130  * this is valid, regarding the PowerPC specs...
2131  * We just have to flush tb while invalidating instruction cache lines...
2132  */
2133 /* dcbf */
2134 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2135 {
2136     if (rA(ctx->opcode) == 0) {
2137         gen_op_load_gpr_T0(rB(ctx->opcode));
2138     } else {
2139         gen_op_load_gpr_T0(rA(ctx->opcode));
2140         gen_op_load_gpr_T1(rB(ctx->opcode));
2141         gen_op_add();
2142     }
2143     op_ldst(lbz);
2144 }
2145
2146 /* dcbi (Supervisor only) */
2147 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2148 {
2149 #if defined(CONFIG_USER_ONLY)
2150     RET_PRIVOPC(ctx);
2151 #else
2152     if (!ctx->supervisor) {
2153         RET_PRIVOPC(ctx);
2154         return;
2155     }
2156     if (rA(ctx->opcode) == 0) {
2157         gen_op_load_gpr_T0(rB(ctx->opcode));
2158     } else {
2159         gen_op_load_gpr_T0(rA(ctx->opcode));
2160         gen_op_load_gpr_T1(rB(ctx->opcode));
2161         gen_op_add();
2162     }
2163     op_ldst(lbz);
2164     op_ldst(stb);
2165 #endif
2166 }
2167
2168 /* dcdst */
2169 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2170 {
2171     if (rA(ctx->opcode) == 0) {
2172         gen_op_load_gpr_T0(rB(ctx->opcode));
2173     } else {
2174         gen_op_load_gpr_T0(rA(ctx->opcode));
2175         gen_op_load_gpr_T1(rB(ctx->opcode));
2176         gen_op_add();
2177     }
2178     op_ldst(lbz);
2179 }
2180
2181 /* dcbt */
2182 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2183 {
2184 }
2185
2186 /* dcbtst */
2187 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2188 {
2189 }
2190
2191 /* dcbz */
2192 #if defined(CONFIG_USER_ONLY)
2193 #define op_dcbz() gen_op_dcbz_raw()
2194 #else
2195 #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2196 static GenOpFunc *gen_op_dcbz[] = {
2197     &gen_op_dcbz_user,
2198     &gen_op_dcbz_user,
2199     &gen_op_dcbz_kernel,
2200     &gen_op_dcbz_kernel,
2201 };
2202 #endif
2203
2204 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2205 {
2206     if (rA(ctx->opcode) == 0) {
2207         gen_op_load_gpr_T0(rB(ctx->opcode));
2208     } else {
2209         gen_op_load_gpr_T0(rA(ctx->opcode));
2210         gen_op_load_gpr_T1(rB(ctx->opcode));
2211         gen_op_add();
2212     }
2213     op_dcbz();
2214     gen_op_check_reservation();
2215 }
2216
2217 /* icbi */
2218 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2219 {
2220     if (rA(ctx->opcode) == 0) {
2221         gen_op_load_gpr_T0(rB(ctx->opcode));
2222     } else {
2223         gen_op_load_gpr_T0(rA(ctx->opcode));
2224         gen_op_load_gpr_T1(rB(ctx->opcode));
2225         gen_op_add();
2226     }
2227     gen_op_icbi();
2228 }
2229
2230 /* Optional: */
2231 /* dcba */
2232 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
2233 {
2234 }
2235
2236 /***                    Segment register manipulation                      ***/
2237 /* Supervisor only: */
2238 /* mfsr */
2239 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2240 {
2241 #if defined(CONFIG_USER_ONLY)
2242     RET_PRIVREG(ctx);
2243 #else
2244     if (!ctx->supervisor) {
2245         RET_PRIVREG(ctx);
2246         return;
2247     }
2248     gen_op_load_sr(SR(ctx->opcode));
2249     gen_op_store_T0_gpr(rD(ctx->opcode));
2250 #endif
2251 }
2252
2253 /* mfsrin */
2254 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2255 {
2256 #if defined(CONFIG_USER_ONLY)
2257     RET_PRIVREG(ctx);
2258 #else
2259     if (!ctx->supervisor) {
2260         RET_PRIVREG(ctx);
2261         return;
2262     }
2263     gen_op_load_gpr_T1(rB(ctx->opcode));
2264     gen_op_load_srin();
2265     gen_op_store_T0_gpr(rD(ctx->opcode));
2266 #endif
2267 }
2268
2269 /* mtsr */
2270 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2271 {
2272 #if defined(CONFIG_USER_ONLY)
2273     RET_PRIVREG(ctx);
2274 #else
2275     if (!ctx->supervisor) {
2276         RET_PRIVREG(ctx);
2277         return;
2278     }
2279     gen_op_load_gpr_T0(rS(ctx->opcode));
2280     gen_op_store_sr(SR(ctx->opcode));
2281     RET_MTMSR(ctx);
2282 #endif
2283 }
2284
2285 /* mtsrin */
2286 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2287 {
2288 #if defined(CONFIG_USER_ONLY)
2289     RET_PRIVREG(ctx);
2290 #else
2291     if (!ctx->supervisor) {
2292         RET_PRIVREG(ctx);
2293         return;
2294     }
2295     gen_op_load_gpr_T0(rS(ctx->opcode));
2296     gen_op_load_gpr_T1(rB(ctx->opcode));
2297     gen_op_store_srin();
2298     RET_MTMSR(ctx);
2299 #endif
2300 }
2301
2302 /***                      Lookaside buffer management                      ***/
2303 /* Optional & supervisor only: */
2304 /* tlbia */
2305 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
2306 {
2307 #if defined(CONFIG_USER_ONLY)
2308     RET_PRIVOPC(ctx);
2309 #else
2310     if (!ctx->supervisor) {
2311         if (loglevel)
2312             fprintf(logfile, "%s: ! supervisor\n", __func__);
2313         RET_PRIVOPC(ctx);
2314         return;
2315     }
2316     gen_op_tlbia();
2317     RET_MTMSR(ctx);
2318 #endif
2319 }
2320
2321 /* tlbie */
2322 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
2323 {
2324 #if defined(CONFIG_USER_ONLY)
2325     RET_PRIVOPC(ctx);
2326 #else
2327     if (!ctx->supervisor) {
2328         RET_PRIVOPC(ctx);
2329         return;
2330     }
2331     gen_op_load_gpr_T0(rB(ctx->opcode));
2332     gen_op_tlbie();
2333     RET_MTMSR(ctx);
2334 #endif
2335 }
2336
2337 /* tlbsync */
2338 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
2339 {
2340 #if defined(CONFIG_USER_ONLY)
2341     RET_PRIVOPC(ctx);
2342 #else
2343     if (!ctx->supervisor) {
2344         RET_PRIVOPC(ctx);
2345         return;
2346     }
2347     /* This has no effect: it should ensure that all previous
2348      * tlbie have completed
2349      */
2350     RET_MTMSR(ctx);
2351 #endif
2352 }
2353
2354 /***                              External control                         ***/
2355 /* Optional: */
2356 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2357 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2358 #if defined(CONFIG_USER_ONLY)
2359 static GenOpFunc *gen_op_eciwx[] = {
2360     &gen_op_eciwx_raw,
2361     &gen_op_eciwx_le_raw,
2362 };
2363 static GenOpFunc *gen_op_ecowx[] = {
2364     &gen_op_ecowx_raw,
2365     &gen_op_ecowx_le_raw,
2366 };
2367 #else
2368 static GenOpFunc *gen_op_eciwx[] = {
2369     &gen_op_eciwx_user,
2370     &gen_op_eciwx_le_user,
2371     &gen_op_eciwx_kernel,
2372     &gen_op_eciwx_le_kernel,
2373 };
2374 static GenOpFunc *gen_op_ecowx[] = {
2375     &gen_op_ecowx_user,
2376     &gen_op_ecowx_le_user,
2377     &gen_op_ecowx_kernel,
2378     &gen_op_ecowx_le_kernel,
2379 };
2380 #endif
2381
2382 /* eciwx */
2383 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2384 {
2385     /* Should check EAR[E] & alignment ! */
2386     if (rA(ctx->opcode) == 0) {
2387         gen_op_load_gpr_T0(rB(ctx->opcode));
2388     } else {
2389         gen_op_load_gpr_T0(rA(ctx->opcode));
2390         gen_op_load_gpr_T1(rB(ctx->opcode));
2391         gen_op_add();
2392     }
2393     op_eciwx();
2394     gen_op_store_T0_gpr(rD(ctx->opcode));
2395 }
2396
2397 /* ecowx */
2398 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2399 {
2400     /* Should check EAR[E] & alignment ! */
2401     if (rA(ctx->opcode) == 0) {
2402         gen_op_load_gpr_T0(rB(ctx->opcode));
2403     } else {
2404         gen_op_load_gpr_T0(rA(ctx->opcode));
2405         gen_op_load_gpr_T1(rB(ctx->opcode));
2406         gen_op_add();
2407     }
2408     gen_op_load_gpr_T2(rS(ctx->opcode));
2409     op_ecowx();
2410 }
2411
2412 /* End opcode list */
2413 GEN_OPCODE_MARK(end);
2414
2415 #include "translate_init.c"
2416
2417 /*****************************************************************************/
2418 /* Misc PowerPC helpers */
2419 void cpu_dump_state(CPUState *env, FILE *f,
2420                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2421                     int flags)
2422 {
2423 #if defined(TARGET_PPC64) || 1
2424 #define FILL ""
2425 #define REGX "%016llx"
2426 #define RGPL  4
2427 #define RFPL  4
2428 #else
2429 #define FILL "        "
2430 #define REGX "%08llx"
2431 #define RGPL  8
2432 #define RFPL  4
2433 #endif
2434
2435     int i;
2436
2437     cpu_fprintf(f, "NIP " REGX " LR " REGX " CTR " REGX "\n",
2438                 env->nip, env->lr, env->ctr);
2439     cpu_fprintf(f, "MSR " REGX FILL " XER %08x      TB %08x %08x DECR %08x\n",
2440                 do_load_msr(env), do_load_xer(env), cpu_ppc_load_tbu(env),
2441                 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
2442         for (i = 0; i < 32; i++) {
2443         if ((i & (RGPL - 1)) == 0)
2444             cpu_fprintf(f, "GPR%02d", i);
2445         cpu_fprintf(f, " " REGX, env->gpr[i]);
2446         if ((i & (RGPL - 1)) == (RGPL - 1))
2447             cpu_fprintf(f, "\n");
2448         }
2449     cpu_fprintf(f, "CR ");
2450         for (i = 0; i < 8; i++)
2451         cpu_fprintf(f, "%01x", env->crf[i]);
2452     cpu_fprintf(f, "  [");
2453         for (i = 0; i < 8; i++) {
2454             char a = '-';
2455             if (env->crf[i] & 0x08)
2456                 a = 'L';
2457             else if (env->crf[i] & 0x04)
2458                 a = 'G';
2459             else if (env->crf[i] & 0x02)
2460                 a = 'E';
2461         cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
2462         }
2463     cpu_fprintf(f, " ]             " FILL "RES " REGX "\n", env->reserve);
2464     for (i = 0; i < 32; i++) {
2465         if ((i & (RFPL - 1)) == 0)
2466             cpu_fprintf(f, "FPR%02d", i);
2467         cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
2468         if ((i & (RFPL - 1)) == (RFPL - 1))
2469             cpu_fprintf(f, "\n");
2470     }
2471     cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX "         " FILL FILL FILL
2472                 "SDR1 " REGX "\n",
2473                 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
2474
2475 #undef REGX
2476 #undef RGPL
2477 #undef RFPL
2478 #undef FILL
2479 }
2480
2481 /*****************************************************************************/
2482 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
2483                                     int search_pc)
2484 {
2485     DisasContext ctx, *ctxp = &ctx;
2486     opc_handler_t **table, *handler;
2487     target_ulong pc_start;
2488     uint16_t *gen_opc_end;
2489     int j, lj = -1;
2490
2491     pc_start = tb->pc;
2492     gen_opc_ptr = gen_opc_buf;
2493     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2494     gen_opparam_ptr = gen_opparam_buf;
2495     nb_gen_labels = 0;
2496     ctx.nip = pc_start;
2497     ctx.tb = tb;
2498     ctx.exception = EXCP_NONE;
2499     ctx.spr_cb = env->spr_cb;
2500 #if defined(CONFIG_USER_ONLY)
2501     ctx.mem_idx = msr_le;
2502 #else
2503     ctx.supervisor = 1 - msr_pr;
2504     ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le;
2505 #endif
2506     ctx.fpu_enabled = msr_fp;
2507 #if defined (DO_SINGLE_STEP) && 0
2508     /* Single step trace mode */
2509     msr_se = 1;
2510 #endif
2511     /* Set env in case of segfault during code fetch */
2512     while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
2513         if (search_pc) {
2514             j = gen_opc_ptr - gen_opc_buf;
2515             if (lj < j) {
2516                 lj++;
2517                 while (lj < j)
2518                     gen_opc_instr_start[lj++] = 0;
2519                 gen_opc_pc[lj] = ctx.nip;
2520                 gen_opc_instr_start[lj] = 1;
2521             }
2522         }
2523 #if defined PPC_DEBUG_DISAS
2524         if (loglevel & CPU_LOG_TB_IN_ASM) {
2525             fprintf(logfile, "----------------\n");
2526             fprintf(logfile, "nip=%08x super=%d ir=%d\n",
2527                     ctx.nip, 1 - msr_pr, msr_ir);
2528         }
2529 #endif
2530         ctx.opcode = ldl_code(ctx.nip);
2531         if (msr_le) {
2532             ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
2533                 ((ctx.opcode & 0x00FF0000) >> 8) |
2534                 ((ctx.opcode & 0x0000FF00) << 8) |
2535                 ((ctx.opcode & 0x000000FF) << 24);
2536         }
2537 #if defined PPC_DEBUG_DISAS
2538         if (loglevel & CPU_LOG_TB_IN_ASM) {
2539             fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
2540                     ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
2541                     opc3(ctx.opcode), msr_le ? "little" : "big");
2542         }
2543 #endif
2544         ctx.nip += 4;
2545         table = env->opcodes;
2546         handler = table[opc1(ctx.opcode)];
2547         if (is_indirect_opcode(handler)) {
2548             table = ind_table(handler);
2549             handler = table[opc2(ctx.opcode)];
2550             if (is_indirect_opcode(handler)) {
2551                 table = ind_table(handler);
2552                 handler = table[opc3(ctx.opcode)];
2553             }
2554         }
2555         /* Is opcode *REALLY* valid ? */
2556                 if (handler->handler == &gen_invalid) {
2557             if (loglevel > 0) {
2558                     fprintf(logfile, "invalid/unsupported opcode: "
2559                         "%02x - %02x - %02x (%08x) 0x%08x %d\n",
2560                             opc1(ctx.opcode), opc2(ctx.opcode),
2561                         opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2562             } else {
2563                 printf("invalid/unsupported opcode: "
2564                        "%02x - %02x - %02x (%08x) 0x%08x %d\n",
2565                        opc1(ctx.opcode), opc2(ctx.opcode),
2566                        opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2567             }
2568                 } else {
2569             if ((ctx.opcode & handler->inval) != 0) {
2570                 if (loglevel > 0) {
2571                     fprintf(logfile, "invalid bits: %08x for opcode: "
2572                             "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
2573                             ctx.opcode & handler->inval, opc1(ctx.opcode),
2574                             opc2(ctx.opcode), opc3(ctx.opcode),
2575                             ctx.opcode, ctx.nip - 4);
2576                 } else {
2577                     printf("invalid bits: %08x for opcode: "
2578                            "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
2579                             ctx.opcode & handler->inval, opc1(ctx.opcode),
2580                             opc2(ctx.opcode), opc3(ctx.opcode),
2581                            ctx.opcode, ctx.nip - 4);
2582             }
2583                 RET_INVAL(ctxp);
2584                 break;
2585             }
2586         }
2587         (*(handler->handler))(&ctx);
2588         /* Check trace mode exceptions */
2589         if ((msr_be && ctx.exception == EXCP_BRANCH) ||
2590             /* Check in single step trace mode
2591              * we need to stop except if:
2592              * - rfi, trap or syscall
2593              * - first instruction of an exception handler
2594              */
2595             (msr_se && (ctx.nip < 0x100 ||
2596                         ctx.nip > 0xF00 ||
2597                         (ctx.nip & 0xFC) != 0x04) &&
2598              ctx.exception != EXCP_SYSCALL &&
2599              ctx.exception != EXCP_SYSCALL_USER &&
2600              ctx.exception != EXCP_TRAP)) {
2601             RET_EXCP(ctxp, EXCP_TRACE, 0);
2602         }
2603         /* if we reach a page boundary, stop generation */
2604         if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
2605             break;
2606     }
2607 #if defined (DO_SINGLE_STEP)
2608         break;
2609 #endif
2610     }
2611     if (ctx.exception == EXCP_NONE) {
2612         gen_goto_tb(&ctx, 0, ctx.nip);
2613     } else if (ctx.exception != EXCP_BRANCH) {
2614         gen_op_set_T0(0);
2615     }
2616 #if 1
2617     /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
2618      *              do bad business and then qemu crashes !
2619      */
2620     gen_op_set_T0(0);
2621 #endif
2622     /* Generate the return instruction */
2623     gen_op_exit_tb();
2624     *gen_opc_ptr = INDEX_op_end;
2625     if (search_pc) {
2626         j = gen_opc_ptr - gen_opc_buf;
2627         lj++;
2628         while (lj <= j)
2629             gen_opc_instr_start[lj++] = 0;
2630         tb->size = 0;
2631 #if 0
2632         if (loglevel > 0) {
2633             page_dump(logfile);
2634         }
2635 #endif
2636     } else {
2637         tb->size = ctx.nip - pc_start;
2638     }
2639 #ifdef DEBUG_DISAS
2640     if (loglevel & CPU_LOG_TB_CPU) {
2641         fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
2642         cpu_dump_state(env, logfile, fprintf, 0);
2643     }
2644     if (loglevel & CPU_LOG_TB_IN_ASM) {
2645         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2646         target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
2647         fprintf(logfile, "\n");
2648     }
2649     if (loglevel & CPU_LOG_TB_OP) {
2650         fprintf(logfile, "OP:\n");
2651         dump_ops(gen_opc_buf, gen_opparam_buf);
2652         fprintf(logfile, "\n");
2653     }
2654 #endif
2655     return 0;
2656 }
2657
2658 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2659 {
2660     return gen_intermediate_code_internal(env, tb, 0);
2661 }
2662
2663 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2664 {
2665     return gen_intermediate_code_internal(env, tb, 1);
2666 }