2 * PPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 //#define DO_SINGLE_STEP
31 //#define PPC_DEBUG_DISAS
34 #define DEF(s, n, copy_size) INDEX_op_ ## s,
40 static uint16_t *gen_opc_ptr;
41 static uint32_t *gen_opparam_ptr;
45 #define GEN8(func, NAME) \
46 static GenOpFunc *NAME ## _table [8] = { \
47 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
50 static inline void func(int n) \
52 NAME ## _table[n](); \
55 #define GEN16(func, NAME) \
56 static GenOpFunc *NAME ## _table [16] = { \
57 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
62 static inline void func(int n) \
64 NAME ## _table[n](); \
67 #define GEN32(func, NAME) \
68 static GenOpFunc *NAME ## _table [32] = { \
69 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
78 static inline void func(int n) \
80 NAME ## _table[n](); \
83 /* Condition register moves */
84 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
89 /* Floating point condition and status register moves */
90 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93 static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94 &gen_op_store_T0_fpscri_fpscr0,
95 &gen_op_store_T0_fpscri_fpscr1,
96 &gen_op_store_T0_fpscri_fpscr2,
97 &gen_op_store_T0_fpscri_fpscr3,
98 &gen_op_store_T0_fpscri_fpscr4,
99 &gen_op_store_T0_fpscri_fpscr5,
100 &gen_op_store_T0_fpscri_fpscr6,
101 &gen_op_store_T0_fpscri_fpscr7,
103 static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
105 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
108 /* Segment register moves */
109 GEN16(gen_op_load_sr, gen_op_load_sr);
110 GEN16(gen_op_store_sr, gen_op_store_sr);
112 /* General purpose registers moves */
113 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
117 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
121 /* floating point registers moves */
122 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
129 static uint8_t spr_access[1024 / 2];
131 /* internal defines */
132 typedef struct DisasContext {
133 struct TranslationBlock *tb;
137 /* Routine used to access memory */
139 /* Translation flags */
140 #if !defined(CONFIG_USER_ONLY)
146 typedef struct opc_handler_t {
149 /* instruction type */
152 void (*handler)(DisasContext *ctx);
155 #define RET_EXCP(ctx, excp, error) \
157 if ((ctx)->exception == EXCP_NONE) { \
158 gen_op_update_nip((ctx)->nip); \
160 gen_op_raise_exception_err((excp), (error)); \
161 ctx->exception = (excp); \
164 #define RET_INVAL(ctx) \
165 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
167 #define RET_PRIVOPC(ctx) \
168 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
170 #define RET_PRIVREG(ctx) \
171 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
173 #define RET_MTMSR(ctx) \
174 RET_EXCP((ctx), EXCP_MTMSR, 0)
176 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
177 static void gen_##name (DisasContext *ctx); \
178 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
179 static void gen_##name (DisasContext *ctx)
181 typedef struct opcode_t {
182 unsigned char opc1, opc2, opc3;
183 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
184 unsigned char pad[5];
186 unsigned char pad[1];
188 opc_handler_t handler;
191 /*** Instruction decoding ***/
192 #define EXTRACT_HELPER(name, shift, nb) \
193 static inline uint32_t name (uint32_t opcode) \
195 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
198 #define EXTRACT_SHELPER(name, shift, nb) \
199 static inline int32_t name (uint32_t opcode) \
201 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
205 EXTRACT_HELPER(opc1, 26, 6);
207 EXTRACT_HELPER(opc2, 1, 5);
209 EXTRACT_HELPER(opc3, 6, 5);
210 /* Update Cr0 flags */
211 EXTRACT_HELPER(Rc, 0, 1);
213 EXTRACT_HELPER(rD, 21, 5);
215 EXTRACT_HELPER(rS, 21, 5);
217 EXTRACT_HELPER(rA, 16, 5);
219 EXTRACT_HELPER(rB, 11, 5);
221 EXTRACT_HELPER(rC, 6, 5);
223 EXTRACT_HELPER(crfD, 23, 3);
224 EXTRACT_HELPER(crfS, 18, 3);
225 EXTRACT_HELPER(crbD, 21, 5);
226 EXTRACT_HELPER(crbA, 16, 5);
227 EXTRACT_HELPER(crbB, 11, 5);
229 EXTRACT_HELPER(SPR, 11, 10);
230 /*** Get constants ***/
231 EXTRACT_HELPER(IMM, 12, 8);
232 /* 16 bits signed immediate value */
233 EXTRACT_SHELPER(SIMM, 0, 16);
234 /* 16 bits unsigned immediate value */
235 EXTRACT_HELPER(UIMM, 0, 16);
237 EXTRACT_HELPER(NB, 11, 5);
239 EXTRACT_HELPER(SH, 11, 5);
241 EXTRACT_HELPER(MB, 6, 5);
243 EXTRACT_HELPER(ME, 1, 5);
245 EXTRACT_HELPER(TO, 21, 5);
247 EXTRACT_HELPER(CRM, 12, 8);
248 EXTRACT_HELPER(FM, 17, 8);
249 EXTRACT_HELPER(SR, 16, 4);
250 EXTRACT_HELPER(FPIMM, 20, 4);
252 /*** Jump target decoding ***/
254 EXTRACT_SHELPER(d, 0, 16);
255 /* Immediate address */
256 static inline uint32_t LI (uint32_t opcode)
258 return (opcode >> 0) & 0x03FFFFFC;
261 static inline uint32_t BD (uint32_t opcode)
263 return (opcode >> 0) & 0xFFFC;
266 EXTRACT_HELPER(BO, 21, 5);
267 EXTRACT_HELPER(BI, 16, 5);
268 /* Absolute/relative address */
269 EXTRACT_HELPER(AA, 1, 1);
271 EXTRACT_HELPER(LK, 0, 1);
273 /* Create a mask between <start> and <end> bits */
274 static inline uint32_t MASK (uint32_t start, uint32_t end)
278 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
285 #if defined(__APPLE__)
286 #define OPCODES_SECTION \
287 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) ))
289 #define OPCODES_SECTION \
290 __attribute__ ((section(".opcodes"), unused, aligned (8) ))
293 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
294 OPCODES_SECTION opcode_t opc_##name = { \
302 .handler = &gen_##name, \
306 #define GEN_OPCODE_MARK(name) \
307 OPCODES_SECTION opcode_t opc_##name = { \
313 .inval = 0x00000000, \
319 /* Start opcode list */
320 GEN_OPCODE_MARK(start);
322 /* Invalid instruction */
323 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
328 /* Special opcode to stop emulation */
329 GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
331 RET_EXCP(ctx, EXCP_HLT, 0);
334 static opc_handler_t invalid_handler = {
337 .handler = gen_invalid,
340 /*** Integer arithmetic ***/
341 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
342 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
344 gen_op_load_gpr_T0(rA(ctx->opcode)); \
345 gen_op_load_gpr_T1(rB(ctx->opcode)); \
347 if (Rc(ctx->opcode) != 0) \
349 gen_op_store_T0_gpr(rD(ctx->opcode)); \
352 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
353 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
355 gen_op_load_gpr_T0(rA(ctx->opcode)); \
356 gen_op_load_gpr_T1(rB(ctx->opcode)); \
358 if (Rc(ctx->opcode) != 0) \
360 gen_op_store_T0_gpr(rD(ctx->opcode)); \
363 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
364 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
366 gen_op_load_gpr_T0(rA(ctx->opcode)); \
368 if (Rc(ctx->opcode) != 0) \
370 gen_op_store_T0_gpr(rD(ctx->opcode)); \
372 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
373 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
375 gen_op_load_gpr_T0(rA(ctx->opcode)); \
377 if (Rc(ctx->opcode) != 0) \
379 gen_op_store_T0_gpr(rD(ctx->opcode)); \
382 /* Two operands arithmetic functions */
383 #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
384 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
385 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
387 /* Two operands arithmetic functions with no overflow allowed */
388 #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
389 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
391 /* One operand arithmetic functions */
392 #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
393 __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
394 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
396 /* add add. addo addo. */
397 GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
398 /* addc addc. addco addco. */
399 GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
400 /* adde adde. addeo addeo. */
401 GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
402 /* addme addme. addmeo addmeo. */
403 GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
404 /* addze addze. addzeo addzeo. */
405 GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
406 /* divw divw. divwo divwo. */
407 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
408 /* divwu divwu. divwuo divwuo. */
409 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
411 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
413 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
414 /* mullw mullw. mullwo mullwo. */
415 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
416 /* neg neg. nego nego. */
417 GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
418 /* subf subf. subfo subfo. */
419 GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
420 /* subfc subfc. subfco subfco. */
421 GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
422 /* subfe subfe. subfeo subfeo. */
423 GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
424 /* subfme subfme. subfmeo subfmeo. */
425 GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
426 /* subfze subfze. subfzeo subfzeo. */
427 GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
429 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
431 int32_t simm = SIMM(ctx->opcode);
433 if (rA(ctx->opcode) == 0) {
436 gen_op_load_gpr_T0(rA(ctx->opcode));
439 gen_op_store_T0_gpr(rD(ctx->opcode));
442 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444 gen_op_load_gpr_T0(rA(ctx->opcode));
445 gen_op_addic(SIMM(ctx->opcode));
446 gen_op_store_T0_gpr(rD(ctx->opcode));
449 GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
451 gen_op_load_gpr_T0(rA(ctx->opcode));
452 gen_op_addic(SIMM(ctx->opcode));
454 gen_op_store_T0_gpr(rD(ctx->opcode));
457 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
459 int32_t simm = SIMM(ctx->opcode);
461 if (rA(ctx->opcode) == 0) {
462 gen_op_set_T0(simm << 16);
464 gen_op_load_gpr_T0(rA(ctx->opcode));
465 gen_op_addi(simm << 16);
467 gen_op_store_T0_gpr(rD(ctx->opcode));
470 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472 gen_op_load_gpr_T0(rA(ctx->opcode));
473 gen_op_mulli(SIMM(ctx->opcode));
474 gen_op_store_T0_gpr(rD(ctx->opcode));
477 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
479 gen_op_load_gpr_T0(rA(ctx->opcode));
480 gen_op_subfic(SIMM(ctx->opcode));
481 gen_op_store_T0_gpr(rD(ctx->opcode));
484 /*** Integer comparison ***/
485 #define GEN_CMP(name, opc) \
486 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
488 gen_op_load_gpr_T0(rA(ctx->opcode)); \
489 gen_op_load_gpr_T1(rB(ctx->opcode)); \
491 gen_op_store_T0_crf(crfD(ctx->opcode)); \
497 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
499 gen_op_load_gpr_T0(rA(ctx->opcode));
500 gen_op_cmpi(SIMM(ctx->opcode));
501 gen_op_store_T0_crf(crfD(ctx->opcode));
506 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
508 gen_op_load_gpr_T0(rA(ctx->opcode));
509 gen_op_cmpli(UIMM(ctx->opcode));
510 gen_op_store_T0_crf(crfD(ctx->opcode));
513 /*** Integer logical ***/
514 #define __GEN_LOGICAL2(name, opc2, opc3) \
515 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
517 gen_op_load_gpr_T0(rS(ctx->opcode)); \
518 gen_op_load_gpr_T1(rB(ctx->opcode)); \
520 if (Rc(ctx->opcode) != 0) \
522 gen_op_store_T0_gpr(rA(ctx->opcode)); \
524 #define GEN_LOGICAL2(name, opc) \
525 __GEN_LOGICAL2(name, 0x1C, opc)
527 #define GEN_LOGICAL1(name, opc) \
528 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
530 gen_op_load_gpr_T0(rS(ctx->opcode)); \
532 if (Rc(ctx->opcode) != 0) \
534 gen_op_store_T0_gpr(rA(ctx->opcode)); \
538 GEN_LOGICAL2(and, 0x00);
540 GEN_LOGICAL2(andc, 0x01);
542 GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
544 gen_op_load_gpr_T0(rS(ctx->opcode));
545 gen_op_andi_(UIMM(ctx->opcode));
547 gen_op_store_T0_gpr(rA(ctx->opcode));
550 GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
552 gen_op_load_gpr_T0(rS(ctx->opcode));
553 gen_op_andi_(UIMM(ctx->opcode) << 16);
555 gen_op_store_T0_gpr(rA(ctx->opcode));
559 GEN_LOGICAL1(cntlzw, 0x00);
561 GEN_LOGICAL2(eqv, 0x08);
563 GEN_LOGICAL1(extsb, 0x1D);
565 GEN_LOGICAL1(extsh, 0x1C);
567 GEN_LOGICAL2(nand, 0x0E);
569 GEN_LOGICAL2(nor, 0x03);
572 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
574 gen_op_load_gpr_T0(rS(ctx->opcode));
575 /* Optimisation for mr case */
576 if (rS(ctx->opcode) != rB(ctx->opcode)) {
577 gen_op_load_gpr_T1(rB(ctx->opcode));
580 if (Rc(ctx->opcode) != 0)
582 gen_op_store_T0_gpr(rA(ctx->opcode));
586 GEN_LOGICAL2(orc, 0x0C);
588 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
590 gen_op_load_gpr_T0(rS(ctx->opcode));
591 /* Optimisation for "set to zero" case */
592 if (rS(ctx->opcode) != rB(ctx->opcode)) {
593 gen_op_load_gpr_T1(rB(ctx->opcode));
598 if (Rc(ctx->opcode) != 0)
600 gen_op_store_T0_gpr(rA(ctx->opcode));
603 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
605 uint32_t uimm = UIMM(ctx->opcode);
607 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
611 gen_op_load_gpr_T0(rS(ctx->opcode));
614 gen_op_store_T0_gpr(rA(ctx->opcode));
617 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
619 uint32_t uimm = UIMM(ctx->opcode);
621 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
625 gen_op_load_gpr_T0(rS(ctx->opcode));
627 gen_op_ori(uimm << 16);
628 gen_op_store_T0_gpr(rA(ctx->opcode));
631 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
633 uint32_t uimm = UIMM(ctx->opcode);
635 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
639 gen_op_load_gpr_T0(rS(ctx->opcode));
642 gen_op_store_T0_gpr(rA(ctx->opcode));
646 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
648 uint32_t uimm = UIMM(ctx->opcode);
650 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
654 gen_op_load_gpr_T0(rS(ctx->opcode));
656 gen_op_xori(uimm << 16);
657 gen_op_store_T0_gpr(rA(ctx->opcode));
660 /*** Integer rotate ***/
661 /* rlwimi & rlwimi. */
662 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
666 mb = MB(ctx->opcode);
667 me = ME(ctx->opcode);
668 gen_op_load_gpr_T0(rS(ctx->opcode));
669 gen_op_load_gpr_T1(rA(ctx->opcode));
670 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
671 if (Rc(ctx->opcode) != 0)
673 gen_op_store_T0_gpr(rA(ctx->opcode));
675 /* rlwinm & rlwinm. */
676 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
680 sh = SH(ctx->opcode);
681 mb = MB(ctx->opcode);
682 me = ME(ctx->opcode);
683 gen_op_load_gpr_T0(rS(ctx->opcode));
686 gen_op_andi_(MASK(mb, me));
695 } else if (me == (31 - sh)) {
700 } else if (me == 31) {
702 if (sh == (32 - mb)) {
708 gen_op_rlwinm(sh, MASK(mb, me));
710 if (Rc(ctx->opcode) != 0)
712 gen_op_store_T0_gpr(rA(ctx->opcode));
715 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
719 mb = MB(ctx->opcode);
720 me = ME(ctx->opcode);
721 gen_op_load_gpr_T0(rS(ctx->opcode));
722 gen_op_load_gpr_T1(rB(ctx->opcode));
723 if (mb == 0 && me == 31) {
727 gen_op_rlwnm(MASK(mb, me));
729 if (Rc(ctx->opcode) != 0)
731 gen_op_store_T0_gpr(rA(ctx->opcode));
734 /*** Integer shift ***/
736 __GEN_LOGICAL2(slw, 0x18, 0x00);
738 __GEN_LOGICAL2(sraw, 0x18, 0x18);
740 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
742 gen_op_load_gpr_T0(rS(ctx->opcode));
743 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
744 if (Rc(ctx->opcode) != 0)
746 gen_op_store_T0_gpr(rA(ctx->opcode));
749 __GEN_LOGICAL2(srw, 0x18, 0x10);
751 /*** Floating-Point arithmetic ***/
752 #define _GEN_FLOAT_ACB(name, op1, op2) \
753 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
755 if (!ctx->fpu_enabled) { \
756 RET_EXCP(ctx, EXCP_NO_FP, 0); \
759 gen_op_reset_scrfx(); \
760 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
761 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
762 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
764 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
765 if (Rc(ctx->opcode)) \
769 #define GEN_FLOAT_ACB(name, op2) \
770 _GEN_FLOAT_ACB(name, 0x3F, op2); \
771 _GEN_FLOAT_ACB(name##s, 0x3B, op2);
773 #define _GEN_FLOAT_AB(name, op1, op2, inval) \
774 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
776 if (!ctx->fpu_enabled) { \
777 RET_EXCP(ctx, EXCP_NO_FP, 0); \
780 gen_op_reset_scrfx(); \
781 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
782 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
784 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
785 if (Rc(ctx->opcode)) \
788 #define GEN_FLOAT_AB(name, op2, inval) \
789 _GEN_FLOAT_AB(name, 0x3F, op2, inval); \
790 _GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
792 #define _GEN_FLOAT_AC(name, op1, op2, inval) \
793 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
795 if (!ctx->fpu_enabled) { \
796 RET_EXCP(ctx, EXCP_NO_FP, 0); \
799 gen_op_reset_scrfx(); \
800 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
801 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
803 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
804 if (Rc(ctx->opcode)) \
807 #define GEN_FLOAT_AC(name, op2, inval) \
808 _GEN_FLOAT_AC(name, 0x3F, op2, inval); \
809 _GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
811 #define GEN_FLOAT_B(name, op2, op3) \
812 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
814 if (!ctx->fpu_enabled) { \
815 RET_EXCP(ctx, EXCP_NO_FP, 0); \
818 gen_op_reset_scrfx(); \
819 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
821 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
822 if (Rc(ctx->opcode)) \
826 #define GEN_FLOAT_BS(name, op2) \
827 GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
829 if (!ctx->fpu_enabled) { \
830 RET_EXCP(ctx, EXCP_NO_FP, 0); \
833 gen_op_reset_scrfx(); \
834 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
836 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
837 if (Rc(ctx->opcode)) \
842 GEN_FLOAT_AB(add, 0x15, 0x000007C0);
844 GEN_FLOAT_AB(div, 0x12, 0x000007C0);
846 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
849 GEN_FLOAT_BS(res, 0x18);
852 GEN_FLOAT_BS(rsqrte, 0x1A);
855 _GEN_FLOAT_ACB(sel, 0x3F, 0x17);
857 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
860 GEN_FLOAT_BS(sqrt, 0x16);
862 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
864 if (!ctx->fpu_enabled) {
865 RET_EXCP(ctx, EXCP_NO_FP, 0);
868 gen_op_reset_scrfx();
869 gen_op_load_fpr_FT0(rB(ctx->opcode));
871 gen_op_store_FT0_fpr(rD(ctx->opcode));
876 /*** Floating-Point multiply-and-add ***/
878 GEN_FLOAT_ACB(madd, 0x1D);
880 GEN_FLOAT_ACB(msub, 0x1C);
882 GEN_FLOAT_ACB(nmadd, 0x1F);
884 GEN_FLOAT_ACB(nmsub, 0x1E);
886 /*** Floating-Point round & convert ***/
888 GEN_FLOAT_B(ctiw, 0x0E, 0x00);
890 GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
892 GEN_FLOAT_B(rsp, 0x0C, 0x00);
894 /*** Floating-Point compare ***/
896 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
898 if (!ctx->fpu_enabled) {
899 RET_EXCP(ctx, EXCP_NO_FP, 0);
902 gen_op_reset_scrfx();
903 gen_op_load_fpr_FT0(rA(ctx->opcode));
904 gen_op_load_fpr_FT1(rB(ctx->opcode));
906 gen_op_store_T0_crf(crfD(ctx->opcode));
910 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
912 if (!ctx->fpu_enabled) {
913 RET_EXCP(ctx, EXCP_NO_FP, 0);
916 gen_op_reset_scrfx();
917 gen_op_load_fpr_FT0(rA(ctx->opcode));
918 gen_op_load_fpr_FT1(rB(ctx->opcode));
920 gen_op_store_T0_crf(crfD(ctx->opcode));
923 /*** Floating-point move ***/
925 GEN_FLOAT_B(abs, 0x08, 0x08);
928 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
930 if (!ctx->fpu_enabled) {
931 RET_EXCP(ctx, EXCP_NO_FP, 0);
934 gen_op_reset_scrfx();
935 gen_op_load_fpr_FT0(rB(ctx->opcode));
936 gen_op_store_FT0_fpr(rD(ctx->opcode));
942 GEN_FLOAT_B(nabs, 0x08, 0x04);
944 GEN_FLOAT_B(neg, 0x08, 0x01);
946 /*** Floating-Point status & ctrl register ***/
948 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
950 if (!ctx->fpu_enabled) {
951 RET_EXCP(ctx, EXCP_NO_FP, 0);
954 gen_op_load_fpscr_T0(crfS(ctx->opcode));
955 gen_op_store_T0_crf(crfD(ctx->opcode));
956 gen_op_clear_fpscr(crfS(ctx->opcode));
960 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
962 if (!ctx->fpu_enabled) {
963 RET_EXCP(ctx, EXCP_NO_FP, 0);
967 gen_op_store_FT0_fpr(rD(ctx->opcode));
973 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
977 if (!ctx->fpu_enabled) {
978 RET_EXCP(ctx, EXCP_NO_FP, 0);
981 crb = crbD(ctx->opcode) >> 2;
982 gen_op_load_fpscr_T0(crb);
983 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
984 gen_op_store_T0_fpscr(crb);
990 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
994 if (!ctx->fpu_enabled) {
995 RET_EXCP(ctx, EXCP_NO_FP, 0);
998 crb = crbD(ctx->opcode) >> 2;
999 gen_op_load_fpscr_T0(crb);
1000 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1001 gen_op_store_T0_fpscr(crb);
1002 if (Rc(ctx->opcode))
1007 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1009 if (!ctx->fpu_enabled) {
1010 RET_EXCP(ctx, EXCP_NO_FP, 0);
1013 gen_op_load_fpr_FT0(rB(ctx->opcode));
1014 gen_op_store_fpscr(FM(ctx->opcode));
1015 if (Rc(ctx->opcode))
1020 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1022 if (!ctx->fpu_enabled) {
1023 RET_EXCP(ctx, EXCP_NO_FP, 0);
1026 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1027 if (Rc(ctx->opcode))
1031 /*** Integer load ***/
1032 #if defined(CONFIG_USER_ONLY)
1033 #define op_ldst(name) gen_op_##name##_raw()
1034 #define OP_LD_TABLE(width)
1035 #define OP_ST_TABLE(width)
1037 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1038 #define OP_LD_TABLE(width) \
1039 static GenOpFunc *gen_op_l##width[] = { \
1040 &gen_op_l##width##_user, \
1041 &gen_op_l##width##_kernel, \
1043 #define OP_ST_TABLE(width) \
1044 static GenOpFunc *gen_op_st##width[] = { \
1045 &gen_op_st##width##_user, \
1046 &gen_op_st##width##_kernel, \
1050 #define GEN_LD(width, opc) \
1051 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1053 uint32_t simm = SIMM(ctx->opcode); \
1054 if (rA(ctx->opcode) == 0) { \
1055 gen_op_set_T0(simm); \
1057 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1059 gen_op_addi(simm); \
1061 op_ldst(l##width); \
1062 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1065 #define GEN_LDU(width, opc) \
1066 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1068 uint32_t simm = SIMM(ctx->opcode); \
1069 if (rA(ctx->opcode) == 0 || \
1070 rA(ctx->opcode) == rD(ctx->opcode)) { \
1074 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1076 gen_op_addi(simm); \
1077 op_ldst(l##width); \
1078 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1079 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1082 #define GEN_LDUX(width, opc) \
1083 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1085 if (rA(ctx->opcode) == 0 || \
1086 rA(ctx->opcode) == rD(ctx->opcode)) { \
1090 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1091 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1093 op_ldst(l##width); \
1094 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1095 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1098 #define GEN_LDX(width, opc2, opc3) \
1099 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1101 if (rA(ctx->opcode) == 0) { \
1102 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1104 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1105 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1108 op_ldst(l##width); \
1109 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1112 #define GEN_LDS(width, op) \
1113 OP_LD_TABLE(width); \
1114 GEN_LD(width, op | 0x20); \
1115 GEN_LDU(width, op | 0x21); \
1116 GEN_LDUX(width, op | 0x01); \
1117 GEN_LDX(width, 0x17, op | 0x00)
1119 /* lbz lbzu lbzux lbzx */
1121 /* lha lhau lhaux lhax */
1123 /* lhz lhzu lhzux lhzx */
1125 /* lwz lwzu lwzux lwzx */
1128 /*** Integer store ***/
1129 #define GEN_ST(width, opc) \
1130 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1132 uint32_t simm = SIMM(ctx->opcode); \
1133 if (rA(ctx->opcode) == 0) { \
1134 gen_op_set_T0(simm); \
1136 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1138 gen_op_addi(simm); \
1140 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1141 op_ldst(st##width); \
1144 #define GEN_STU(width, opc) \
1145 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1147 uint32_t simm = SIMM(ctx->opcode); \
1148 if (rA(ctx->opcode) == 0) { \
1152 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1154 gen_op_addi(simm); \
1155 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1156 op_ldst(st##width); \
1157 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1160 #define GEN_STUX(width, opc) \
1161 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1163 if (rA(ctx->opcode) == 0) { \
1167 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1168 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1170 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1171 op_ldst(st##width); \
1172 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1175 #define GEN_STX(width, opc2, opc3) \
1176 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1178 if (rA(ctx->opcode) == 0) { \
1179 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1181 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1182 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1185 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1186 op_ldst(st##width); \
1189 #define GEN_STS(width, op) \
1190 OP_ST_TABLE(width); \
1191 GEN_ST(width, op | 0x20); \
1192 GEN_STU(width, op | 0x21); \
1193 GEN_STUX(width, op | 0x01); \
1194 GEN_STX(width, 0x17, op | 0x00)
1196 /* stb stbu stbux stbx */
1198 /* sth sthu sthux sthx */
1200 /* stw stwu stwux stwx */
1203 /*** Integer load and store with byte reverse ***/
1206 GEN_LDX(hbr, 0x16, 0x18);
1209 GEN_LDX(wbr, 0x16, 0x10);
1212 GEN_STX(hbr, 0x16, 0x1C);
1215 GEN_STX(wbr, 0x16, 0x14);
1217 /*** Integer load and store multiple ***/
1218 #if defined(CONFIG_USER_ONLY)
1219 #define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1221 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1222 static GenOpFunc1 *gen_op_lmw[] = {
1226 static GenOpFunc1 *gen_op_stmw[] = {
1228 &gen_op_stmw_kernel,
1233 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1235 int simm = SIMM(ctx->opcode);
1237 if (rA(ctx->opcode) == 0) {
1238 gen_op_set_T0(simm);
1240 gen_op_load_gpr_T0(rA(ctx->opcode));
1244 op_ldstm(lmw, rD(ctx->opcode));
1248 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1250 int simm = SIMM(ctx->opcode);
1252 if (rA(ctx->opcode) == 0) {
1253 gen_op_set_T0(simm);
1255 gen_op_load_gpr_T0(rA(ctx->opcode));
1259 op_ldstm(stmw, rS(ctx->opcode));
1262 /*** Integer load and store strings ***/
1263 #if defined(CONFIG_USER_ONLY)
1264 #define op_ldsts(name, start) gen_op_##name##_raw(start)
1265 #define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1267 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1268 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1269 static GenOpFunc1 *gen_op_lswi[] = {
1271 &gen_op_lswi_kernel,
1273 static GenOpFunc3 *gen_op_lswx[] = {
1275 &gen_op_lswx_kernel,
1277 static GenOpFunc1 *gen_op_stsw[] = {
1279 &gen_op_stsw_kernel,
1284 /* PPC32 specification says we must generate an exception if
1285 * rA is in the range of registers to be loaded.
1286 * In an other hand, IBM says this is valid, but rA won't be loaded.
1287 * For now, I'll follow the spec...
1289 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1291 int nb = NB(ctx->opcode);
1292 int start = rD(ctx->opcode);
1293 int ra = rA(ctx->opcode);
1299 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1300 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1301 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1307 gen_op_load_gpr_T0(ra);
1310 op_ldsts(lswi, start);
1314 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1316 int ra = rA(ctx->opcode);
1317 int rb = rB(ctx->opcode);
1320 gen_op_load_gpr_T0(rb);
1323 gen_op_load_gpr_T0(ra);
1324 gen_op_load_gpr_T1(rb);
1327 gen_op_load_xer_bc();
1328 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1332 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1334 int nb = NB(ctx->opcode);
1336 if (rA(ctx->opcode) == 0) {
1339 gen_op_load_gpr_T0(rA(ctx->opcode));
1344 op_ldsts(stsw, rS(ctx->opcode));
1348 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1350 int ra = rA(ctx->opcode);
1353 gen_op_load_gpr_T0(rB(ctx->opcode));
1354 ra = rB(ctx->opcode);
1356 gen_op_load_gpr_T0(ra);
1357 gen_op_load_gpr_T1(rB(ctx->opcode));
1360 gen_op_load_xer_bc();
1361 op_ldsts(stsw, rS(ctx->opcode));
1364 /*** Memory synchronisation ***/
1366 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1371 GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1376 #if defined(CONFIG_USER_ONLY)
1377 #define op_lwarx() gen_op_lwarx_raw()
1378 #define op_stwcx() gen_op_stwcx_raw()
1380 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1381 static GenOpFunc *gen_op_lwarx[] = {
1383 &gen_op_lwarx_kernel,
1385 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1386 static GenOpFunc *gen_op_stwcx[] = {
1388 &gen_op_stwcx_kernel,
1392 GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1394 if (rA(ctx->opcode) == 0) {
1395 gen_op_load_gpr_T0(rB(ctx->opcode));
1397 gen_op_load_gpr_T0(rA(ctx->opcode));
1398 gen_op_load_gpr_T1(rB(ctx->opcode));
1402 gen_op_store_T1_gpr(rD(ctx->opcode));
1406 GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1408 if (rA(ctx->opcode) == 0) {
1409 gen_op_load_gpr_T0(rB(ctx->opcode));
1411 gen_op_load_gpr_T0(rA(ctx->opcode));
1412 gen_op_load_gpr_T1(rB(ctx->opcode));
1415 gen_op_load_gpr_T1(rS(ctx->opcode));
1420 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1424 /*** Floating-point load ***/
1425 #define GEN_LDF(width, opc) \
1426 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1428 uint32_t simm = SIMM(ctx->opcode); \
1429 if (rA(ctx->opcode) == 0) { \
1430 gen_op_set_T0(simm); \
1432 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1434 gen_op_addi(simm); \
1436 op_ldst(l##width); \
1437 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1440 #define GEN_LDUF(width, opc) \
1441 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1443 uint32_t simm = SIMM(ctx->opcode); \
1444 if (rA(ctx->opcode) == 0 || \
1445 rA(ctx->opcode) == rD(ctx->opcode)) { \
1449 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1451 gen_op_addi(simm); \
1452 op_ldst(l##width); \
1453 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1454 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1457 #define GEN_LDUXF(width, opc) \
1458 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1460 if (rA(ctx->opcode) == 0 || \
1461 rA(ctx->opcode) == rD(ctx->opcode)) { \
1465 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1466 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1468 op_ldst(l##width); \
1469 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1470 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1473 #define GEN_LDXF(width, opc2, opc3) \
1474 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1476 if (rA(ctx->opcode) == 0) { \
1477 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1479 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1480 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1483 op_ldst(l##width); \
1484 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1487 #define GEN_LDFS(width, op) \
1488 OP_LD_TABLE(width); \
1489 GEN_LDF(width, op | 0x20); \
1490 GEN_LDUF(width, op | 0x21); \
1491 GEN_LDUXF(width, op | 0x01); \
1492 GEN_LDXF(width, 0x17, op | 0x00)
1494 /* lfd lfdu lfdux lfdx */
1496 /* lfs lfsu lfsux lfsx */
1499 /*** Floating-point store ***/
1500 #define GEN_STF(width, opc) \
1501 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1503 uint32_t simm = SIMM(ctx->opcode); \
1504 if (rA(ctx->opcode) == 0) { \
1505 gen_op_set_T0(simm); \
1507 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1509 gen_op_addi(simm); \
1511 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1512 op_ldst(st##width); \
1515 #define GEN_STUF(width, opc) \
1516 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1518 uint32_t simm = SIMM(ctx->opcode); \
1519 if (rA(ctx->opcode) == 0) { \
1523 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1525 gen_op_addi(simm); \
1526 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1527 op_ldst(st##width); \
1528 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1531 #define GEN_STUXF(width, opc) \
1532 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1534 if (rA(ctx->opcode) == 0) { \
1538 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1539 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1541 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1542 op_ldst(st##width); \
1543 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1546 #define GEN_STXF(width, opc2, opc3) \
1547 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1549 if (rA(ctx->opcode) == 0) { \
1550 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1552 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1553 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1556 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1557 op_ldst(st##width); \
1560 #define GEN_STFS(width, op) \
1561 OP_ST_TABLE(width); \
1562 GEN_STF(width, op | 0x20); \
1563 GEN_STUF(width, op | 0x21); \
1564 GEN_STUXF(width, op | 0x01); \
1565 GEN_STXF(width, 0x17, op | 0x00)
1567 /* stfd stfdu stfdux stfdx */
1569 /* stfs stfsu stfsux stfsx */
1574 GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1576 if (!ctx->fpu_enabled) {
1577 RET_EXCP(ctx, EXCP_NO_FP, 0);
1586 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1588 uint32_t li, target;
1590 /* sign extend LI */
1591 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1593 if (AA(ctx->opcode) == 0)
1594 target = ctx->nip + li - 4;
1597 if (LK(ctx->opcode)) {
1598 gen_op_setlr(ctx->nip);
1600 gen_op_b((long)ctx->tb, target);
1601 ctx->exception = EXCP_BRANCH;
1608 static inline void gen_bcond(DisasContext *ctx, int type)
1610 uint32_t target = 0;
1611 uint32_t bo = BO(ctx->opcode);
1612 uint32_t bi = BI(ctx->opcode);
1616 if ((bo & 0x4) == 0)
1620 li = (int32_t)((int16_t)(BD(ctx->opcode)));
1621 if (AA(ctx->opcode) == 0) {
1622 target = ctx->nip + li - 4;
1628 gen_op_movl_T1_ctr();
1632 gen_op_movl_T1_lr();
1635 if (LK(ctx->opcode)) {
1636 gen_op_setlr(ctx->nip);
1639 /* No CR condition */
1650 if (type == BCOND_IM) {
1651 gen_op_b((long)ctx->tb, target);
1658 mask = 1 << (3 - (bi & 0x03));
1659 gen_op_load_crf_T0(bi >> 2);
1663 gen_op_test_ctr_true(mask);
1666 gen_op_test_ctrz_true(mask);
1671 gen_op_test_true(mask);
1677 gen_op_test_ctr_false(mask);
1680 gen_op_test_ctrz_false(mask);
1685 gen_op_test_false(mask);
1690 if (type == BCOND_IM) {
1691 gen_op_btest((long)ctx->tb, target, ctx->nip);
1693 gen_op_btest_T1(ctx->nip);
1696 ctx->exception = EXCP_BRANCH;
1699 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1701 gen_bcond(ctx, BCOND_IM);
1704 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1706 gen_bcond(ctx, BCOND_CTR);
1709 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1711 gen_bcond(ctx, BCOND_LR);
1714 /*** Condition register logical ***/
1715 #define GEN_CRLOGIC(op, opc) \
1716 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1718 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1719 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1720 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1721 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1723 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1724 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1725 3 - (crbD(ctx->opcode) & 0x03)); \
1726 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
1730 GEN_CRLOGIC(and, 0x08)
1732 GEN_CRLOGIC(andc, 0x04)
1734 GEN_CRLOGIC(eqv, 0x09)
1736 GEN_CRLOGIC(nand, 0x07)
1738 GEN_CRLOGIC(nor, 0x01)
1740 GEN_CRLOGIC(or, 0x0E)
1742 GEN_CRLOGIC(orc, 0x0D)
1744 GEN_CRLOGIC(xor, 0x06)
1746 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1748 gen_op_load_crf_T0(crfS(ctx->opcode));
1749 gen_op_store_T0_crf(crfD(ctx->opcode));
1752 /*** System linkage ***/
1753 /* rfi (supervisor only) */
1754 GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1756 #if defined(CONFIG_USER_ONLY)
1759 /* Restore CPU state */
1760 if (!ctx->supervisor) {
1765 RET_EXCP(ctx, EXCP_RFI, 0);
1770 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1772 #if defined(CONFIG_USER_ONLY)
1773 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1775 RET_EXCP(ctx, EXCP_SYSCALL, 0);
1781 GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1783 gen_op_load_gpr_T0(rA(ctx->opcode));
1784 gen_op_load_gpr_T1(rB(ctx->opcode));
1785 gen_op_tw(TO(ctx->opcode));
1789 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1791 gen_op_load_gpr_T0(rA(ctx->opcode));
1793 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1794 SIMM(ctx->opcode), TO(ctx->opcode));
1796 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1799 /*** Processor control ***/
1800 static inline int check_spr_access (int spr, int rw, int supervisor)
1802 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1805 if (spr != LR && spr != CTR) {
1807 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1808 SPR_ENCODE(spr), supervisor, rw, rights,
1809 (rights >> ((2 * supervisor) + rw)) & 1);
1811 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1812 SPR_ENCODE(spr), supervisor, rw, rights,
1813 (rights >> ((2 * supervisor) + rw)) & 1);
1819 rights = rights >> (2 * supervisor);
1820 rights = rights >> rw;
1826 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1828 gen_op_load_xer_cr();
1829 gen_op_store_T0_crf(crfD(ctx->opcode));
1830 gen_op_clear_xer_cr();
1834 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1837 gen_op_store_T0_gpr(rD(ctx->opcode));
1841 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1843 #if defined(CONFIG_USER_ONLY)
1846 if (!ctx->supervisor) {
1851 gen_op_store_T0_gpr(rD(ctx->opcode));
1856 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1858 uint32_t sprn = SPR(ctx->opcode);
1860 #if defined(CONFIG_USER_ONLY)
1861 switch (check_spr_access(sprn, 0, 0))
1863 switch (check_spr_access(sprn, 0, ctx->supervisor))
1867 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1886 gen_op_load_ibat(0, 0);
1889 gen_op_load_ibat(0, 1);
1892 gen_op_load_ibat(0, 2);
1895 gen_op_load_ibat(0, 3);
1898 gen_op_load_ibat(0, 4);
1901 gen_op_load_ibat(0, 5);
1904 gen_op_load_ibat(0, 6);
1907 gen_op_load_ibat(0, 7);
1910 gen_op_load_ibat(1, 0);
1913 gen_op_load_ibat(1, 1);
1916 gen_op_load_ibat(1, 2);
1919 gen_op_load_ibat(1, 3);
1922 gen_op_load_ibat(1, 4);
1925 gen_op_load_ibat(1, 5);
1928 gen_op_load_ibat(1, 6);
1931 gen_op_load_ibat(1, 7);
1934 gen_op_load_dbat(0, 0);
1937 gen_op_load_dbat(0, 1);
1940 gen_op_load_dbat(0, 2);
1943 gen_op_load_dbat(0, 3);
1946 gen_op_load_dbat(0, 4);
1949 gen_op_load_dbat(0, 5);
1952 gen_op_load_dbat(0, 6);
1955 gen_op_load_dbat(0, 7);
1958 gen_op_load_dbat(1, 0);
1961 gen_op_load_dbat(1, 1);
1964 gen_op_load_dbat(1, 2);
1967 gen_op_load_dbat(1, 3);
1970 gen_op_load_dbat(1, 4);
1973 gen_op_load_dbat(1, 5);
1976 gen_op_load_dbat(1, 6);
1979 gen_op_load_dbat(1, 7);
1994 gen_op_load_spr(sprn);
1997 gen_op_store_T0_gpr(rD(ctx->opcode));
2001 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
2003 uint32_t sprn = SPR(ctx->opcode);
2005 /* We need to update the time base before reading it */
2017 gen_op_store_T0_gpr(rD(ctx->opcode));
2021 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
2023 gen_op_load_gpr_T0(rS(ctx->opcode));
2024 gen_op_store_cr(CRM(ctx->opcode));
2028 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2030 #if defined(CONFIG_USER_ONLY)
2033 if (!ctx->supervisor) {
2037 gen_op_load_gpr_T0(rS(ctx->opcode));
2039 /* Must stop the translation as machine state (may have) changed */
2045 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2047 uint32_t sprn = SPR(ctx->opcode);
2051 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2052 rS(ctx->opcode), sprn);
2055 #if defined(CONFIG_USER_ONLY)
2056 switch (check_spr_access(sprn, 1, 0))
2058 switch (check_spr_access(sprn, 1, ctx->supervisor))
2062 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2070 gen_op_load_gpr_T0(rS(ctx->opcode));
2082 gen_op_store_ibat(0, 0);
2086 gen_op_store_ibat(0, 1);
2090 gen_op_store_ibat(0, 2);
2094 gen_op_store_ibat(0, 3);
2098 gen_op_store_ibat(0, 4);
2102 gen_op_store_ibat(0, 5);
2106 gen_op_store_ibat(0, 6);
2110 gen_op_store_ibat(0, 7);
2114 gen_op_store_ibat(1, 0);
2118 gen_op_store_ibat(1, 1);
2122 gen_op_store_ibat(1, 2);
2126 gen_op_store_ibat(1, 3);
2130 gen_op_store_ibat(1, 4);
2134 gen_op_store_ibat(1, 5);
2138 gen_op_store_ibat(1, 6);
2142 gen_op_store_ibat(1, 7);
2146 gen_op_store_dbat(0, 0);
2150 gen_op_store_dbat(0, 1);
2154 gen_op_store_dbat(0, 2);
2158 gen_op_store_dbat(0, 3);
2162 gen_op_store_dbat(0, 4);
2166 gen_op_store_dbat(0, 5);
2170 gen_op_store_dbat(0, 6);
2174 gen_op_store_dbat(0, 7);
2178 gen_op_store_dbat(1, 0);
2182 gen_op_store_dbat(1, 1);
2186 gen_op_store_dbat(1, 2);
2190 gen_op_store_dbat(1, 3);
2194 gen_op_store_dbat(1, 4);
2198 gen_op_store_dbat(1, 5);
2202 gen_op_store_dbat(1, 6);
2206 gen_op_store_dbat(1, 7);
2210 gen_op_store_sdr1();
2220 gen_op_store_decr();
2223 gen_op_store_spr(sprn);
2228 /*** Cache management ***/
2229 /* For now, all those will be implemented as nop:
2230 * this is valid, regarding the PowerPC specs...
2231 * We just have to flush tb while invalidating instruction cache lines...
2234 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2236 if (rA(ctx->opcode) == 0) {
2237 gen_op_load_gpr_T0(rB(ctx->opcode));
2239 gen_op_load_gpr_T0(rA(ctx->opcode));
2240 gen_op_load_gpr_T1(rB(ctx->opcode));
2246 /* dcbi (Supervisor only) */
2247 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2249 #if defined(CONFIG_USER_ONLY)
2252 if (!ctx->supervisor) {
2256 if (rA(ctx->opcode) == 0) {
2257 gen_op_load_gpr_T0(rB(ctx->opcode));
2259 gen_op_load_gpr_T0(rA(ctx->opcode));
2260 gen_op_load_gpr_T1(rB(ctx->opcode));
2269 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2271 if (rA(ctx->opcode) == 0) {
2272 gen_op_load_gpr_T0(rB(ctx->opcode));
2274 gen_op_load_gpr_T0(rA(ctx->opcode));
2275 gen_op_load_gpr_T1(rB(ctx->opcode));
2282 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2287 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2292 #if defined(CONFIG_USER_ONLY)
2293 #define op_dcbz() gen_op_dcbz_raw()
2295 #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2296 static GenOpFunc *gen_op_dcbz[] = {
2298 &gen_op_dcbz_kernel,
2302 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2304 if (rA(ctx->opcode) == 0) {
2305 gen_op_load_gpr_T0(rB(ctx->opcode));
2307 gen_op_load_gpr_T0(rA(ctx->opcode));
2308 gen_op_load_gpr_T1(rB(ctx->opcode));
2312 gen_op_check_reservation();
2316 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2318 if (rA(ctx->opcode) == 0) {
2319 gen_op_load_gpr_T0(rB(ctx->opcode));
2321 gen_op_load_gpr_T0(rA(ctx->opcode));
2322 gen_op_load_gpr_T1(rB(ctx->opcode));
2330 GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
2334 /*** Segment register manipulation ***/
2335 /* Supervisor only: */
2337 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2339 #if defined(CONFIG_USER_ONLY)
2342 if (!ctx->supervisor) {
2346 gen_op_load_sr(SR(ctx->opcode));
2347 gen_op_store_T0_gpr(rD(ctx->opcode));
2352 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2354 #if defined(CONFIG_USER_ONLY)
2357 if (!ctx->supervisor) {
2361 gen_op_load_gpr_T1(rB(ctx->opcode));
2363 gen_op_store_T0_gpr(rD(ctx->opcode));
2368 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2370 #if defined(CONFIG_USER_ONLY)
2373 if (!ctx->supervisor) {
2377 gen_op_load_gpr_T0(rS(ctx->opcode));
2378 gen_op_store_sr(SR(ctx->opcode));
2383 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2385 #if defined(CONFIG_USER_ONLY)
2388 if (!ctx->supervisor) {
2392 gen_op_load_gpr_T0(rS(ctx->opcode));
2393 gen_op_load_gpr_T1(rB(ctx->opcode));
2394 gen_op_store_srin();
2398 /*** Lookaside buffer management ***/
2399 /* Optional & supervisor only: */
2401 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
2403 #if defined(CONFIG_USER_ONLY)
2406 if (!ctx->supervisor) {
2408 fprintf(logfile, "%s: ! supervisor\n", __func__);
2418 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
2420 #if defined(CONFIG_USER_ONLY)
2423 if (!ctx->supervisor) {
2427 gen_op_load_gpr_T0(rB(ctx->opcode));
2434 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
2436 #if defined(CONFIG_USER_ONLY)
2439 if (!ctx->supervisor) {
2443 /* This has no effect: it should ensure that all previous
2444 * tlbie have completed
2450 /*** External control ***/
2453 #if defined(CONFIG_USER_ONLY)
2454 #define op_eciwx() gen_op_eciwx_raw()
2455 #define op_ecowx() gen_op_ecowx_raw()
2457 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2458 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2459 static GenOpFunc *gen_op_eciwx[] = {
2461 &gen_op_eciwx_kernel,
2463 static GenOpFunc *gen_op_ecowx[] = {
2465 &gen_op_ecowx_kernel,
2469 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2471 /* Should check EAR[E] & alignment ! */
2472 if (rA(ctx->opcode) == 0) {
2473 gen_op_load_gpr_T0(rB(ctx->opcode));
2475 gen_op_load_gpr_T0(rA(ctx->opcode));
2476 gen_op_load_gpr_T1(rB(ctx->opcode));
2480 gen_op_store_T0_gpr(rD(ctx->opcode));
2484 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2486 /* Should check EAR[E] & alignment ! */
2487 if (rA(ctx->opcode) == 0) {
2488 gen_op_load_gpr_T0(rB(ctx->opcode));
2490 gen_op_load_gpr_T0(rA(ctx->opcode));
2491 gen_op_load_gpr_T1(rB(ctx->opcode));
2494 gen_op_load_gpr_T2(rS(ctx->opcode));
2498 /* End opcode list */
2499 GEN_OPCODE_MARK(end);
2501 /*****************************************************************************/
2505 int fflush (FILE *stream);
2507 /* Main ppc opcodes table:
2508 * at init, all opcodes are invalids
2510 static opc_handler_t *ppc_opcodes[0x40];
2514 PPC_DIRECT = 0, /* Opcode routine */
2515 PPC_INDIRECT = 1, /* Indirect opcode table */
2518 static inline int is_indirect_opcode (void *handler)
2520 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2523 static inline opc_handler_t **ind_table(void *handler)
2525 return (opc_handler_t **)((unsigned long)handler & ~3);
2528 /* Instruction table creation */
2529 /* Opcodes tables creation */
2530 static void fill_new_table (opc_handler_t **table, int len)
2534 for (i = 0; i < len; i++)
2535 table[i] = &invalid_handler;
2538 static int create_new_table (opc_handler_t **table, unsigned char idx)
2540 opc_handler_t **tmp;
2542 tmp = malloc(0x20 * sizeof(opc_handler_t));
2545 fill_new_table(tmp, 0x20);
2546 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2551 static int insert_in_table (opc_handler_t **table, unsigned char idx,
2552 opc_handler_t *handler)
2554 if (table[idx] != &invalid_handler)
2556 table[idx] = handler;
2561 static int register_direct_insn (opc_handler_t **ppc_opcodes,
2562 unsigned char idx, opc_handler_t *handler)
2564 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2565 printf("*** ERROR: opcode %02x already assigned in main "
2566 "opcode table\n", idx);
2573 static int register_ind_in_table (opc_handler_t **table,
2574 unsigned char idx1, unsigned char idx2,
2575 opc_handler_t *handler)
2577 if (table[idx1] == &invalid_handler) {
2578 if (create_new_table(table, idx1) < 0) {
2579 printf("*** ERROR: unable to create indirect table "
2580 "idx=%02x\n", idx1);
2584 if (!is_indirect_opcode(table[idx1])) {
2585 printf("*** ERROR: idx %02x already assigned to a direct "
2590 if (handler != NULL &&
2591 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2592 printf("*** ERROR: opcode %02x already assigned in "
2593 "opcode table %02x\n", idx2, idx1);
2600 static int register_ind_insn (opc_handler_t **ppc_opcodes,
2601 unsigned char idx1, unsigned char idx2,
2602 opc_handler_t *handler)
2606 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2611 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2612 unsigned char idx1, unsigned char idx2,
2613 unsigned char idx3, opc_handler_t *handler)
2615 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2616 printf("*** ERROR: unable to join indirect table idx "
2617 "[%02x-%02x]\n", idx1, idx2);
2620 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2622 printf("*** ERROR: unable to insert opcode "
2623 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2630 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2632 if (insn->opc2 != 0xFF) {
2633 if (insn->opc3 != 0xFF) {
2634 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2635 insn->opc3, &insn->handler) < 0)
2638 if (register_ind_insn(ppc_opcodes, insn->opc1,
2639 insn->opc2, &insn->handler) < 0)
2643 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2650 static int test_opcode_table (opc_handler_t **table, int len)
2654 for (i = 0, count = 0; i < len; i++) {
2655 /* Consistency fixup */
2656 if (table[i] == NULL)
2657 table[i] = &invalid_handler;
2658 if (table[i] != &invalid_handler) {
2659 if (is_indirect_opcode(table[i])) {
2660 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2663 table[i] = &invalid_handler;
2676 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2678 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2679 printf("*** WARNING: no opcode defined !\n");
2682 #define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
2683 #define SPR_UR SPR_RIGHTS(0, 0)
2684 #define SPR_UW SPR_RIGHTS(1, 0)
2685 #define SPR_SR SPR_RIGHTS(0, 1)
2686 #define SPR_SW SPR_RIGHTS(1, 1)
2688 #define spr_set_rights(spr, rights) \
2690 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2693 static void init_spr_rights (uint32_t pvr)
2696 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2698 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2700 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2702 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
2704 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
2705 /* DSISR (SPR 18) */
2706 spr_set_rights(DSISR, SPR_SR | SPR_SW);
2708 spr_set_rights(DAR, SPR_SR | SPR_SW);
2710 spr_set_rights(DECR, SPR_SR | SPR_SW);
2712 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2714 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2716 spr_set_rights(SRR1, SPR_SR | SPR_SW);
2717 /* SPRG0 (SPR 272) */
2718 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
2719 /* SPRG1 (SPR 273) */
2720 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
2721 /* SPRG2 (SPR 274) */
2722 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
2723 /* SPRG3 (SPR 275) */
2724 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
2726 spr_set_rights(ASR, SPR_SR | SPR_SW);
2728 spr_set_rights(EAR, SPR_SR | SPR_SW);
2730 spr_set_rights(O_TBL, SPR_SW);
2732 spr_set_rights(O_TBU, SPR_SW);
2734 spr_set_rights(PVR, SPR_SR);
2735 /* IBAT0U (SPR 528) */
2736 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
2737 /* IBAT0L (SPR 529) */
2738 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
2739 /* IBAT1U (SPR 530) */
2740 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
2741 /* IBAT1L (SPR 531) */
2742 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
2743 /* IBAT2U (SPR 532) */
2744 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
2745 /* IBAT2L (SPR 533) */
2746 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
2747 /* IBAT3U (SPR 534) */
2748 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
2749 /* IBAT3L (SPR 535) */
2750 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
2751 /* DBAT0U (SPR 536) */
2752 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
2753 /* DBAT0L (SPR 537) */
2754 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
2755 /* DBAT1U (SPR 538) */
2756 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
2757 /* DBAT1L (SPR 539) */
2758 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
2759 /* DBAT2U (SPR 540) */
2760 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
2761 /* DBAT2L (SPR 541) */
2762 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
2763 /* DBAT3U (SPR 542) */
2764 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
2765 /* DBAT3L (SPR 543) */
2766 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
2767 /* FPECR (SPR 1022) */
2768 spr_set_rights(FPECR, SPR_SR | SPR_SW);
2769 /* Special registers for PPC 604 */
2770 if ((pvr & 0xFFFF0000) == 0x00040000) {
2772 spr_set_rights(IABR , SPR_SR | SPR_SW);
2773 /* DABR (SPR 1013) */
2774 spr_set_rights(DABR, SPR_SR | SPR_SW);
2776 spr_set_rights(HID0, SPR_SR | SPR_SW);
2778 spr_set_rights(PIR, SPR_SR | SPR_SW);
2780 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2782 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2784 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2786 spr_set_rights(SIA, SPR_SR | SPR_SW);
2788 spr_set_rights(SDA, SPR_SR | SPR_SW);
2790 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2791 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2792 (pvr & 0xFFFF0000) == 0x70000000) {
2794 spr_set_rights(HID0, SPR_SR | SPR_SW);
2796 spr_set_rights(HID1, SPR_SR | SPR_SW);
2798 spr_set_rights(IABR, SPR_SR | SPR_SW);
2800 spr_set_rights(ICTC, SPR_SR | SPR_SW);
2802 spr_set_rights(L2CR, SPR_SR | SPR_SW);
2804 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2806 spr_set_rights(MMCR1, SPR_SR | SPR_SW);
2808 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2810 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2812 spr_set_rights(PMC3, SPR_SR | SPR_SW);
2814 spr_set_rights(PMC4, SPR_SR | SPR_SW);
2816 spr_set_rights(SIA, SPR_SR | SPR_SW);
2818 spr_set_rights(SDA, SPR_SR | SPR_SW);
2820 spr_set_rights(THRM1, SPR_SR | SPR_SW);
2822 spr_set_rights(THRM2, SPR_SR | SPR_SW);
2824 spr_set_rights(THRM3, SPR_SR | SPR_SW);
2826 spr_set_rights(UMMCR0, SPR_UR | SPR_UW);
2828 spr_set_rights(UMMCR1, SPR_UR | SPR_UW);
2830 spr_set_rights(UPMC1, SPR_UR | SPR_UW);
2832 spr_set_rights(UPMC2, SPR_UR | SPR_UW);
2834 spr_set_rights(UPMC3, SPR_UR | SPR_UW);
2836 spr_set_rights(UPMC4, SPR_UR | SPR_UW);
2838 spr_set_rights(USIA, SPR_UR | SPR_UW);
2840 /* MPC755 has special registers */
2841 if (pvr == 0x00083100) {
2843 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2845 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2847 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2849 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2851 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2853 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2855 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2857 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2859 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2861 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2863 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2865 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2867 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2869 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2871 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2873 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2875 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2877 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2879 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2881 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2883 spr_set_rights(DMISS, SPR_SR | SPR_SW);
2885 spr_set_rights(DCMP, SPR_SR | SPR_SW);
2887 spr_set_rights(DHASH1, SPR_SR | SPR_SW);
2889 spr_set_rights(DHASH2, SPR_SR | SPR_SW);
2891 spr_set_rights(IMISS, SPR_SR | SPR_SW);
2893 spr_set_rights(ICMP, SPR_SR | SPR_SW);
2895 spr_set_rights(RPA, SPR_SR | SPR_SW);
2897 spr_set_rights(HID2, SPR_SR | SPR_SW);
2899 spr_set_rights(L2PM, SPR_SR | SPR_SW);
2903 /*****************************************************************************/
2904 /* PPC "main stream" common instructions (no optional ones) */
2906 typedef struct ppc_proc_t {
2911 typedef struct ppc_def_t {
2913 unsigned long pvr_mask;
2917 static ppc_proc_t ppc_proc_common = {
2918 .flags = PPC_COMMON,
2922 static ppc_proc_t ppc_proc_G3 = {
2927 static ppc_def_t ppc_defs[] =
2929 /* MPC740/745/750/755 (G3) */
2932 .pvr_mask = 0xFFFF0000,
2933 .proc = &ppc_proc_G3,
2935 /* IBM 750FX (G3 embedded) */
2938 .pvr_mask = 0xFFFF0000,
2939 .proc = &ppc_proc_G3,
2941 /* Fallback (generic PPC) */
2944 .pvr_mask = 0x00000000,
2945 .proc = &ppc_proc_common,
2949 static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
2951 opcode_t *opc, *start, *end;
2954 fill_new_table(ppc_opcodes, 0x40);
2955 for (i = 0; ; i++) {
2956 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2957 (pvr & ppc_defs[i].pvr_mask)) {
2958 flags = ppc_defs[i].proc->flags;
2963 if (&opc_start < &opc_end) {
2970 for (opc = start + 1; opc != end; opc++) {
2971 if ((opc->handler.type & flags) != 0)
2972 if (register_insn(ppc_opcodes, opc) < 0) {
2973 printf("*** ERROR initializing PPC instruction "
2974 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2979 fix_opcode_tables(ppc_opcodes);
2985 /*****************************************************************************/
2986 /* Misc PPC helpers */
2988 void cpu_dump_state(CPUState *env, FILE *f,
2989 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2994 cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2995 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
2996 _load_xer(env), _load_msr(env));
2997 for (i = 0; i < 32; i++) {
2999 cpu_fprintf(f, "GPR%02d:", i);
3000 cpu_fprintf(f, " %08x", env->gpr[i]);
3002 cpu_fprintf(f, "\n");
3004 cpu_fprintf(f, "CR: 0x");
3005 for (i = 0; i < 8; i++)
3006 cpu_fprintf(f, "%01x", env->crf[i]);
3007 cpu_fprintf(f, " [");
3008 for (i = 0; i < 8; i++) {
3010 if (env->crf[i] & 0x08)
3012 else if (env->crf[i] & 0x04)
3014 else if (env->crf[i] & 0x02)
3016 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
3018 cpu_fprintf(f, " ] ");
3019 cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
3020 cpu_ppc_load_tbl(env));
3021 for (i = 0; i < 16; i++) {
3023 cpu_fprintf(f, "FPR%02d:", i);
3024 cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
3026 cpu_fprintf(f, "\n");
3028 cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
3029 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
3030 cpu_fprintf(f, "reservation 0x%08x\n", env->reserve);
3033 CPUPPCState *cpu_ppc_init(void)
3039 env = qemu_mallocz(sizeof(CPUPPCState));
3042 // env->spr[PVR] = 0; /* Basic PPC */
3043 env->spr[PVR] = 0x00080100; /* G3 CPU */
3044 // env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
3045 // env->spr[PVR] = 0x00070100; /* IBM 750FX */
3047 #if defined (DO_SINGLE_STEP)
3048 /* Single step trace mode */
3051 msr_fp = 1; /* Allow floating point exceptions */
3052 msr_me = 1; /* Allow machine check exceptions */
3053 #if defined(CONFIG_USER_ONLY)
3055 cpu_ppc_register(env, 0x00080000);
3057 env->nip = 0xFFFFFFFC;
3059 cpu_single_env = env;
3063 int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3065 env->spr[PVR] = pvr;
3066 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3068 init_spr_rights(env->spr[PVR]);
3073 void cpu_ppc_close(CPUPPCState *env)
3075 /* Should also remove all opcode tables... */
3079 /*****************************************************************************/
3080 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3083 DisasContext ctx, *ctxp = &ctx;
3084 opc_handler_t **table, *handler;
3085 target_ulong pc_start;
3086 uint16_t *gen_opc_end;
3090 gen_opc_ptr = gen_opc_buf;
3091 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3092 gen_opparam_ptr = gen_opparam_buf;
3095 ctx.exception = EXCP_NONE;
3096 #if defined(CONFIG_USER_ONLY)
3099 ctx.supervisor = 1 - msr_pr;
3100 ctx.mem_idx = 1 - msr_pr;
3102 ctx.fpu_enabled = msr_fp;
3103 #if defined (DO_SINGLE_STEP)
3104 /* Single step trace mode */
3107 /* Set env in case of segfault during code fetch */
3108 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
3110 j = gen_opc_ptr - gen_opc_buf;
3114 gen_opc_instr_start[lj++] = 0;
3115 gen_opc_pc[lj] = ctx.nip;
3116 gen_opc_instr_start[lj] = 1;
3119 #if defined PPC_DEBUG_DISAS
3120 if (loglevel & CPU_LOG_TB_IN_ASM) {
3121 fprintf(logfile, "----------------\n");
3122 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
3123 ctx.nip, 1 - msr_pr, msr_ir);
3126 ctx.opcode = ldl_code(ctx.nip);
3127 #if defined PPC_DEBUG_DISAS
3128 if (loglevel & CPU_LOG_TB_IN_ASM) {
3129 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3130 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3135 table = ppc_opcodes;
3136 handler = table[opc1(ctx.opcode)];
3137 if (is_indirect_opcode(handler)) {
3138 table = ind_table(handler);
3139 handler = table[opc2(ctx.opcode)];
3140 if (is_indirect_opcode(handler)) {
3141 table = ind_table(handler);
3142 handler = table[opc3(ctx.opcode)];
3145 /* Is opcode *REALLY* valid ? */
3146 if (handler->handler == &gen_invalid) {
3148 fprintf(logfile, "invalid/unsupported opcode: "
3149 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3150 opc1(ctx.opcode), opc2(ctx.opcode),
3151 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3153 printf("invalid/unsupported opcode: "
3154 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3155 opc1(ctx.opcode), opc2(ctx.opcode),
3156 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3159 if ((ctx.opcode & handler->inval) != 0) {
3161 fprintf(logfile, "invalid bits: %08x for opcode: "
3162 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3163 ctx.opcode & handler->inval, opc1(ctx.opcode),
3164 opc2(ctx.opcode), opc3(ctx.opcode),
3165 ctx.opcode, ctx.nip - 4);
3167 printf("invalid bits: %08x for opcode: "
3168 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3169 ctx.opcode & handler->inval, opc1(ctx.opcode),
3170 opc2(ctx.opcode), opc3(ctx.opcode),
3171 ctx.opcode, ctx.nip - 4);
3177 (*(handler->handler))(&ctx);
3178 /* Check trace mode exceptions */
3179 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3180 /* Check in single step trace mode
3181 * we need to stop except if:
3182 * - rfi, trap or syscall
3183 * - first instruction of an exception handler
3185 (msr_se && (ctx.nip < 0x100 ||
3187 (ctx.nip & 0xFC) != 0x04) &&
3188 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3189 ctx.exception != EXCP_TRAP)) {
3190 RET_EXCP(ctxp, EXCP_TRACE, 0);
3192 /* if we reach a page boundary, stop generation */
3193 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
3194 RET_EXCP(ctxp, EXCP_BRANCH, 0);
3197 if (ctx.exception == EXCP_NONE) {
3198 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3199 } else if (ctx.exception != EXCP_BRANCH) {
3203 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3204 * do bad business and then qemu crashes !
3208 /* Generate the return instruction */
3210 *gen_opc_ptr = INDEX_op_end;
3212 j = gen_opc_ptr - gen_opc_buf;
3215 gen_opc_instr_start[lj++] = 0;
3223 tb->size = ctx.nip - pc_start;
3226 if (loglevel & CPU_LOG_TB_CPU) {
3227 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3228 cpu_dump_state(env, logfile, fprintf, 0);
3230 if (loglevel & CPU_LOG_TB_IN_ASM) {
3231 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3232 target_disas(logfile, pc_start, ctx.nip - pc_start, 0);
3233 fprintf(logfile, "\n");
3235 if (loglevel & CPU_LOG_TB_OP) {
3236 fprintf(logfile, "OP:\n");
3237 dump_ops(gen_opc_buf, gen_opparam_buf);
3238 fprintf(logfile, "\n");
3244 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3246 return gen_intermediate_code_internal(env, tb, 0);
3249 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3251 return gen_intermediate_code_internal(env, tb, 1);