2 * PPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 //#define DO_SINGLE_STEP
31 //#define PPC_DEBUG_DISAS
34 #define DEF(s, n, copy_size) INDEX_op_ ## s,
40 static uint16_t *gen_opc_ptr;
41 static uint32_t *gen_opparam_ptr;
45 #define GEN8(func, NAME) \
46 static GenOpFunc *NAME ## _table [8] = { \
47 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
50 static inline void func(int n) \
52 NAME ## _table[n](); \
55 #define GEN16(func, NAME) \
56 static GenOpFunc *NAME ## _table [16] = { \
57 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
62 static inline void func(int n) \
64 NAME ## _table[n](); \
67 #define GEN32(func, NAME) \
68 static GenOpFunc *NAME ## _table [32] = { \
69 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
78 static inline void func(int n) \
80 NAME ## _table[n](); \
83 /* Condition register moves */
84 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
89 /* Floating point condition and status register moves */
90 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93 static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94 &gen_op_store_T0_fpscri_fpscr0,
95 &gen_op_store_T0_fpscri_fpscr1,
96 &gen_op_store_T0_fpscri_fpscr2,
97 &gen_op_store_T0_fpscri_fpscr3,
98 &gen_op_store_T0_fpscri_fpscr4,
99 &gen_op_store_T0_fpscri_fpscr5,
100 &gen_op_store_T0_fpscri_fpscr6,
101 &gen_op_store_T0_fpscri_fpscr7,
103 static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
105 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
108 /* Segment register moves */
109 GEN16(gen_op_load_sr, gen_op_load_sr);
110 GEN16(gen_op_store_sr, gen_op_store_sr);
112 /* General purpose registers moves */
113 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
117 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
121 /* floating point registers moves */
122 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
129 static uint8_t spr_access[1024 / 2];
131 /* internal defines */
132 typedef struct DisasContext {
133 struct TranslationBlock *tb;
138 #if !defined(CONFIG_USER_ONLY)
141 /* Routine used to access memory */
145 typedef struct opc_handler_t {
148 /* instruction type */
151 void (*handler)(DisasContext *ctx);
154 #define RET_EXCP(ctx, excp, error) \
156 if ((ctx)->exception == EXCP_NONE) { \
157 gen_op_update_nip((ctx)->nip); \
159 gen_op_raise_exception_err((excp), (error)); \
160 ctx->exception = (excp); \
163 #define RET_INVAL(ctx) \
164 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
166 #define RET_PRIVOPC(ctx) \
167 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
169 #define RET_PRIVREG(ctx) \
170 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
172 #define RET_MTMSR(ctx) \
173 RET_EXCP((ctx), EXCP_MTMSR, 0)
175 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
176 static void gen_##name (DisasContext *ctx); \
177 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
178 static void gen_##name (DisasContext *ctx)
180 typedef struct opcode_t {
181 unsigned char opc1, opc2, opc3;
182 opc_handler_t handler;
185 /*** Instruction decoding ***/
186 #define EXTRACT_HELPER(name, shift, nb) \
187 static inline uint32_t name (uint32_t opcode) \
189 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
192 #define EXTRACT_SHELPER(name, shift, nb) \
193 static inline int32_t name (uint32_t opcode) \
195 return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
199 EXTRACT_HELPER(opc1, 26, 6);
201 EXTRACT_HELPER(opc2, 1, 5);
203 EXTRACT_HELPER(opc3, 6, 5);
204 /* Update Cr0 flags */
205 EXTRACT_HELPER(Rc, 0, 1);
207 EXTRACT_HELPER(rD, 21, 5);
209 EXTRACT_HELPER(rS, 21, 5);
211 EXTRACT_HELPER(rA, 16, 5);
213 EXTRACT_HELPER(rB, 11, 5);
215 EXTRACT_HELPER(rC, 6, 5);
217 EXTRACT_HELPER(crfD, 23, 3);
218 EXTRACT_HELPER(crfS, 18, 3);
219 EXTRACT_HELPER(crbD, 21, 5);
220 EXTRACT_HELPER(crbA, 16, 5);
221 EXTRACT_HELPER(crbB, 11, 5);
223 EXTRACT_HELPER(SPR, 11, 10);
224 /*** Get constants ***/
225 EXTRACT_HELPER(IMM, 12, 8);
226 /* 16 bits signed immediate value */
227 EXTRACT_SHELPER(SIMM, 0, 16);
228 /* 16 bits unsigned immediate value */
229 EXTRACT_HELPER(UIMM, 0, 16);
231 EXTRACT_HELPER(NB, 11, 5);
233 EXTRACT_HELPER(SH, 11, 5);
235 EXTRACT_HELPER(MB, 6, 5);
237 EXTRACT_HELPER(ME, 1, 5);
239 EXTRACT_HELPER(TO, 21, 5);
241 EXTRACT_HELPER(CRM, 12, 8);
242 EXTRACT_HELPER(FM, 17, 8);
243 EXTRACT_HELPER(SR, 16, 4);
244 EXTRACT_HELPER(FPIMM, 20, 4);
246 /*** Jump target decoding ***/
248 EXTRACT_SHELPER(d, 0, 16);
249 /* Immediate address */
250 static inline uint32_t LI (uint32_t opcode)
252 return (opcode >> 0) & 0x03FFFFFC;
255 static inline uint32_t BD (uint32_t opcode)
257 return (opcode >> 0) & 0xFFFC;
260 EXTRACT_HELPER(BO, 21, 5);
261 EXTRACT_HELPER(BI, 16, 5);
262 /* Absolute/relative address */
263 EXTRACT_HELPER(AA, 1, 1);
265 EXTRACT_HELPER(LK, 0, 1);
267 /* Create a mask between <start> and <end> bits */
268 static inline uint32_t MASK (uint32_t start, uint32_t end)
272 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
279 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
280 __attribute__ ((section(".opcodes"), unused, aligned (8) )) \
281 static opcode_t opc_##name = { \
288 .handler = &gen_##name, \
292 #define GEN_OPCODE_MARK(name) \
293 __attribute__ ((section(".opcodes"), unused, aligned (8) )) \
294 static opcode_t opc_##name = { \
299 .inval = 0x00000000, \
305 /* Start opcode list */
306 GEN_OPCODE_MARK(start);
308 /* Invalid instruction */
309 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
314 /* Special opcode to stop emulation */
315 GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
317 RET_EXCP(ctx, EXCP_HLT, 0);
320 /* Special opcode to call open-firmware */
321 GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
323 RET_EXCP(ctx, EXCP_OFCALL, 0);
326 /* Special opcode to call RTAS */
327 GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
329 printf("RTAS entry point !\n");
330 RET_EXCP(ctx, EXCP_RTASCALL, 0);
333 static opc_handler_t invalid_handler = {
336 .handler = gen_invalid,
339 /*** Integer arithmetic ***/
340 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
341 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
343 gen_op_load_gpr_T0(rA(ctx->opcode)); \
344 gen_op_load_gpr_T1(rB(ctx->opcode)); \
346 if (Rc(ctx->opcode) != 0) \
348 gen_op_store_T0_gpr(rD(ctx->opcode)); \
351 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
352 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
354 gen_op_load_gpr_T0(rA(ctx->opcode)); \
355 gen_op_load_gpr_T1(rB(ctx->opcode)); \
357 if (Rc(ctx->opcode) != 0) \
358 gen_op_set_Rc0_ov(); \
359 gen_op_store_T0_gpr(rD(ctx->opcode)); \
362 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
363 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
365 gen_op_load_gpr_T0(rA(ctx->opcode)); \
367 if (Rc(ctx->opcode) != 0) \
369 gen_op_store_T0_gpr(rD(ctx->opcode)); \
371 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
372 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
374 gen_op_load_gpr_T0(rA(ctx->opcode)); \
376 if (Rc(ctx->opcode) != 0) \
377 gen_op_set_Rc0_ov(); \
378 gen_op_store_T0_gpr(rD(ctx->opcode)); \
381 /* Two operands arithmetic functions */
382 #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
383 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
384 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
386 /* Two operands arithmetic functions with no overflow allowed */
387 #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
388 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
390 /* One operand arithmetic functions */
391 #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
392 __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
393 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
395 /* add add. addo addo. */
396 GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
397 /* addc addc. addco addco. */
398 GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
399 /* adde adde. addeo addeo. */
400 GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
401 /* addme addme. addmeo addmeo. */
402 GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
403 /* addze addze. addzeo addzeo. */
404 GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
405 /* divw divw. divwo divwo. */
406 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
407 /* divwu divwu. divwuo divwuo. */
408 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
410 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
412 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
413 /* mullw mullw. mullwo mullwo. */
414 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
415 /* neg neg. nego nego. */
416 GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
417 /* subf subf. subfo subfo. */
418 GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
419 /* subfc subfc. subfco subfco. */
420 GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
421 /* subfe subfe. subfeo subfeo. */
422 GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
423 /* subfme subfme. subfmeo subfmeo. */
424 GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
425 /* subfze subfze. subfzeo subfzeo. */
426 GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
428 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
430 int32_t simm = SIMM(ctx->opcode);
432 if (rA(ctx->opcode) == 0) {
435 gen_op_load_gpr_T0(rA(ctx->opcode));
438 gen_op_store_T0_gpr(rD(ctx->opcode));
441 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
443 gen_op_load_gpr_T0(rA(ctx->opcode));
444 gen_op_addic(SIMM(ctx->opcode));
445 gen_op_store_T0_gpr(rD(ctx->opcode));
448 GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
450 gen_op_load_gpr_T0(rA(ctx->opcode));
451 gen_op_addic(SIMM(ctx->opcode));
453 gen_op_store_T0_gpr(rD(ctx->opcode));
456 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
458 int32_t simm = SIMM(ctx->opcode);
460 if (rA(ctx->opcode) == 0) {
461 gen_op_set_T0(simm << 16);
463 gen_op_load_gpr_T0(rA(ctx->opcode));
464 gen_op_addi(simm << 16);
466 gen_op_store_T0_gpr(rD(ctx->opcode));
469 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
471 gen_op_load_gpr_T0(rA(ctx->opcode));
472 gen_op_mulli(SIMM(ctx->opcode));
473 gen_op_store_T0_gpr(rD(ctx->opcode));
476 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
478 gen_op_load_gpr_T0(rA(ctx->opcode));
479 gen_op_subfic(SIMM(ctx->opcode));
480 gen_op_store_T0_gpr(rD(ctx->opcode));
483 /*** Integer comparison ***/
484 #define GEN_CMP(name, opc) \
485 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
487 gen_op_load_gpr_T0(rA(ctx->opcode)); \
488 gen_op_load_gpr_T1(rB(ctx->opcode)); \
490 gen_op_store_T0_crf(crfD(ctx->opcode)); \
496 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
498 gen_op_load_gpr_T0(rA(ctx->opcode));
499 gen_op_cmpi(SIMM(ctx->opcode));
500 gen_op_store_T0_crf(crfD(ctx->opcode));
505 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
507 gen_op_load_gpr_T0(rA(ctx->opcode));
508 gen_op_cmpli(UIMM(ctx->opcode));
509 gen_op_store_T0_crf(crfD(ctx->opcode));
512 /*** Integer logical ***/
513 #define __GEN_LOGICAL2(name, opc2, opc3) \
514 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
516 gen_op_load_gpr_T0(rS(ctx->opcode)); \
517 gen_op_load_gpr_T1(rB(ctx->opcode)); \
519 if (Rc(ctx->opcode) != 0) \
521 gen_op_store_T0_gpr(rA(ctx->opcode)); \
523 #define GEN_LOGICAL2(name, opc) \
524 __GEN_LOGICAL2(name, 0x1C, opc)
526 #define GEN_LOGICAL1(name, opc) \
527 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
529 gen_op_load_gpr_T0(rS(ctx->opcode)); \
531 if (Rc(ctx->opcode) != 0) \
533 gen_op_store_T0_gpr(rA(ctx->opcode)); \
537 GEN_LOGICAL2(and, 0x00);
539 GEN_LOGICAL2(andc, 0x01);
541 GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
543 gen_op_load_gpr_T0(rS(ctx->opcode));
544 gen_op_andi_(UIMM(ctx->opcode));
546 gen_op_store_T0_gpr(rA(ctx->opcode));
549 GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
551 gen_op_load_gpr_T0(rS(ctx->opcode));
552 gen_op_andi_(UIMM(ctx->opcode) << 16);
554 gen_op_store_T0_gpr(rA(ctx->opcode));
558 GEN_LOGICAL1(cntlzw, 0x00);
560 GEN_LOGICAL2(eqv, 0x08);
562 GEN_LOGICAL1(extsb, 0x1D);
564 GEN_LOGICAL1(extsh, 0x1C);
566 GEN_LOGICAL2(nand, 0x0E);
568 GEN_LOGICAL2(nor, 0x03);
571 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
573 gen_op_load_gpr_T0(rS(ctx->opcode));
574 /* Optimisation for mr case */
575 if (rS(ctx->opcode) != rB(ctx->opcode)) {
576 gen_op_load_gpr_T1(rB(ctx->opcode));
579 if (Rc(ctx->opcode) != 0)
581 gen_op_store_T0_gpr(rA(ctx->opcode));
585 GEN_LOGICAL2(orc, 0x0C);
587 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
589 gen_op_load_gpr_T0(rS(ctx->opcode));
590 /* Optimisation for "set to zero" case */
591 if (rS(ctx->opcode) != rB(ctx->opcode)) {
592 gen_op_load_gpr_T1(rB(ctx->opcode));
597 if (Rc(ctx->opcode) != 0)
599 gen_op_store_T0_gpr(rA(ctx->opcode));
602 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
604 uint32_t uimm = UIMM(ctx->opcode);
606 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
610 gen_op_load_gpr_T0(rS(ctx->opcode));
613 gen_op_store_T0_gpr(rA(ctx->opcode));
616 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
618 uint32_t uimm = UIMM(ctx->opcode);
620 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
624 gen_op_load_gpr_T0(rS(ctx->opcode));
626 gen_op_ori(uimm << 16);
627 gen_op_store_T0_gpr(rA(ctx->opcode));
630 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
632 uint32_t uimm = UIMM(ctx->opcode);
634 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
638 gen_op_load_gpr_T0(rS(ctx->opcode));
641 gen_op_store_T0_gpr(rA(ctx->opcode));
645 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
647 uint32_t uimm = UIMM(ctx->opcode);
649 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
653 gen_op_load_gpr_T0(rS(ctx->opcode));
655 gen_op_xori(uimm << 16);
656 gen_op_store_T0_gpr(rA(ctx->opcode));
659 /*** Integer rotate ***/
660 /* rlwimi & rlwimi. */
661 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
665 mb = MB(ctx->opcode);
666 me = ME(ctx->opcode);
667 gen_op_load_gpr_T0(rS(ctx->opcode));
668 gen_op_load_gpr_T1(rA(ctx->opcode));
669 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
670 if (Rc(ctx->opcode) != 0)
672 gen_op_store_T0_gpr(rA(ctx->opcode));
674 /* rlwinm & rlwinm. */
675 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
679 sh = SH(ctx->opcode);
680 mb = MB(ctx->opcode);
681 me = ME(ctx->opcode);
682 gen_op_load_gpr_T0(rS(ctx->opcode));
685 gen_op_andi_(MASK(mb, me));
694 } else if (me == (31 - sh)) {
699 } else if (me == 31) {
701 if (sh == (32 - mb)) {
707 gen_op_rlwinm(sh, MASK(mb, me));
709 if (Rc(ctx->opcode) != 0)
711 gen_op_store_T0_gpr(rA(ctx->opcode));
714 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
718 mb = MB(ctx->opcode);
719 me = ME(ctx->opcode);
720 gen_op_load_gpr_T0(rS(ctx->opcode));
721 gen_op_load_gpr_T1(rB(ctx->opcode));
722 if (mb == 0 && me == 31) {
726 gen_op_rlwnm(MASK(mb, me));
728 if (Rc(ctx->opcode) != 0)
730 gen_op_store_T0_gpr(rA(ctx->opcode));
733 /*** Integer shift ***/
735 __GEN_LOGICAL2(slw, 0x18, 0x00);
737 __GEN_LOGICAL2(sraw, 0x18, 0x18);
739 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
741 gen_op_load_gpr_T0(rS(ctx->opcode));
742 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
743 if (Rc(ctx->opcode) != 0)
745 gen_op_store_T0_gpr(rA(ctx->opcode));
748 __GEN_LOGICAL2(srw, 0x18, 0x10);
750 /*** Floating-Point arithmetic ***/
751 #define _GEN_FLOAT_ACB(name, op1, op2) \
752 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
754 gen_op_reset_scrfx(); \
755 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
756 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
757 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
759 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
760 if (Rc(ctx->opcode)) \
764 #define GEN_FLOAT_ACB(name, op2) \
765 _GEN_FLOAT_ACB(name, 0x3F, op2); \
766 _GEN_FLOAT_ACB(name##s, 0x3B, op2);
768 #define _GEN_FLOAT_AB(name, op1, op2, inval) \
769 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
771 gen_op_reset_scrfx(); \
772 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
773 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
775 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
776 if (Rc(ctx->opcode)) \
779 #define GEN_FLOAT_AB(name, op2, inval) \
780 _GEN_FLOAT_AB(name, 0x3F, op2, inval); \
781 _GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
783 #define _GEN_FLOAT_AC(name, op1, op2, inval) \
784 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
786 gen_op_reset_scrfx(); \
787 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
788 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
790 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
791 if (Rc(ctx->opcode)) \
794 #define GEN_FLOAT_AC(name, op2, inval) \
795 _GEN_FLOAT_AC(name, 0x3F, op2, inval); \
796 _GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
798 #define GEN_FLOAT_B(name, op2, op3) \
799 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
801 gen_op_reset_scrfx(); \
802 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
804 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
805 if (Rc(ctx->opcode)) \
809 #define GEN_FLOAT_BS(name, op2) \
810 GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
812 gen_op_reset_scrfx(); \
813 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
815 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
816 if (Rc(ctx->opcode)) \
821 GEN_FLOAT_AB(add, 0x15, 0x000007C0);
823 GEN_FLOAT_AB(div, 0x12, 0x000007C0);
825 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
828 GEN_FLOAT_BS(res, 0x18);
831 GEN_FLOAT_BS(rsqrte, 0x1A);
834 _GEN_FLOAT_ACB(sel, 0x3F, 0x17);
836 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
839 GEN_FLOAT_BS(sqrt, 0x16);
841 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
843 gen_op_reset_scrfx();
844 gen_op_load_fpr_FT0(rB(ctx->opcode));
846 gen_op_store_FT0_fpr(rD(ctx->opcode));
851 /*** Floating-Point multiply-and-add ***/
853 GEN_FLOAT_ACB(madd, 0x1D);
855 GEN_FLOAT_ACB(msub, 0x1C);
857 GEN_FLOAT_ACB(nmadd, 0x1F);
859 GEN_FLOAT_ACB(nmsub, 0x1E);
861 /*** Floating-Point round & convert ***/
863 GEN_FLOAT_B(ctiw, 0x0E, 0x00);
865 GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
867 GEN_FLOAT_B(rsp, 0x0C, 0x00);
869 /*** Floating-Point compare ***/
871 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
873 gen_op_reset_scrfx();
874 gen_op_load_fpr_FT0(rA(ctx->opcode));
875 gen_op_load_fpr_FT1(rB(ctx->opcode));
877 gen_op_store_T0_crf(crfD(ctx->opcode));
881 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
883 gen_op_reset_scrfx();
884 gen_op_load_fpr_FT0(rA(ctx->opcode));
885 gen_op_load_fpr_FT1(rB(ctx->opcode));
887 gen_op_store_T0_crf(crfD(ctx->opcode));
890 /*** Floating-point move ***/
892 GEN_FLOAT_B(abs, 0x08, 0x08);
895 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
897 gen_op_reset_scrfx();
898 gen_op_load_fpr_FT0(rB(ctx->opcode));
899 gen_op_store_FT0_fpr(rD(ctx->opcode));
905 GEN_FLOAT_B(nabs, 0x08, 0x04);
907 GEN_FLOAT_B(neg, 0x08, 0x01);
909 /*** Floating-Point status & ctrl register ***/
911 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
913 gen_op_load_fpscr_T0(crfS(ctx->opcode));
914 gen_op_store_T0_crf(crfD(ctx->opcode));
915 gen_op_clear_fpscr(crfS(ctx->opcode));
919 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
922 gen_op_store_FT0_fpr(rD(ctx->opcode));
928 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
932 crb = crbD(ctx->opcode) >> 2;
933 gen_op_load_fpscr_T0(crb);
934 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
935 gen_op_store_T0_fpscr(crb);
941 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
945 crb = crbD(ctx->opcode) >> 2;
946 gen_op_load_fpscr_T0(crb);
947 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
948 gen_op_store_T0_fpscr(crb);
954 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
956 gen_op_load_fpr_FT0(rB(ctx->opcode));
957 gen_op_store_fpscr(FM(ctx->opcode));
963 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
965 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
970 /*** Integer load ***/
971 #if defined(CONFIG_USER_ONLY)
972 #define op_ldst(name) gen_op_##name##_raw()
973 #define OP_LD_TABLE(width)
974 #define OP_ST_TABLE(width)
976 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
977 #define OP_LD_TABLE(width) \
978 static GenOpFunc *gen_op_l##width[] = { \
979 &gen_op_l##width##_user, \
980 &gen_op_l##width##_kernel, \
982 #define OP_ST_TABLE(width) \
983 static GenOpFunc *gen_op_st##width[] = { \
984 &gen_op_st##width##_user, \
985 &gen_op_st##width##_kernel, \
989 #define GEN_LD(width, opc) \
990 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
992 uint32_t simm = SIMM(ctx->opcode); \
993 if (rA(ctx->opcode) == 0) { \
994 gen_op_set_T0(simm); \
996 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1000 op_ldst(l##width); \
1001 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1004 #define GEN_LDU(width, opc) \
1005 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1007 uint32_t simm = SIMM(ctx->opcode); \
1008 if (rA(ctx->opcode) == 0 || \
1009 rA(ctx->opcode) == rD(ctx->opcode)) { \
1013 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1015 gen_op_addi(simm); \
1016 op_ldst(l##width); \
1017 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1018 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1021 #define GEN_LDUX(width, opc) \
1022 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1024 if (rA(ctx->opcode) == 0 || \
1025 rA(ctx->opcode) == rD(ctx->opcode)) { \
1029 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1030 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1032 op_ldst(l##width); \
1033 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1034 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1037 #define GEN_LDX(width, opc2, opc3) \
1038 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1040 if (rA(ctx->opcode) == 0) { \
1041 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1043 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1044 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1047 op_ldst(l##width); \
1048 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1051 #define GEN_LDS(width, op) \
1052 OP_LD_TABLE(width); \
1053 GEN_LD(width, op | 0x20); \
1054 GEN_LDU(width, op | 0x21); \
1055 GEN_LDUX(width, op | 0x01); \
1056 GEN_LDX(width, 0x17, op | 0x00)
1058 /* lbz lbzu lbzux lbzx */
1060 /* lha lhau lhaux lhax */
1062 /* lhz lhzu lhzux lhzx */
1064 /* lwz lwzu lwzux lwzx */
1067 /*** Integer store ***/
1068 #define GEN_ST(width, opc) \
1069 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1071 uint32_t simm = SIMM(ctx->opcode); \
1072 if (rA(ctx->opcode) == 0) { \
1073 gen_op_set_T0(simm); \
1075 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1077 gen_op_addi(simm); \
1079 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1080 op_ldst(st##width); \
1083 #define GEN_STU(width, opc) \
1084 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1086 uint32_t simm = SIMM(ctx->opcode); \
1087 if (rA(ctx->opcode) == 0) { \
1091 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1093 gen_op_addi(simm); \
1094 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1095 op_ldst(st##width); \
1096 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1099 #define GEN_STUX(width, opc) \
1100 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1102 if (rA(ctx->opcode) == 0) { \
1106 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1107 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1109 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1110 op_ldst(st##width); \
1111 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1114 #define GEN_STX(width, opc2, opc3) \
1115 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1117 if (rA(ctx->opcode) == 0) { \
1118 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1120 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1121 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1124 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1125 op_ldst(st##width); \
1128 #define GEN_STS(width, op) \
1129 OP_ST_TABLE(width); \
1130 GEN_ST(width, op | 0x20); \
1131 GEN_STU(width, op | 0x21); \
1132 GEN_STUX(width, op | 0x01); \
1133 GEN_STX(width, 0x17, op | 0x00)
1135 /* stb stbu stbux stbx */
1137 /* sth sthu sthux sthx */
1139 /* stw stwu stwux stwx */
1142 /*** Integer load and store with byte reverse ***/
1145 GEN_LDX(hbr, 0x16, 0x18);
1148 GEN_LDX(wbr, 0x16, 0x10);
1151 GEN_STX(hbr, 0x16, 0x1C);
1154 GEN_STX(wbr, 0x16, 0x14);
1156 /*** Integer load and store multiple ***/
1157 #if defined(CONFIG_USER_ONLY)
1158 #define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1160 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1161 static GenOpFunc1 *gen_op_lmw[] = {
1165 static GenOpFunc1 *gen_op_stmw[] = {
1167 &gen_op_stmw_kernel,
1172 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1174 int simm = SIMM(ctx->opcode);
1176 if (rA(ctx->opcode) == 0) {
1177 gen_op_set_T0(simm);
1179 gen_op_load_gpr_T0(rA(ctx->opcode));
1183 op_ldstm(lmw, rD(ctx->opcode));
1187 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1189 int simm = SIMM(ctx->opcode);
1191 if (rA(ctx->opcode) == 0) {
1192 gen_op_set_T0(simm);
1194 gen_op_load_gpr_T0(rA(ctx->opcode));
1198 op_ldstm(stmw, rS(ctx->opcode));
1201 /*** Integer load and store strings ***/
1202 #if defined(CONFIG_USER_ONLY)
1203 #define op_ldsts(name, start) gen_op_##name##_raw(start)
1204 #define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1206 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1207 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1208 static GenOpFunc1 *gen_op_lswi[] = {
1210 &gen_op_lswi_kernel,
1212 static GenOpFunc3 *gen_op_lswx[] = {
1214 &gen_op_lswx_kernel,
1216 static GenOpFunc1 *gen_op_stsw[] = {
1218 &gen_op_stsw_kernel,
1223 /* PPC32 specification says we must generate an exception if
1224 * rA is in the range of registers to be loaded.
1225 * In an other hand, IBM says this is valid, but rA won't be loaded.
1226 * For now, I'll follow the spec...
1228 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1230 int nb = NB(ctx->opcode);
1231 int start = rD(ctx->opcode);
1232 int ra = rA(ctx->opcode);
1238 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1239 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1240 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1246 gen_op_load_gpr_T0(ra);
1249 op_ldsts(lswi, start);
1253 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1255 int ra = rA(ctx->opcode);
1256 int rb = rB(ctx->opcode);
1259 gen_op_load_gpr_T0(rb);
1262 gen_op_load_gpr_T0(ra);
1263 gen_op_load_gpr_T1(rb);
1266 gen_op_load_xer_bc();
1267 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1271 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1273 int nb = NB(ctx->opcode);
1275 if (rA(ctx->opcode) == 0) {
1278 gen_op_load_gpr_T0(rA(ctx->opcode));
1283 op_ldsts(stsw, rS(ctx->opcode));
1287 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1289 int ra = rA(ctx->opcode);
1292 gen_op_load_gpr_T0(rB(ctx->opcode));
1293 ra = rB(ctx->opcode);
1295 gen_op_load_gpr_T0(ra);
1296 gen_op_load_gpr_T1(rB(ctx->opcode));
1299 gen_op_load_xer_bc();
1300 op_ldsts(stsw, rS(ctx->opcode));
1303 /*** Memory synchronisation ***/
1305 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1310 GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1315 #if defined(CONFIG_USER_ONLY)
1316 #define op_lwarx() gen_op_lwarx_raw()
1317 #define op_stwcx() gen_op_stwcx_raw()
1319 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1320 static GenOpFunc *gen_op_lwarx[] = {
1322 &gen_op_lwarx_kernel,
1324 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1325 static GenOpFunc *gen_op_stwcx[] = {
1327 &gen_op_stwcx_kernel,
1331 GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1333 if (rA(ctx->opcode) == 0) {
1334 gen_op_load_gpr_T0(rB(ctx->opcode));
1336 gen_op_load_gpr_T0(rA(ctx->opcode));
1337 gen_op_load_gpr_T1(rB(ctx->opcode));
1341 gen_op_store_T1_gpr(rD(ctx->opcode));
1345 GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1347 if (rA(ctx->opcode) == 0) {
1348 gen_op_load_gpr_T0(rB(ctx->opcode));
1350 gen_op_load_gpr_T0(rA(ctx->opcode));
1351 gen_op_load_gpr_T1(rB(ctx->opcode));
1354 gen_op_load_gpr_T1(rS(ctx->opcode));
1359 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1363 /*** Floating-point load ***/
1364 #define GEN_LDF(width, opc) \
1365 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1367 uint32_t simm = SIMM(ctx->opcode); \
1368 if (rA(ctx->opcode) == 0) { \
1369 gen_op_set_T0(simm); \
1371 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1373 gen_op_addi(simm); \
1375 op_ldst(l##width); \
1376 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1379 #define GEN_LDUF(width, opc) \
1380 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1382 uint32_t simm = SIMM(ctx->opcode); \
1383 if (rA(ctx->opcode) == 0 || \
1384 rA(ctx->opcode) == rD(ctx->opcode)) { \
1388 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1390 gen_op_addi(simm); \
1391 op_ldst(l##width); \
1392 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1393 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1396 #define GEN_LDUXF(width, opc) \
1397 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1399 if (rA(ctx->opcode) == 0 || \
1400 rA(ctx->opcode) == rD(ctx->opcode)) { \
1404 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1405 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1407 op_ldst(l##width); \
1408 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1409 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1412 #define GEN_LDXF(width, opc2, opc3) \
1413 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1415 if (rA(ctx->opcode) == 0) { \
1416 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1418 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1419 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1422 op_ldst(l##width); \
1423 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1426 #define GEN_LDFS(width, op) \
1427 OP_LD_TABLE(width); \
1428 GEN_LDF(width, op | 0x20); \
1429 GEN_LDUF(width, op | 0x21); \
1430 GEN_LDUXF(width, op | 0x01); \
1431 GEN_LDXF(width, 0x17, op | 0x00)
1433 /* lfd lfdu lfdux lfdx */
1435 /* lfs lfsu lfsux lfsx */
1438 /*** Floating-point store ***/
1439 #define GEN_STF(width, opc) \
1440 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1442 uint32_t simm = SIMM(ctx->opcode); \
1443 if (rA(ctx->opcode) == 0) { \
1444 gen_op_set_T0(simm); \
1446 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1448 gen_op_addi(simm); \
1450 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1451 op_ldst(st##width); \
1454 #define GEN_STUF(width, opc) \
1455 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1457 uint32_t simm = SIMM(ctx->opcode); \
1458 if (rA(ctx->opcode) == 0) { \
1462 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1464 gen_op_addi(simm); \
1465 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1466 op_ldst(st##width); \
1467 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1470 #define GEN_STUXF(width, opc) \
1471 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1473 if (rA(ctx->opcode) == 0) { \
1477 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1478 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1480 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1481 op_ldst(st##width); \
1482 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1485 #define GEN_STXF(width, opc2, opc3) \
1486 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1488 if (rA(ctx->opcode) == 0) { \
1489 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1491 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1492 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1495 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1496 op_ldst(st##width); \
1499 #define GEN_STFS(width, op) \
1500 OP_ST_TABLE(width); \
1501 GEN_STF(width, op | 0x20); \
1502 GEN_STUF(width, op | 0x21); \
1503 GEN_STUXF(width, op | 0x01); \
1504 GEN_STXF(width, 0x17, op | 0x00)
1506 /* stfd stfdu stfdux stfdx */
1508 /* stfs stfsu stfsux stfsx */
1513 GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1521 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1523 uint32_t li, target;
1525 /* sign extend LI */
1526 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1528 if (AA(ctx->opcode) == 0)
1529 target = ctx->nip + li - 4;
1532 if (LK(ctx->opcode)) {
1533 gen_op_setlr(ctx->nip);
1535 gen_op_b((long)ctx->tb, target);
1536 ctx->exception = EXCP_BRANCH;
1543 static inline void gen_bcond(DisasContext *ctx, int type)
1545 uint32_t target = 0;
1546 uint32_t bo = BO(ctx->opcode);
1547 uint32_t bi = BI(ctx->opcode);
1551 if ((bo & 0x4) == 0)
1555 li = s_ext16(BD(ctx->opcode));
1556 if (AA(ctx->opcode) == 0) {
1557 target = ctx->nip + li - 4;
1563 gen_op_movl_T1_ctr();
1567 gen_op_movl_T1_lr();
1570 if (LK(ctx->opcode)) {
1571 gen_op_setlr(ctx->nip);
1574 /* No CR condition */
1585 if (type == BCOND_IM) {
1586 gen_op_b((long)ctx->tb, target);
1593 mask = 1 << (3 - (bi & 0x03));
1594 gen_op_load_crf_T0(bi >> 2);
1598 gen_op_test_ctr_true(mask);
1601 gen_op_test_ctrz_true(mask);
1606 gen_op_test_true(mask);
1612 gen_op_test_ctr_false(mask);
1615 gen_op_test_ctrz_false(mask);
1620 gen_op_test_false(mask);
1625 if (type == BCOND_IM) {
1626 gen_op_btest((long)ctx->tb, target, ctx->nip);
1628 gen_op_btest_T1(ctx->nip);
1631 ctx->exception = EXCP_BRANCH;
1634 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1636 gen_bcond(ctx, BCOND_IM);
1639 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1641 gen_bcond(ctx, BCOND_CTR);
1644 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1646 gen_bcond(ctx, BCOND_LR);
1649 /*** Condition register logical ***/
1650 #define GEN_CRLOGIC(op, opc) \
1651 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1653 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1654 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1655 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1656 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1658 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1659 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1660 3 - (crbD(ctx->opcode) & 0x03)); \
1661 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
1665 GEN_CRLOGIC(and, 0x08)
1667 GEN_CRLOGIC(andc, 0x04)
1669 GEN_CRLOGIC(eqv, 0x09)
1671 GEN_CRLOGIC(nand, 0x07)
1673 GEN_CRLOGIC(nor, 0x01)
1675 GEN_CRLOGIC(or, 0x0E)
1677 GEN_CRLOGIC(orc, 0x0D)
1679 GEN_CRLOGIC(xor, 0x06)
1681 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1683 gen_op_load_crf_T0(crfS(ctx->opcode));
1684 gen_op_store_T0_crf(crfD(ctx->opcode));
1687 /*** System linkage ***/
1688 /* rfi (supervisor only) */
1689 GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1691 #if defined(CONFIG_USER_ONLY)
1694 /* Restore CPU state */
1695 if (!ctx->supervisor) {
1700 RET_EXCP(ctx, EXCP_RFI, 0);
1705 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1707 #if defined(CONFIG_USER_ONLY)
1708 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1710 RET_EXCP(ctx, EXCP_SYSCALL, 0);
1716 GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1718 gen_op_load_gpr_T0(rA(ctx->opcode));
1719 gen_op_load_gpr_T1(rB(ctx->opcode));
1720 gen_op_tw(TO(ctx->opcode));
1724 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1726 gen_op_load_gpr_T0(rA(ctx->opcode));
1728 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1729 SIMM(ctx->opcode), TO(ctx->opcode));
1731 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1734 /*** Processor control ***/
1735 static inline int check_spr_access (int spr, int rw, int supervisor)
1737 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1740 if (spr != LR && spr != CTR) {
1742 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1743 SPR_ENCODE(spr), supervisor, rw, rights,
1744 (rights >> ((2 * supervisor) + rw)) & 1);
1746 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1747 SPR_ENCODE(spr), supervisor, rw, rights,
1748 (rights >> ((2 * supervisor) + rw)) & 1);
1754 rights = rights >> (2 * supervisor);
1755 rights = rights >> rw;
1761 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1763 gen_op_load_xer_cr();
1764 gen_op_store_T0_crf(crfD(ctx->opcode));
1765 gen_op_clear_xer_cr();
1769 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1772 gen_op_store_T0_gpr(rD(ctx->opcode));
1776 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1778 #if defined(CONFIG_USER_ONLY)
1781 if (!ctx->supervisor) {
1786 gen_op_store_T0_gpr(rD(ctx->opcode));
1791 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1793 uint32_t sprn = SPR(ctx->opcode);
1795 #if defined(CONFIG_USER_ONLY)
1796 switch (check_spr_access(sprn, 0, 0))
1798 switch (check_spr_access(sprn, 0, ctx->supervisor))
1802 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1821 gen_op_load_ibat(0, 0);
1824 gen_op_load_ibat(0, 1);
1827 gen_op_load_ibat(0, 2);
1830 gen_op_load_ibat(0, 3);
1833 gen_op_load_ibat(0, 4);
1836 gen_op_load_ibat(0, 5);
1839 gen_op_load_ibat(0, 6);
1842 gen_op_load_ibat(0, 7);
1845 gen_op_load_ibat(1, 0);
1848 gen_op_load_ibat(1, 1);
1851 gen_op_load_ibat(1, 2);
1854 gen_op_load_ibat(1, 3);
1857 gen_op_load_ibat(1, 4);
1860 gen_op_load_ibat(1, 5);
1863 gen_op_load_ibat(1, 6);
1866 gen_op_load_ibat(1, 7);
1869 gen_op_load_dbat(0, 0);
1872 gen_op_load_dbat(0, 1);
1875 gen_op_load_dbat(0, 2);
1878 gen_op_load_dbat(0, 3);
1881 gen_op_load_dbat(0, 4);
1884 gen_op_load_dbat(0, 5);
1887 gen_op_load_dbat(0, 6);
1890 gen_op_load_dbat(0, 7);
1893 gen_op_load_dbat(1, 0);
1896 gen_op_load_dbat(1, 1);
1899 gen_op_load_dbat(1, 2);
1902 gen_op_load_dbat(1, 3);
1905 gen_op_load_dbat(1, 4);
1908 gen_op_load_dbat(1, 5);
1911 gen_op_load_dbat(1, 6);
1914 gen_op_load_dbat(1, 7);
1929 gen_op_load_spr(sprn);
1932 gen_op_store_T0_gpr(rD(ctx->opcode));
1936 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1938 uint32_t sprn = SPR(ctx->opcode);
1940 /* We need to update the time base before reading it */
1952 gen_op_store_T0_gpr(rD(ctx->opcode));
1956 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
1958 gen_op_load_gpr_T0(rS(ctx->opcode));
1959 gen_op_store_cr(CRM(ctx->opcode));
1963 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
1965 #if defined(CONFIG_USER_ONLY)
1968 if (!ctx->supervisor) {
1972 gen_op_load_gpr_T0(rS(ctx->opcode));
1974 /* Must stop the translation as machine state (may have) changed */
1980 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
1982 uint32_t sprn = SPR(ctx->opcode);
1986 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
1987 rS(ctx->opcode), sprn);
1990 #if defined(CONFIG_USER_ONLY)
1991 switch (check_spr_access(sprn, 1, 0))
1993 switch (check_spr_access(sprn, 1, ctx->supervisor))
1997 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2005 gen_op_load_gpr_T0(rS(ctx->opcode));
2017 gen_op_store_ibat(0, 0);
2021 gen_op_store_ibat(0, 1);
2025 gen_op_store_ibat(0, 2);
2029 gen_op_store_ibat(0, 3);
2033 gen_op_store_ibat(0, 4);
2037 gen_op_store_ibat(0, 5);
2041 gen_op_store_ibat(0, 6);
2045 gen_op_store_ibat(0, 7);
2049 gen_op_store_ibat(1, 0);
2053 gen_op_store_ibat(1, 1);
2057 gen_op_store_ibat(1, 2);
2061 gen_op_store_ibat(1, 3);
2065 gen_op_store_ibat(1, 4);
2069 gen_op_store_ibat(1, 5);
2073 gen_op_store_ibat(1, 6);
2077 gen_op_store_ibat(1, 7);
2081 gen_op_store_dbat(0, 0);
2085 gen_op_store_dbat(0, 1);
2089 gen_op_store_dbat(0, 2);
2093 gen_op_store_dbat(0, 3);
2097 gen_op_store_dbat(0, 4);
2101 gen_op_store_dbat(0, 5);
2105 gen_op_store_dbat(0, 6);
2109 gen_op_store_dbat(0, 7);
2113 gen_op_store_dbat(1, 0);
2117 gen_op_store_dbat(1, 1);
2121 gen_op_store_dbat(1, 2);
2125 gen_op_store_dbat(1, 3);
2129 gen_op_store_dbat(1, 4);
2133 gen_op_store_dbat(1, 5);
2137 gen_op_store_dbat(1, 6);
2141 gen_op_store_dbat(1, 7);
2145 gen_op_store_sdr1();
2155 gen_op_store_decr();
2159 gen_op_store_hid0();
2163 gen_op_store_spr(sprn);
2168 /*** Cache management ***/
2169 /* For now, all those will be implemented as nop:
2170 * this is valid, regarding the PowerPC specs...
2171 * We just have to flush tb while invalidating instruction cache lines...
2174 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2176 if (rA(ctx->opcode) == 0) {
2177 gen_op_load_gpr_T0(rB(ctx->opcode));
2179 gen_op_load_gpr_T0(rA(ctx->opcode));
2180 gen_op_load_gpr_T1(rB(ctx->opcode));
2186 /* dcbi (Supervisor only) */
2187 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2189 #if defined(CONFIG_USER_ONLY)
2192 if (!ctx->supervisor) {
2196 if (rA(ctx->opcode) == 0) {
2197 gen_op_load_gpr_T0(rB(ctx->opcode));
2199 gen_op_load_gpr_T0(rA(ctx->opcode));
2200 gen_op_load_gpr_T1(rB(ctx->opcode));
2209 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2211 if (rA(ctx->opcode) == 0) {
2212 gen_op_load_gpr_T0(rB(ctx->opcode));
2214 gen_op_load_gpr_T0(rA(ctx->opcode));
2215 gen_op_load_gpr_T1(rB(ctx->opcode));
2222 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2227 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2232 #if defined(CONFIG_USER_ONLY)
2233 #define op_dcbz() gen_op_dcbz_raw()
2235 #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2236 static GenOpFunc *gen_op_dcbz[] = {
2238 &gen_op_dcbz_kernel,
2242 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2244 if (rA(ctx->opcode) == 0) {
2245 gen_op_load_gpr_T0(rB(ctx->opcode));
2247 gen_op_load_gpr_T0(rA(ctx->opcode));
2248 gen_op_load_gpr_T1(rB(ctx->opcode));
2252 gen_op_check_reservation();
2256 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2258 if (rA(ctx->opcode) == 0) {
2259 gen_op_load_gpr_T0(rB(ctx->opcode));
2261 gen_op_load_gpr_T0(rA(ctx->opcode));
2262 gen_op_load_gpr_T1(rB(ctx->opcode));
2270 GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
2274 /*** Segment register manipulation ***/
2275 /* Supervisor only: */
2277 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2279 #if defined(CONFIG_USER_ONLY)
2282 if (!ctx->supervisor) {
2286 gen_op_load_sr(SR(ctx->opcode));
2287 gen_op_store_T0_gpr(rD(ctx->opcode));
2292 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2294 #if defined(CONFIG_USER_ONLY)
2297 if (!ctx->supervisor) {
2301 gen_op_load_gpr_T1(rB(ctx->opcode));
2303 gen_op_store_T0_gpr(rD(ctx->opcode));
2308 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2310 #if defined(CONFIG_USER_ONLY)
2313 if (!ctx->supervisor) {
2317 gen_op_load_gpr_T0(rS(ctx->opcode));
2318 gen_op_store_sr(SR(ctx->opcode));
2323 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2325 #if defined(CONFIG_USER_ONLY)
2328 if (!ctx->supervisor) {
2332 gen_op_load_gpr_T0(rS(ctx->opcode));
2333 gen_op_load_gpr_T1(rB(ctx->opcode));
2334 gen_op_store_srin();
2338 /*** Lookaside buffer management ***/
2339 /* Optional & supervisor only: */
2341 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
2343 #if defined(CONFIG_USER_ONLY)
2346 if (!ctx->supervisor) {
2348 fprintf(logfile, "%s: ! supervisor\n", __func__);
2358 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
2360 #if defined(CONFIG_USER_ONLY)
2363 if (!ctx->supervisor) {
2367 gen_op_load_gpr_T0(rB(ctx->opcode));
2374 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
2376 #if defined(CONFIG_USER_ONLY)
2379 if (!ctx->supervisor) {
2383 /* This has no effect: it should ensure that all previous
2384 * tlbie have completed
2390 /*** External control ***/
2393 #if defined(CONFIG_USER_ONLY)
2394 #define op_eciwx() gen_op_eciwx_raw()
2395 #define op_ecowx() gen_op_ecowx_raw()
2397 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2398 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2399 static GenOpFunc *gen_op_eciwx[] = {
2401 &gen_op_eciwx_kernel,
2403 static GenOpFunc *gen_op_ecowx[] = {
2405 &gen_op_ecowx_kernel,
2409 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2411 /* Should check EAR[E] & alignment ! */
2412 if (rA(ctx->opcode) == 0) {
2413 gen_op_load_gpr_T0(rB(ctx->opcode));
2415 gen_op_load_gpr_T0(rA(ctx->opcode));
2416 gen_op_load_gpr_T1(rB(ctx->opcode));
2420 gen_op_store_T0_gpr(rD(ctx->opcode));
2424 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2426 /* Should check EAR[E] & alignment ! */
2427 if (rA(ctx->opcode) == 0) {
2428 gen_op_load_gpr_T0(rB(ctx->opcode));
2430 gen_op_load_gpr_T0(rA(ctx->opcode));
2431 gen_op_load_gpr_T1(rB(ctx->opcode));
2434 gen_op_load_gpr_T2(rS(ctx->opcode));
2438 /* End opcode list */
2439 GEN_OPCODE_MARK(end);
2441 /*****************************************************************************/
2445 int fflush (FILE *stream);
2447 /* Main ppc opcodes table:
2448 * at init, all opcodes are invalids
2450 static opc_handler_t *ppc_opcodes[0x40];
2454 PPC_DIRECT = 0, /* Opcode routine */
2455 PPC_INDIRECT = 1, /* Indirect opcode table */
2458 static inline int is_indirect_opcode (void *handler)
2460 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2463 static inline opc_handler_t **ind_table(void *handler)
2465 return (opc_handler_t **)((unsigned long)handler & ~3);
2468 /* Instruction table creation */
2469 /* Opcodes tables creation */
2470 static void fill_new_table (opc_handler_t **table, int len)
2474 for (i = 0; i < len; i++)
2475 table[i] = &invalid_handler;
2478 static int create_new_table (opc_handler_t **table, unsigned char idx)
2480 opc_handler_t **tmp;
2482 tmp = malloc(0x20 * sizeof(opc_handler_t));
2485 fill_new_table(tmp, 0x20);
2486 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2491 static int insert_in_table (opc_handler_t **table, unsigned char idx,
2492 opc_handler_t *handler)
2494 if (table[idx] != &invalid_handler)
2496 table[idx] = handler;
2501 static int register_direct_insn (opc_handler_t **ppc_opcodes,
2502 unsigned char idx, opc_handler_t *handler)
2504 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2505 printf("*** ERROR: opcode %02x already assigned in main "
2506 "opcode table\n", idx);
2513 static int register_ind_in_table (opc_handler_t **table,
2514 unsigned char idx1, unsigned char idx2,
2515 opc_handler_t *handler)
2517 if (table[idx1] == &invalid_handler) {
2518 if (create_new_table(table, idx1) < 0) {
2519 printf("*** ERROR: unable to create indirect table "
2520 "idx=%02x\n", idx1);
2524 if (!is_indirect_opcode(table[idx1])) {
2525 printf("*** ERROR: idx %02x already assigned to a direct "
2530 if (handler != NULL &&
2531 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2532 printf("*** ERROR: opcode %02x already assigned in "
2533 "opcode table %02x\n", idx2, idx1);
2540 static int register_ind_insn (opc_handler_t **ppc_opcodes,
2541 unsigned char idx1, unsigned char idx2,
2542 opc_handler_t *handler)
2546 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2551 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2552 unsigned char idx1, unsigned char idx2,
2553 unsigned char idx3, opc_handler_t *handler)
2555 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2556 printf("*** ERROR: unable to join indirect table idx "
2557 "[%02x-%02x]\n", idx1, idx2);
2560 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2562 printf("*** ERROR: unable to insert opcode "
2563 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2570 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2572 if (insn->opc2 != 0xFF) {
2573 if (insn->opc3 != 0xFF) {
2574 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2575 insn->opc3, &insn->handler) < 0)
2578 if (register_ind_insn(ppc_opcodes, insn->opc1,
2579 insn->opc2, &insn->handler) < 0)
2583 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2590 static int test_opcode_table (opc_handler_t **table, int len)
2594 for (i = 0, count = 0; i < len; i++) {
2595 /* Consistency fixup */
2596 if (table[i] == NULL)
2597 table[i] = &invalid_handler;
2598 if (table[i] != &invalid_handler) {
2599 if (is_indirect_opcode(table[i])) {
2600 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2603 table[i] = &invalid_handler;
2616 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2618 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2619 printf("*** WARNING: no opcode defined !\n");
2622 #define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
2623 #define SPR_UR SPR_RIGHTS(0, 0)
2624 #define SPR_UW SPR_RIGHTS(1, 0)
2625 #define SPR_SR SPR_RIGHTS(0, 1)
2626 #define SPR_SW SPR_RIGHTS(1, 1)
2628 #define spr_set_rights(spr, rights) \
2630 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2633 static void init_spr_rights (uint32_t pvr)
2636 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2638 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2640 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
2642 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
2644 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
2645 /* DSISR (SPR 18) */
2646 spr_set_rights(DSISR, SPR_SR | SPR_SW);
2648 spr_set_rights(DAR, SPR_SR | SPR_SW);
2650 spr_set_rights(DECR, SPR_SR | SPR_SW);
2652 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2654 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2656 spr_set_rights(SRR1, SPR_SR | SPR_SW);
2657 /* SPRG0 (SPR 272) */
2658 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
2659 /* SPRG1 (SPR 273) */
2660 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
2661 /* SPRG2 (SPR 274) */
2662 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
2663 /* SPRG3 (SPR 275) */
2664 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
2666 spr_set_rights(ASR, SPR_SR | SPR_SW);
2668 spr_set_rights(EAR, SPR_SR | SPR_SW);
2670 spr_set_rights(O_TBL, SPR_SW);
2672 spr_set_rights(O_TBU, SPR_SW);
2674 spr_set_rights(PVR, SPR_SR);
2675 /* IBAT0U (SPR 528) */
2676 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
2677 /* IBAT0L (SPR 529) */
2678 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
2679 /* IBAT1U (SPR 530) */
2680 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
2681 /* IBAT1L (SPR 531) */
2682 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
2683 /* IBAT2U (SPR 532) */
2684 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
2685 /* IBAT2L (SPR 533) */
2686 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
2687 /* IBAT3U (SPR 534) */
2688 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
2689 /* IBAT3L (SPR 535) */
2690 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
2691 /* DBAT0U (SPR 536) */
2692 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
2693 /* DBAT0L (SPR 537) */
2694 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
2695 /* DBAT1U (SPR 538) */
2696 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
2697 /* DBAT1L (SPR 539) */
2698 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
2699 /* DBAT2U (SPR 540) */
2700 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
2701 /* DBAT2L (SPR 541) */
2702 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
2703 /* DBAT3U (SPR 542) */
2704 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
2705 /* DBAT3L (SPR 543) */
2706 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
2707 /* FPECR (SPR 1022) */
2708 spr_set_rights(FPECR, SPR_SR | SPR_SW);
2709 /* Special registers for PPC 604 */
2710 if ((pvr & 0xFFFF0000) == 0x00040000) {
2712 spr_set_rights(IABR , SPR_SR | SPR_SW);
2713 /* DABR (SPR 1013) */
2714 spr_set_rights(DABR, SPR_SR | SPR_SW);
2716 spr_set_rights(HID0, SPR_SR | SPR_SW);
2718 spr_set_rights(PIR, SPR_SR | SPR_SW);
2720 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2722 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2724 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2726 spr_set_rights(SIA, SPR_SR | SPR_SW);
2728 spr_set_rights(SDA, SPR_SR | SPR_SW);
2730 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2731 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2732 (pvr & 0xFFFF0000) == 0x70000000) {
2734 spr_set_rights(HID0, SPR_SR | SPR_SW);
2736 spr_set_rights(HID1, SPR_SR | SPR_SW);
2738 spr_set_rights(IABR, SPR_SR | SPR_SW);
2740 spr_set_rights(ICTC, SPR_SR | SPR_SW);
2742 spr_set_rights(L2CR, SPR_SR | SPR_SW);
2744 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2746 spr_set_rights(MMCR1, SPR_SR | SPR_SW);
2748 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2750 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2752 spr_set_rights(PMC3, SPR_SR | SPR_SW);
2754 spr_set_rights(PMC4, SPR_SR | SPR_SW);
2756 spr_set_rights(SIA, SPR_SR | SPR_SW);
2758 spr_set_rights(SDA, SPR_SR | SPR_SW);
2760 spr_set_rights(THRM1, SPR_SR | SPR_SW);
2762 spr_set_rights(THRM2, SPR_SR | SPR_SW);
2764 spr_set_rights(THRM3, SPR_SR | SPR_SW);
2766 spr_set_rights(UMMCR0, SPR_UR | SPR_UW);
2768 spr_set_rights(UMMCR1, SPR_UR | SPR_UW);
2770 spr_set_rights(UPMC1, SPR_UR | SPR_UW);
2772 spr_set_rights(UPMC2, SPR_UR | SPR_UW);
2774 spr_set_rights(UPMC3, SPR_UR | SPR_UW);
2776 spr_set_rights(UPMC4, SPR_UR | SPR_UW);
2778 spr_set_rights(USIA, SPR_UR | SPR_UW);
2780 /* MPC755 has special registers */
2781 if (pvr == 0x00083100) {
2783 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2785 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2787 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2789 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2791 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2793 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2795 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2797 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2799 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2801 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2803 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2805 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2807 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2809 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2811 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2813 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2815 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2817 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2819 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2821 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2823 spr_set_rights(DMISS, SPR_SR | SPR_SW);
2825 spr_set_rights(DCMP, SPR_SR | SPR_SW);
2827 spr_set_rights(DHASH1, SPR_SR | SPR_SW);
2829 spr_set_rights(DHASH2, SPR_SR | SPR_SW);
2831 spr_set_rights(IMISS, SPR_SR | SPR_SW);
2833 spr_set_rights(ICMP, SPR_SR | SPR_SW);
2835 spr_set_rights(RPA, SPR_SR | SPR_SW);
2837 spr_set_rights(HID2, SPR_SR | SPR_SW);
2839 spr_set_rights(L2PM, SPR_SR | SPR_SW);
2843 /*****************************************************************************/
2844 /* PPC "main stream" common instructions (no optional ones) */
2846 typedef struct ppc_proc_t {
2851 typedef struct ppc_def_t {
2853 unsigned long pvr_mask;
2857 static ppc_proc_t ppc_proc_common = {
2858 .flags = PPC_COMMON,
2862 static ppc_proc_t ppc_proc_G3 = {
2867 static ppc_def_t ppc_defs[] =
2869 /* MPC740/745/750/755 (G3) */
2872 .pvr_mask = 0xFFFF0000,
2873 .proc = &ppc_proc_G3,
2875 /* IBM 750FX (G3 embedded) */
2878 .pvr_mask = 0xFFFF0000,
2879 .proc = &ppc_proc_G3,
2881 /* Fallback (generic PPC) */
2884 .pvr_mask = 0x00000000,
2885 .proc = &ppc_proc_common,
2889 static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
2894 fill_new_table(ppc_opcodes, 0x40);
2895 for (i = 0; ; i++) {
2896 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2897 (pvr & ppc_defs[i].pvr_mask)) {
2898 flags = ppc_defs[i].proc->flags;
2903 for (opc = &opc_start + 1; opc != &opc_end; opc++) {
2904 if ((opc->handler.type & flags) != 0)
2905 if (register_insn(ppc_opcodes, opc) < 0) {
2906 printf("*** ERROR initializing PPC instruction "
2907 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2912 fix_opcode_tables(ppc_opcodes);
2918 /*****************************************************************************/
2919 /* Misc PPC helpers */
2921 void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags)
2925 fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2926 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
2927 _load_xer(env), _load_msr(env));
2928 for (i = 0; i < 32; i++) {
2930 fprintf(f, "GPR%02d:", i);
2931 fprintf(f, " %08x", env->gpr[i]);
2935 fprintf(f, "CR: 0x");
2936 for (i = 0; i < 8; i++)
2937 fprintf(f, "%01x", env->crf[i]);
2939 for (i = 0; i < 8; i++) {
2941 if (env->crf[i] & 0x08)
2943 else if (env->crf[i] & 0x04)
2945 else if (env->crf[i] & 0x02)
2947 fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
2950 fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
2951 cpu_ppc_load_tbl(env));
2952 for (i = 0; i < 16; i++) {
2954 fprintf(f, "FPR%02d:", i);
2955 fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
2959 fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
2960 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
2961 fprintf(f, "reservation 0x%08x\n", env->reserve);
2965 #if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2966 int setup_machine (CPUPPCState *env, uint32_t mid);
2969 CPUPPCState *cpu_ppc_init(void)
2975 env = qemu_mallocz(sizeof(CPUPPCState));
2978 #if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2979 setup_machine(env, 0);
2981 // env->spr[PVR] = 0; /* Basic PPC */
2982 env->spr[PVR] = 0x00080100; /* G3 CPU */
2983 // env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2984 // env->spr[PVR] = 0x00070100; /* IBM 750FX */
2987 #if defined (DO_SINGLE_STEP)
2988 /* Single step trace mode */
2991 msr_fp = 1; /* Allow floating point exceptions */
2992 msr_me = 1; /* Allow machine check exceptions */
2993 #if defined(CONFIG_USER_ONLY)
2995 cpu_ppc_register(env, 0x00080000);
2997 env->nip = 0xFFFFFFFC;
2999 env->access_type = ACCESS_INT;
3000 cpu_single_env = env;
3004 int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3006 env->spr[PVR] = pvr;
3007 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3009 init_spr_rights(env->spr[PVR]);
3014 void cpu_ppc_close(CPUPPCState *env)
3016 /* Should also remove all opcode tables... */
3020 /*****************************************************************************/
3021 int print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
3024 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3027 DisasContext ctx, *ctxp = &ctx;
3028 opc_handler_t **table, *handler;
3030 uint16_t *gen_opc_end;
3034 gen_opc_ptr = gen_opc_buf;
3035 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3036 gen_opparam_ptr = gen_opparam_buf;
3039 ctx.exception = EXCP_NONE;
3040 #if defined(CONFIG_USER_ONLY)
3043 ctx.supervisor = 1 - msr_pr;
3044 ctx.mem_idx = (1 - msr_pr);
3046 #if defined (DO_SINGLE_STEP)
3047 /* Single step trace mode */
3050 env->access_type = ACCESS_CODE;
3051 /* Set env in case of segfault during code fetch */
3052 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
3055 fprintf(logfile, "Search PC...\n");
3056 j = gen_opc_ptr - gen_opc_buf;
3060 gen_opc_instr_start[lj++] = 0;
3061 gen_opc_pc[lj] = ctx.nip;
3062 gen_opc_instr_start[lj] = 1;
3065 #if defined PPC_DEBUG_DISAS
3066 if (loglevel & CPU_LOG_TB_IN_ASM) {
3067 fprintf(logfile, "----------------\n");
3068 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
3069 ctx.nip, 1 - msr_pr, msr_ir);
3072 ctx.opcode = ldl_code((void *)ctx.nip);
3073 #if defined PPC_DEBUG_DISAS
3074 if (loglevel & CPU_LOG_TB_IN_ASM) {
3075 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3076 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3081 table = ppc_opcodes;
3082 handler = table[opc1(ctx.opcode)];
3083 if (is_indirect_opcode(handler)) {
3084 table = ind_table(handler);
3085 handler = table[opc2(ctx.opcode)];
3086 if (is_indirect_opcode(handler)) {
3087 table = ind_table(handler);
3088 handler = table[opc3(ctx.opcode)];
3091 /* Is opcode *REALLY* valid ? */
3092 if (handler->handler == &gen_invalid) {
3094 fprintf(logfile, "invalid/unsupported opcode: "
3095 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3096 opc1(ctx.opcode), opc2(ctx.opcode),
3097 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3099 printf("invalid/unsupported opcode: "
3100 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3101 opc1(ctx.opcode), opc2(ctx.opcode),
3102 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3105 if ((ctx.opcode & handler->inval) != 0) {
3107 fprintf(logfile, "invalid bits: %08x for opcode: "
3108 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3109 ctx.opcode & handler->inval, opc1(ctx.opcode),
3110 opc2(ctx.opcode), opc3(ctx.opcode),
3111 ctx.opcode, ctx.nip - 4);
3113 printf("invalid bits: %08x for opcode: "
3114 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3115 ctx.opcode & handler->inval, opc1(ctx.opcode),
3116 opc2(ctx.opcode), opc3(ctx.opcode),
3117 ctx.opcode, ctx.nip - 4);
3123 (*(handler->handler))(&ctx);
3124 /* Check trace mode exceptions */
3125 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3126 /* Check in single step trace mode
3127 * we need to stop except if:
3128 * - rfi, trap or syscall
3129 * - first instruction of an exception handler
3131 (msr_se && (ctx.nip < 0x100 ||
3133 (ctx.nip & 0xFC) != 0x04) &&
3134 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3135 ctx.exception != EXCP_TRAP)) {
3136 RET_EXCP(ctxp, EXCP_TRACE, 0);
3138 /* if we reach a page boundary, stop generation */
3139 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
3140 RET_EXCP(ctxp, EXCP_BRANCH, 0);
3143 if (ctx.exception == EXCP_NONE) {
3144 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3145 } else if (ctx.exception != EXCP_BRANCH) {
3149 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3150 * do bad business and then qemu crashes !
3154 /* Generate the return instruction */
3156 *gen_opc_ptr = INDEX_op_end;
3158 j = gen_opc_ptr - gen_opc_buf;
3161 gen_opc_instr_start[lj++] = 0;
3169 tb->size = ctx.nip - pc_start;
3172 if (loglevel & CPU_LOG_TB_CPU) {
3173 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3174 cpu_ppc_dump_state(env, logfile, 0);
3176 if (loglevel & CPU_LOG_TB_IN_ASM) {
3177 fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
3178 disas(logfile, (void *)pc_start, ctx.nip - pc_start, 0, 0);
3179 fprintf(logfile, "\n");
3181 if (loglevel & CPU_LOG_TB_OP) {
3182 fprintf(logfile, "OP:\n");
3183 dump_ops(gen_opc_buf, gen_opparam_buf);
3184 fprintf(logfile, "\n");
3187 env->access_type = ACCESS_INT;
3192 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3194 return gen_intermediate_code_internal(env, tb, 0);
3197 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3199 return gen_intermediate_code_internal(env, tb, 1);