2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
25 #include "op_helper.h"
27 #define MEMSUFFIX _raw
28 #include "op_helper.h"
29 #include "op_helper_mem.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #define MEMSUFFIX _user
32 #include "op_helper.h"
33 #include "op_helper_mem.h"
34 #define MEMSUFFIX _kernel
35 #include "op_helper.h"
36 #include "op_helper_mem.h"
37 #define MEMSUFFIX _hypv
38 #include "op_helper.h"
39 #include "op_helper_mem.h"
43 //#define DEBUG_EXCEPTIONS
44 //#define DEBUG_SOFTWARE_TLB
46 /*****************************************************************************/
47 /* Exceptions processing helpers */
49 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
51 raise_exception_err(env, exception, error_code);
54 void helper_raise_debug (void)
56 raise_exception(env, EXCP_DEBUG);
59 /*****************************************************************************/
60 /* Registers load and stores */
61 target_ulong helper_load_cr (void)
63 return (env->crf[0] << 28) |
73 void helper_store_cr (target_ulong val, uint32_t mask)
77 for (i = 0, sh = 7; i < 8; i++, sh--) {
79 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
83 #if defined(TARGET_PPC64)
84 void do_store_pri (int prio)
86 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
87 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
91 target_ulong ppc_load_dump_spr (int sprn)
94 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
95 sprn, sprn, env->spr[sprn]);
98 return env->spr[sprn];
101 void ppc_store_dump_spr (int sprn, target_ulong val)
104 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
105 sprn, sprn, env->spr[sprn], val);
107 env->spr[sprn] = val;
110 /*****************************************************************************/
111 /* Memory load and stores */
113 static always_inline target_ulong get_addr(target_ulong addr)
115 #if defined(TARGET_PPC64)
120 return (uint32_t)addr;
123 void helper_lmw (target_ulong addr, uint32_t reg)
125 #ifdef CONFIG_USER_ONLY
126 #define ldfun ldl_raw
128 int (*ldfun)(target_ulong);
130 switch (env->mmu_idx) {
132 case 0: ldfun = ldl_user;
134 case 1: ldfun = ldl_kernel;
136 case 2: ldfun = ldl_hypv;
140 for (; reg < 32; reg++, addr += 4) {
142 env->gpr[reg] = bswap32(ldfun(get_addr(addr)));
144 env->gpr[reg] = ldfun(get_addr(addr));
148 void helper_stmw (target_ulong addr, uint32_t reg)
150 #ifdef CONFIG_USER_ONLY
151 #define stfun stl_raw
153 void (*stfun)(target_ulong, int);
155 switch (env->mmu_idx) {
157 case 0: stfun = stl_user;
159 case 1: stfun = stl_kernel;
161 case 2: stfun = stl_hypv;
165 for (; reg < 32; reg++, addr += 4) {
167 stfun(get_addr(addr), bswap32((uint32_t)env->gpr[reg]));
169 stfun(get_addr(addr), (uint32_t)env->gpr[reg]);
173 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
176 #ifdef CONFIG_USER_ONLY
177 #define ldfunl ldl_raw
178 #define ldfunb ldub_raw
180 int (*ldfunl)(target_ulong);
181 int (*ldfunb)(target_ulong);
183 switch (env->mmu_idx) {
191 ldfunb = ldub_kernel;
199 for (; nb > 3; nb -= 4, addr += 4) {
200 env->gpr[reg] = ldfunl(get_addr(addr));
201 reg = (reg + 1) % 32;
203 if (unlikely(nb > 0)) {
205 for (sh = 24; nb > 0; nb--, addr++, sh -= 8) {
206 env->gpr[reg] |= ldfunb(get_addr(addr)) << sh;
210 /* PPC32 specification says we must generate an exception if
211 * rA is in the range of registers to be loaded.
212 * In an other hand, IBM says this is valid, but rA won't be loaded.
213 * For now, I'll follow the spec...
215 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
217 if (likely(xer_bc != 0)) {
218 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
219 (reg < rb && (reg + xer_bc) > rb))) {
220 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
222 POWERPC_EXCP_INVAL_LSWX);
224 helper_lsw(addr, xer_bc, reg);
229 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
232 #ifdef CONFIG_USER_ONLY
233 #define stfunl stl_raw
234 #define stfunb stb_raw
236 void (*stfunl)(target_ulong, int);
237 void (*stfunb)(target_ulong, int);
239 switch (env->mmu_idx) {
256 for (; nb > 3; nb -= 4, addr += 4) {
257 stfunl(get_addr(addr), env->gpr[reg]);
258 reg = (reg + 1) % 32;
260 if (unlikely(nb > 0)) {
261 for (sh = 24; nb > 0; nb--, addr++, sh -= 8)
262 stfunb(get_addr(addr), (env->gpr[reg] >> sh) & 0xFF);
266 static void do_dcbz(target_ulong addr, int dcache_line_size)
268 target_long mask = get_addr(~(dcache_line_size - 1));
270 #ifdef CONFIG_USER_ONLY
271 #define stfun stl_raw
273 void (*stfun)(target_ulong, int);
275 switch (env->mmu_idx) {
277 case 0: stfun = stl_user;
279 case 1: stfun = stl_kernel;
281 case 2: stfun = stl_hypv;
286 for (i = 0 ; i < dcache_line_size ; i += 4) {
289 if ((env->reserve & mask) == addr)
290 env->reserve = (target_ulong)-1ULL;
293 void helper_dcbz(target_ulong addr)
295 do_dcbz(addr, env->dcache_line_size);
298 void helper_dcbz_970(target_ulong addr)
300 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
303 do_dcbz(addr, env->dcache_line_size);
306 void helper_icbi(target_ulong addr)
310 addr = get_addr(addr & ~(env->dcache_line_size - 1));
311 /* Invalidate one cache line :
312 * PowerPC specification says this is to be treated like a load
313 * (not a fetch) by the MMU. To be sure it will be so,
314 * do the load "by hand".
316 #ifdef CONFIG_USER_ONLY
319 switch (env->mmu_idx) {
321 case 0: tmp = ldl_user(addr);
323 case 1: tmp = ldl_kernel(addr);
325 case 2: tmp = ldl_hypv(addr);
329 tb_invalidate_page_range(addr, addr + env->icache_line_size);
332 /*****************************************************************************/
333 /* Fixed point operations helpers */
334 #if defined(TARGET_PPC64)
336 /* multiply high word */
337 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
341 muls64(&tl, &th, arg1, arg2);
345 /* multiply high word unsigned */
346 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
350 mulu64(&tl, &th, arg1, arg2);
354 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
359 muls64(&tl, (uint64_t *)&th, arg1, arg2);
360 /* If th != 0 && th != -1, then we had an overflow */
361 if (likely((uint64_t)(th + 1) <= 1)) {
362 env->xer &= ~(1 << XER_OV);
364 env->xer |= (1 << XER_OV) | (1 << XER_SO);
370 target_ulong helper_cntlzw (target_ulong t)
375 #if defined(TARGET_PPC64)
376 target_ulong helper_cntlzd (target_ulong t)
382 /* shift right arithmetic helper */
383 target_ulong helper_sraw (target_ulong value, target_ulong shift)
387 if (likely(!(shift & 0x20))) {
388 if (likely((uint32_t)shift != 0)) {
390 ret = (int32_t)value >> shift;
391 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
392 env->xer &= ~(1 << XER_CA);
394 env->xer |= (1 << XER_CA);
397 ret = (int32_t)value;
398 env->xer &= ~(1 << XER_CA);
401 ret = (int32_t)value >> 31;
403 env->xer |= (1 << XER_CA);
405 env->xer &= ~(1 << XER_CA);
408 return (target_long)ret;
411 #if defined(TARGET_PPC64)
412 target_ulong helper_srad (target_ulong value, target_ulong shift)
416 if (likely(!(shift & 0x40))) {
417 if (likely((uint64_t)shift != 0)) {
419 ret = (int64_t)value >> shift;
420 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
421 env->xer &= ~(1 << XER_CA);
423 env->xer |= (1 << XER_CA);
426 ret = (int64_t)value;
427 env->xer &= ~(1 << XER_CA);
430 ret = (int64_t)value >> 63;
432 env->xer |= (1 << XER_CA);
434 env->xer &= ~(1 << XER_CA);
441 target_ulong helper_popcntb (target_ulong val)
443 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
444 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
445 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
449 #if defined(TARGET_PPC64)
450 target_ulong helper_popcntb_64 (target_ulong val)
452 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
453 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
454 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
459 /*****************************************************************************/
460 /* Floating point operations helpers */
461 uint64_t helper_float32_to_float64(uint32_t arg)
466 d.d = float32_to_float64(f.f, &env->fp_status);
470 uint32_t helper_float64_to_float32(uint64_t arg)
475 f.f = float64_to_float32(d.d, &env->fp_status);
479 static always_inline int fpisneg (float64 d)
485 return u.ll >> 63 != 0;
488 static always_inline int isden (float64 d)
494 return ((u.ll >> 52) & 0x7FF) == 0;
497 static always_inline int iszero (float64 d)
503 return (u.ll & ~0x8000000000000000ULL) == 0;
506 static always_inline int isinfinity (float64 d)
512 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
513 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
516 #ifdef CONFIG_SOFTFLOAT
517 static always_inline int isfinite (float64 d)
523 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
526 static always_inline int isnormal (float64 d)
532 uint32_t exp = (u.ll >> 52) & 0x7FF;
533 return ((0 < exp) && (exp < 0x7FF));
537 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
543 isneg = fpisneg(farg.d);
544 if (unlikely(float64_is_nan(farg.d))) {
545 if (float64_is_signaling_nan(farg.d)) {
546 /* Signaling NaN: flags are undefined */
552 } else if (unlikely(isinfinity(farg.d))) {
559 if (iszero(farg.d)) {
567 /* Denormalized numbers */
570 /* Normalized numbers */
581 /* We update FPSCR_FPRF */
582 env->fpscr &= ~(0x1F << FPSCR_FPRF);
583 env->fpscr |= ret << FPSCR_FPRF;
585 /* We just need fpcc to update Rc1 */
589 /* Floating-point invalid operations exception */
590 static always_inline uint64_t fload_invalid_op_excp (int op)
596 if (op & POWERPC_EXCP_FP_VXSNAN) {
597 /* Operation on signaling NaN */
598 env->fpscr |= 1 << FPSCR_VXSNAN;
600 if (op & POWERPC_EXCP_FP_VXSOFT) {
601 /* Software-defined condition */
602 env->fpscr |= 1 << FPSCR_VXSOFT;
604 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
605 case POWERPC_EXCP_FP_VXISI:
606 /* Magnitude subtraction of infinities */
607 env->fpscr |= 1 << FPSCR_VXISI;
609 case POWERPC_EXCP_FP_VXIDI:
610 /* Division of infinity by infinity */
611 env->fpscr |= 1 << FPSCR_VXIDI;
613 case POWERPC_EXCP_FP_VXZDZ:
614 /* Division of zero by zero */
615 env->fpscr |= 1 << FPSCR_VXZDZ;
617 case POWERPC_EXCP_FP_VXIMZ:
618 /* Multiplication of zero by infinity */
619 env->fpscr |= 1 << FPSCR_VXIMZ;
621 case POWERPC_EXCP_FP_VXVC:
622 /* Ordered comparison of NaN */
623 env->fpscr |= 1 << FPSCR_VXVC;
624 env->fpscr &= ~(0xF << FPSCR_FPCC);
625 env->fpscr |= 0x11 << FPSCR_FPCC;
626 /* We must update the target FPR before raising the exception */
628 env->exception_index = POWERPC_EXCP_PROGRAM;
629 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
630 /* Update the floating-point enabled exception summary */
631 env->fpscr |= 1 << FPSCR_FEX;
632 /* Exception is differed */
636 case POWERPC_EXCP_FP_VXSQRT:
637 /* Square root of a negative number */
638 env->fpscr |= 1 << FPSCR_VXSQRT;
640 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
642 /* Set the result to quiet NaN */
644 env->fpscr &= ~(0xF << FPSCR_FPCC);
645 env->fpscr |= 0x11 << FPSCR_FPCC;
648 case POWERPC_EXCP_FP_VXCVI:
649 /* Invalid conversion */
650 env->fpscr |= 1 << FPSCR_VXCVI;
651 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
653 /* Set the result to quiet NaN */
655 env->fpscr &= ~(0xF << FPSCR_FPCC);
656 env->fpscr |= 0x11 << FPSCR_FPCC;
660 /* Update the floating-point invalid operation summary */
661 env->fpscr |= 1 << FPSCR_VX;
662 /* Update the floating-point exception summary */
663 env->fpscr |= 1 << FPSCR_FX;
665 /* Update the floating-point enabled exception summary */
666 env->fpscr |= 1 << FPSCR_FEX;
667 if (msr_fe0 != 0 || msr_fe1 != 0)
668 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
673 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
675 env->fpscr |= 1 << FPSCR_ZX;
676 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
677 /* Update the floating-point exception summary */
678 env->fpscr |= 1 << FPSCR_FX;
680 /* Update the floating-point enabled exception summary */
681 env->fpscr |= 1 << FPSCR_FEX;
682 if (msr_fe0 != 0 || msr_fe1 != 0) {
683 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
684 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
687 /* Set the result to infinity */
688 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
689 arg1 |= 0x7FFULL << 52;
694 static always_inline void float_overflow_excp (void)
696 env->fpscr |= 1 << FPSCR_OX;
697 /* Update the floating-point exception summary */
698 env->fpscr |= 1 << FPSCR_FX;
700 /* XXX: should adjust the result */
701 /* Update the floating-point enabled exception summary */
702 env->fpscr |= 1 << FPSCR_FEX;
703 /* We must update the target FPR before raising the exception */
704 env->exception_index = POWERPC_EXCP_PROGRAM;
705 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
707 env->fpscr |= 1 << FPSCR_XX;
708 env->fpscr |= 1 << FPSCR_FI;
712 static always_inline void float_underflow_excp (void)
714 env->fpscr |= 1 << FPSCR_UX;
715 /* Update the floating-point exception summary */
716 env->fpscr |= 1 << FPSCR_FX;
718 /* XXX: should adjust the result */
719 /* Update the floating-point enabled exception summary */
720 env->fpscr |= 1 << FPSCR_FEX;
721 /* We must update the target FPR before raising the exception */
722 env->exception_index = POWERPC_EXCP_PROGRAM;
723 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
727 static always_inline void float_inexact_excp (void)
729 env->fpscr |= 1 << FPSCR_XX;
730 /* Update the floating-point exception summary */
731 env->fpscr |= 1 << FPSCR_FX;
733 /* Update the floating-point enabled exception summary */
734 env->fpscr |= 1 << FPSCR_FEX;
735 /* We must update the target FPR before raising the exception */
736 env->exception_index = POWERPC_EXCP_PROGRAM;
737 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
741 static always_inline void fpscr_set_rounding_mode (void)
745 /* Set rounding mode */
748 /* Best approximation (round to nearest) */
749 rnd_type = float_round_nearest_even;
752 /* Smaller magnitude (round toward zero) */
753 rnd_type = float_round_to_zero;
756 /* Round toward +infinite */
757 rnd_type = float_round_up;
761 /* Round toward -infinite */
762 rnd_type = float_round_down;
765 set_float_rounding_mode(rnd_type, &env->fp_status);
768 void helper_fpscr_setbit (uint32_t bit)
772 prev = (env->fpscr >> bit) & 1;
773 env->fpscr |= 1 << bit;
777 env->fpscr |= 1 << FPSCR_FX;
781 env->fpscr |= 1 << FPSCR_FX;
786 env->fpscr |= 1 << FPSCR_FX;
791 env->fpscr |= 1 << FPSCR_FX;
796 env->fpscr |= 1 << FPSCR_FX;
809 env->fpscr |= 1 << FPSCR_VX;
810 env->fpscr |= 1 << FPSCR_FX;
817 env->error_code = POWERPC_EXCP_FP;
819 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
821 env->error_code |= POWERPC_EXCP_FP_VXISI;
823 env->error_code |= POWERPC_EXCP_FP_VXIDI;
825 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
827 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
829 env->error_code |= POWERPC_EXCP_FP_VXVC;
831 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
833 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
835 env->error_code |= POWERPC_EXCP_FP_VXCVI;
842 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
849 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
856 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
863 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
869 fpscr_set_rounding_mode();
874 /* Update the floating-point enabled exception summary */
875 env->fpscr |= 1 << FPSCR_FEX;
876 /* We have to update Rc1 before raising the exception */
877 env->exception_index = POWERPC_EXCP_PROGRAM;
883 void helper_store_fpscr (uint64_t arg, uint32_t mask)
886 * We use only the 32 LSB of the incoming fpr
894 new |= prev & 0x90000000;
895 for (i = 0; i < 7; i++) {
896 if (mask & (1 << i)) {
897 env->fpscr &= ~(0xF << (4 * i));
898 env->fpscr |= new & (0xF << (4 * i));
901 /* Update VX and FEX */
903 env->fpscr |= 1 << FPSCR_VX;
905 env->fpscr &= ~(1 << FPSCR_VX);
906 if ((fpscr_ex & fpscr_eex) != 0) {
907 env->fpscr |= 1 << FPSCR_FEX;
908 env->exception_index = POWERPC_EXCP_PROGRAM;
909 /* XXX: we should compute it properly */
910 env->error_code = POWERPC_EXCP_FP;
913 env->fpscr &= ~(1 << FPSCR_FEX);
914 fpscr_set_rounding_mode();
917 void helper_float_check_status (void)
919 #ifdef CONFIG_SOFTFLOAT
920 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
921 (env->error_code & POWERPC_EXCP_FP)) {
922 /* Differred floating-point exception after target FPR update */
923 if (msr_fe0 != 0 || msr_fe1 != 0)
924 raise_exception_err(env, env->exception_index, env->error_code);
925 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
926 float_overflow_excp();
927 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
928 float_underflow_excp();
929 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
930 float_inexact_excp();
933 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
934 (env->error_code & POWERPC_EXCP_FP)) {
935 /* Differred floating-point exception after target FPR update */
936 if (msr_fe0 != 0 || msr_fe1 != 0)
937 raise_exception_err(env, env->exception_index, env->error_code);
943 #ifdef CONFIG_SOFTFLOAT
944 void helper_reset_fpstatus (void)
946 env->fp_status.float_exception_flags = 0;
951 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
953 CPU_DoubleU farg1, farg2;
957 #if USE_PRECISE_EMULATION
958 if (unlikely(float64_is_signaling_nan(farg1.d) ||
959 float64_is_signaling_nan(farg2.d))) {
961 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
962 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
963 fpisneg(farg1.d) == fpisneg(farg2.d))) {
964 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
966 /* Magnitude subtraction of infinities */
967 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
970 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
976 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
978 CPU_DoubleU farg1, farg2;
982 #if USE_PRECISE_EMULATION
984 if (unlikely(float64_is_signaling_nan(farg1.d) ||
985 float64_is_signaling_nan(farg2.d))) {
986 /* sNaN subtraction */
987 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
988 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
989 fpisneg(farg1.d) != fpisneg(farg2.d))) {
990 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
992 /* Magnitude subtraction of infinities */
993 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
997 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1003 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1005 CPU_DoubleU farg1, farg2;
1009 #if USE_PRECISE_EMULATION
1010 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1011 float64_is_signaling_nan(farg2.d))) {
1012 /* sNaN multiplication */
1013 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1014 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
1015 (iszero(farg1.d) && isinfinity(farg2.d)))) {
1016 /* Multiplication of zero by infinity */
1017 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1019 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1023 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1029 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1031 CPU_DoubleU farg1, farg2;
1035 #if USE_PRECISE_EMULATION
1036 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1037 float64_is_signaling_nan(farg2.d))) {
1039 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1040 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
1041 /* Division of infinity by infinity */
1042 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1043 } else if (unlikely(iszero(farg2.d))) {
1044 if (iszero(farg1.d)) {
1045 /* Division of zero by zero */
1046 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1048 /* Division by zero */
1049 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1052 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1055 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1061 uint64_t helper_fabs (uint64_t arg)
1066 farg.d = float64_abs(farg.d);
1071 uint64_t helper_fnabs (uint64_t arg)
1076 farg.d = float64_abs(farg.d);
1077 farg.d = float64_chs(farg.d);
1082 uint64_t helper_fneg (uint64_t arg)
1087 farg.d = float64_chs(farg.d);
1091 /* fctiw - fctiw. */
1092 uint64_t helper_fctiw (uint64_t arg)
1097 if (unlikely(float64_is_signaling_nan(farg.d))) {
1098 /* sNaN conversion */
1099 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1100 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1101 /* qNan / infinity conversion */
1102 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1104 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1105 #if USE_PRECISE_EMULATION
1106 /* XXX: higher bits are not supposed to be significant.
1107 * to make tests easier, return the same as a real PowerPC 750
1109 farg.ll |= 0xFFF80000ULL << 32;
1115 /* fctiwz - fctiwz. */
1116 uint64_t helper_fctiwz (uint64_t arg)
1121 if (unlikely(float64_is_signaling_nan(farg.d))) {
1122 /* sNaN conversion */
1123 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1124 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1125 /* qNan / infinity conversion */
1126 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1128 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1129 #if USE_PRECISE_EMULATION
1130 /* XXX: higher bits are not supposed to be significant.
1131 * to make tests easier, return the same as a real PowerPC 750
1133 farg.ll |= 0xFFF80000ULL << 32;
1139 #if defined(TARGET_PPC64)
1140 /* fcfid - fcfid. */
1141 uint64_t helper_fcfid (uint64_t arg)
1144 farg.d = int64_to_float64(arg, &env->fp_status);
1148 /* fctid - fctid. */
1149 uint64_t helper_fctid (uint64_t arg)
1154 if (unlikely(float64_is_signaling_nan(farg.d))) {
1155 /* sNaN conversion */
1156 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1157 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1158 /* qNan / infinity conversion */
1159 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1161 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1166 /* fctidz - fctidz. */
1167 uint64_t helper_fctidz (uint64_t arg)
1172 if (unlikely(float64_is_signaling_nan(farg.d))) {
1173 /* sNaN conversion */
1174 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1175 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1176 /* qNan / infinity conversion */
1177 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1179 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1186 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1191 if (unlikely(float64_is_signaling_nan(farg.d))) {
1193 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1194 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1195 /* qNan / infinity round */
1196 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1198 set_float_rounding_mode(rounding_mode, &env->fp_status);
1199 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1200 /* Restore rounding mode from FPSCR */
1201 fpscr_set_rounding_mode();
1206 uint64_t helper_frin (uint64_t arg)
1208 return do_fri(arg, float_round_nearest_even);
1211 uint64_t helper_friz (uint64_t arg)
1213 return do_fri(arg, float_round_to_zero);
1216 uint64_t helper_frip (uint64_t arg)
1218 return do_fri(arg, float_round_up);
1221 uint64_t helper_frim (uint64_t arg)
1223 return do_fri(arg, float_round_down);
1226 /* fmadd - fmadd. */
1227 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1229 CPU_DoubleU farg1, farg2, farg3;
1234 #if USE_PRECISE_EMULATION
1235 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1236 float64_is_signaling_nan(farg2.d) ||
1237 float64_is_signaling_nan(farg3.d))) {
1238 /* sNaN operation */
1239 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1242 /* This is the way the PowerPC specification defines it */
1243 float128 ft0_128, ft1_128;
1245 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1246 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1247 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1248 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1249 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1250 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1252 /* This is OK on x86 hosts */
1253 farg1.d = (farg1.d * farg2.d) + farg3.d;
1257 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1258 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1263 /* fmsub - fmsub. */
1264 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1266 CPU_DoubleU farg1, farg2, farg3;
1271 #if USE_PRECISE_EMULATION
1272 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1273 float64_is_signaling_nan(farg2.d) ||
1274 float64_is_signaling_nan(farg3.d))) {
1275 /* sNaN operation */
1276 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1279 /* This is the way the PowerPC specification defines it */
1280 float128 ft0_128, ft1_128;
1282 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1283 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1284 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1285 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1286 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1287 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1289 /* This is OK on x86 hosts */
1290 farg1.d = (farg1.d * farg2.d) - farg3.d;
1294 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1295 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1300 /* fnmadd - fnmadd. */
1301 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1303 CPU_DoubleU farg1, farg2, farg3;
1309 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1310 float64_is_signaling_nan(farg2.d) ||
1311 float64_is_signaling_nan(farg3.d))) {
1312 /* sNaN operation */
1313 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1315 #if USE_PRECISE_EMULATION
1317 /* This is the way the PowerPC specification defines it */
1318 float128 ft0_128, ft1_128;
1320 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1321 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1322 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1323 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1324 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1325 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1327 /* This is OK on x86 hosts */
1328 farg1.d = (farg1.d * farg2.d) + farg3.d;
1331 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1332 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1334 if (likely(!isnan(farg1.d)))
1335 farg1.d = float64_chs(farg1.d);
1340 /* fnmsub - fnmsub. */
1341 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1343 CPU_DoubleU farg1, farg2, farg3;
1349 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1350 float64_is_signaling_nan(farg2.d) ||
1351 float64_is_signaling_nan(farg3.d))) {
1352 /* sNaN operation */
1353 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1355 #if USE_PRECISE_EMULATION
1357 /* This is the way the PowerPC specification defines it */
1358 float128 ft0_128, ft1_128;
1360 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1361 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1362 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1363 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1364 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1365 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1367 /* This is OK on x86 hosts */
1368 farg1.d = (farg1.d * farg2.d) - farg3.d;
1371 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1372 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1374 if (likely(!isnan(farg1.d)))
1375 farg1.d = float64_chs(farg1.d);
1381 uint64_t helper_frsp (uint64_t arg)
1386 #if USE_PRECISE_EMULATION
1387 if (unlikely(float64_is_signaling_nan(farg.d))) {
1388 /* sNaN square root */
1389 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1391 fard.d = float64_to_float32(farg.d, &env->fp_status);
1394 farg.d = float64_to_float32(farg.d, &env->fp_status);
1399 /* fsqrt - fsqrt. */
1400 uint64_t helper_fsqrt (uint64_t arg)
1405 if (unlikely(float64_is_signaling_nan(farg.d))) {
1406 /* sNaN square root */
1407 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1408 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1409 /* Square root of a negative nonzero number */
1410 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1412 farg.d = float64_sqrt(farg.d, &env->fp_status);
1418 uint64_t helper_fre (uint64_t arg)
1423 if (unlikely(float64_is_signaling_nan(farg.d))) {
1424 /* sNaN reciprocal */
1425 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1426 } else if (unlikely(iszero(farg.d))) {
1427 /* Zero reciprocal */
1428 farg.ll = float_zero_divide_excp(1.0, farg.d);
1429 } else if (likely(isnormal(farg.d))) {
1430 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1432 if (farg.ll == 0x8000000000000000ULL) {
1433 farg.ll = 0xFFF0000000000000ULL;
1434 } else if (farg.ll == 0x0000000000000000ULL) {
1435 farg.ll = 0x7FF0000000000000ULL;
1436 } else if (isnan(farg.d)) {
1437 farg.ll = 0x7FF8000000000000ULL;
1438 } else if (fpisneg(farg.d)) {
1439 farg.ll = 0x8000000000000000ULL;
1441 farg.ll = 0x0000000000000000ULL;
1448 uint64_t helper_fres (uint64_t arg)
1453 if (unlikely(float64_is_signaling_nan(farg.d))) {
1454 /* sNaN reciprocal */
1455 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1456 } else if (unlikely(iszero(farg.d))) {
1457 /* Zero reciprocal */
1458 farg.ll = float_zero_divide_excp(1.0, farg.d);
1459 } else if (likely(isnormal(farg.d))) {
1460 #if USE_PRECISE_EMULATION
1461 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1462 farg.d = float64_to_float32(farg.d, &env->fp_status);
1464 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1467 if (farg.ll == 0x8000000000000000ULL) {
1468 farg.ll = 0xFFF0000000000000ULL;
1469 } else if (farg.ll == 0x0000000000000000ULL) {
1470 farg.ll = 0x7FF0000000000000ULL;
1471 } else if (isnan(farg.d)) {
1472 farg.ll = 0x7FF8000000000000ULL;
1473 } else if (fpisneg(farg.d)) {
1474 farg.ll = 0x8000000000000000ULL;
1476 farg.ll = 0x0000000000000000ULL;
1482 /* frsqrte - frsqrte. */
1483 uint64_t helper_frsqrte (uint64_t arg)
1488 if (unlikely(float64_is_signaling_nan(farg.d))) {
1489 /* sNaN reciprocal square root */
1490 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1491 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1492 /* Reciprocal square root of a negative nonzero number */
1493 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1494 } else if (likely(isnormal(farg.d))) {
1495 farg.d = float64_sqrt(farg.d, &env->fp_status);
1496 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1498 if (farg.ll == 0x8000000000000000ULL) {
1499 farg.ll = 0xFFF0000000000000ULL;
1500 } else if (farg.ll == 0x0000000000000000ULL) {
1501 farg.ll = 0x7FF0000000000000ULL;
1502 } else if (isnan(farg.d)) {
1503 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1504 } else if (fpisneg(farg.d)) {
1505 farg.ll = 0x7FF8000000000000ULL;
1507 farg.ll = 0x0000000000000000ULL;
1514 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1516 CPU_DoubleU farg1, farg2, farg3;
1522 if (!fpisneg(farg1.d) || iszero(farg1.d))
1528 uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
1530 CPU_DoubleU farg1, farg2;
1535 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1536 float64_is_signaling_nan(farg2.d))) {
1537 /* sNaN comparison */
1538 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1540 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1542 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1548 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1549 env->fpscr |= ret << FPSCR_FPRF;
1553 uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
1555 CPU_DoubleU farg1, farg2;
1560 if (unlikely(float64_is_nan(farg1.d) ||
1561 float64_is_nan(farg2.d))) {
1562 if (float64_is_signaling_nan(farg1.d) ||
1563 float64_is_signaling_nan(farg2.d)) {
1564 /* sNaN comparison */
1565 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1566 POWERPC_EXCP_FP_VXVC);
1568 /* qNaN comparison */
1569 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1572 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1574 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1580 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1581 env->fpscr |= ret << FPSCR_FPRF;
1585 #if !defined (CONFIG_USER_ONLY)
1586 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1588 void do_store_msr (void)
1590 T0 = hreg_store_msr(env, T0, 0);
1592 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1593 raise_exception(env, T0);
1597 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1598 target_ulong msrm, int keep_msrh)
1600 #if defined(TARGET_PPC64)
1601 if (msr & (1ULL << MSR_SF)) {
1602 nip = (uint64_t)nip;
1603 msr &= (uint64_t)msrm;
1605 nip = (uint32_t)nip;
1606 msr = (uint32_t)(msr & msrm);
1608 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1611 nip = (uint32_t)nip;
1612 msr &= (uint32_t)msrm;
1614 /* XXX: beware: this is false if VLE is supported */
1615 env->nip = nip & ~((target_ulong)0x00000003);
1616 hreg_store_msr(env, msr, 1);
1617 #if defined (DEBUG_OP)
1618 cpu_dump_rfi(env->nip, env->msr);
1620 /* No need to raise an exception here,
1621 * as rfi is always the last insn of a TB
1623 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1628 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1629 ~((target_ulong)0xFFFF0000), 1);
1632 #if defined(TARGET_PPC64)
1635 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1636 ~((target_ulong)0xFFFF0000), 0);
1639 void do_hrfid (void)
1641 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1642 ~((target_ulong)0xFFFF0000), 0);
1647 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1649 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1650 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1651 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1652 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1653 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1654 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1658 #if defined(TARGET_PPC64)
1659 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1661 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1662 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1663 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1664 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1665 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1666 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1670 /*****************************************************************************/
1671 /* PowerPC 601 specific instructions (POWER bridge) */
1672 void do_POWER_abso (void)
1674 if ((int32_t)T0 == INT32_MIN) {
1676 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1677 } else if ((int32_t)T0 < 0) {
1679 env->xer &= ~(1 << XER_OV);
1681 env->xer &= ~(1 << XER_OV);
1685 void do_POWER_clcs (void)
1689 /* Instruction cache line size */
1690 T0 = env->icache_line_size;
1693 /* Data cache line size */
1694 T0 = env->dcache_line_size;
1697 /* Minimum cache line size */
1698 T0 = env->icache_line_size < env->dcache_line_size ?
1699 env->icache_line_size : env->dcache_line_size;
1702 /* Maximum cache line size */
1703 T0 = env->icache_line_size > env->dcache_line_size ?
1704 env->icache_line_size : env->dcache_line_size;
1712 void do_POWER_div (void)
1716 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1718 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1719 env->spr[SPR_MQ] = 0;
1721 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1722 env->spr[SPR_MQ] = tmp % T1;
1723 T0 = tmp / (int32_t)T1;
1727 void do_POWER_divo (void)
1731 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1733 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1734 env->spr[SPR_MQ] = 0;
1735 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1737 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1738 env->spr[SPR_MQ] = tmp % T1;
1740 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1741 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1743 env->xer &= ~(1 << XER_OV);
1749 void do_POWER_divs (void)
1751 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1753 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1754 env->spr[SPR_MQ] = 0;
1756 env->spr[SPR_MQ] = T0 % T1;
1757 T0 = (int32_t)T0 / (int32_t)T1;
1761 void do_POWER_divso (void)
1763 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1765 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1766 env->spr[SPR_MQ] = 0;
1767 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1769 T0 = (int32_t)T0 / (int32_t)T1;
1770 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1771 env->xer &= ~(1 << XER_OV);
1775 void do_POWER_dozo (void)
1777 if ((int32_t)T1 > (int32_t)T0) {
1780 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1781 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1782 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1784 env->xer &= ~(1 << XER_OV);
1788 env->xer &= ~(1 << XER_OV);
1792 void do_POWER_maskg (void)
1796 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1799 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1800 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1801 if ((uint32_t)T0 > (uint32_t)T1)
1807 void do_POWER_mulo (void)
1811 tmp = (uint64_t)T0 * (uint64_t)T1;
1812 env->spr[SPR_MQ] = tmp >> 32;
1814 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1815 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1817 env->xer &= ~(1 << XER_OV);
1821 #if !defined (CONFIG_USER_ONLY)
1822 void do_POWER_rac (void)
1827 /* We don't have to generate many instances of this instruction,
1828 * as rac is supervisor only.
1830 /* XXX: FIX THIS: Pretend we have no BAT */
1831 nb_BATs = env->nb_BATs;
1833 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1835 env->nb_BATs = nb_BATs;
1838 void do_POWER_rfsvc (void)
1840 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1843 void do_store_hid0_601 (void)
1847 hid0 = env->spr[SPR_HID0];
1848 if ((T0 ^ hid0) & 0x00000008) {
1849 /* Change current endianness */
1850 env->hflags &= ~(1 << MSR_LE);
1851 env->hflags_nmsr &= ~(1 << MSR_LE);
1852 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1853 env->hflags |= env->hflags_nmsr;
1854 if (loglevel != 0) {
1855 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1856 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1859 env->spr[SPR_HID0] = T0;
1863 /*****************************************************************************/
1864 /* 602 specific instructions */
1865 /* mfrom is the most crazy instruction ever seen, imho ! */
1866 /* Real implementation uses a ROM table. Do the same */
1867 #define USE_MFROM_ROM_TABLE
1868 target_ulong helper_602_mfrom (target_ulong arg)
1870 if (likely(arg < 602)) {
1871 #if defined(USE_MFROM_ROM_TABLE)
1872 #include "mfrom_table.c"
1873 return mfrom_ROM_table[T0];
1876 /* Extremly decomposed:
1878 * return 256 * log10(10 + 1.0) + 0.5
1881 d = float64_div(d, 256, &env->fp_status);
1883 d = exp10(d); // XXX: use float emulation function
1884 d = float64_add(d, 1.0, &env->fp_status);
1885 d = log10(d); // XXX: use float emulation function
1886 d = float64_mul(d, 256, &env->fp_status);
1887 d = float64_add(d, 0.5, &env->fp_status);
1888 return float64_round_to_int(d, &env->fp_status);
1895 /*****************************************************************************/
1896 /* Embedded PowerPC specific helpers */
1898 /* XXX: to be improved to check access rights when in user-mode */
1899 void do_load_dcr (void)
1903 if (unlikely(env->dcr_env == NULL)) {
1904 if (loglevel != 0) {
1905 fprintf(logfile, "No DCR environment\n");
1907 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1908 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1909 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1910 if (loglevel != 0) {
1911 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1913 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1914 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1920 void do_store_dcr (void)
1922 if (unlikely(env->dcr_env == NULL)) {
1923 if (loglevel != 0) {
1924 fprintf(logfile, "No DCR environment\n");
1926 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1927 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1928 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1929 if (loglevel != 0) {
1930 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1932 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1933 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1937 #if !defined(CONFIG_USER_ONLY)
1938 void do_40x_rfci (void)
1940 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1941 ~((target_ulong)0xFFFF0000), 0);
1946 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1947 ~((target_ulong)0x3FFF0000), 0);
1952 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1953 ~((target_ulong)0x3FFF0000), 0);
1956 void do_rfmci (void)
1958 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1959 ~((target_ulong)0x3FFF0000), 0);
1962 void do_load_403_pb (int num)
1967 void do_store_403_pb (int num)
1969 if (likely(env->pb[num] != T0)) {
1971 /* Should be optimized */
1978 void do_440_dlmzb (void)
1984 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1985 if ((T0 & mask) == 0)
1989 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1990 if ((T1 & mask) == 0)
1998 /*****************************************************************************/
1999 /* SPE extension helpers */
2000 /* Use a table to make this quicker */
2001 static uint8_t hbrev[16] = {
2002 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2003 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2006 static always_inline uint8_t byte_reverse (uint8_t val)
2008 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2011 static always_inline uint32_t word_reverse (uint32_t val)
2013 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2014 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2017 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2018 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2020 uint32_t a, b, d, mask;
2022 mask = UINT32_MAX >> (32 - MASKBITS);
2025 d = word_reverse(1 + word_reverse(a | ~b));
2026 return (arg1 & ~mask) | (d & b);
2029 uint32_t helper_cntlsw32 (uint32_t val)
2031 if (val & 0x80000000)
2037 uint32_t helper_cntlzw32 (uint32_t val)
2042 /* Single-precision floating-point conversions */
2043 static always_inline uint32_t efscfsi (uint32_t val)
2047 u.f = int32_to_float32(val, &env->spe_status);
2052 static always_inline uint32_t efscfui (uint32_t val)
2056 u.f = uint32_to_float32(val, &env->spe_status);
2061 static always_inline int32_t efsctsi (uint32_t val)
2066 /* NaN are not treated the same way IEEE 754 does */
2067 if (unlikely(isnan(u.f)))
2070 return float32_to_int32(u.f, &env->spe_status);
2073 static always_inline uint32_t efsctui (uint32_t val)
2078 /* NaN are not treated the same way IEEE 754 does */
2079 if (unlikely(isnan(u.f)))
2082 return float32_to_uint32(u.f, &env->spe_status);
2085 static always_inline uint32_t efsctsiz (uint32_t val)
2090 /* NaN are not treated the same way IEEE 754 does */
2091 if (unlikely(isnan(u.f)))
2094 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2097 static always_inline uint32_t efsctuiz (uint32_t val)
2102 /* NaN are not treated the same way IEEE 754 does */
2103 if (unlikely(isnan(u.f)))
2106 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2109 static always_inline uint32_t efscfsf (uint32_t val)
2114 u.f = int32_to_float32(val, &env->spe_status);
2115 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2116 u.f = float32_div(u.f, tmp, &env->spe_status);
2121 static always_inline uint32_t efscfuf (uint32_t val)
2126 u.f = uint32_to_float32(val, &env->spe_status);
2127 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2128 u.f = float32_div(u.f, tmp, &env->spe_status);
2133 static always_inline uint32_t efsctsf (uint32_t val)
2139 /* NaN are not treated the same way IEEE 754 does */
2140 if (unlikely(isnan(u.f)))
2142 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2143 u.f = float32_mul(u.f, tmp, &env->spe_status);
2145 return float32_to_int32(u.f, &env->spe_status);
2148 static always_inline uint32_t efsctuf (uint32_t val)
2154 /* NaN are not treated the same way IEEE 754 does */
2155 if (unlikely(isnan(u.f)))
2157 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2158 u.f = float32_mul(u.f, tmp, &env->spe_status);
2160 return float32_to_uint32(u.f, &env->spe_status);
2163 #define HELPER_SPE_SINGLE_CONV(name) \
2164 uint32_t helper_e##name (uint32_t val) \
2166 return e##name(val); \
2169 HELPER_SPE_SINGLE_CONV(fscfsi);
2171 HELPER_SPE_SINGLE_CONV(fscfui);
2173 HELPER_SPE_SINGLE_CONV(fscfuf);
2175 HELPER_SPE_SINGLE_CONV(fscfsf);
2177 HELPER_SPE_SINGLE_CONV(fsctsi);
2179 HELPER_SPE_SINGLE_CONV(fsctui);
2181 HELPER_SPE_SINGLE_CONV(fsctsiz);
2183 HELPER_SPE_SINGLE_CONV(fsctuiz);
2185 HELPER_SPE_SINGLE_CONV(fsctsf);
2187 HELPER_SPE_SINGLE_CONV(fsctuf);
2189 #define HELPER_SPE_VECTOR_CONV(name) \
2190 uint64_t helper_ev##name (uint64_t val) \
2192 return ((uint64_t)e##name(val >> 32) << 32) | \
2193 (uint64_t)e##name(val); \
2196 HELPER_SPE_VECTOR_CONV(fscfsi);
2198 HELPER_SPE_VECTOR_CONV(fscfui);
2200 HELPER_SPE_VECTOR_CONV(fscfuf);
2202 HELPER_SPE_VECTOR_CONV(fscfsf);
2204 HELPER_SPE_VECTOR_CONV(fsctsi);
2206 HELPER_SPE_VECTOR_CONV(fsctui);
2208 HELPER_SPE_VECTOR_CONV(fsctsiz);
2210 HELPER_SPE_VECTOR_CONV(fsctuiz);
2212 HELPER_SPE_VECTOR_CONV(fsctsf);
2214 HELPER_SPE_VECTOR_CONV(fsctuf);
2216 /* Single-precision floating-point arithmetic */
2217 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2222 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2226 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2231 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2235 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2240 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2244 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2249 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2253 #define HELPER_SPE_SINGLE_ARITH(name) \
2254 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2256 return e##name(op1, op2); \
2259 HELPER_SPE_SINGLE_ARITH(fsadd);
2261 HELPER_SPE_SINGLE_ARITH(fssub);
2263 HELPER_SPE_SINGLE_ARITH(fsmul);
2265 HELPER_SPE_SINGLE_ARITH(fsdiv);
2267 #define HELPER_SPE_VECTOR_ARITH(name) \
2268 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2270 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2271 (uint64_t)e##name(op1, op2); \
2274 HELPER_SPE_VECTOR_ARITH(fsadd);
2276 HELPER_SPE_VECTOR_ARITH(fssub);
2278 HELPER_SPE_VECTOR_ARITH(fsmul);
2280 HELPER_SPE_VECTOR_ARITH(fsdiv);
2282 /* Single-precision floating-point comparisons */
2283 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2288 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2291 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2296 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2299 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2304 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2307 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2309 /* XXX: TODO: test special values (NaN, infinites, ...) */
2310 return efststlt(op1, op2);
2313 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2315 /* XXX: TODO: test special values (NaN, infinites, ...) */
2316 return efststgt(op1, op2);
2319 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2321 /* XXX: TODO: test special values (NaN, infinites, ...) */
2322 return efststeq(op1, op2);
2325 #define HELPER_SINGLE_SPE_CMP(name) \
2326 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2328 return e##name(op1, op2) << 2; \
2331 HELPER_SINGLE_SPE_CMP(fststlt);
2333 HELPER_SINGLE_SPE_CMP(fststgt);
2335 HELPER_SINGLE_SPE_CMP(fststeq);
2337 HELPER_SINGLE_SPE_CMP(fscmplt);
2339 HELPER_SINGLE_SPE_CMP(fscmpgt);
2341 HELPER_SINGLE_SPE_CMP(fscmpeq);
2343 static always_inline uint32_t evcmp_merge (int t0, int t1)
2345 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2348 #define HELPER_VECTOR_SPE_CMP(name) \
2349 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2351 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2354 HELPER_VECTOR_SPE_CMP(fststlt);
2356 HELPER_VECTOR_SPE_CMP(fststgt);
2358 HELPER_VECTOR_SPE_CMP(fststeq);
2360 HELPER_VECTOR_SPE_CMP(fscmplt);
2362 HELPER_VECTOR_SPE_CMP(fscmpgt);
2364 HELPER_VECTOR_SPE_CMP(fscmpeq);
2366 /* Double-precision floating-point conversion */
2367 uint64_t helper_efdcfsi (uint32_t val)
2371 u.d = int32_to_float64(val, &env->spe_status);
2376 uint64_t helper_efdcfsid (uint64_t val)
2380 u.d = int64_to_float64(val, &env->spe_status);
2385 uint64_t helper_efdcfui (uint32_t val)
2389 u.d = uint32_to_float64(val, &env->spe_status);
2394 uint64_t helper_efdcfuid (uint64_t val)
2398 u.d = uint64_to_float64(val, &env->spe_status);
2403 uint32_t helper_efdctsi (uint64_t val)
2408 /* NaN are not treated the same way IEEE 754 does */
2409 if (unlikely(isnan(u.d)))
2412 return float64_to_int32(u.d, &env->spe_status);
2415 uint32_t helper_efdctui (uint64_t val)
2420 /* NaN are not treated the same way IEEE 754 does */
2421 if (unlikely(isnan(u.d)))
2424 return float64_to_uint32(u.d, &env->spe_status);
2427 uint32_t helper_efdctsiz (uint64_t val)
2432 /* NaN are not treated the same way IEEE 754 does */
2433 if (unlikely(isnan(u.d)))
2436 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2439 uint64_t helper_efdctsidz (uint64_t val)
2444 /* NaN are not treated the same way IEEE 754 does */
2445 if (unlikely(isnan(u.d)))
2448 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2451 uint32_t helper_efdctuiz (uint64_t val)
2456 /* NaN are not treated the same way IEEE 754 does */
2457 if (unlikely(isnan(u.d)))
2460 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2463 uint64_t helper_efdctuidz (uint64_t val)
2468 /* NaN are not treated the same way IEEE 754 does */
2469 if (unlikely(isnan(u.d)))
2472 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2475 uint64_t helper_efdcfsf (uint32_t val)
2480 u.d = int32_to_float64(val, &env->spe_status);
2481 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2482 u.d = float64_div(u.d, tmp, &env->spe_status);
2487 uint64_t helper_efdcfuf (uint32_t val)
2492 u.d = uint32_to_float64(val, &env->spe_status);
2493 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2494 u.d = float64_div(u.d, tmp, &env->spe_status);
2499 uint32_t helper_efdctsf (uint64_t val)
2505 /* NaN are not treated the same way IEEE 754 does */
2506 if (unlikely(isnan(u.d)))
2508 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2509 u.d = float64_mul(u.d, tmp, &env->spe_status);
2511 return float64_to_int32(u.d, &env->spe_status);
2514 uint32_t helper_efdctuf (uint64_t val)
2520 /* NaN are not treated the same way IEEE 754 does */
2521 if (unlikely(isnan(u.d)))
2523 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2524 u.d = float64_mul(u.d, tmp, &env->spe_status);
2526 return float64_to_uint32(u.d, &env->spe_status);
2529 uint32_t helper_efscfd (uint64_t val)
2535 u2.f = float64_to_float32(u1.d, &env->spe_status);
2540 uint64_t helper_efdcfs (uint32_t val)
2546 u2.d = float32_to_float64(u1.f, &env->spe_status);
2551 /* Double precision fixed-point arithmetic */
2552 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2557 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2561 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2566 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2570 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2575 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2579 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2584 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2588 /* Double precision floating point helpers */
2589 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2594 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2597 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2602 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2605 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2610 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2613 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2615 /* XXX: TODO: test special values (NaN, infinites, ...) */
2616 return helper_efdtstlt(op1, op2);
2619 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2621 /* XXX: TODO: test special values (NaN, infinites, ...) */
2622 return helper_efdtstgt(op1, op2);
2625 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2627 /* XXX: TODO: test special values (NaN, infinites, ...) */
2628 return helper_efdtsteq(op1, op2);
2631 /*****************************************************************************/
2632 /* Softmmu support */
2633 #if !defined (CONFIG_USER_ONLY)
2635 #define MMUSUFFIX _mmu
2638 #include "softmmu_template.h"
2641 #include "softmmu_template.h"
2644 #include "softmmu_template.h"
2647 #include "softmmu_template.h"
2649 /* try to fill the TLB and return an exception if error. If retaddr is
2650 NULL, it means that the function was called in C code (i.e. not
2651 from generated code or from helper.c) */
2652 /* XXX: fix it to restore all registers */
2653 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2655 TranslationBlock *tb;
2656 CPUState *saved_env;
2660 /* XXX: hack to restore env in all cases, even if not called from
2663 env = cpu_single_env;
2664 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2665 if (unlikely(ret != 0)) {
2666 if (likely(retaddr)) {
2667 /* now we have a real cpu fault */
2668 pc = (unsigned long)retaddr;
2669 tb = tb_find_pc(pc);
2671 /* the PC is inside the translated code. It means that we have
2672 a virtual CPU fault */
2673 cpu_restore_state(tb, env, pc, NULL);
2676 raise_exception_err(env, env->exception_index, env->error_code);
2681 /* Software driven TLBs management */
2682 /* PowerPC 602/603 software TLB load instructions helpers */
2683 static void helper_load_6xx_tlb (target_ulong new_EPN, int is_code)
2685 target_ulong RPN, CMP, EPN;
2688 RPN = env->spr[SPR_RPA];
2690 CMP = env->spr[SPR_ICMP];
2691 EPN = env->spr[SPR_IMISS];
2693 CMP = env->spr[SPR_DCMP];
2694 EPN = env->spr[SPR_DMISS];
2696 way = (env->spr[SPR_SRR1] >> 17) & 1;
2697 #if defined (DEBUG_SOFTWARE_TLB)
2698 if (loglevel != 0) {
2699 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2700 " PTE1 " ADDRX " way %d\n",
2701 __func__, T0, EPN, CMP, RPN, way);
2704 /* Store this TLB */
2705 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2706 way, is_code, CMP, RPN);
2709 void helper_load_6xx_tlbd (target_ulong EPN)
2711 helper_load_6xx_tlb(EPN, 0);
2714 void helper_load_6xx_tlbi (target_ulong EPN)
2716 helper_load_6xx_tlb(EPN, 1);
2719 /* PowerPC 74xx software TLB load instructions helpers */
2720 static void helper_load_74xx_tlb (target_ulong new_EPN, int is_code)
2722 target_ulong RPN, CMP, EPN;
2725 RPN = env->spr[SPR_PTELO];
2726 CMP = env->spr[SPR_PTEHI];
2727 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2728 way = env->spr[SPR_TLBMISS] & 0x3;
2729 #if defined (DEBUG_SOFTWARE_TLB)
2730 if (loglevel != 0) {
2731 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2732 " PTE1 " ADDRX " way %d\n",
2733 __func__, T0, EPN, CMP, RPN, way);
2736 /* Store this TLB */
2737 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2738 way, is_code, CMP, RPN);
2741 void helper_load_74xx_tlbd (target_ulong EPN)
2743 helper_load_74xx_tlb(EPN, 0);
2746 void helper_load_74xx_tlbi (target_ulong EPN)
2748 helper_load_74xx_tlb(EPN, 1);
2751 static always_inline target_ulong booke_tlb_to_page_size (int size)
2753 return 1024 << (2 * size);
2756 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2760 switch (page_size) {
2794 #if defined (TARGET_PPC64)
2795 case 0x000100000000ULL:
2798 case 0x000400000000ULL:
2801 case 0x001000000000ULL:
2804 case 0x004000000000ULL:
2807 case 0x010000000000ULL:
2819 /* Helpers for 4xx TLB management */
2820 void do_4xx_tlbre_lo (void)
2826 tlb = &env->tlb[T0].tlbe;
2828 if (tlb->prot & PAGE_VALID)
2830 size = booke_page_size_to_tlb(tlb->size);
2831 if (size < 0 || size > 0x7)
2834 env->spr[SPR_40x_PID] = tlb->PID;
2837 void do_4xx_tlbre_hi (void)
2842 tlb = &env->tlb[T0].tlbe;
2844 if (tlb->prot & PAGE_EXEC)
2846 if (tlb->prot & PAGE_WRITE)
2850 void do_4xx_tlbwe_hi (void)
2853 target_ulong page, end;
2855 #if defined (DEBUG_SOFTWARE_TLB)
2856 if (loglevel != 0) {
2857 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2861 tlb = &env->tlb[T0].tlbe;
2862 /* Invalidate previous TLB (if it's valid) */
2863 if (tlb->prot & PAGE_VALID) {
2864 end = tlb->EPN + tlb->size;
2865 #if defined (DEBUG_SOFTWARE_TLB)
2866 if (loglevel != 0) {
2867 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2868 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2871 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2872 tlb_flush_page(env, page);
2874 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2875 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2876 * If this ever occurs, one should use the ppcemb target instead
2877 * of the ppc or ppc64 one
2879 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2880 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2881 "are not supported (%d)\n",
2882 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2884 tlb->EPN = T1 & ~(tlb->size - 1);
2886 tlb->prot |= PAGE_VALID;
2888 tlb->prot &= ~PAGE_VALID;
2890 /* XXX: TO BE FIXED */
2891 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2893 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2894 tlb->attr = T1 & 0xFF;
2895 #if defined (DEBUG_SOFTWARE_TLB)
2896 if (loglevel != 0) {
2897 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2898 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2899 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2900 tlb->prot & PAGE_READ ? 'r' : '-',
2901 tlb->prot & PAGE_WRITE ? 'w' : '-',
2902 tlb->prot & PAGE_EXEC ? 'x' : '-',
2903 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2906 /* Invalidate new TLB (if valid) */
2907 if (tlb->prot & PAGE_VALID) {
2908 end = tlb->EPN + tlb->size;
2909 #if defined (DEBUG_SOFTWARE_TLB)
2910 if (loglevel != 0) {
2911 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2912 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2915 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2916 tlb_flush_page(env, page);
2920 void do_4xx_tlbwe_lo (void)
2924 #if defined (DEBUG_SOFTWARE_TLB)
2925 if (loglevel != 0) {
2926 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2930 tlb = &env->tlb[T0].tlbe;
2931 tlb->RPN = T1 & 0xFFFFFC00;
2932 tlb->prot = PAGE_READ;
2934 tlb->prot |= PAGE_EXEC;
2936 tlb->prot |= PAGE_WRITE;
2937 #if defined (DEBUG_SOFTWARE_TLB)
2938 if (loglevel != 0) {
2939 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2940 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2941 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2942 tlb->prot & PAGE_READ ? 'r' : '-',
2943 tlb->prot & PAGE_WRITE ? 'w' : '-',
2944 tlb->prot & PAGE_EXEC ? 'x' : '-',
2945 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2950 /* PowerPC 440 TLB management */
2951 void do_440_tlbwe (int word)
2954 target_ulong EPN, RPN, size;
2957 #if defined (DEBUG_SOFTWARE_TLB)
2958 if (loglevel != 0) {
2959 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2960 __func__, word, T0, T1);
2965 tlb = &env->tlb[T0].tlbe;
2968 /* Just here to please gcc */
2970 EPN = T1 & 0xFFFFFC00;
2971 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2974 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2975 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2979 tlb->attr |= (T1 >> 8) & 1;
2981 tlb->prot |= PAGE_VALID;
2983 if (tlb->prot & PAGE_VALID) {
2984 tlb->prot &= ~PAGE_VALID;
2988 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2993 RPN = T1 & 0xFFFFFC0F;
2994 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2999 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
3000 tlb->prot = tlb->prot & PAGE_VALID;
3002 tlb->prot |= PAGE_READ << 4;
3004 tlb->prot |= PAGE_WRITE << 4;
3006 tlb->prot |= PAGE_EXEC << 4;
3008 tlb->prot |= PAGE_READ;
3010 tlb->prot |= PAGE_WRITE;
3012 tlb->prot |= PAGE_EXEC;
3017 void do_440_tlbre (int word)
3023 tlb = &env->tlb[T0].tlbe;
3026 /* Just here to please gcc */
3029 size = booke_page_size_to_tlb(tlb->size);
3030 if (size < 0 || size > 0xF)
3033 if (tlb->attr & 0x1)
3035 if (tlb->prot & PAGE_VALID)
3037 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3038 env->spr[SPR_440_MMUCR] |= tlb->PID;
3044 T0 = tlb->attr & ~0x1;
3045 if (tlb->prot & (PAGE_READ << 4))
3047 if (tlb->prot & (PAGE_WRITE << 4))
3049 if (tlb->prot & (PAGE_EXEC << 4))
3051 if (tlb->prot & PAGE_READ)
3053 if (tlb->prot & PAGE_WRITE)
3055 if (tlb->prot & PAGE_EXEC)
3060 #endif /* !CONFIG_USER_ONLY */