2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
25 #include "op_helper.h"
28 //#define DEBUG_EXCEPTIONS
29 //#define DEBUG_SOFTWARE_TLB
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
34 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
36 raise_exception_err(env, exception, error_code);
39 void helper_raise_debug (void)
41 raise_exception(env, EXCP_DEBUG);
44 /*****************************************************************************/
45 /* Registers load and stores */
46 target_ulong helper_load_cr (void)
48 return (env->crf[0] << 28) |
58 void helper_store_cr (target_ulong val, uint32_t mask)
62 for (i = 0, sh = 7; i < 8; i++, sh--) {
64 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
68 #if defined(TARGET_PPC64)
69 void do_store_pri (int prio)
71 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
72 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
76 target_ulong ppc_load_dump_spr (int sprn)
79 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
80 sprn, sprn, env->spr[sprn]);
83 return env->spr[sprn];
86 void ppc_store_dump_spr (int sprn, target_ulong val)
89 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
90 sprn, sprn, env->spr[sprn], val);
95 /*****************************************************************************/
96 /* Memory load and stores */
98 static always_inline target_ulong get_addr(target_ulong addr)
100 #if defined(TARGET_PPC64)
105 return (uint32_t)addr;
108 void helper_lmw (target_ulong addr, uint32_t reg)
110 for (; reg < 32; reg++, addr += 4) {
112 env->gpr[reg] = bswap32(ldl(get_addr(addr)));
114 env->gpr[reg] = ldl(get_addr(addr));
118 void helper_stmw (target_ulong addr, uint32_t reg)
120 for (; reg < 32; reg++, addr += 4) {
122 stl(get_addr(addr), bswap32((uint32_t)env->gpr[reg]));
124 stl(get_addr(addr), (uint32_t)env->gpr[reg]);
128 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
131 for (; nb > 3; nb -= 4, addr += 4) {
132 env->gpr[reg] = ldl(get_addr(addr));
133 reg = (reg + 1) % 32;
135 if (unlikely(nb > 0)) {
137 for (sh = 24; nb > 0; nb--, addr++, sh -= 8) {
138 env->gpr[reg] |= ldub(get_addr(addr)) << sh;
142 /* PPC32 specification says we must generate an exception if
143 * rA is in the range of registers to be loaded.
144 * In an other hand, IBM says this is valid, but rA won't be loaded.
145 * For now, I'll follow the spec...
147 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
149 if (likely(xer_bc != 0)) {
150 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
151 (reg < rb && (reg + xer_bc) > rb))) {
152 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
154 POWERPC_EXCP_INVAL_LSWX);
156 helper_lsw(addr, xer_bc, reg);
161 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
164 for (; nb > 3; nb -= 4, addr += 4) {
165 stl(get_addr(addr), env->gpr[reg]);
166 reg = (reg + 1) % 32;
168 if (unlikely(nb > 0)) {
169 for (sh = 24; nb > 0; nb--, addr++, sh -= 8)
170 stb(get_addr(addr), (env->gpr[reg] >> sh) & 0xFF);
174 static void do_dcbz(target_ulong addr, int dcache_line_size)
176 target_long mask = get_addr(~(dcache_line_size - 1));
179 for (i = 0 ; i < dcache_line_size ; i += 4) {
182 if ((env->reserve & mask) == addr)
183 env->reserve = (target_ulong)-1ULL;
186 void helper_dcbz(target_ulong addr)
188 do_dcbz(addr, env->dcache_line_size);
191 void helper_dcbz_970(target_ulong addr)
193 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
196 do_dcbz(addr, env->dcache_line_size);
199 void helper_icbi(target_ulong addr)
203 addr = get_addr(addr & ~(env->dcache_line_size - 1));
204 /* Invalidate one cache line :
205 * PowerPC specification says this is to be treated like a load
206 * (not a fetch) by the MMU. To be sure it will be so,
207 * do the load "by hand".
210 tb_invalidate_page_range(addr, addr + env->icache_line_size);
214 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
218 for (i = 0; i < xer_bc; i++) {
219 c = ldub((uint32_t)addr++);
220 /* ra (if not 0) and rb are never modified */
221 if (likely(reg != rb && (ra == 0 || reg != ra))) {
222 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
224 if (unlikely(c == xer_cmp))
226 if (likely(d != 0)) {
237 /*****************************************************************************/
238 /* Fixed point operations helpers */
239 #if defined(TARGET_PPC64)
241 /* multiply high word */
242 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
246 muls64(&tl, &th, arg1, arg2);
250 /* multiply high word unsigned */
251 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
255 mulu64(&tl, &th, arg1, arg2);
259 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
264 muls64(&tl, (uint64_t *)&th, arg1, arg2);
265 /* If th != 0 && th != -1, then we had an overflow */
266 if (likely((uint64_t)(th + 1) <= 1)) {
267 env->xer &= ~(1 << XER_OV);
269 env->xer |= (1 << XER_OV) | (1 << XER_SO);
275 target_ulong helper_cntlzw (target_ulong t)
280 #if defined(TARGET_PPC64)
281 target_ulong helper_cntlzd (target_ulong t)
287 /* shift right arithmetic helper */
288 target_ulong helper_sraw (target_ulong value, target_ulong shift)
292 if (likely(!(shift & 0x20))) {
293 if (likely((uint32_t)shift != 0)) {
295 ret = (int32_t)value >> shift;
296 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
297 env->xer &= ~(1 << XER_CA);
299 env->xer |= (1 << XER_CA);
302 ret = (int32_t)value;
303 env->xer &= ~(1 << XER_CA);
306 ret = (int32_t)value >> 31;
308 env->xer |= (1 << XER_CA);
310 env->xer &= ~(1 << XER_CA);
313 return (target_long)ret;
316 #if defined(TARGET_PPC64)
317 target_ulong helper_srad (target_ulong value, target_ulong shift)
321 if (likely(!(shift & 0x40))) {
322 if (likely((uint64_t)shift != 0)) {
324 ret = (int64_t)value >> shift;
325 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
326 env->xer &= ~(1 << XER_CA);
328 env->xer |= (1 << XER_CA);
331 ret = (int64_t)value;
332 env->xer &= ~(1 << XER_CA);
335 ret = (int64_t)value >> 63;
337 env->xer |= (1 << XER_CA);
339 env->xer &= ~(1 << XER_CA);
346 target_ulong helper_popcntb (target_ulong val)
348 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
349 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
350 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
354 #if defined(TARGET_PPC64)
355 target_ulong helper_popcntb_64 (target_ulong val)
357 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
358 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
359 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
364 /*****************************************************************************/
365 /* Floating point operations helpers */
366 uint64_t helper_float32_to_float64(uint32_t arg)
371 d.d = float32_to_float64(f.f, &env->fp_status);
375 uint32_t helper_float64_to_float32(uint64_t arg)
380 f.f = float64_to_float32(d.d, &env->fp_status);
384 static always_inline int fpisneg (float64 d)
390 return u.ll >> 63 != 0;
393 static always_inline int isden (float64 d)
399 return ((u.ll >> 52) & 0x7FF) == 0;
402 static always_inline int iszero (float64 d)
408 return (u.ll & ~0x8000000000000000ULL) == 0;
411 static always_inline int isinfinity (float64 d)
417 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
418 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
421 #ifdef CONFIG_SOFTFLOAT
422 static always_inline int isfinite (float64 d)
428 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
431 static always_inline int isnormal (float64 d)
437 uint32_t exp = (u.ll >> 52) & 0x7FF;
438 return ((0 < exp) && (exp < 0x7FF));
442 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
448 isneg = fpisneg(farg.d);
449 if (unlikely(float64_is_nan(farg.d))) {
450 if (float64_is_signaling_nan(farg.d)) {
451 /* Signaling NaN: flags are undefined */
457 } else if (unlikely(isinfinity(farg.d))) {
464 if (iszero(farg.d)) {
472 /* Denormalized numbers */
475 /* Normalized numbers */
486 /* We update FPSCR_FPRF */
487 env->fpscr &= ~(0x1F << FPSCR_FPRF);
488 env->fpscr |= ret << FPSCR_FPRF;
490 /* We just need fpcc to update Rc1 */
494 /* Floating-point invalid operations exception */
495 static always_inline uint64_t fload_invalid_op_excp (int op)
501 if (op & POWERPC_EXCP_FP_VXSNAN) {
502 /* Operation on signaling NaN */
503 env->fpscr |= 1 << FPSCR_VXSNAN;
505 if (op & POWERPC_EXCP_FP_VXSOFT) {
506 /* Software-defined condition */
507 env->fpscr |= 1 << FPSCR_VXSOFT;
509 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
510 case POWERPC_EXCP_FP_VXISI:
511 /* Magnitude subtraction of infinities */
512 env->fpscr |= 1 << FPSCR_VXISI;
514 case POWERPC_EXCP_FP_VXIDI:
515 /* Division of infinity by infinity */
516 env->fpscr |= 1 << FPSCR_VXIDI;
518 case POWERPC_EXCP_FP_VXZDZ:
519 /* Division of zero by zero */
520 env->fpscr |= 1 << FPSCR_VXZDZ;
522 case POWERPC_EXCP_FP_VXIMZ:
523 /* Multiplication of zero by infinity */
524 env->fpscr |= 1 << FPSCR_VXIMZ;
526 case POWERPC_EXCP_FP_VXVC:
527 /* Ordered comparison of NaN */
528 env->fpscr |= 1 << FPSCR_VXVC;
529 env->fpscr &= ~(0xF << FPSCR_FPCC);
530 env->fpscr |= 0x11 << FPSCR_FPCC;
531 /* We must update the target FPR before raising the exception */
533 env->exception_index = POWERPC_EXCP_PROGRAM;
534 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
535 /* Update the floating-point enabled exception summary */
536 env->fpscr |= 1 << FPSCR_FEX;
537 /* Exception is differed */
541 case POWERPC_EXCP_FP_VXSQRT:
542 /* Square root of a negative number */
543 env->fpscr |= 1 << FPSCR_VXSQRT;
545 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
547 /* Set the result to quiet NaN */
549 env->fpscr &= ~(0xF << FPSCR_FPCC);
550 env->fpscr |= 0x11 << FPSCR_FPCC;
553 case POWERPC_EXCP_FP_VXCVI:
554 /* Invalid conversion */
555 env->fpscr |= 1 << FPSCR_VXCVI;
556 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
558 /* Set the result to quiet NaN */
560 env->fpscr &= ~(0xF << FPSCR_FPCC);
561 env->fpscr |= 0x11 << FPSCR_FPCC;
565 /* Update the floating-point invalid operation summary */
566 env->fpscr |= 1 << FPSCR_VX;
567 /* Update the floating-point exception summary */
568 env->fpscr |= 1 << FPSCR_FX;
570 /* Update the floating-point enabled exception summary */
571 env->fpscr |= 1 << FPSCR_FEX;
572 if (msr_fe0 != 0 || msr_fe1 != 0)
573 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
578 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
580 env->fpscr |= 1 << FPSCR_ZX;
581 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
582 /* Update the floating-point exception summary */
583 env->fpscr |= 1 << FPSCR_FX;
585 /* Update the floating-point enabled exception summary */
586 env->fpscr |= 1 << FPSCR_FEX;
587 if (msr_fe0 != 0 || msr_fe1 != 0) {
588 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
589 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
592 /* Set the result to infinity */
593 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
594 arg1 |= 0x7FFULL << 52;
599 static always_inline void float_overflow_excp (void)
601 env->fpscr |= 1 << FPSCR_OX;
602 /* Update the floating-point exception summary */
603 env->fpscr |= 1 << FPSCR_FX;
605 /* XXX: should adjust the result */
606 /* Update the floating-point enabled exception summary */
607 env->fpscr |= 1 << FPSCR_FEX;
608 /* We must update the target FPR before raising the exception */
609 env->exception_index = POWERPC_EXCP_PROGRAM;
610 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
612 env->fpscr |= 1 << FPSCR_XX;
613 env->fpscr |= 1 << FPSCR_FI;
617 static always_inline void float_underflow_excp (void)
619 env->fpscr |= 1 << FPSCR_UX;
620 /* Update the floating-point exception summary */
621 env->fpscr |= 1 << FPSCR_FX;
623 /* XXX: should adjust the result */
624 /* Update the floating-point enabled exception summary */
625 env->fpscr |= 1 << FPSCR_FEX;
626 /* We must update the target FPR before raising the exception */
627 env->exception_index = POWERPC_EXCP_PROGRAM;
628 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
632 static always_inline void float_inexact_excp (void)
634 env->fpscr |= 1 << FPSCR_XX;
635 /* Update the floating-point exception summary */
636 env->fpscr |= 1 << FPSCR_FX;
638 /* Update the floating-point enabled exception summary */
639 env->fpscr |= 1 << FPSCR_FEX;
640 /* We must update the target FPR before raising the exception */
641 env->exception_index = POWERPC_EXCP_PROGRAM;
642 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
646 static always_inline void fpscr_set_rounding_mode (void)
650 /* Set rounding mode */
653 /* Best approximation (round to nearest) */
654 rnd_type = float_round_nearest_even;
657 /* Smaller magnitude (round toward zero) */
658 rnd_type = float_round_to_zero;
661 /* Round toward +infinite */
662 rnd_type = float_round_up;
666 /* Round toward -infinite */
667 rnd_type = float_round_down;
670 set_float_rounding_mode(rnd_type, &env->fp_status);
673 void helper_fpscr_setbit (uint32_t bit)
677 prev = (env->fpscr >> bit) & 1;
678 env->fpscr |= 1 << bit;
682 env->fpscr |= 1 << FPSCR_FX;
686 env->fpscr |= 1 << FPSCR_FX;
691 env->fpscr |= 1 << FPSCR_FX;
696 env->fpscr |= 1 << FPSCR_FX;
701 env->fpscr |= 1 << FPSCR_FX;
714 env->fpscr |= 1 << FPSCR_VX;
715 env->fpscr |= 1 << FPSCR_FX;
722 env->error_code = POWERPC_EXCP_FP;
724 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
726 env->error_code |= POWERPC_EXCP_FP_VXISI;
728 env->error_code |= POWERPC_EXCP_FP_VXIDI;
730 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
732 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
734 env->error_code |= POWERPC_EXCP_FP_VXVC;
736 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
738 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
740 env->error_code |= POWERPC_EXCP_FP_VXCVI;
747 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
754 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
761 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
768 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
774 fpscr_set_rounding_mode();
779 /* Update the floating-point enabled exception summary */
780 env->fpscr |= 1 << FPSCR_FEX;
781 /* We have to update Rc1 before raising the exception */
782 env->exception_index = POWERPC_EXCP_PROGRAM;
788 void helper_store_fpscr (uint64_t arg, uint32_t mask)
791 * We use only the 32 LSB of the incoming fpr
799 new |= prev & 0x90000000;
800 for (i = 0; i < 7; i++) {
801 if (mask & (1 << i)) {
802 env->fpscr &= ~(0xF << (4 * i));
803 env->fpscr |= new & (0xF << (4 * i));
806 /* Update VX and FEX */
808 env->fpscr |= 1 << FPSCR_VX;
810 env->fpscr &= ~(1 << FPSCR_VX);
811 if ((fpscr_ex & fpscr_eex) != 0) {
812 env->fpscr |= 1 << FPSCR_FEX;
813 env->exception_index = POWERPC_EXCP_PROGRAM;
814 /* XXX: we should compute it properly */
815 env->error_code = POWERPC_EXCP_FP;
818 env->fpscr &= ~(1 << FPSCR_FEX);
819 fpscr_set_rounding_mode();
822 void helper_float_check_status (void)
824 #ifdef CONFIG_SOFTFLOAT
825 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
826 (env->error_code & POWERPC_EXCP_FP)) {
827 /* Differred floating-point exception after target FPR update */
828 if (msr_fe0 != 0 || msr_fe1 != 0)
829 raise_exception_err(env, env->exception_index, env->error_code);
830 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
831 float_overflow_excp();
832 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
833 float_underflow_excp();
834 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
835 float_inexact_excp();
838 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
839 (env->error_code & POWERPC_EXCP_FP)) {
840 /* Differred floating-point exception after target FPR update */
841 if (msr_fe0 != 0 || msr_fe1 != 0)
842 raise_exception_err(env, env->exception_index, env->error_code);
848 #ifdef CONFIG_SOFTFLOAT
849 void helper_reset_fpstatus (void)
851 env->fp_status.float_exception_flags = 0;
856 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
858 CPU_DoubleU farg1, farg2;
862 #if USE_PRECISE_EMULATION
863 if (unlikely(float64_is_signaling_nan(farg1.d) ||
864 float64_is_signaling_nan(farg2.d))) {
866 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
867 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
868 fpisneg(farg1.d) == fpisneg(farg2.d))) {
869 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
871 /* Magnitude subtraction of infinities */
872 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
875 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
881 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
883 CPU_DoubleU farg1, farg2;
887 #if USE_PRECISE_EMULATION
889 if (unlikely(float64_is_signaling_nan(farg1.d) ||
890 float64_is_signaling_nan(farg2.d))) {
891 /* sNaN subtraction */
892 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
893 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
894 fpisneg(farg1.d) != fpisneg(farg2.d))) {
895 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
897 /* Magnitude subtraction of infinities */
898 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
902 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
908 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
910 CPU_DoubleU farg1, farg2;
914 #if USE_PRECISE_EMULATION
915 if (unlikely(float64_is_signaling_nan(farg1.d) ||
916 float64_is_signaling_nan(farg2.d))) {
917 /* sNaN multiplication */
918 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
919 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
920 (iszero(farg1.d) && isinfinity(farg2.d)))) {
921 /* Multiplication of zero by infinity */
922 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
924 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
928 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
934 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
936 CPU_DoubleU farg1, farg2;
940 #if USE_PRECISE_EMULATION
941 if (unlikely(float64_is_signaling_nan(farg1.d) ||
942 float64_is_signaling_nan(farg2.d))) {
944 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
945 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
946 /* Division of infinity by infinity */
947 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
948 } else if (unlikely(iszero(farg2.d))) {
949 if (iszero(farg1.d)) {
950 /* Division of zero by zero */
951 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
953 /* Division by zero */
954 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
957 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
960 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
966 uint64_t helper_fabs (uint64_t arg)
971 farg.d = float64_abs(farg.d);
976 uint64_t helper_fnabs (uint64_t arg)
981 farg.d = float64_abs(farg.d);
982 farg.d = float64_chs(farg.d);
987 uint64_t helper_fneg (uint64_t arg)
992 farg.d = float64_chs(farg.d);
997 uint64_t helper_fctiw (uint64_t arg)
1002 if (unlikely(float64_is_signaling_nan(farg.d))) {
1003 /* sNaN conversion */
1004 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1005 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1006 /* qNan / infinity conversion */
1007 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1009 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1010 #if USE_PRECISE_EMULATION
1011 /* XXX: higher bits are not supposed to be significant.
1012 * to make tests easier, return the same as a real PowerPC 750
1014 farg.ll |= 0xFFF80000ULL << 32;
1020 /* fctiwz - fctiwz. */
1021 uint64_t helper_fctiwz (uint64_t arg)
1026 if (unlikely(float64_is_signaling_nan(farg.d))) {
1027 /* sNaN conversion */
1028 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1029 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1030 /* qNan / infinity conversion */
1031 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1033 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1034 #if USE_PRECISE_EMULATION
1035 /* XXX: higher bits are not supposed to be significant.
1036 * to make tests easier, return the same as a real PowerPC 750
1038 farg.ll |= 0xFFF80000ULL << 32;
1044 #if defined(TARGET_PPC64)
1045 /* fcfid - fcfid. */
1046 uint64_t helper_fcfid (uint64_t arg)
1049 farg.d = int64_to_float64(arg, &env->fp_status);
1053 /* fctid - fctid. */
1054 uint64_t helper_fctid (uint64_t arg)
1059 if (unlikely(float64_is_signaling_nan(farg.d))) {
1060 /* sNaN conversion */
1061 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1062 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1063 /* qNan / infinity conversion */
1064 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1066 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1071 /* fctidz - fctidz. */
1072 uint64_t helper_fctidz (uint64_t arg)
1077 if (unlikely(float64_is_signaling_nan(farg.d))) {
1078 /* sNaN conversion */
1079 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1080 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1081 /* qNan / infinity conversion */
1082 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1084 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1091 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1096 if (unlikely(float64_is_signaling_nan(farg.d))) {
1098 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1099 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1100 /* qNan / infinity round */
1101 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1103 set_float_rounding_mode(rounding_mode, &env->fp_status);
1104 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1105 /* Restore rounding mode from FPSCR */
1106 fpscr_set_rounding_mode();
1111 uint64_t helper_frin (uint64_t arg)
1113 return do_fri(arg, float_round_nearest_even);
1116 uint64_t helper_friz (uint64_t arg)
1118 return do_fri(arg, float_round_to_zero);
1121 uint64_t helper_frip (uint64_t arg)
1123 return do_fri(arg, float_round_up);
1126 uint64_t helper_frim (uint64_t arg)
1128 return do_fri(arg, float_round_down);
1131 /* fmadd - fmadd. */
1132 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1134 CPU_DoubleU farg1, farg2, farg3;
1139 #if USE_PRECISE_EMULATION
1140 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1141 float64_is_signaling_nan(farg2.d) ||
1142 float64_is_signaling_nan(farg3.d))) {
1143 /* sNaN operation */
1144 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1147 /* This is the way the PowerPC specification defines it */
1148 float128 ft0_128, ft1_128;
1150 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1151 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1152 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1153 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1154 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1155 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1157 /* This is OK on x86 hosts */
1158 farg1.d = (farg1.d * farg2.d) + farg3.d;
1162 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1163 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1168 /* fmsub - fmsub. */
1169 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1171 CPU_DoubleU farg1, farg2, farg3;
1176 #if USE_PRECISE_EMULATION
1177 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1178 float64_is_signaling_nan(farg2.d) ||
1179 float64_is_signaling_nan(farg3.d))) {
1180 /* sNaN operation */
1181 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1184 /* This is the way the PowerPC specification defines it */
1185 float128 ft0_128, ft1_128;
1187 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1188 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1189 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1190 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1191 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1192 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1194 /* This is OK on x86 hosts */
1195 farg1.d = (farg1.d * farg2.d) - farg3.d;
1199 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1200 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1205 /* fnmadd - fnmadd. */
1206 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1208 CPU_DoubleU farg1, farg2, farg3;
1214 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1215 float64_is_signaling_nan(farg2.d) ||
1216 float64_is_signaling_nan(farg3.d))) {
1217 /* sNaN operation */
1218 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1220 #if USE_PRECISE_EMULATION
1222 /* This is the way the PowerPC specification defines it */
1223 float128 ft0_128, ft1_128;
1225 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1226 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1227 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1228 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1229 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1230 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1232 /* This is OK on x86 hosts */
1233 farg1.d = (farg1.d * farg2.d) + farg3.d;
1236 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1237 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1239 if (likely(!isnan(farg1.d)))
1240 farg1.d = float64_chs(farg1.d);
1245 /* fnmsub - fnmsub. */
1246 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1248 CPU_DoubleU farg1, farg2, farg3;
1254 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1255 float64_is_signaling_nan(farg2.d) ||
1256 float64_is_signaling_nan(farg3.d))) {
1257 /* sNaN operation */
1258 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1260 #if USE_PRECISE_EMULATION
1262 /* This is the way the PowerPC specification defines it */
1263 float128 ft0_128, ft1_128;
1265 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1266 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1267 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1268 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1269 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1270 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1272 /* This is OK on x86 hosts */
1273 farg1.d = (farg1.d * farg2.d) - farg3.d;
1276 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1277 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1279 if (likely(!isnan(farg1.d)))
1280 farg1.d = float64_chs(farg1.d);
1286 uint64_t helper_frsp (uint64_t arg)
1291 #if USE_PRECISE_EMULATION
1292 if (unlikely(float64_is_signaling_nan(farg.d))) {
1293 /* sNaN square root */
1294 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1296 fard.d = float64_to_float32(farg.d, &env->fp_status);
1299 farg.d = float64_to_float32(farg.d, &env->fp_status);
1304 /* fsqrt - fsqrt. */
1305 uint64_t helper_fsqrt (uint64_t arg)
1310 if (unlikely(float64_is_signaling_nan(farg.d))) {
1311 /* sNaN square root */
1312 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1313 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1314 /* Square root of a negative nonzero number */
1315 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1317 farg.d = float64_sqrt(farg.d, &env->fp_status);
1323 uint64_t helper_fre (uint64_t arg)
1328 if (unlikely(float64_is_signaling_nan(farg.d))) {
1329 /* sNaN reciprocal */
1330 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1331 } else if (unlikely(iszero(farg.d))) {
1332 /* Zero reciprocal */
1333 farg.ll = float_zero_divide_excp(1.0, farg.d);
1334 } else if (likely(isnormal(farg.d))) {
1335 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1337 if (farg.ll == 0x8000000000000000ULL) {
1338 farg.ll = 0xFFF0000000000000ULL;
1339 } else if (farg.ll == 0x0000000000000000ULL) {
1340 farg.ll = 0x7FF0000000000000ULL;
1341 } else if (isnan(farg.d)) {
1342 farg.ll = 0x7FF8000000000000ULL;
1343 } else if (fpisneg(farg.d)) {
1344 farg.ll = 0x8000000000000000ULL;
1346 farg.ll = 0x0000000000000000ULL;
1353 uint64_t helper_fres (uint64_t arg)
1358 if (unlikely(float64_is_signaling_nan(farg.d))) {
1359 /* sNaN reciprocal */
1360 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1361 } else if (unlikely(iszero(farg.d))) {
1362 /* Zero reciprocal */
1363 farg.ll = float_zero_divide_excp(1.0, farg.d);
1364 } else if (likely(isnormal(farg.d))) {
1365 #if USE_PRECISE_EMULATION
1366 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1367 farg.d = float64_to_float32(farg.d, &env->fp_status);
1369 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1372 if (farg.ll == 0x8000000000000000ULL) {
1373 farg.ll = 0xFFF0000000000000ULL;
1374 } else if (farg.ll == 0x0000000000000000ULL) {
1375 farg.ll = 0x7FF0000000000000ULL;
1376 } else if (isnan(farg.d)) {
1377 farg.ll = 0x7FF8000000000000ULL;
1378 } else if (fpisneg(farg.d)) {
1379 farg.ll = 0x8000000000000000ULL;
1381 farg.ll = 0x0000000000000000ULL;
1387 /* frsqrte - frsqrte. */
1388 uint64_t helper_frsqrte (uint64_t arg)
1393 if (unlikely(float64_is_signaling_nan(farg.d))) {
1394 /* sNaN reciprocal square root */
1395 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1396 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1397 /* Reciprocal square root of a negative nonzero number */
1398 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1399 } else if (likely(isnormal(farg.d))) {
1400 farg.d = float64_sqrt(farg.d, &env->fp_status);
1401 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1403 if (farg.ll == 0x8000000000000000ULL) {
1404 farg.ll = 0xFFF0000000000000ULL;
1405 } else if (farg.ll == 0x0000000000000000ULL) {
1406 farg.ll = 0x7FF0000000000000ULL;
1407 } else if (isnan(farg.d)) {
1408 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1409 } else if (fpisneg(farg.d)) {
1410 farg.ll = 0x7FF8000000000000ULL;
1412 farg.ll = 0x0000000000000000ULL;
1419 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1421 CPU_DoubleU farg1, farg2, farg3;
1427 if (!fpisneg(farg1.d) || iszero(farg1.d))
1433 uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
1435 CPU_DoubleU farg1, farg2;
1440 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1441 float64_is_signaling_nan(farg2.d))) {
1442 /* sNaN comparison */
1443 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1445 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1447 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1453 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1454 env->fpscr |= ret << FPSCR_FPRF;
1458 uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
1460 CPU_DoubleU farg1, farg2;
1465 if (unlikely(float64_is_nan(farg1.d) ||
1466 float64_is_nan(farg2.d))) {
1467 if (float64_is_signaling_nan(farg1.d) ||
1468 float64_is_signaling_nan(farg2.d)) {
1469 /* sNaN comparison */
1470 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1471 POWERPC_EXCP_FP_VXVC);
1473 /* qNaN comparison */
1474 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1477 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1479 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1485 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1486 env->fpscr |= ret << FPSCR_FPRF;
1490 #if !defined (CONFIG_USER_ONLY)
1491 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1493 void do_store_msr (void)
1495 T0 = hreg_store_msr(env, T0, 0);
1497 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1498 raise_exception(env, T0);
1502 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1503 target_ulong msrm, int keep_msrh)
1505 #if defined(TARGET_PPC64)
1506 if (msr & (1ULL << MSR_SF)) {
1507 nip = (uint64_t)nip;
1508 msr &= (uint64_t)msrm;
1510 nip = (uint32_t)nip;
1511 msr = (uint32_t)(msr & msrm);
1513 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1516 nip = (uint32_t)nip;
1517 msr &= (uint32_t)msrm;
1519 /* XXX: beware: this is false if VLE is supported */
1520 env->nip = nip & ~((target_ulong)0x00000003);
1521 hreg_store_msr(env, msr, 1);
1522 #if defined (DEBUG_OP)
1523 cpu_dump_rfi(env->nip, env->msr);
1525 /* No need to raise an exception here,
1526 * as rfi is always the last insn of a TB
1528 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1531 void helper_rfi (void)
1533 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1534 ~((target_ulong)0xFFFF0000), 1);
1537 #if defined(TARGET_PPC64)
1538 void helper_rfid (void)
1540 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1541 ~((target_ulong)0xFFFF0000), 0);
1544 void helper_hrfid (void)
1546 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1547 ~((target_ulong)0xFFFF0000), 0);
1552 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1554 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1555 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1556 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1557 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1558 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1559 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1563 #if defined(TARGET_PPC64)
1564 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1566 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1567 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1568 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1569 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1570 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1571 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1575 /*****************************************************************************/
1576 /* PowerPC 601 specific instructions (POWER bridge) */
1577 void do_POWER_abso (void)
1579 if ((int32_t)T0 == INT32_MIN) {
1581 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1582 } else if ((int32_t)T0 < 0) {
1584 env->xer &= ~(1 << XER_OV);
1586 env->xer &= ~(1 << XER_OV);
1590 void do_POWER_clcs (void)
1594 /* Instruction cache line size */
1595 T0 = env->icache_line_size;
1598 /* Data cache line size */
1599 T0 = env->dcache_line_size;
1602 /* Minimum cache line size */
1603 T0 = env->icache_line_size < env->dcache_line_size ?
1604 env->icache_line_size : env->dcache_line_size;
1607 /* Maximum cache line size */
1608 T0 = env->icache_line_size > env->dcache_line_size ?
1609 env->icache_line_size : env->dcache_line_size;
1617 void do_POWER_div (void)
1621 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1623 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1624 env->spr[SPR_MQ] = 0;
1626 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1627 env->spr[SPR_MQ] = tmp % T1;
1628 T0 = tmp / (int32_t)T1;
1632 void do_POWER_divo (void)
1636 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1638 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1639 env->spr[SPR_MQ] = 0;
1640 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1642 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1643 env->spr[SPR_MQ] = tmp % T1;
1645 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1646 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1648 env->xer &= ~(1 << XER_OV);
1654 void do_POWER_divs (void)
1656 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1658 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1659 env->spr[SPR_MQ] = 0;
1661 env->spr[SPR_MQ] = T0 % T1;
1662 T0 = (int32_t)T0 / (int32_t)T1;
1666 void do_POWER_divso (void)
1668 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1670 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1671 env->spr[SPR_MQ] = 0;
1672 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1674 T0 = (int32_t)T0 / (int32_t)T1;
1675 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1676 env->xer &= ~(1 << XER_OV);
1680 void do_POWER_dozo (void)
1682 if ((int32_t)T1 > (int32_t)T0) {
1685 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1686 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1687 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1689 env->xer &= ~(1 << XER_OV);
1693 env->xer &= ~(1 << XER_OV);
1697 void do_POWER_maskg (void)
1701 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1704 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1705 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1706 if ((uint32_t)T0 > (uint32_t)T1)
1712 void do_POWER_mulo (void)
1716 tmp = (uint64_t)T0 * (uint64_t)T1;
1717 env->spr[SPR_MQ] = tmp >> 32;
1719 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1720 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1722 env->xer &= ~(1 << XER_OV);
1726 #if !defined (CONFIG_USER_ONLY)
1727 void do_POWER_rac (void)
1732 /* We don't have to generate many instances of this instruction,
1733 * as rac is supervisor only.
1735 /* XXX: FIX THIS: Pretend we have no BAT */
1736 nb_BATs = env->nb_BATs;
1738 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1740 env->nb_BATs = nb_BATs;
1743 void helper_rfsvc (void)
1745 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1748 void do_store_hid0_601 (void)
1752 hid0 = env->spr[SPR_HID0];
1753 if ((T0 ^ hid0) & 0x00000008) {
1754 /* Change current endianness */
1755 env->hflags &= ~(1 << MSR_LE);
1756 env->hflags_nmsr &= ~(1 << MSR_LE);
1757 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1758 env->hflags |= env->hflags_nmsr;
1759 if (loglevel != 0) {
1760 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1761 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1764 env->spr[SPR_HID0] = T0;
1768 /*****************************************************************************/
1769 /* 602 specific instructions */
1770 /* mfrom is the most crazy instruction ever seen, imho ! */
1771 /* Real implementation uses a ROM table. Do the same */
1772 #define USE_MFROM_ROM_TABLE
1773 target_ulong helper_602_mfrom (target_ulong arg)
1775 if (likely(arg < 602)) {
1776 #if defined(USE_MFROM_ROM_TABLE)
1777 #include "mfrom_table.c"
1778 return mfrom_ROM_table[T0];
1781 /* Extremly decomposed:
1783 * return 256 * log10(10 + 1.0) + 0.5
1786 d = float64_div(d, 256, &env->fp_status);
1788 d = exp10(d); // XXX: use float emulation function
1789 d = float64_add(d, 1.0, &env->fp_status);
1790 d = log10(d); // XXX: use float emulation function
1791 d = float64_mul(d, 256, &env->fp_status);
1792 d = float64_add(d, 0.5, &env->fp_status);
1793 return float64_round_to_int(d, &env->fp_status);
1800 /*****************************************************************************/
1801 /* Embedded PowerPC specific helpers */
1803 /* XXX: to be improved to check access rights when in user-mode */
1804 void do_load_dcr (void)
1808 if (unlikely(env->dcr_env == NULL)) {
1809 if (loglevel != 0) {
1810 fprintf(logfile, "No DCR environment\n");
1812 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1813 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1814 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1815 if (loglevel != 0) {
1816 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1818 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1819 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1825 void do_store_dcr (void)
1827 if (unlikely(env->dcr_env == NULL)) {
1828 if (loglevel != 0) {
1829 fprintf(logfile, "No DCR environment\n");
1831 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1832 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1833 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1834 if (loglevel != 0) {
1835 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1837 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1838 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1842 #if !defined(CONFIG_USER_ONLY)
1843 void helper_40x_rfci (void)
1845 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1846 ~((target_ulong)0xFFFF0000), 0);
1849 void helper_rfci (void)
1851 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1852 ~((target_ulong)0x3FFF0000), 0);
1855 void helper_rfdi (void)
1857 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1858 ~((target_ulong)0x3FFF0000), 0);
1861 void helper_rfmci (void)
1863 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1864 ~((target_ulong)0x3FFF0000), 0);
1867 void do_load_403_pb (int num)
1872 void do_store_403_pb (int num)
1874 if (likely(env->pb[num] != T0)) {
1876 /* Should be optimized */
1883 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1889 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1890 if ((high & mask) == 0) {
1898 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1899 if ((low & mask) == 0) {
1911 env->xer = (env->xer & ~0x7F) | i;
1913 env->crf[0] |= xer_so;
1918 /*****************************************************************************/
1919 /* SPE extension helpers */
1920 /* Use a table to make this quicker */
1921 static uint8_t hbrev[16] = {
1922 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1923 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1926 static always_inline uint8_t byte_reverse (uint8_t val)
1928 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1931 static always_inline uint32_t word_reverse (uint32_t val)
1933 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1934 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1937 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1938 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
1940 uint32_t a, b, d, mask;
1942 mask = UINT32_MAX >> (32 - MASKBITS);
1945 d = word_reverse(1 + word_reverse(a | ~b));
1946 return (arg1 & ~mask) | (d & b);
1949 uint32_t helper_cntlsw32 (uint32_t val)
1951 if (val & 0x80000000)
1957 uint32_t helper_cntlzw32 (uint32_t val)
1962 /* Single-precision floating-point conversions */
1963 static always_inline uint32_t efscfsi (uint32_t val)
1967 u.f = int32_to_float32(val, &env->spe_status);
1972 static always_inline uint32_t efscfui (uint32_t val)
1976 u.f = uint32_to_float32(val, &env->spe_status);
1981 static always_inline int32_t efsctsi (uint32_t val)
1986 /* NaN are not treated the same way IEEE 754 does */
1987 if (unlikely(isnan(u.f)))
1990 return float32_to_int32(u.f, &env->spe_status);
1993 static always_inline uint32_t efsctui (uint32_t val)
1998 /* NaN are not treated the same way IEEE 754 does */
1999 if (unlikely(isnan(u.f)))
2002 return float32_to_uint32(u.f, &env->spe_status);
2005 static always_inline uint32_t efsctsiz (uint32_t val)
2010 /* NaN are not treated the same way IEEE 754 does */
2011 if (unlikely(isnan(u.f)))
2014 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2017 static always_inline uint32_t efsctuiz (uint32_t val)
2022 /* NaN are not treated the same way IEEE 754 does */
2023 if (unlikely(isnan(u.f)))
2026 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2029 static always_inline uint32_t efscfsf (uint32_t val)
2034 u.f = int32_to_float32(val, &env->spe_status);
2035 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2036 u.f = float32_div(u.f, tmp, &env->spe_status);
2041 static always_inline uint32_t efscfuf (uint32_t val)
2046 u.f = uint32_to_float32(val, &env->spe_status);
2047 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2048 u.f = float32_div(u.f, tmp, &env->spe_status);
2053 static always_inline uint32_t efsctsf (uint32_t val)
2059 /* NaN are not treated the same way IEEE 754 does */
2060 if (unlikely(isnan(u.f)))
2062 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2063 u.f = float32_mul(u.f, tmp, &env->spe_status);
2065 return float32_to_int32(u.f, &env->spe_status);
2068 static always_inline uint32_t efsctuf (uint32_t val)
2074 /* NaN are not treated the same way IEEE 754 does */
2075 if (unlikely(isnan(u.f)))
2077 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2078 u.f = float32_mul(u.f, tmp, &env->spe_status);
2080 return float32_to_uint32(u.f, &env->spe_status);
2083 #define HELPER_SPE_SINGLE_CONV(name) \
2084 uint32_t helper_e##name (uint32_t val) \
2086 return e##name(val); \
2089 HELPER_SPE_SINGLE_CONV(fscfsi);
2091 HELPER_SPE_SINGLE_CONV(fscfui);
2093 HELPER_SPE_SINGLE_CONV(fscfuf);
2095 HELPER_SPE_SINGLE_CONV(fscfsf);
2097 HELPER_SPE_SINGLE_CONV(fsctsi);
2099 HELPER_SPE_SINGLE_CONV(fsctui);
2101 HELPER_SPE_SINGLE_CONV(fsctsiz);
2103 HELPER_SPE_SINGLE_CONV(fsctuiz);
2105 HELPER_SPE_SINGLE_CONV(fsctsf);
2107 HELPER_SPE_SINGLE_CONV(fsctuf);
2109 #define HELPER_SPE_VECTOR_CONV(name) \
2110 uint64_t helper_ev##name (uint64_t val) \
2112 return ((uint64_t)e##name(val >> 32) << 32) | \
2113 (uint64_t)e##name(val); \
2116 HELPER_SPE_VECTOR_CONV(fscfsi);
2118 HELPER_SPE_VECTOR_CONV(fscfui);
2120 HELPER_SPE_VECTOR_CONV(fscfuf);
2122 HELPER_SPE_VECTOR_CONV(fscfsf);
2124 HELPER_SPE_VECTOR_CONV(fsctsi);
2126 HELPER_SPE_VECTOR_CONV(fsctui);
2128 HELPER_SPE_VECTOR_CONV(fsctsiz);
2130 HELPER_SPE_VECTOR_CONV(fsctuiz);
2132 HELPER_SPE_VECTOR_CONV(fsctsf);
2134 HELPER_SPE_VECTOR_CONV(fsctuf);
2136 /* Single-precision floating-point arithmetic */
2137 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2142 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2146 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2151 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2155 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2160 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2164 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2169 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2173 #define HELPER_SPE_SINGLE_ARITH(name) \
2174 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2176 return e##name(op1, op2); \
2179 HELPER_SPE_SINGLE_ARITH(fsadd);
2181 HELPER_SPE_SINGLE_ARITH(fssub);
2183 HELPER_SPE_SINGLE_ARITH(fsmul);
2185 HELPER_SPE_SINGLE_ARITH(fsdiv);
2187 #define HELPER_SPE_VECTOR_ARITH(name) \
2188 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2190 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2191 (uint64_t)e##name(op1, op2); \
2194 HELPER_SPE_VECTOR_ARITH(fsadd);
2196 HELPER_SPE_VECTOR_ARITH(fssub);
2198 HELPER_SPE_VECTOR_ARITH(fsmul);
2200 HELPER_SPE_VECTOR_ARITH(fsdiv);
2202 /* Single-precision floating-point comparisons */
2203 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2208 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2211 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2216 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2219 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2224 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2227 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2229 /* XXX: TODO: test special values (NaN, infinites, ...) */
2230 return efststlt(op1, op2);
2233 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2235 /* XXX: TODO: test special values (NaN, infinites, ...) */
2236 return efststgt(op1, op2);
2239 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2241 /* XXX: TODO: test special values (NaN, infinites, ...) */
2242 return efststeq(op1, op2);
2245 #define HELPER_SINGLE_SPE_CMP(name) \
2246 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2248 return e##name(op1, op2) << 2; \
2251 HELPER_SINGLE_SPE_CMP(fststlt);
2253 HELPER_SINGLE_SPE_CMP(fststgt);
2255 HELPER_SINGLE_SPE_CMP(fststeq);
2257 HELPER_SINGLE_SPE_CMP(fscmplt);
2259 HELPER_SINGLE_SPE_CMP(fscmpgt);
2261 HELPER_SINGLE_SPE_CMP(fscmpeq);
2263 static always_inline uint32_t evcmp_merge (int t0, int t1)
2265 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2268 #define HELPER_VECTOR_SPE_CMP(name) \
2269 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2271 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2274 HELPER_VECTOR_SPE_CMP(fststlt);
2276 HELPER_VECTOR_SPE_CMP(fststgt);
2278 HELPER_VECTOR_SPE_CMP(fststeq);
2280 HELPER_VECTOR_SPE_CMP(fscmplt);
2282 HELPER_VECTOR_SPE_CMP(fscmpgt);
2284 HELPER_VECTOR_SPE_CMP(fscmpeq);
2286 /* Double-precision floating-point conversion */
2287 uint64_t helper_efdcfsi (uint32_t val)
2291 u.d = int32_to_float64(val, &env->spe_status);
2296 uint64_t helper_efdcfsid (uint64_t val)
2300 u.d = int64_to_float64(val, &env->spe_status);
2305 uint64_t helper_efdcfui (uint32_t val)
2309 u.d = uint32_to_float64(val, &env->spe_status);
2314 uint64_t helper_efdcfuid (uint64_t val)
2318 u.d = uint64_to_float64(val, &env->spe_status);
2323 uint32_t helper_efdctsi (uint64_t val)
2328 /* NaN are not treated the same way IEEE 754 does */
2329 if (unlikely(isnan(u.d)))
2332 return float64_to_int32(u.d, &env->spe_status);
2335 uint32_t helper_efdctui (uint64_t val)
2340 /* NaN are not treated the same way IEEE 754 does */
2341 if (unlikely(isnan(u.d)))
2344 return float64_to_uint32(u.d, &env->spe_status);
2347 uint32_t helper_efdctsiz (uint64_t val)
2352 /* NaN are not treated the same way IEEE 754 does */
2353 if (unlikely(isnan(u.d)))
2356 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2359 uint64_t helper_efdctsidz (uint64_t val)
2364 /* NaN are not treated the same way IEEE 754 does */
2365 if (unlikely(isnan(u.d)))
2368 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2371 uint32_t helper_efdctuiz (uint64_t val)
2376 /* NaN are not treated the same way IEEE 754 does */
2377 if (unlikely(isnan(u.d)))
2380 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2383 uint64_t helper_efdctuidz (uint64_t val)
2388 /* NaN are not treated the same way IEEE 754 does */
2389 if (unlikely(isnan(u.d)))
2392 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2395 uint64_t helper_efdcfsf (uint32_t val)
2400 u.d = int32_to_float64(val, &env->spe_status);
2401 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2402 u.d = float64_div(u.d, tmp, &env->spe_status);
2407 uint64_t helper_efdcfuf (uint32_t val)
2412 u.d = uint32_to_float64(val, &env->spe_status);
2413 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2414 u.d = float64_div(u.d, tmp, &env->spe_status);
2419 uint32_t helper_efdctsf (uint64_t val)
2425 /* NaN are not treated the same way IEEE 754 does */
2426 if (unlikely(isnan(u.d)))
2428 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2429 u.d = float64_mul(u.d, tmp, &env->spe_status);
2431 return float64_to_int32(u.d, &env->spe_status);
2434 uint32_t helper_efdctuf (uint64_t val)
2440 /* NaN are not treated the same way IEEE 754 does */
2441 if (unlikely(isnan(u.d)))
2443 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2444 u.d = float64_mul(u.d, tmp, &env->spe_status);
2446 return float64_to_uint32(u.d, &env->spe_status);
2449 uint32_t helper_efscfd (uint64_t val)
2455 u2.f = float64_to_float32(u1.d, &env->spe_status);
2460 uint64_t helper_efdcfs (uint32_t val)
2466 u2.d = float32_to_float64(u1.f, &env->spe_status);
2471 /* Double precision fixed-point arithmetic */
2472 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2477 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2481 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2486 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2490 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2495 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2499 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2504 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2508 /* Double precision floating point helpers */
2509 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2514 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2517 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2522 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2525 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2530 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2533 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2535 /* XXX: TODO: test special values (NaN, infinites, ...) */
2536 return helper_efdtstlt(op1, op2);
2539 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2541 /* XXX: TODO: test special values (NaN, infinites, ...) */
2542 return helper_efdtstgt(op1, op2);
2545 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2547 /* XXX: TODO: test special values (NaN, infinites, ...) */
2548 return helper_efdtsteq(op1, op2);
2551 /*****************************************************************************/
2552 /* Softmmu support */
2553 #if !defined (CONFIG_USER_ONLY)
2555 #define MMUSUFFIX _mmu
2558 #include "softmmu_template.h"
2561 #include "softmmu_template.h"
2564 #include "softmmu_template.h"
2567 #include "softmmu_template.h"
2569 /* try to fill the TLB and return an exception if error. If retaddr is
2570 NULL, it means that the function was called in C code (i.e. not
2571 from generated code or from helper.c) */
2572 /* XXX: fix it to restore all registers */
2573 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2575 TranslationBlock *tb;
2576 CPUState *saved_env;
2580 /* XXX: hack to restore env in all cases, even if not called from
2583 env = cpu_single_env;
2584 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2585 if (unlikely(ret != 0)) {
2586 if (likely(retaddr)) {
2587 /* now we have a real cpu fault */
2588 pc = (unsigned long)retaddr;
2589 tb = tb_find_pc(pc);
2591 /* the PC is inside the translated code. It means that we have
2592 a virtual CPU fault */
2593 cpu_restore_state(tb, env, pc, NULL);
2596 raise_exception_err(env, env->exception_index, env->error_code);
2601 /* Software driven TLBs management */
2602 /* PowerPC 602/603 software TLB load instructions helpers */
2603 static void helper_load_6xx_tlb (target_ulong new_EPN, int is_code)
2605 target_ulong RPN, CMP, EPN;
2608 RPN = env->spr[SPR_RPA];
2610 CMP = env->spr[SPR_ICMP];
2611 EPN = env->spr[SPR_IMISS];
2613 CMP = env->spr[SPR_DCMP];
2614 EPN = env->spr[SPR_DMISS];
2616 way = (env->spr[SPR_SRR1] >> 17) & 1;
2617 #if defined (DEBUG_SOFTWARE_TLB)
2618 if (loglevel != 0) {
2619 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2620 " PTE1 " ADDRX " way %d\n",
2621 __func__, T0, EPN, CMP, RPN, way);
2624 /* Store this TLB */
2625 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2626 way, is_code, CMP, RPN);
2629 void helper_load_6xx_tlbd (target_ulong EPN)
2631 helper_load_6xx_tlb(EPN, 0);
2634 void helper_load_6xx_tlbi (target_ulong EPN)
2636 helper_load_6xx_tlb(EPN, 1);
2639 /* PowerPC 74xx software TLB load instructions helpers */
2640 static void helper_load_74xx_tlb (target_ulong new_EPN, int is_code)
2642 target_ulong RPN, CMP, EPN;
2645 RPN = env->spr[SPR_PTELO];
2646 CMP = env->spr[SPR_PTEHI];
2647 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2648 way = env->spr[SPR_TLBMISS] & 0x3;
2649 #if defined (DEBUG_SOFTWARE_TLB)
2650 if (loglevel != 0) {
2651 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2652 " PTE1 " ADDRX " way %d\n",
2653 __func__, T0, EPN, CMP, RPN, way);
2656 /* Store this TLB */
2657 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2658 way, is_code, CMP, RPN);
2661 void helper_load_74xx_tlbd (target_ulong EPN)
2663 helper_load_74xx_tlb(EPN, 0);
2666 void helper_load_74xx_tlbi (target_ulong EPN)
2668 helper_load_74xx_tlb(EPN, 1);
2671 static always_inline target_ulong booke_tlb_to_page_size (int size)
2673 return 1024 << (2 * size);
2676 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2680 switch (page_size) {
2714 #if defined (TARGET_PPC64)
2715 case 0x000100000000ULL:
2718 case 0x000400000000ULL:
2721 case 0x001000000000ULL:
2724 case 0x004000000000ULL:
2727 case 0x010000000000ULL:
2739 /* Helpers for 4xx TLB management */
2740 void do_4xx_tlbre_lo (void)
2746 tlb = &env->tlb[T0].tlbe;
2748 if (tlb->prot & PAGE_VALID)
2750 size = booke_page_size_to_tlb(tlb->size);
2751 if (size < 0 || size > 0x7)
2754 env->spr[SPR_40x_PID] = tlb->PID;
2757 void do_4xx_tlbre_hi (void)
2762 tlb = &env->tlb[T0].tlbe;
2764 if (tlb->prot & PAGE_EXEC)
2766 if (tlb->prot & PAGE_WRITE)
2770 void do_4xx_tlbwe_hi (void)
2773 target_ulong page, end;
2775 #if defined (DEBUG_SOFTWARE_TLB)
2776 if (loglevel != 0) {
2777 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2781 tlb = &env->tlb[T0].tlbe;
2782 /* Invalidate previous TLB (if it's valid) */
2783 if (tlb->prot & PAGE_VALID) {
2784 end = tlb->EPN + tlb->size;
2785 #if defined (DEBUG_SOFTWARE_TLB)
2786 if (loglevel != 0) {
2787 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2788 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2791 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2792 tlb_flush_page(env, page);
2794 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2795 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2796 * If this ever occurs, one should use the ppcemb target instead
2797 * of the ppc or ppc64 one
2799 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2800 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2801 "are not supported (%d)\n",
2802 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2804 tlb->EPN = T1 & ~(tlb->size - 1);
2806 tlb->prot |= PAGE_VALID;
2808 tlb->prot &= ~PAGE_VALID;
2810 /* XXX: TO BE FIXED */
2811 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2813 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2814 tlb->attr = T1 & 0xFF;
2815 #if defined (DEBUG_SOFTWARE_TLB)
2816 if (loglevel != 0) {
2817 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2818 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2819 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2820 tlb->prot & PAGE_READ ? 'r' : '-',
2821 tlb->prot & PAGE_WRITE ? 'w' : '-',
2822 tlb->prot & PAGE_EXEC ? 'x' : '-',
2823 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2826 /* Invalidate new TLB (if valid) */
2827 if (tlb->prot & PAGE_VALID) {
2828 end = tlb->EPN + tlb->size;
2829 #if defined (DEBUG_SOFTWARE_TLB)
2830 if (loglevel != 0) {
2831 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2832 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2835 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2836 tlb_flush_page(env, page);
2840 void do_4xx_tlbwe_lo (void)
2844 #if defined (DEBUG_SOFTWARE_TLB)
2845 if (loglevel != 0) {
2846 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2850 tlb = &env->tlb[T0].tlbe;
2851 tlb->RPN = T1 & 0xFFFFFC00;
2852 tlb->prot = PAGE_READ;
2854 tlb->prot |= PAGE_EXEC;
2856 tlb->prot |= PAGE_WRITE;
2857 #if defined (DEBUG_SOFTWARE_TLB)
2858 if (loglevel != 0) {
2859 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2860 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2861 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2862 tlb->prot & PAGE_READ ? 'r' : '-',
2863 tlb->prot & PAGE_WRITE ? 'w' : '-',
2864 tlb->prot & PAGE_EXEC ? 'x' : '-',
2865 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2870 /* PowerPC 440 TLB management */
2871 void do_440_tlbwe (int word)
2874 target_ulong EPN, RPN, size;
2877 #if defined (DEBUG_SOFTWARE_TLB)
2878 if (loglevel != 0) {
2879 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2880 __func__, word, T0, T1);
2885 tlb = &env->tlb[T0].tlbe;
2888 /* Just here to please gcc */
2890 EPN = T1 & 0xFFFFFC00;
2891 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2894 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2895 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2899 tlb->attr |= (T1 >> 8) & 1;
2901 tlb->prot |= PAGE_VALID;
2903 if (tlb->prot & PAGE_VALID) {
2904 tlb->prot &= ~PAGE_VALID;
2908 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2913 RPN = T1 & 0xFFFFFC0F;
2914 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2919 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2920 tlb->prot = tlb->prot & PAGE_VALID;
2922 tlb->prot |= PAGE_READ << 4;
2924 tlb->prot |= PAGE_WRITE << 4;
2926 tlb->prot |= PAGE_EXEC << 4;
2928 tlb->prot |= PAGE_READ;
2930 tlb->prot |= PAGE_WRITE;
2932 tlb->prot |= PAGE_EXEC;
2937 void do_440_tlbre (int word)
2943 tlb = &env->tlb[T0].tlbe;
2946 /* Just here to please gcc */
2949 size = booke_page_size_to_tlb(tlb->size);
2950 if (size < 0 || size > 0xF)
2953 if (tlb->attr & 0x1)
2955 if (tlb->prot & PAGE_VALID)
2957 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2958 env->spr[SPR_440_MMUCR] |= tlb->PID;
2964 T0 = tlb->attr & ~0x1;
2965 if (tlb->prot & (PAGE_READ << 4))
2967 if (tlb->prot & (PAGE_WRITE << 4))
2969 if (tlb->prot & (PAGE_EXEC << 4))
2971 if (tlb->prot & PAGE_READ)
2973 if (tlb->prot & PAGE_WRITE)
2975 if (tlb->prot & PAGE_EXEC)
2980 #endif /* !CONFIG_USER_ONLY */