2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
25 #include "op_helper.h"
27 #define MEMSUFFIX _raw
28 #include "op_helper.h"
29 #include "op_helper_mem.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #define MEMSUFFIX _user
32 #include "op_helper.h"
33 #include "op_helper_mem.h"
34 #define MEMSUFFIX _kernel
35 #include "op_helper.h"
36 #include "op_helper_mem.h"
37 #define MEMSUFFIX _hypv
38 #include "op_helper.h"
39 #include "op_helper_mem.h"
43 //#define DEBUG_EXCEPTIONS
44 //#define DEBUG_SOFTWARE_TLB
46 /*****************************************************************************/
47 /* Exceptions processing helpers */
49 void do_raise_exception_err (uint32_t exception, int error_code)
52 printf("Raise exception %3x code : %d\n", exception, error_code);
54 env->exception_index = exception;
55 env->error_code = error_code;
59 void do_raise_exception (uint32_t exception)
61 do_raise_exception_err(exception, 0);
64 /*****************************************************************************/
65 /* Registers load and stores */
66 target_ulong helper_load_cr (void)
68 return (env->crf[0] << 28) |
78 void helper_store_cr (target_ulong val, uint32_t mask)
82 for (i = 0, sh = 7; i < 8; i++, sh--) {
84 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
88 #if defined(TARGET_PPC64)
89 void do_store_pri (int prio)
91 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
92 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
96 target_ulong ppc_load_dump_spr (int sprn)
99 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
100 sprn, sprn, env->spr[sprn]);
103 return env->spr[sprn];
106 void ppc_store_dump_spr (int sprn, target_ulong val)
109 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
110 sprn, sprn, env->spr[sprn], val);
112 env->spr[sprn] = val;
115 /*****************************************************************************/
116 /* Fixed point operations helpers */
117 #if defined(TARGET_PPC64)
119 /* multiply high word */
120 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
124 muls64(&tl, &th, arg1, arg2);
128 /* multiply high word unsigned */
129 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
133 mulu64(&tl, &th, arg1, arg2);
137 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
142 muls64(&tl, (uint64_t *)&th, arg1, arg2);
143 /* If th != 0 && th != -1, then we had an overflow */
144 if (likely((uint64_t)(th + 1) <= 1)) {
145 env->xer &= ~(1 << XER_OV);
147 env->xer |= (1 << XER_OV) | (1 << XER_SO);
153 target_ulong helper_cntlzw (target_ulong t)
158 #if defined(TARGET_PPC64)
159 target_ulong helper_cntlzd (target_ulong t)
165 /* shift right arithmetic helper */
166 target_ulong helper_sraw (target_ulong value, target_ulong shift)
170 if (likely(!(shift & 0x20))) {
171 if (likely((uint32_t)shift != 0)) {
173 ret = (int32_t)value >> shift;
174 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
175 env->xer &= ~(1 << XER_CA);
177 env->xer |= (1 << XER_CA);
180 ret = (int32_t)value;
181 env->xer &= ~(1 << XER_CA);
184 ret = (int32_t)value >> 31;
186 env->xer |= (1 << XER_CA);
188 env->xer &= ~(1 << XER_CA);
191 return (target_long)ret;
194 #if defined(TARGET_PPC64)
195 target_ulong helper_srad (target_ulong value, target_ulong shift)
199 if (likely(!(shift & 0x40))) {
200 if (likely((uint64_t)shift != 0)) {
202 ret = (int64_t)value >> shift;
203 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
204 env->xer &= ~(1 << XER_CA);
206 env->xer |= (1 << XER_CA);
209 ret = (int64_t)value;
210 env->xer &= ~(1 << XER_CA);
213 ret = (int64_t)value >> 63;
215 env->xer |= (1 << XER_CA);
217 env->xer &= ~(1 << XER_CA);
224 target_ulong helper_popcntb (target_ulong val)
226 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
227 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
228 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
232 #if defined(TARGET_PPC64)
233 target_ulong helper_popcntb_64 (target_ulong val)
235 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
236 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
237 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
242 /*****************************************************************************/
243 /* Floating point operations helpers */
244 static always_inline int fpisneg (float64 d)
250 return u.ll >> 63 != 0;
253 static always_inline int isden (float64 d)
259 return ((u.ll >> 52) & 0x7FF) == 0;
262 static always_inline int iszero (float64 d)
268 return (u.ll & ~0x8000000000000000ULL) == 0;
271 static always_inline int isinfinity (float64 d)
277 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
278 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
281 #ifdef CONFIG_SOFTFLOAT
282 static always_inline int isfinite (float64 d)
288 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
291 static always_inline int isnormal (float64 d)
297 uint32_t exp = (u.ll >> 52) & 0x7FF;
298 return ((0 < exp) && (exp < 0x7FF));
302 void do_compute_fprf (int set_fprf)
306 isneg = fpisneg(FT0);
307 if (unlikely(float64_is_nan(FT0))) {
308 if (float64_is_signaling_nan(FT0)) {
309 /* Signaling NaN: flags are undefined */
315 } else if (unlikely(isinfinity(FT0))) {
330 /* Denormalized numbers */
333 /* Normalized numbers */
344 /* We update FPSCR_FPRF */
345 env->fpscr &= ~(0x1F << FPSCR_FPRF);
346 env->fpscr |= T0 << FPSCR_FPRF;
348 /* We just need fpcc to update Rc1 */
352 /* Floating-point invalid operations exception */
353 static always_inline void fload_invalid_op_excp (int op)
358 if (op & POWERPC_EXCP_FP_VXSNAN) {
359 /* Operation on signaling NaN */
360 env->fpscr |= 1 << FPSCR_VXSNAN;
362 if (op & POWERPC_EXCP_FP_VXSOFT) {
363 /* Software-defined condition */
364 env->fpscr |= 1 << FPSCR_VXSOFT;
366 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
367 case POWERPC_EXCP_FP_VXISI:
368 /* Magnitude subtraction of infinities */
369 env->fpscr |= 1 << FPSCR_VXISI;
371 case POWERPC_EXCP_FP_VXIDI:
372 /* Division of infinity by infinity */
373 env->fpscr |= 1 << FPSCR_VXIDI;
375 case POWERPC_EXCP_FP_VXZDZ:
376 /* Division of zero by zero */
377 env->fpscr |= 1 << FPSCR_VXZDZ;
379 case POWERPC_EXCP_FP_VXIMZ:
380 /* Multiplication of zero by infinity */
381 env->fpscr |= 1 << FPSCR_VXIMZ;
383 case POWERPC_EXCP_FP_VXVC:
384 /* Ordered comparison of NaN */
385 env->fpscr |= 1 << FPSCR_VXVC;
386 env->fpscr &= ~(0xF << FPSCR_FPCC);
387 env->fpscr |= 0x11 << FPSCR_FPCC;
388 /* We must update the target FPR before raising the exception */
390 env->exception_index = POWERPC_EXCP_PROGRAM;
391 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
392 /* Update the floating-point enabled exception summary */
393 env->fpscr |= 1 << FPSCR_FEX;
394 /* Exception is differed */
398 case POWERPC_EXCP_FP_VXSQRT:
399 /* Square root of a negative number */
400 env->fpscr |= 1 << FPSCR_VXSQRT;
402 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
404 /* Set the result to quiet NaN */
406 env->fpscr &= ~(0xF << FPSCR_FPCC);
407 env->fpscr |= 0x11 << FPSCR_FPCC;
410 case POWERPC_EXCP_FP_VXCVI:
411 /* Invalid conversion */
412 env->fpscr |= 1 << FPSCR_VXCVI;
413 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
415 /* Set the result to quiet NaN */
417 env->fpscr &= ~(0xF << FPSCR_FPCC);
418 env->fpscr |= 0x11 << FPSCR_FPCC;
422 /* Update the floating-point invalid operation summary */
423 env->fpscr |= 1 << FPSCR_VX;
424 /* Update the floating-point exception summary */
425 env->fpscr |= 1 << FPSCR_FX;
427 /* Update the floating-point enabled exception summary */
428 env->fpscr |= 1 << FPSCR_FEX;
429 if (msr_fe0 != 0 || msr_fe1 != 0)
430 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
434 static always_inline void float_zero_divide_excp (void)
438 env->fpscr |= 1 << FPSCR_ZX;
439 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
440 /* Update the floating-point exception summary */
441 env->fpscr |= 1 << FPSCR_FX;
443 /* Update the floating-point enabled exception summary */
444 env->fpscr |= 1 << FPSCR_FEX;
445 if (msr_fe0 != 0 || msr_fe1 != 0) {
446 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
447 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
450 /* Set the result to infinity */
453 u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
454 u0.ll |= 0x7FFULL << 52;
459 static always_inline void float_overflow_excp (void)
461 env->fpscr |= 1 << FPSCR_OX;
462 /* Update the floating-point exception summary */
463 env->fpscr |= 1 << FPSCR_FX;
465 /* XXX: should adjust the result */
466 /* Update the floating-point enabled exception summary */
467 env->fpscr |= 1 << FPSCR_FEX;
468 /* We must update the target FPR before raising the exception */
469 env->exception_index = POWERPC_EXCP_PROGRAM;
470 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
472 env->fpscr |= 1 << FPSCR_XX;
473 env->fpscr |= 1 << FPSCR_FI;
477 static always_inline void float_underflow_excp (void)
479 env->fpscr |= 1 << FPSCR_UX;
480 /* Update the floating-point exception summary */
481 env->fpscr |= 1 << FPSCR_FX;
483 /* XXX: should adjust the result */
484 /* Update the floating-point enabled exception summary */
485 env->fpscr |= 1 << FPSCR_FEX;
486 /* We must update the target FPR before raising the exception */
487 env->exception_index = POWERPC_EXCP_PROGRAM;
488 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
492 static always_inline void float_inexact_excp (void)
494 env->fpscr |= 1 << FPSCR_XX;
495 /* Update the floating-point exception summary */
496 env->fpscr |= 1 << FPSCR_FX;
498 /* Update the floating-point enabled exception summary */
499 env->fpscr |= 1 << FPSCR_FEX;
500 /* We must update the target FPR before raising the exception */
501 env->exception_index = POWERPC_EXCP_PROGRAM;
502 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
506 static always_inline void fpscr_set_rounding_mode (void)
510 /* Set rounding mode */
513 /* Best approximation (round to nearest) */
514 rnd_type = float_round_nearest_even;
517 /* Smaller magnitude (round toward zero) */
518 rnd_type = float_round_to_zero;
521 /* Round toward +infinite */
522 rnd_type = float_round_up;
526 /* Round toward -infinite */
527 rnd_type = float_round_down;
530 set_float_rounding_mode(rnd_type, &env->fp_status);
533 void do_fpscr_setbit (int bit)
537 prev = (env->fpscr >> bit) & 1;
538 env->fpscr |= 1 << bit;
542 env->fpscr |= 1 << FPSCR_FX;
546 env->fpscr |= 1 << FPSCR_FX;
551 env->fpscr |= 1 << FPSCR_FX;
556 env->fpscr |= 1 << FPSCR_FX;
561 env->fpscr |= 1 << FPSCR_FX;
574 env->fpscr |= 1 << FPSCR_VX;
575 env->fpscr |= 1 << FPSCR_FX;
582 env->error_code = POWERPC_EXCP_FP;
584 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
586 env->error_code |= POWERPC_EXCP_FP_VXISI;
588 env->error_code |= POWERPC_EXCP_FP_VXIDI;
590 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
592 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
594 env->error_code |= POWERPC_EXCP_FP_VXVC;
596 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
598 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
600 env->error_code |= POWERPC_EXCP_FP_VXCVI;
607 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
614 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
621 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
628 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
634 fpscr_set_rounding_mode();
639 /* Update the floating-point enabled exception summary */
640 env->fpscr |= 1 << FPSCR_FEX;
641 /* We have to update Rc1 before raising the exception */
642 env->exception_index = POWERPC_EXCP_PROGRAM;
648 #if defined(WORDS_BIGENDIAN)
655 void do_store_fpscr (uint32_t mask)
658 * We use only the 32 LSB of the incoming fpr
668 new |= prev & 0x90000000;
669 for (i = 0; i < 7; i++) {
670 if (mask & (1 << i)) {
671 env->fpscr &= ~(0xF << (4 * i));
672 env->fpscr |= new & (0xF << (4 * i));
675 /* Update VX and FEX */
677 env->fpscr |= 1 << FPSCR_VX;
679 env->fpscr &= ~(1 << FPSCR_VX);
680 if ((fpscr_ex & fpscr_eex) != 0) {
681 env->fpscr |= 1 << FPSCR_FEX;
682 env->exception_index = POWERPC_EXCP_PROGRAM;
683 /* XXX: we should compute it properly */
684 env->error_code = POWERPC_EXCP_FP;
687 env->fpscr &= ~(1 << FPSCR_FEX);
688 fpscr_set_rounding_mode();
693 #ifdef CONFIG_SOFTFLOAT
694 void do_float_check_status (void)
696 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
697 (env->error_code & POWERPC_EXCP_FP)) {
698 /* Differred floating-point exception after target FPR update */
699 if (msr_fe0 != 0 || msr_fe1 != 0)
700 do_raise_exception_err(env->exception_index, env->error_code);
701 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
702 float_overflow_excp();
703 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
704 float_underflow_excp();
705 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
706 float_inexact_excp();
711 #if USE_PRECISE_EMULATION
714 if (unlikely(float64_is_signaling_nan(FT0) ||
715 float64_is_signaling_nan(FT1))) {
717 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
718 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
719 fpisneg(FT0) == fpisneg(FT1))) {
720 FT0 = float64_add(FT0, FT1, &env->fp_status);
722 /* Magnitude subtraction of infinities */
723 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
729 if (unlikely(float64_is_signaling_nan(FT0) ||
730 float64_is_signaling_nan(FT1))) {
731 /* sNaN subtraction */
732 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
733 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
734 fpisneg(FT0) != fpisneg(FT1))) {
735 FT0 = float64_sub(FT0, FT1, &env->fp_status);
737 /* Magnitude subtraction of infinities */
738 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
744 if (unlikely(float64_is_signaling_nan(FT0) ||
745 float64_is_signaling_nan(FT1))) {
746 /* sNaN multiplication */
747 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
748 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
749 (iszero(FT0) && isinfinity(FT1)))) {
750 /* Multiplication of zero by infinity */
751 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
753 FT0 = float64_mul(FT0, FT1, &env->fp_status);
759 if (unlikely(float64_is_signaling_nan(FT0) ||
760 float64_is_signaling_nan(FT1))) {
762 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
763 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
764 /* Division of infinity by infinity */
765 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
766 } else if (unlikely(iszero(FT1))) {
768 /* Division of zero by zero */
769 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
771 /* Division by zero */
772 float_zero_divide_excp();
775 FT0 = float64_div(FT0, FT1, &env->fp_status);
778 #endif /* USE_PRECISE_EMULATION */
784 if (unlikely(float64_is_signaling_nan(FT0))) {
785 /* sNaN conversion */
786 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
787 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
788 /* qNan / infinity conversion */
789 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
791 p.ll = float64_to_int32(FT0, &env->fp_status);
792 #if USE_PRECISE_EMULATION
793 /* XXX: higher bits are not supposed to be significant.
794 * to make tests easier, return the same as a real PowerPC 750
796 p.ll |= 0xFFF80000ULL << 32;
802 void do_fctiwz (void)
806 if (unlikely(float64_is_signaling_nan(FT0))) {
807 /* sNaN conversion */
808 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
809 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
810 /* qNan / infinity conversion */
811 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
813 p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
814 #if USE_PRECISE_EMULATION
815 /* XXX: higher bits are not supposed to be significant.
816 * to make tests easier, return the same as a real PowerPC 750
818 p.ll |= 0xFFF80000ULL << 32;
824 #if defined(TARGET_PPC64)
830 FT0 = int64_to_float64(p.ll, &env->fp_status);
837 if (unlikely(float64_is_signaling_nan(FT0))) {
838 /* sNaN conversion */
839 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
840 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
841 /* qNan / infinity conversion */
842 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
844 p.ll = float64_to_int64(FT0, &env->fp_status);
849 void do_fctidz (void)
853 if (unlikely(float64_is_signaling_nan(FT0))) {
854 /* sNaN conversion */
855 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
856 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
857 /* qNan / infinity conversion */
858 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
860 p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
867 static always_inline void do_fri (int rounding_mode)
869 if (unlikely(float64_is_signaling_nan(FT0))) {
871 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
872 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
873 /* qNan / infinity round */
874 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
876 set_float_rounding_mode(rounding_mode, &env->fp_status);
877 FT0 = float64_round_to_int(FT0, &env->fp_status);
878 /* Restore rounding mode from FPSCR */
879 fpscr_set_rounding_mode();
885 do_fri(float_round_nearest_even);
890 do_fri(float_round_to_zero);
895 do_fri(float_round_up);
900 do_fri(float_round_down);
903 #if USE_PRECISE_EMULATION
906 if (unlikely(float64_is_signaling_nan(FT0) ||
907 float64_is_signaling_nan(FT1) ||
908 float64_is_signaling_nan(FT2))) {
910 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
913 /* This is the way the PowerPC specification defines it */
914 float128 ft0_128, ft1_128;
916 ft0_128 = float64_to_float128(FT0, &env->fp_status);
917 ft1_128 = float64_to_float128(FT1, &env->fp_status);
918 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
919 ft1_128 = float64_to_float128(FT2, &env->fp_status);
920 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
921 FT0 = float128_to_float64(ft0_128, &env->fp_status);
923 /* This is OK on x86 hosts */
924 FT0 = (FT0 * FT1) + FT2;
931 if (unlikely(float64_is_signaling_nan(FT0) ||
932 float64_is_signaling_nan(FT1) ||
933 float64_is_signaling_nan(FT2))) {
935 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
938 /* This is the way the PowerPC specification defines it */
939 float128 ft0_128, ft1_128;
941 ft0_128 = float64_to_float128(FT0, &env->fp_status);
942 ft1_128 = float64_to_float128(FT1, &env->fp_status);
943 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
944 ft1_128 = float64_to_float128(FT2, &env->fp_status);
945 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
946 FT0 = float128_to_float64(ft0_128, &env->fp_status);
948 /* This is OK on x86 hosts */
949 FT0 = (FT0 * FT1) - FT2;
953 #endif /* USE_PRECISE_EMULATION */
955 void do_fnmadd (void)
957 if (unlikely(float64_is_signaling_nan(FT0) ||
958 float64_is_signaling_nan(FT1) ||
959 float64_is_signaling_nan(FT2))) {
961 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
963 #if USE_PRECISE_EMULATION
965 /* This is the way the PowerPC specification defines it */
966 float128 ft0_128, ft1_128;
968 ft0_128 = float64_to_float128(FT0, &env->fp_status);
969 ft1_128 = float64_to_float128(FT1, &env->fp_status);
970 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
971 ft1_128 = float64_to_float128(FT2, &env->fp_status);
972 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
973 FT0 = float128_to_float64(ft0_128, &env->fp_status);
975 /* This is OK on x86 hosts */
976 FT0 = (FT0 * FT1) + FT2;
979 FT0 = float64_mul(FT0, FT1, &env->fp_status);
980 FT0 = float64_add(FT0, FT2, &env->fp_status);
982 if (likely(!isnan(FT0)))
983 FT0 = float64_chs(FT0);
987 void do_fnmsub (void)
989 if (unlikely(float64_is_signaling_nan(FT0) ||
990 float64_is_signaling_nan(FT1) ||
991 float64_is_signaling_nan(FT2))) {
993 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
995 #if USE_PRECISE_EMULATION
997 /* This is the way the PowerPC specification defines it */
998 float128 ft0_128, ft1_128;
1000 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1001 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1002 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1003 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1004 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1005 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1007 /* This is OK on x86 hosts */
1008 FT0 = (FT0 * FT1) - FT2;
1011 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1012 FT0 = float64_sub(FT0, FT2, &env->fp_status);
1014 if (likely(!isnan(FT0)))
1015 FT0 = float64_chs(FT0);
1019 #if USE_PRECISE_EMULATION
1022 if (unlikely(float64_is_signaling_nan(FT0))) {
1023 /* sNaN square root */
1024 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1026 FT0 = float64_to_float32(FT0, &env->fp_status);
1029 #endif /* USE_PRECISE_EMULATION */
1031 void do_fsqrt (void)
1033 if (unlikely(float64_is_signaling_nan(FT0))) {
1034 /* sNaN square root */
1035 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1036 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1037 /* Square root of a negative nonzero number */
1038 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1040 FT0 = float64_sqrt(FT0, &env->fp_status);
1048 if (unlikely(float64_is_signaling_nan(FT0))) {
1049 /* sNaN reciprocal */
1050 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1051 } else if (unlikely(iszero(FT0))) {
1052 /* Zero reciprocal */
1053 float_zero_divide_excp();
1054 } else if (likely(isnormal(FT0))) {
1055 FT0 = float64_div(1.0, FT0, &env->fp_status);
1058 if (p.ll == 0x8000000000000000ULL) {
1059 p.ll = 0xFFF0000000000000ULL;
1060 } else if (p.ll == 0x0000000000000000ULL) {
1061 p.ll = 0x7FF0000000000000ULL;
1062 } else if (isnan(FT0)) {
1063 p.ll = 0x7FF8000000000000ULL;
1064 } else if (fpisneg(FT0)) {
1065 p.ll = 0x8000000000000000ULL;
1067 p.ll = 0x0000000000000000ULL;
1077 if (unlikely(float64_is_signaling_nan(FT0))) {
1078 /* sNaN reciprocal */
1079 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1080 } else if (unlikely(iszero(FT0))) {
1081 /* Zero reciprocal */
1082 float_zero_divide_excp();
1083 } else if (likely(isnormal(FT0))) {
1084 #if USE_PRECISE_EMULATION
1085 FT0 = float64_div(1.0, FT0, &env->fp_status);
1086 FT0 = float64_to_float32(FT0, &env->fp_status);
1088 FT0 = float32_div(1.0, FT0, &env->fp_status);
1092 if (p.ll == 0x8000000000000000ULL) {
1093 p.ll = 0xFFF0000000000000ULL;
1094 } else if (p.ll == 0x0000000000000000ULL) {
1095 p.ll = 0x7FF0000000000000ULL;
1096 } else if (isnan(FT0)) {
1097 p.ll = 0x7FF8000000000000ULL;
1098 } else if (fpisneg(FT0)) {
1099 p.ll = 0x8000000000000000ULL;
1101 p.ll = 0x0000000000000000ULL;
1107 void do_frsqrte (void)
1111 if (unlikely(float64_is_signaling_nan(FT0))) {
1112 /* sNaN reciprocal square root */
1113 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1114 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1115 /* Reciprocal square root of a negative nonzero number */
1116 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1117 } else if (likely(isnormal(FT0))) {
1118 FT0 = float64_sqrt(FT0, &env->fp_status);
1119 FT0 = float32_div(1.0, FT0, &env->fp_status);
1122 if (p.ll == 0x8000000000000000ULL) {
1123 p.ll = 0xFFF0000000000000ULL;
1124 } else if (p.ll == 0x0000000000000000ULL) {
1125 p.ll = 0x7FF0000000000000ULL;
1126 } else if (isnan(FT0)) {
1127 p.ll |= 0x000FFFFFFFFFFFFFULL;
1128 } else if (fpisneg(FT0)) {
1129 p.ll = 0x7FF8000000000000ULL;
1131 p.ll = 0x0000000000000000ULL;
1139 if (!fpisneg(FT0) || iszero(FT0))
1145 uint32_t helper_fcmpu (void)
1149 if (unlikely(float64_is_signaling_nan(FT0) ||
1150 float64_is_signaling_nan(FT1))) {
1151 /* sNaN comparison */
1152 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1154 if (float64_lt(FT0, FT1, &env->fp_status)) {
1156 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1162 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1163 env->fpscr |= ret << FPSCR_FPRF;
1167 uint32_t helper_fcmpo (void)
1171 if (unlikely(float64_is_nan(FT0) ||
1172 float64_is_nan(FT1))) {
1173 if (float64_is_signaling_nan(FT0) ||
1174 float64_is_signaling_nan(FT1)) {
1175 /* sNaN comparison */
1176 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1177 POWERPC_EXCP_FP_VXVC);
1179 /* qNaN comparison */
1180 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1183 if (float64_lt(FT0, FT1, &env->fp_status)) {
1185 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1191 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1192 env->fpscr |= ret << FPSCR_FPRF;
1196 #if !defined (CONFIG_USER_ONLY)
1197 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1199 void do_store_msr (void)
1201 T0 = hreg_store_msr(env, T0, 0);
1203 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1204 do_raise_exception(T0);
1208 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1209 target_ulong msrm, int keep_msrh)
1211 #if defined(TARGET_PPC64)
1212 if (msr & (1ULL << MSR_SF)) {
1213 nip = (uint64_t)nip;
1214 msr &= (uint64_t)msrm;
1216 nip = (uint32_t)nip;
1217 msr = (uint32_t)(msr & msrm);
1219 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1222 nip = (uint32_t)nip;
1223 msr &= (uint32_t)msrm;
1225 /* XXX: beware: this is false if VLE is supported */
1226 env->nip = nip & ~((target_ulong)0x00000003);
1227 hreg_store_msr(env, msr, 1);
1228 #if defined (DEBUG_OP)
1229 cpu_dump_rfi(env->nip, env->msr);
1231 /* No need to raise an exception here,
1232 * as rfi is always the last insn of a TB
1234 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1239 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1240 ~((target_ulong)0xFFFF0000), 1);
1243 #if defined(TARGET_PPC64)
1246 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1247 ~((target_ulong)0xFFFF0000), 0);
1250 void do_hrfid (void)
1252 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1253 ~((target_ulong)0xFFFF0000), 0);
1258 void do_tw (int flags)
1260 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1261 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1262 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1263 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
1264 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
1265 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1269 #if defined(TARGET_PPC64)
1270 void do_td (int flags)
1272 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1273 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1274 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1275 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1276 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
1277 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1281 /*****************************************************************************/
1282 /* PowerPC 601 specific instructions (POWER bridge) */
1283 void do_POWER_abso (void)
1285 if ((int32_t)T0 == INT32_MIN) {
1287 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1288 } else if ((int32_t)T0 < 0) {
1290 env->xer &= ~(1 << XER_OV);
1292 env->xer &= ~(1 << XER_OV);
1296 void do_POWER_clcs (void)
1300 /* Instruction cache line size */
1301 T0 = env->icache_line_size;
1304 /* Data cache line size */
1305 T0 = env->dcache_line_size;
1308 /* Minimum cache line size */
1309 T0 = env->icache_line_size < env->dcache_line_size ?
1310 env->icache_line_size : env->dcache_line_size;
1313 /* Maximum cache line size */
1314 T0 = env->icache_line_size > env->dcache_line_size ?
1315 env->icache_line_size : env->dcache_line_size;
1323 void do_POWER_div (void)
1327 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1329 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1330 env->spr[SPR_MQ] = 0;
1332 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1333 env->spr[SPR_MQ] = tmp % T1;
1334 T0 = tmp / (int32_t)T1;
1338 void do_POWER_divo (void)
1342 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1344 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1345 env->spr[SPR_MQ] = 0;
1346 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1348 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1349 env->spr[SPR_MQ] = tmp % T1;
1351 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1352 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1354 env->xer &= ~(1 << XER_OV);
1360 void do_POWER_divs (void)
1362 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1364 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1365 env->spr[SPR_MQ] = 0;
1367 env->spr[SPR_MQ] = T0 % T1;
1368 T0 = (int32_t)T0 / (int32_t)T1;
1372 void do_POWER_divso (void)
1374 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1376 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1377 env->spr[SPR_MQ] = 0;
1378 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1380 T0 = (int32_t)T0 / (int32_t)T1;
1381 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1382 env->xer &= ~(1 << XER_OV);
1386 void do_POWER_dozo (void)
1388 if ((int32_t)T1 > (int32_t)T0) {
1391 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1392 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1393 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1395 env->xer &= ~(1 << XER_OV);
1399 env->xer &= ~(1 << XER_OV);
1403 void do_POWER_maskg (void)
1407 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1410 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1411 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1412 if ((uint32_t)T0 > (uint32_t)T1)
1418 void do_POWER_mulo (void)
1422 tmp = (uint64_t)T0 * (uint64_t)T1;
1423 env->spr[SPR_MQ] = tmp >> 32;
1425 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1426 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1428 env->xer &= ~(1 << XER_OV);
1432 #if !defined (CONFIG_USER_ONLY)
1433 void do_POWER_rac (void)
1438 /* We don't have to generate many instances of this instruction,
1439 * as rac is supervisor only.
1441 /* XXX: FIX THIS: Pretend we have no BAT */
1442 nb_BATs = env->nb_BATs;
1444 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1446 env->nb_BATs = nb_BATs;
1449 void do_POWER_rfsvc (void)
1451 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1454 void do_store_hid0_601 (void)
1458 hid0 = env->spr[SPR_HID0];
1459 if ((T0 ^ hid0) & 0x00000008) {
1460 /* Change current endianness */
1461 env->hflags &= ~(1 << MSR_LE);
1462 env->hflags_nmsr &= ~(1 << MSR_LE);
1463 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1464 env->hflags |= env->hflags_nmsr;
1465 if (loglevel != 0) {
1466 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1467 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1470 env->spr[SPR_HID0] = T0;
1474 /*****************************************************************************/
1475 /* 602 specific instructions */
1476 /* mfrom is the most crazy instruction ever seen, imho ! */
1477 /* Real implementation uses a ROM table. Do the same */
1478 #define USE_MFROM_ROM_TABLE
1479 void do_op_602_mfrom (void)
1481 if (likely(T0 < 602)) {
1482 #if defined(USE_MFROM_ROM_TABLE)
1483 #include "mfrom_table.c"
1484 T0 = mfrom_ROM_table[T0];
1487 /* Extremly decomposed:
1489 * T0 = 256 * log10(10 + 1.0) + 0.5
1492 d = float64_div(d, 256, &env->fp_status);
1494 d = exp10(d); // XXX: use float emulation function
1495 d = float64_add(d, 1.0, &env->fp_status);
1496 d = log10(d); // XXX: use float emulation function
1497 d = float64_mul(d, 256, &env->fp_status);
1498 d = float64_add(d, 0.5, &env->fp_status);
1499 T0 = float64_round_to_int(d, &env->fp_status);
1506 /*****************************************************************************/
1507 /* Embedded PowerPC specific helpers */
1509 /* XXX: to be improved to check access rights when in user-mode */
1510 void do_load_dcr (void)
1514 if (unlikely(env->dcr_env == NULL)) {
1515 if (loglevel != 0) {
1516 fprintf(logfile, "No DCR environment\n");
1518 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1519 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1520 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1521 if (loglevel != 0) {
1522 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1524 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1525 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1531 void do_store_dcr (void)
1533 if (unlikely(env->dcr_env == NULL)) {
1534 if (loglevel != 0) {
1535 fprintf(logfile, "No DCR environment\n");
1537 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1538 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1539 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1540 if (loglevel != 0) {
1541 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1543 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1544 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1548 #if !defined(CONFIG_USER_ONLY)
1549 void do_40x_rfci (void)
1551 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1552 ~((target_ulong)0xFFFF0000), 0);
1557 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1558 ~((target_ulong)0x3FFF0000), 0);
1563 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1564 ~((target_ulong)0x3FFF0000), 0);
1567 void do_rfmci (void)
1569 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1570 ~((target_ulong)0x3FFF0000), 0);
1573 void do_load_403_pb (int num)
1578 void do_store_403_pb (int num)
1580 if (likely(env->pb[num] != T0)) {
1582 /* Should be optimized */
1589 void do_440_dlmzb (void)
1595 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1596 if ((T0 & mask) == 0)
1600 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1601 if ((T1 & mask) == 0)
1609 /* SPE extension helpers */
1610 /* Use a table to make this quicker */
1611 static uint8_t hbrev[16] = {
1612 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1613 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1616 static always_inline uint8_t byte_reverse (uint8_t val)
1618 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1621 static always_inline uint32_t word_reverse (uint32_t val)
1623 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1624 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1627 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1628 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
1630 uint32_t a, b, d, mask;
1632 mask = UINT32_MAX >> (32 - MASKBITS);
1635 d = word_reverse(1 + word_reverse(a | ~b));
1636 return (arg1 & ~mask) | (d & b);
1639 uint32_t helper_cntlsw32 (uint32_t val)
1641 if (val & 0x80000000)
1647 uint32_t helper_cntlzw32 (uint32_t val)
1652 #define DO_SPE_OP1(name) \
1653 void do_ev##name (void) \
1655 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1656 (uint64_t)_do_e##name(T0_64); \
1659 #define DO_SPE_OP2(name) \
1660 void do_ev##name (void) \
1662 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1663 (uint64_t)_do_e##name(T0_64, T1_64); \
1666 /* Fixed-point vector comparisons */
1667 #define DO_SPE_CMP(name) \
1668 void do_ev##name (void) \
1670 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1671 T1_64 >> 32) << 32, \
1672 _do_e##name(T0_64, T1_64)); \
1675 static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
1677 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1680 /* Single precision floating-point conversions from/to integer */
1681 static always_inline uint32_t _do_efscfsi (int32_t val)
1685 u.f = int32_to_float32(val, &env->spe_status);
1690 static always_inline uint32_t _do_efscfui (uint32_t val)
1694 u.f = uint32_to_float32(val, &env->spe_status);
1699 static always_inline int32_t _do_efsctsi (uint32_t val)
1704 /* NaN are not treated the same way IEEE 754 does */
1705 if (unlikely(isnan(u.f)))
1708 return float32_to_int32(u.f, &env->spe_status);
1711 static always_inline uint32_t _do_efsctui (uint32_t val)
1716 /* NaN are not treated the same way IEEE 754 does */
1717 if (unlikely(isnan(u.f)))
1720 return float32_to_uint32(u.f, &env->spe_status);
1723 static always_inline int32_t _do_efsctsiz (uint32_t val)
1728 /* NaN are not treated the same way IEEE 754 does */
1729 if (unlikely(isnan(u.f)))
1732 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1735 static always_inline uint32_t _do_efsctuiz (uint32_t val)
1740 /* NaN are not treated the same way IEEE 754 does */
1741 if (unlikely(isnan(u.f)))
1744 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1747 void do_efscfsi (void)
1749 T0_64 = _do_efscfsi(T0_64);
1752 void do_efscfui (void)
1754 T0_64 = _do_efscfui(T0_64);
1757 void do_efsctsi (void)
1759 T0_64 = _do_efsctsi(T0_64);
1762 void do_efsctui (void)
1764 T0_64 = _do_efsctui(T0_64);
1767 void do_efsctsiz (void)
1769 T0_64 = _do_efsctsiz(T0_64);
1772 void do_efsctuiz (void)
1774 T0_64 = _do_efsctuiz(T0_64);
1777 /* Single precision floating-point conversion to/from fractional */
1778 static always_inline uint32_t _do_efscfsf (uint32_t val)
1783 u.f = int32_to_float32(val, &env->spe_status);
1784 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1785 u.f = float32_div(u.f, tmp, &env->spe_status);
1790 static always_inline uint32_t _do_efscfuf (uint32_t val)
1795 u.f = uint32_to_float32(val, &env->spe_status);
1796 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1797 u.f = float32_div(u.f, tmp, &env->spe_status);
1802 static always_inline int32_t _do_efsctsf (uint32_t val)
1808 /* NaN are not treated the same way IEEE 754 does */
1809 if (unlikely(isnan(u.f)))
1811 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1812 u.f = float32_mul(u.f, tmp, &env->spe_status);
1814 return float32_to_int32(u.f, &env->spe_status);
1817 static always_inline uint32_t _do_efsctuf (uint32_t val)
1823 /* NaN are not treated the same way IEEE 754 does */
1824 if (unlikely(isnan(u.f)))
1826 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1827 u.f = float32_mul(u.f, tmp, &env->spe_status);
1829 return float32_to_uint32(u.f, &env->spe_status);
1832 static always_inline int32_t _do_efsctsfz (uint32_t val)
1838 /* NaN are not treated the same way IEEE 754 does */
1839 if (unlikely(isnan(u.f)))
1841 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1842 u.f = float32_mul(u.f, tmp, &env->spe_status);
1844 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1847 static always_inline uint32_t _do_efsctufz (uint32_t val)
1853 /* NaN are not treated the same way IEEE 754 does */
1854 if (unlikely(isnan(u.f)))
1856 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1857 u.f = float32_mul(u.f, tmp, &env->spe_status);
1859 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1862 void do_efscfsf (void)
1864 T0_64 = _do_efscfsf(T0_64);
1867 void do_efscfuf (void)
1869 T0_64 = _do_efscfuf(T0_64);
1872 void do_efsctsf (void)
1874 T0_64 = _do_efsctsf(T0_64);
1877 void do_efsctuf (void)
1879 T0_64 = _do_efsctuf(T0_64);
1882 void do_efsctsfz (void)
1884 T0_64 = _do_efsctsfz(T0_64);
1887 void do_efsctufz (void)
1889 T0_64 = _do_efsctufz(T0_64);
1892 /* Double precision floating point helpers */
1893 static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
1895 /* XXX: TODO: test special values (NaN, infinites, ...) */
1896 return _do_efdtstlt(op1, op2);
1899 static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
1901 /* XXX: TODO: test special values (NaN, infinites, ...) */
1902 return _do_efdtstgt(op1, op2);
1905 static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
1907 /* XXX: TODO: test special values (NaN, infinites, ...) */
1908 return _do_efdtsteq(op1, op2);
1911 void do_efdcmplt (void)
1913 T0 = _do_efdcmplt(T0_64, T1_64);
1916 void do_efdcmpgt (void)
1918 T0 = _do_efdcmpgt(T0_64, T1_64);
1921 void do_efdcmpeq (void)
1923 T0 = _do_efdcmpeq(T0_64, T1_64);
1926 /* Double precision floating-point conversion to/from integer */
1927 static always_inline uint64_t _do_efdcfsi (int64_t val)
1931 u.d = int64_to_float64(val, &env->spe_status);
1936 static always_inline uint64_t _do_efdcfui (uint64_t val)
1940 u.d = uint64_to_float64(val, &env->spe_status);
1945 static always_inline int64_t _do_efdctsi (uint64_t val)
1950 /* NaN are not treated the same way IEEE 754 does */
1951 if (unlikely(isnan(u.d)))
1954 return float64_to_int64(u.d, &env->spe_status);
1957 static always_inline uint64_t _do_efdctui (uint64_t val)
1962 /* NaN are not treated the same way IEEE 754 does */
1963 if (unlikely(isnan(u.d)))
1966 return float64_to_uint64(u.d, &env->spe_status);
1969 static always_inline int64_t _do_efdctsiz (uint64_t val)
1974 /* NaN are not treated the same way IEEE 754 does */
1975 if (unlikely(isnan(u.d)))
1978 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
1981 static always_inline uint64_t _do_efdctuiz (uint64_t val)
1986 /* NaN are not treated the same way IEEE 754 does */
1987 if (unlikely(isnan(u.d)))
1990 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
1993 void do_efdcfsi (void)
1995 T0_64 = _do_efdcfsi(T0_64);
1998 void do_efdcfui (void)
2000 T0_64 = _do_efdcfui(T0_64);
2003 void do_efdctsi (void)
2005 T0_64 = _do_efdctsi(T0_64);
2008 void do_efdctui (void)
2010 T0_64 = _do_efdctui(T0_64);
2013 void do_efdctsiz (void)
2015 T0_64 = _do_efdctsiz(T0_64);
2018 void do_efdctuiz (void)
2020 T0_64 = _do_efdctuiz(T0_64);
2023 /* Double precision floating-point conversion to/from fractional */
2024 static always_inline uint64_t _do_efdcfsf (int64_t val)
2029 u.d = int32_to_float64(val, &env->spe_status);
2030 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2031 u.d = float64_div(u.d, tmp, &env->spe_status);
2036 static always_inline uint64_t _do_efdcfuf (uint64_t val)
2041 u.d = uint32_to_float64(val, &env->spe_status);
2042 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2043 u.d = float64_div(u.d, tmp, &env->spe_status);
2048 static always_inline int64_t _do_efdctsf (uint64_t val)
2054 /* NaN are not treated the same way IEEE 754 does */
2055 if (unlikely(isnan(u.d)))
2057 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2058 u.d = float64_mul(u.d, tmp, &env->spe_status);
2060 return float64_to_int32(u.d, &env->spe_status);
2063 static always_inline uint64_t _do_efdctuf (uint64_t val)
2069 /* NaN are not treated the same way IEEE 754 does */
2070 if (unlikely(isnan(u.d)))
2072 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2073 u.d = float64_mul(u.d, tmp, &env->spe_status);
2075 return float64_to_uint32(u.d, &env->spe_status);
2078 static always_inline int64_t _do_efdctsfz (uint64_t val)
2084 /* NaN are not treated the same way IEEE 754 does */
2085 if (unlikely(isnan(u.d)))
2087 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2088 u.d = float64_mul(u.d, tmp, &env->spe_status);
2090 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2093 static always_inline uint64_t _do_efdctufz (uint64_t val)
2099 /* NaN are not treated the same way IEEE 754 does */
2100 if (unlikely(isnan(u.d)))
2102 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2103 u.d = float64_mul(u.d, tmp, &env->spe_status);
2105 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2108 void do_efdcfsf (void)
2110 T0_64 = _do_efdcfsf(T0_64);
2113 void do_efdcfuf (void)
2115 T0_64 = _do_efdcfuf(T0_64);
2118 void do_efdctsf (void)
2120 T0_64 = _do_efdctsf(T0_64);
2123 void do_efdctuf (void)
2125 T0_64 = _do_efdctuf(T0_64);
2128 void do_efdctsfz (void)
2130 T0_64 = _do_efdctsfz(T0_64);
2133 void do_efdctufz (void)
2135 T0_64 = _do_efdctufz(T0_64);
2138 /* Floating point conversion between single and double precision */
2139 static always_inline uint32_t _do_efscfd (uint64_t val)
2145 u2.f = float64_to_float32(u1.d, &env->spe_status);
2150 static always_inline uint64_t _do_efdcfs (uint32_t val)
2156 u2.d = float32_to_float64(u1.f, &env->spe_status);
2161 void do_efscfd (void)
2163 T0_64 = _do_efscfd(T0_64);
2166 void do_efdcfs (void)
2168 T0_64 = _do_efdcfs(T0_64);
2171 /* Single precision fixed-point vector arithmetic */
2187 /* Single-precision floating-point comparisons */
2188 static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2190 /* XXX: TODO: test special values (NaN, infinites, ...) */
2191 return _do_efststlt(op1, op2);
2194 static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2196 /* XXX: TODO: test special values (NaN, infinites, ...) */
2197 return _do_efststgt(op1, op2);
2200 static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2202 /* XXX: TODO: test special values (NaN, infinites, ...) */
2203 return _do_efststeq(op1, op2);
2206 void do_efscmplt (void)
2208 T0 = _do_efscmplt(T0_64, T1_64);
2211 void do_efscmpgt (void)
2213 T0 = _do_efscmpgt(T0_64, T1_64);
2216 void do_efscmpeq (void)
2218 T0 = _do_efscmpeq(T0_64, T1_64);
2221 /* Single-precision floating-point vector comparisons */
2223 DO_SPE_CMP(fscmplt);
2225 DO_SPE_CMP(fscmpgt);
2227 DO_SPE_CMP(fscmpeq);
2229 DO_SPE_CMP(fststlt);
2231 DO_SPE_CMP(fststgt);
2233 DO_SPE_CMP(fststeq);
2235 /* Single-precision floating-point vector conversions */
2249 DO_SPE_OP1(fsctsiz);
2251 DO_SPE_OP1(fsctuiz);
2257 /*****************************************************************************/
2258 /* Softmmu support */
2259 #if !defined (CONFIG_USER_ONLY)
2261 #define MMUSUFFIX _mmu
2264 #include "softmmu_template.h"
2267 #include "softmmu_template.h"
2270 #include "softmmu_template.h"
2273 #include "softmmu_template.h"
2275 /* try to fill the TLB and return an exception if error. If retaddr is
2276 NULL, it means that the function was called in C code (i.e. not
2277 from generated code or from helper.c) */
2278 /* XXX: fix it to restore all registers */
2279 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2281 TranslationBlock *tb;
2282 CPUState *saved_env;
2286 /* XXX: hack to restore env in all cases, even if not called from
2289 env = cpu_single_env;
2290 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2291 if (unlikely(ret != 0)) {
2292 if (likely(retaddr)) {
2293 /* now we have a real cpu fault */
2294 pc = (unsigned long)retaddr;
2295 tb = tb_find_pc(pc);
2297 /* the PC is inside the translated code. It means that we have
2298 a virtual CPU fault */
2299 cpu_restore_state(tb, env, pc, NULL);
2302 do_raise_exception_err(env->exception_index, env->error_code);
2307 /* Software driven TLBs management */
2308 /* PowerPC 602/603 software TLB load instructions helpers */
2309 void do_load_6xx_tlb (int is_code)
2311 target_ulong RPN, CMP, EPN;
2314 RPN = env->spr[SPR_RPA];
2316 CMP = env->spr[SPR_ICMP];
2317 EPN = env->spr[SPR_IMISS];
2319 CMP = env->spr[SPR_DCMP];
2320 EPN = env->spr[SPR_DMISS];
2322 way = (env->spr[SPR_SRR1] >> 17) & 1;
2323 #if defined (DEBUG_SOFTWARE_TLB)
2324 if (loglevel != 0) {
2325 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2326 " PTE1 " ADDRX " way %d\n",
2327 __func__, T0, EPN, CMP, RPN, way);
2330 /* Store this TLB */
2331 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2332 way, is_code, CMP, RPN);
2335 void do_load_74xx_tlb (int is_code)
2337 target_ulong RPN, CMP, EPN;
2340 RPN = env->spr[SPR_PTELO];
2341 CMP = env->spr[SPR_PTEHI];
2342 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2343 way = env->spr[SPR_TLBMISS] & 0x3;
2344 #if defined (DEBUG_SOFTWARE_TLB)
2345 if (loglevel != 0) {
2346 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2347 " PTE1 " ADDRX " way %d\n",
2348 __func__, T0, EPN, CMP, RPN, way);
2351 /* Store this TLB */
2352 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2353 way, is_code, CMP, RPN);
2356 static always_inline target_ulong booke_tlb_to_page_size (int size)
2358 return 1024 << (2 * size);
2361 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2365 switch (page_size) {
2399 #if defined (TARGET_PPC64)
2400 case 0x000100000000ULL:
2403 case 0x000400000000ULL:
2406 case 0x001000000000ULL:
2409 case 0x004000000000ULL:
2412 case 0x010000000000ULL:
2424 /* Helpers for 4xx TLB management */
2425 void do_4xx_tlbre_lo (void)
2431 tlb = &env->tlb[T0].tlbe;
2433 if (tlb->prot & PAGE_VALID)
2435 size = booke_page_size_to_tlb(tlb->size);
2436 if (size < 0 || size > 0x7)
2439 env->spr[SPR_40x_PID] = tlb->PID;
2442 void do_4xx_tlbre_hi (void)
2447 tlb = &env->tlb[T0].tlbe;
2449 if (tlb->prot & PAGE_EXEC)
2451 if (tlb->prot & PAGE_WRITE)
2455 void do_4xx_tlbwe_hi (void)
2458 target_ulong page, end;
2460 #if defined (DEBUG_SOFTWARE_TLB)
2461 if (loglevel != 0) {
2462 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2466 tlb = &env->tlb[T0].tlbe;
2467 /* Invalidate previous TLB (if it's valid) */
2468 if (tlb->prot & PAGE_VALID) {
2469 end = tlb->EPN + tlb->size;
2470 #if defined (DEBUG_SOFTWARE_TLB)
2471 if (loglevel != 0) {
2472 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2473 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2476 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2477 tlb_flush_page(env, page);
2479 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2480 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2481 * If this ever occurs, one should use the ppcemb target instead
2482 * of the ppc or ppc64 one
2484 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2485 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2486 "are not supported (%d)\n",
2487 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2489 tlb->EPN = T1 & ~(tlb->size - 1);
2491 tlb->prot |= PAGE_VALID;
2493 tlb->prot &= ~PAGE_VALID;
2495 /* XXX: TO BE FIXED */
2496 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2498 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2499 tlb->attr = T1 & 0xFF;
2500 #if defined (DEBUG_SOFTWARE_TLB)
2501 if (loglevel != 0) {
2502 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2503 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2504 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2505 tlb->prot & PAGE_READ ? 'r' : '-',
2506 tlb->prot & PAGE_WRITE ? 'w' : '-',
2507 tlb->prot & PAGE_EXEC ? 'x' : '-',
2508 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2511 /* Invalidate new TLB (if valid) */
2512 if (tlb->prot & PAGE_VALID) {
2513 end = tlb->EPN + tlb->size;
2514 #if defined (DEBUG_SOFTWARE_TLB)
2515 if (loglevel != 0) {
2516 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2517 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2520 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2521 tlb_flush_page(env, page);
2525 void do_4xx_tlbwe_lo (void)
2529 #if defined (DEBUG_SOFTWARE_TLB)
2530 if (loglevel != 0) {
2531 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2535 tlb = &env->tlb[T0].tlbe;
2536 tlb->RPN = T1 & 0xFFFFFC00;
2537 tlb->prot = PAGE_READ;
2539 tlb->prot |= PAGE_EXEC;
2541 tlb->prot |= PAGE_WRITE;
2542 #if defined (DEBUG_SOFTWARE_TLB)
2543 if (loglevel != 0) {
2544 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2545 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2546 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2547 tlb->prot & PAGE_READ ? 'r' : '-',
2548 tlb->prot & PAGE_WRITE ? 'w' : '-',
2549 tlb->prot & PAGE_EXEC ? 'x' : '-',
2550 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2555 /* PowerPC 440 TLB management */
2556 void do_440_tlbwe (int word)
2559 target_ulong EPN, RPN, size;
2562 #if defined (DEBUG_SOFTWARE_TLB)
2563 if (loglevel != 0) {
2564 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2565 __func__, word, T0, T1);
2570 tlb = &env->tlb[T0].tlbe;
2573 /* Just here to please gcc */
2575 EPN = T1 & 0xFFFFFC00;
2576 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2579 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2580 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2584 tlb->attr |= (T1 >> 8) & 1;
2586 tlb->prot |= PAGE_VALID;
2588 if (tlb->prot & PAGE_VALID) {
2589 tlb->prot &= ~PAGE_VALID;
2593 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2598 RPN = T1 & 0xFFFFFC0F;
2599 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2604 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2605 tlb->prot = tlb->prot & PAGE_VALID;
2607 tlb->prot |= PAGE_READ << 4;
2609 tlb->prot |= PAGE_WRITE << 4;
2611 tlb->prot |= PAGE_EXEC << 4;
2613 tlb->prot |= PAGE_READ;
2615 tlb->prot |= PAGE_WRITE;
2617 tlb->prot |= PAGE_EXEC;
2622 void do_440_tlbre (int word)
2628 tlb = &env->tlb[T0].tlbe;
2631 /* Just here to please gcc */
2634 size = booke_page_size_to_tlb(tlb->size);
2635 if (size < 0 || size > 0xF)
2638 if (tlb->attr & 0x1)
2640 if (tlb->prot & PAGE_VALID)
2642 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2643 env->spr[SPR_440_MMUCR] |= tlb->PID;
2649 T0 = tlb->attr & ~0x1;
2650 if (tlb->prot & (PAGE_READ << 4))
2652 if (tlb->prot & (PAGE_WRITE << 4))
2654 if (tlb->prot & (PAGE_EXEC << 4))
2656 if (tlb->prot & PAGE_READ)
2658 if (tlb->prot & PAGE_WRITE)
2660 if (tlb->prot & PAGE_EXEC)
2665 #endif /* !CONFIG_USER_ONLY */