2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
25 #include "op_helper.h"
27 #define MEMSUFFIX _raw
28 #include "op_helper.h"
29 #include "op_helper_mem.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #define MEMSUFFIX _user
32 #include "op_helper.h"
33 #include "op_helper_mem.h"
34 #define MEMSUFFIX _kernel
35 #include "op_helper.h"
36 #include "op_helper_mem.h"
37 #define MEMSUFFIX _hypv
38 #include "op_helper.h"
39 #include "op_helper_mem.h"
43 //#define DEBUG_EXCEPTIONS
44 //#define DEBUG_SOFTWARE_TLB
46 /*****************************************************************************/
47 /* Exceptions processing helpers */
49 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
51 raise_exception_err(env, exception, error_code);
54 void helper_raise_debug (void)
56 raise_exception(env, EXCP_DEBUG);
60 /*****************************************************************************/
61 /* Registers load and stores */
62 target_ulong helper_load_cr (void)
64 return (env->crf[0] << 28) |
74 void helper_store_cr (target_ulong val, uint32_t mask)
78 for (i = 0, sh = 7; i < 8; i++, sh--) {
80 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
84 #if defined(TARGET_PPC64)
85 void do_store_pri (int prio)
87 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
88 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
92 target_ulong ppc_load_dump_spr (int sprn)
95 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
96 sprn, sprn, env->spr[sprn]);
99 return env->spr[sprn];
102 void ppc_store_dump_spr (int sprn, target_ulong val)
105 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
106 sprn, sprn, env->spr[sprn], val);
108 env->spr[sprn] = val;
111 /*****************************************************************************/
112 /* Fixed point operations helpers */
113 #if defined(TARGET_PPC64)
115 /* multiply high word */
116 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
120 muls64(&tl, &th, arg1, arg2);
124 /* multiply high word unsigned */
125 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
129 mulu64(&tl, &th, arg1, arg2);
133 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
138 muls64(&tl, (uint64_t *)&th, arg1, arg2);
139 /* If th != 0 && th != -1, then we had an overflow */
140 if (likely((uint64_t)(th + 1) <= 1)) {
141 env->xer &= ~(1 << XER_OV);
143 env->xer |= (1 << XER_OV) | (1 << XER_SO);
149 target_ulong helper_cntlzw (target_ulong t)
154 #if defined(TARGET_PPC64)
155 target_ulong helper_cntlzd (target_ulong t)
161 /* shift right arithmetic helper */
162 target_ulong helper_sraw (target_ulong value, target_ulong shift)
166 if (likely(!(shift & 0x20))) {
167 if (likely((uint32_t)shift != 0)) {
169 ret = (int32_t)value >> shift;
170 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
171 env->xer &= ~(1 << XER_CA);
173 env->xer |= (1 << XER_CA);
176 ret = (int32_t)value;
177 env->xer &= ~(1 << XER_CA);
180 ret = (int32_t)value >> 31;
182 env->xer |= (1 << XER_CA);
184 env->xer &= ~(1 << XER_CA);
187 return (target_long)ret;
190 #if defined(TARGET_PPC64)
191 target_ulong helper_srad (target_ulong value, target_ulong shift)
195 if (likely(!(shift & 0x40))) {
196 if (likely((uint64_t)shift != 0)) {
198 ret = (int64_t)value >> shift;
199 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
200 env->xer &= ~(1 << XER_CA);
202 env->xer |= (1 << XER_CA);
205 ret = (int64_t)value;
206 env->xer &= ~(1 << XER_CA);
209 ret = (int64_t)value >> 63;
211 env->xer |= (1 << XER_CA);
213 env->xer &= ~(1 << XER_CA);
220 target_ulong helper_popcntb (target_ulong val)
222 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
223 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
224 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
228 #if defined(TARGET_PPC64)
229 target_ulong helper_popcntb_64 (target_ulong val)
231 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
232 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
233 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
238 /*****************************************************************************/
239 /* Floating point operations helpers */
240 static always_inline int fpisneg (float64 d)
246 return u.ll >> 63 != 0;
249 static always_inline int isden (float64 d)
255 return ((u.ll >> 52) & 0x7FF) == 0;
258 static always_inline int iszero (float64 d)
264 return (u.ll & ~0x8000000000000000ULL) == 0;
267 static always_inline int isinfinity (float64 d)
273 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
274 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
277 #ifdef CONFIG_SOFTFLOAT
278 static always_inline int isfinite (float64 d)
284 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
287 static always_inline int isnormal (float64 d)
293 uint32_t exp = (u.ll >> 52) & 0x7FF;
294 return ((0 < exp) && (exp < 0x7FF));
298 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
304 isneg = fpisneg(farg.d);
305 if (unlikely(float64_is_nan(farg.d))) {
306 if (float64_is_signaling_nan(farg.d)) {
307 /* Signaling NaN: flags are undefined */
313 } else if (unlikely(isinfinity(farg.d))) {
320 if (iszero(farg.d)) {
328 /* Denormalized numbers */
331 /* Normalized numbers */
342 /* We update FPSCR_FPRF */
343 env->fpscr &= ~(0x1F << FPSCR_FPRF);
344 env->fpscr |= ret << FPSCR_FPRF;
346 /* We just need fpcc to update Rc1 */
350 /* Floating-point invalid operations exception */
351 static always_inline uint64_t fload_invalid_op_excp (int op)
357 if (op & POWERPC_EXCP_FP_VXSNAN) {
358 /* Operation on signaling NaN */
359 env->fpscr |= 1 << FPSCR_VXSNAN;
361 if (op & POWERPC_EXCP_FP_VXSOFT) {
362 /* Software-defined condition */
363 env->fpscr |= 1 << FPSCR_VXSOFT;
365 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
366 case POWERPC_EXCP_FP_VXISI:
367 /* Magnitude subtraction of infinities */
368 env->fpscr |= 1 << FPSCR_VXISI;
370 case POWERPC_EXCP_FP_VXIDI:
371 /* Division of infinity by infinity */
372 env->fpscr |= 1 << FPSCR_VXIDI;
374 case POWERPC_EXCP_FP_VXZDZ:
375 /* Division of zero by zero */
376 env->fpscr |= 1 << FPSCR_VXZDZ;
378 case POWERPC_EXCP_FP_VXIMZ:
379 /* Multiplication of zero by infinity */
380 env->fpscr |= 1 << FPSCR_VXIMZ;
382 case POWERPC_EXCP_FP_VXVC:
383 /* Ordered comparison of NaN */
384 env->fpscr |= 1 << FPSCR_VXVC;
385 env->fpscr &= ~(0xF << FPSCR_FPCC);
386 env->fpscr |= 0x11 << FPSCR_FPCC;
387 /* We must update the target FPR before raising the exception */
389 env->exception_index = POWERPC_EXCP_PROGRAM;
390 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
391 /* Update the floating-point enabled exception summary */
392 env->fpscr |= 1 << FPSCR_FEX;
393 /* Exception is differed */
397 case POWERPC_EXCP_FP_VXSQRT:
398 /* Square root of a negative number */
399 env->fpscr |= 1 << FPSCR_VXSQRT;
401 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
403 /* Set the result to quiet NaN */
405 env->fpscr &= ~(0xF << FPSCR_FPCC);
406 env->fpscr |= 0x11 << FPSCR_FPCC;
409 case POWERPC_EXCP_FP_VXCVI:
410 /* Invalid conversion */
411 env->fpscr |= 1 << FPSCR_VXCVI;
412 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
414 /* Set the result to quiet NaN */
416 env->fpscr &= ~(0xF << FPSCR_FPCC);
417 env->fpscr |= 0x11 << FPSCR_FPCC;
421 /* Update the floating-point invalid operation summary */
422 env->fpscr |= 1 << FPSCR_VX;
423 /* Update the floating-point exception summary */
424 env->fpscr |= 1 << FPSCR_FX;
426 /* Update the floating-point enabled exception summary */
427 env->fpscr |= 1 << FPSCR_FEX;
428 if (msr_fe0 != 0 || msr_fe1 != 0)
429 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
434 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
436 env->fpscr |= 1 << FPSCR_ZX;
437 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
438 /* Update the floating-point exception summary */
439 env->fpscr |= 1 << FPSCR_FX;
441 /* Update the floating-point enabled exception summary */
442 env->fpscr |= 1 << FPSCR_FEX;
443 if (msr_fe0 != 0 || msr_fe1 != 0) {
444 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
445 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
448 /* Set the result to infinity */
449 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
450 arg1 |= 0x7FFULL << 52;
455 static always_inline void float_overflow_excp (void)
457 env->fpscr |= 1 << FPSCR_OX;
458 /* Update the floating-point exception summary */
459 env->fpscr |= 1 << FPSCR_FX;
461 /* XXX: should adjust the result */
462 /* Update the floating-point enabled exception summary */
463 env->fpscr |= 1 << FPSCR_FEX;
464 /* We must update the target FPR before raising the exception */
465 env->exception_index = POWERPC_EXCP_PROGRAM;
466 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
468 env->fpscr |= 1 << FPSCR_XX;
469 env->fpscr |= 1 << FPSCR_FI;
473 static always_inline void float_underflow_excp (void)
475 env->fpscr |= 1 << FPSCR_UX;
476 /* Update the floating-point exception summary */
477 env->fpscr |= 1 << FPSCR_FX;
479 /* XXX: should adjust the result */
480 /* Update the floating-point enabled exception summary */
481 env->fpscr |= 1 << FPSCR_FEX;
482 /* We must update the target FPR before raising the exception */
483 env->exception_index = POWERPC_EXCP_PROGRAM;
484 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
488 static always_inline void float_inexact_excp (void)
490 env->fpscr |= 1 << FPSCR_XX;
491 /* Update the floating-point exception summary */
492 env->fpscr |= 1 << FPSCR_FX;
494 /* Update the floating-point enabled exception summary */
495 env->fpscr |= 1 << FPSCR_FEX;
496 /* We must update the target FPR before raising the exception */
497 env->exception_index = POWERPC_EXCP_PROGRAM;
498 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
502 static always_inline void fpscr_set_rounding_mode (void)
506 /* Set rounding mode */
509 /* Best approximation (round to nearest) */
510 rnd_type = float_round_nearest_even;
513 /* Smaller magnitude (round toward zero) */
514 rnd_type = float_round_to_zero;
517 /* Round toward +infinite */
518 rnd_type = float_round_up;
522 /* Round toward -infinite */
523 rnd_type = float_round_down;
526 set_float_rounding_mode(rnd_type, &env->fp_status);
529 void helper_fpscr_setbit (uint32_t bit)
533 prev = (env->fpscr >> bit) & 1;
534 env->fpscr |= 1 << bit;
538 env->fpscr |= 1 << FPSCR_FX;
542 env->fpscr |= 1 << FPSCR_FX;
547 env->fpscr |= 1 << FPSCR_FX;
552 env->fpscr |= 1 << FPSCR_FX;
557 env->fpscr |= 1 << FPSCR_FX;
570 env->fpscr |= 1 << FPSCR_VX;
571 env->fpscr |= 1 << FPSCR_FX;
578 env->error_code = POWERPC_EXCP_FP;
580 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
582 env->error_code |= POWERPC_EXCP_FP_VXISI;
584 env->error_code |= POWERPC_EXCP_FP_VXIDI;
586 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
588 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
590 env->error_code |= POWERPC_EXCP_FP_VXVC;
592 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
594 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
596 env->error_code |= POWERPC_EXCP_FP_VXCVI;
603 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
610 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
617 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
624 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
630 fpscr_set_rounding_mode();
635 /* Update the floating-point enabled exception summary */
636 env->fpscr |= 1 << FPSCR_FEX;
637 /* We have to update Rc1 before raising the exception */
638 env->exception_index = POWERPC_EXCP_PROGRAM;
644 void helper_store_fpscr (uint64_t arg, uint32_t mask)
647 * We use only the 32 LSB of the incoming fpr
655 new |= prev & 0x90000000;
656 for (i = 0; i < 7; i++) {
657 if (mask & (1 << i)) {
658 env->fpscr &= ~(0xF << (4 * i));
659 env->fpscr |= new & (0xF << (4 * i));
662 /* Update VX and FEX */
664 env->fpscr |= 1 << FPSCR_VX;
666 env->fpscr &= ~(1 << FPSCR_VX);
667 if ((fpscr_ex & fpscr_eex) != 0) {
668 env->fpscr |= 1 << FPSCR_FEX;
669 env->exception_index = POWERPC_EXCP_PROGRAM;
670 /* XXX: we should compute it properly */
671 env->error_code = POWERPC_EXCP_FP;
674 env->fpscr &= ~(1 << FPSCR_FEX);
675 fpscr_set_rounding_mode();
678 void helper_float_check_status (void)
680 #ifdef CONFIG_SOFTFLOAT
681 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
682 (env->error_code & POWERPC_EXCP_FP)) {
683 /* Differred floating-point exception after target FPR update */
684 if (msr_fe0 != 0 || msr_fe1 != 0)
685 raise_exception_err(env, env->exception_index, env->error_code);
686 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
687 float_overflow_excp();
688 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
689 float_underflow_excp();
690 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
691 float_inexact_excp();
694 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
695 (env->error_code & POWERPC_EXCP_FP)) {
696 /* Differred floating-point exception after target FPR update */
697 if (msr_fe0 != 0 || msr_fe1 != 0)
698 raise_exception_err(env, env->exception_index, env->error_code);
704 #ifdef CONFIG_SOFTFLOAT
705 void helper_reset_fpstatus (void)
707 env->fp_status.float_exception_flags = 0;
712 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
714 CPU_DoubleU farg1, farg2;
718 #if USE_PRECISE_EMULATION
719 if (unlikely(float64_is_signaling_nan(farg1.d) ||
720 float64_is_signaling_nan(farg2.d))) {
722 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
723 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
724 fpisneg(farg1.d) == fpisneg(farg2.d))) {
725 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
727 /* Magnitude subtraction of infinities */
728 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
731 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
737 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
739 CPU_DoubleU farg1, farg2;
743 #if USE_PRECISE_EMULATION
745 if (unlikely(float64_is_signaling_nan(farg1.d) ||
746 float64_is_signaling_nan(farg2.d))) {
747 /* sNaN subtraction */
748 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
749 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
750 fpisneg(farg1.d) != fpisneg(farg2.d))) {
751 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
753 /* Magnitude subtraction of infinities */
754 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
758 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
764 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
766 CPU_DoubleU farg1, farg2;
770 #if USE_PRECISE_EMULATION
771 if (unlikely(float64_is_signaling_nan(farg1.d) ||
772 float64_is_signaling_nan(farg2.d))) {
773 /* sNaN multiplication */
774 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
775 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
776 (iszero(farg1.d) && isinfinity(farg2.d)))) {
777 /* Multiplication of zero by infinity */
778 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
780 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
784 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
790 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
792 CPU_DoubleU farg1, farg2;
796 #if USE_PRECISE_EMULATION
797 if (unlikely(float64_is_signaling_nan(farg1.d) ||
798 float64_is_signaling_nan(farg2.d))) {
800 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
801 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
802 /* Division of infinity by infinity */
803 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
804 } else if (unlikely(iszero(farg2.d))) {
805 if (iszero(farg1.d)) {
806 /* Division of zero by zero */
807 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
809 /* Division by zero */
810 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
813 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
816 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
822 uint64_t helper_fabs (uint64_t arg)
827 farg.d = float64_abs(farg.d);
832 uint64_t helper_fnabs (uint64_t arg)
837 farg.d = float64_abs(farg.d);
838 farg.d = float64_chs(farg.d);
843 uint64_t helper_fneg (uint64_t arg)
848 farg.d = float64_chs(farg.d);
853 uint64_t helper_fctiw (uint64_t arg)
858 if (unlikely(float64_is_signaling_nan(farg.d))) {
859 /* sNaN conversion */
860 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
861 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
862 /* qNan / infinity conversion */
863 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
865 farg.ll = float64_to_int32(farg.d, &env->fp_status);
866 #if USE_PRECISE_EMULATION
867 /* XXX: higher bits are not supposed to be significant.
868 * to make tests easier, return the same as a real PowerPC 750
870 farg.ll |= 0xFFF80000ULL << 32;
876 /* fctiwz - fctiwz. */
877 uint64_t helper_fctiwz (uint64_t arg)
882 if (unlikely(float64_is_signaling_nan(farg.d))) {
883 /* sNaN conversion */
884 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
885 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
886 /* qNan / infinity conversion */
887 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
889 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
890 #if USE_PRECISE_EMULATION
891 /* XXX: higher bits are not supposed to be significant.
892 * to make tests easier, return the same as a real PowerPC 750
894 farg.ll |= 0xFFF80000ULL << 32;
900 #if defined(TARGET_PPC64)
902 uint64_t helper_fcfid (uint64_t arg)
905 farg.d = int64_to_float64(arg, &env->fp_status);
910 uint64_t helper_fctid (uint64_t arg)
915 if (unlikely(float64_is_signaling_nan(farg.d))) {
916 /* sNaN conversion */
917 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
918 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
919 /* qNan / infinity conversion */
920 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
922 farg.ll = float64_to_int64(farg.d, &env->fp_status);
927 /* fctidz - fctidz. */
928 uint64_t helper_fctidz (uint64_t arg)
933 if (unlikely(float64_is_signaling_nan(farg.d))) {
934 /* sNaN conversion */
935 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
936 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
937 /* qNan / infinity conversion */
938 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
940 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
947 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
952 if (unlikely(float64_is_signaling_nan(farg.d))) {
954 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
955 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
956 /* qNan / infinity round */
957 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
959 set_float_rounding_mode(rounding_mode, &env->fp_status);
960 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
961 /* Restore rounding mode from FPSCR */
962 fpscr_set_rounding_mode();
967 uint64_t helper_frin (uint64_t arg)
969 return do_fri(arg, float_round_nearest_even);
972 uint64_t helper_friz (uint64_t arg)
974 return do_fri(arg, float_round_to_zero);
977 uint64_t helper_frip (uint64_t arg)
979 return do_fri(arg, float_round_up);
982 uint64_t helper_frim (uint64_t arg)
984 return do_fri(arg, float_round_down);
988 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
990 CPU_DoubleU farg1, farg2, farg3;
995 #if USE_PRECISE_EMULATION
996 if (unlikely(float64_is_signaling_nan(farg1.d) ||
997 float64_is_signaling_nan(farg2.d) ||
998 float64_is_signaling_nan(farg3.d))) {
1000 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1003 /* This is the way the PowerPC specification defines it */
1004 float128 ft0_128, ft1_128;
1006 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1007 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1008 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1009 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1010 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1011 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1013 /* This is OK on x86 hosts */
1014 farg1.d = (farg1.d * farg2.d) + farg3.d;
1018 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1019 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1024 /* fmsub - fmsub. */
1025 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1027 CPU_DoubleU farg1, farg2, farg3;
1032 #if USE_PRECISE_EMULATION
1033 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1034 float64_is_signaling_nan(farg2.d) ||
1035 float64_is_signaling_nan(farg3.d))) {
1036 /* sNaN operation */
1037 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1040 /* This is the way the PowerPC specification defines it */
1041 float128 ft0_128, ft1_128;
1043 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1044 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1045 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1046 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1047 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1048 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1050 /* This is OK on x86 hosts */
1051 farg1.d = (farg1.d * farg2.d) - farg3.d;
1055 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1056 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1061 /* fnmadd - fnmadd. */
1062 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1064 CPU_DoubleU farg1, farg2, farg3;
1070 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1071 float64_is_signaling_nan(farg2.d) ||
1072 float64_is_signaling_nan(farg3.d))) {
1073 /* sNaN operation */
1074 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1076 #if USE_PRECISE_EMULATION
1078 /* This is the way the PowerPC specification defines it */
1079 float128 ft0_128, ft1_128;
1081 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1082 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1083 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1084 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1085 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1086 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1088 /* This is OK on x86 hosts */
1089 farg1.d = (farg1.d * farg2.d) + farg3.d;
1092 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1093 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1095 if (likely(!isnan(farg1.d)))
1096 farg1.d = float64_chs(farg1.d);
1101 /* fnmsub - fnmsub. */
1102 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1104 CPU_DoubleU farg1, farg2, farg3;
1110 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1111 float64_is_signaling_nan(farg2.d) ||
1112 float64_is_signaling_nan(farg3.d))) {
1113 /* sNaN operation */
1114 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1116 #if USE_PRECISE_EMULATION
1118 /* This is the way the PowerPC specification defines it */
1119 float128 ft0_128, ft1_128;
1121 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1122 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1123 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1124 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1125 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1126 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1128 /* This is OK on x86 hosts */
1129 farg1.d = (farg1.d * farg2.d) - farg3.d;
1132 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1133 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1135 if (likely(!isnan(farg1.d)))
1136 farg1.d = float64_chs(farg1.d);
1143 uint64_t helper_frsp (uint64_t arg)
1148 #if USE_PRECISE_EMULATION
1149 if (unlikely(float64_is_signaling_nan(farg.d))) {
1150 /* sNaN square root */
1151 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1153 fard.d = float64_to_float32(farg.d, &env->fp_status);
1156 farg.d = float64_to_float32(farg.d, &env->fp_status);
1161 /* fsqrt - fsqrt. */
1162 uint64_t helper_fsqrt (uint64_t arg)
1167 if (unlikely(float64_is_signaling_nan(farg.d))) {
1168 /* sNaN square root */
1169 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1170 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1171 /* Square root of a negative nonzero number */
1172 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1174 farg.d = float64_sqrt(farg.d, &env->fp_status);
1180 uint64_t helper_fre (uint64_t arg)
1185 if (unlikely(float64_is_signaling_nan(farg.d))) {
1186 /* sNaN reciprocal */
1187 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1188 } else if (unlikely(iszero(farg.d))) {
1189 /* Zero reciprocal */
1190 farg.ll = float_zero_divide_excp(1.0, farg.d);
1191 } else if (likely(isnormal(farg.d))) {
1192 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1194 if (farg.ll == 0x8000000000000000ULL) {
1195 farg.ll = 0xFFF0000000000000ULL;
1196 } else if (farg.ll == 0x0000000000000000ULL) {
1197 farg.ll = 0x7FF0000000000000ULL;
1198 } else if (isnan(farg.d)) {
1199 farg.ll = 0x7FF8000000000000ULL;
1200 } else if (fpisneg(farg.d)) {
1201 farg.ll = 0x8000000000000000ULL;
1203 farg.ll = 0x0000000000000000ULL;
1210 uint64_t helper_fres (uint64_t arg)
1215 if (unlikely(float64_is_signaling_nan(farg.d))) {
1216 /* sNaN reciprocal */
1217 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1218 } else if (unlikely(iszero(farg.d))) {
1219 /* Zero reciprocal */
1220 farg.ll = float_zero_divide_excp(1.0, farg.d);
1221 } else if (likely(isnormal(farg.d))) {
1222 #if USE_PRECISE_EMULATION
1223 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1224 farg.d = float64_to_float32(farg.d, &env->fp_status);
1226 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1229 if (farg.ll == 0x8000000000000000ULL) {
1230 farg.ll = 0xFFF0000000000000ULL;
1231 } else if (farg.ll == 0x0000000000000000ULL) {
1232 farg.ll = 0x7FF0000000000000ULL;
1233 } else if (isnan(farg.d)) {
1234 farg.ll = 0x7FF8000000000000ULL;
1235 } else if (fpisneg(farg.d)) {
1236 farg.ll = 0x8000000000000000ULL;
1238 farg.ll = 0x0000000000000000ULL;
1244 /* frsqrte - frsqrte. */
1245 uint64_t helper_frsqrte (uint64_t arg)
1250 if (unlikely(float64_is_signaling_nan(farg.d))) {
1251 /* sNaN reciprocal square root */
1252 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1253 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1254 /* Reciprocal square root of a negative nonzero number */
1255 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1256 } else if (likely(isnormal(farg.d))) {
1257 farg.d = float64_sqrt(farg.d, &env->fp_status);
1258 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1260 if (farg.ll == 0x8000000000000000ULL) {
1261 farg.ll = 0xFFF0000000000000ULL;
1262 } else if (farg.ll == 0x0000000000000000ULL) {
1263 farg.ll = 0x7FF0000000000000ULL;
1264 } else if (isnan(farg.d)) {
1265 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1266 } else if (fpisneg(farg.d)) {
1267 farg.ll = 0x7FF8000000000000ULL;
1269 farg.ll = 0x0000000000000000ULL;
1276 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1278 CPU_DoubleU farg1, farg2, farg3;
1284 if (!fpisneg(farg1.d) || iszero(farg1.d))
1290 uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
1292 CPU_DoubleU farg1, farg2;
1297 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1298 float64_is_signaling_nan(farg2.d))) {
1299 /* sNaN comparison */
1300 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1302 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1304 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1310 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1311 env->fpscr |= ret << FPSCR_FPRF;
1315 uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
1317 CPU_DoubleU farg1, farg2;
1322 if (unlikely(float64_is_nan(farg1.d) ||
1323 float64_is_nan(farg2.d))) {
1324 if (float64_is_signaling_nan(farg1.d) ||
1325 float64_is_signaling_nan(farg2.d)) {
1326 /* sNaN comparison */
1327 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1328 POWERPC_EXCP_FP_VXVC);
1330 /* qNaN comparison */
1331 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1334 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1336 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1342 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1343 env->fpscr |= ret << FPSCR_FPRF;
1347 #if !defined (CONFIG_USER_ONLY)
1348 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1350 void do_store_msr (void)
1352 T0 = hreg_store_msr(env, T0, 0);
1354 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1355 raise_exception(env, T0);
1359 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1360 target_ulong msrm, int keep_msrh)
1362 #if defined(TARGET_PPC64)
1363 if (msr & (1ULL << MSR_SF)) {
1364 nip = (uint64_t)nip;
1365 msr &= (uint64_t)msrm;
1367 nip = (uint32_t)nip;
1368 msr = (uint32_t)(msr & msrm);
1370 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1373 nip = (uint32_t)nip;
1374 msr &= (uint32_t)msrm;
1376 /* XXX: beware: this is false if VLE is supported */
1377 env->nip = nip & ~((target_ulong)0x00000003);
1378 hreg_store_msr(env, msr, 1);
1379 #if defined (DEBUG_OP)
1380 cpu_dump_rfi(env->nip, env->msr);
1382 /* No need to raise an exception here,
1383 * as rfi is always the last insn of a TB
1385 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1390 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1391 ~((target_ulong)0xFFFF0000), 1);
1394 #if defined(TARGET_PPC64)
1397 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1398 ~((target_ulong)0xFFFF0000), 0);
1401 void do_hrfid (void)
1403 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1404 ~((target_ulong)0xFFFF0000), 0);
1409 void do_tw (int flags)
1411 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1412 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1413 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1414 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
1415 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
1416 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1420 #if defined(TARGET_PPC64)
1421 void do_td (int flags)
1423 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1424 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1425 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1426 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1427 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
1428 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1432 /*****************************************************************************/
1433 /* PowerPC 601 specific instructions (POWER bridge) */
1434 void do_POWER_abso (void)
1436 if ((int32_t)T0 == INT32_MIN) {
1438 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1439 } else if ((int32_t)T0 < 0) {
1441 env->xer &= ~(1 << XER_OV);
1443 env->xer &= ~(1 << XER_OV);
1447 void do_POWER_clcs (void)
1451 /* Instruction cache line size */
1452 T0 = env->icache_line_size;
1455 /* Data cache line size */
1456 T0 = env->dcache_line_size;
1459 /* Minimum cache line size */
1460 T0 = env->icache_line_size < env->dcache_line_size ?
1461 env->icache_line_size : env->dcache_line_size;
1464 /* Maximum cache line size */
1465 T0 = env->icache_line_size > env->dcache_line_size ?
1466 env->icache_line_size : env->dcache_line_size;
1474 void do_POWER_div (void)
1478 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1480 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1481 env->spr[SPR_MQ] = 0;
1483 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1484 env->spr[SPR_MQ] = tmp % T1;
1485 T0 = tmp / (int32_t)T1;
1489 void do_POWER_divo (void)
1493 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1495 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1496 env->spr[SPR_MQ] = 0;
1497 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1499 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1500 env->spr[SPR_MQ] = tmp % T1;
1502 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1503 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1505 env->xer &= ~(1 << XER_OV);
1511 void do_POWER_divs (void)
1513 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1515 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1516 env->spr[SPR_MQ] = 0;
1518 env->spr[SPR_MQ] = T0 % T1;
1519 T0 = (int32_t)T0 / (int32_t)T1;
1523 void do_POWER_divso (void)
1525 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1527 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1528 env->spr[SPR_MQ] = 0;
1529 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1531 T0 = (int32_t)T0 / (int32_t)T1;
1532 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1533 env->xer &= ~(1 << XER_OV);
1537 void do_POWER_dozo (void)
1539 if ((int32_t)T1 > (int32_t)T0) {
1542 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1543 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1544 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1546 env->xer &= ~(1 << XER_OV);
1550 env->xer &= ~(1 << XER_OV);
1554 void do_POWER_maskg (void)
1558 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1561 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1562 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1563 if ((uint32_t)T0 > (uint32_t)T1)
1569 void do_POWER_mulo (void)
1573 tmp = (uint64_t)T0 * (uint64_t)T1;
1574 env->spr[SPR_MQ] = tmp >> 32;
1576 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1577 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1579 env->xer &= ~(1 << XER_OV);
1583 #if !defined (CONFIG_USER_ONLY)
1584 void do_POWER_rac (void)
1589 /* We don't have to generate many instances of this instruction,
1590 * as rac is supervisor only.
1592 /* XXX: FIX THIS: Pretend we have no BAT */
1593 nb_BATs = env->nb_BATs;
1595 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1597 env->nb_BATs = nb_BATs;
1600 void do_POWER_rfsvc (void)
1602 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1605 void do_store_hid0_601 (void)
1609 hid0 = env->spr[SPR_HID0];
1610 if ((T0 ^ hid0) & 0x00000008) {
1611 /* Change current endianness */
1612 env->hflags &= ~(1 << MSR_LE);
1613 env->hflags_nmsr &= ~(1 << MSR_LE);
1614 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1615 env->hflags |= env->hflags_nmsr;
1616 if (loglevel != 0) {
1617 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1618 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1621 env->spr[SPR_HID0] = T0;
1625 /*****************************************************************************/
1626 /* 602 specific instructions */
1627 /* mfrom is the most crazy instruction ever seen, imho ! */
1628 /* Real implementation uses a ROM table. Do the same */
1629 #define USE_MFROM_ROM_TABLE
1630 void do_op_602_mfrom (void)
1632 if (likely(T0 < 602)) {
1633 #if defined(USE_MFROM_ROM_TABLE)
1634 #include "mfrom_table.c"
1635 T0 = mfrom_ROM_table[T0];
1638 /* Extremly decomposed:
1640 * T0 = 256 * log10(10 + 1.0) + 0.5
1643 d = float64_div(d, 256, &env->fp_status);
1645 d = exp10(d); // XXX: use float emulation function
1646 d = float64_add(d, 1.0, &env->fp_status);
1647 d = log10(d); // XXX: use float emulation function
1648 d = float64_mul(d, 256, &env->fp_status);
1649 d = float64_add(d, 0.5, &env->fp_status);
1650 T0 = float64_round_to_int(d, &env->fp_status);
1657 /*****************************************************************************/
1658 /* Embedded PowerPC specific helpers */
1660 /* XXX: to be improved to check access rights when in user-mode */
1661 void do_load_dcr (void)
1665 if (unlikely(env->dcr_env == NULL)) {
1666 if (loglevel != 0) {
1667 fprintf(logfile, "No DCR environment\n");
1669 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1670 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1671 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1672 if (loglevel != 0) {
1673 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1675 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1676 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1682 void do_store_dcr (void)
1684 if (unlikely(env->dcr_env == NULL)) {
1685 if (loglevel != 0) {
1686 fprintf(logfile, "No DCR environment\n");
1688 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1689 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1690 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1691 if (loglevel != 0) {
1692 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1694 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1695 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1699 #if !defined(CONFIG_USER_ONLY)
1700 void do_40x_rfci (void)
1702 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1703 ~((target_ulong)0xFFFF0000), 0);
1708 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1709 ~((target_ulong)0x3FFF0000), 0);
1714 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1715 ~((target_ulong)0x3FFF0000), 0);
1718 void do_rfmci (void)
1720 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1721 ~((target_ulong)0x3FFF0000), 0);
1724 void do_load_403_pb (int num)
1729 void do_store_403_pb (int num)
1731 if (likely(env->pb[num] != T0)) {
1733 /* Should be optimized */
1740 void do_440_dlmzb (void)
1746 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1747 if ((T0 & mask) == 0)
1751 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1752 if ((T1 & mask) == 0)
1760 /* SPE extension helpers */
1761 /* Use a table to make this quicker */
1762 static uint8_t hbrev[16] = {
1763 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1764 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1767 static always_inline uint8_t byte_reverse (uint8_t val)
1769 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1772 static always_inline uint32_t word_reverse (uint32_t val)
1774 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1775 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1778 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1779 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
1781 uint32_t a, b, d, mask;
1783 mask = UINT32_MAX >> (32 - MASKBITS);
1786 d = word_reverse(1 + word_reverse(a | ~b));
1787 return (arg1 & ~mask) | (d & b);
1790 uint32_t helper_cntlsw32 (uint32_t val)
1792 if (val & 0x80000000)
1798 uint32_t helper_cntlzw32 (uint32_t val)
1803 #define DO_SPE_OP1(name) \
1804 void do_ev##name (void) \
1806 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1807 (uint64_t)_do_e##name(T0_64); \
1810 #define DO_SPE_OP2(name) \
1811 void do_ev##name (void) \
1813 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1814 (uint64_t)_do_e##name(T0_64, T1_64); \
1817 /* Fixed-point vector comparisons */
1818 #define DO_SPE_CMP(name) \
1819 void do_ev##name (void) \
1821 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1822 T1_64 >> 32) << 32, \
1823 _do_e##name(T0_64, T1_64)); \
1826 static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
1828 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1831 /* Single precision floating-point conversions from/to integer */
1832 static always_inline uint32_t _do_efscfsi (int32_t val)
1836 u.f = int32_to_float32(val, &env->spe_status);
1841 static always_inline uint32_t _do_efscfui (uint32_t val)
1845 u.f = uint32_to_float32(val, &env->spe_status);
1850 static always_inline int32_t _do_efsctsi (uint32_t val)
1855 /* NaN are not treated the same way IEEE 754 does */
1856 if (unlikely(isnan(u.f)))
1859 return float32_to_int32(u.f, &env->spe_status);
1862 static always_inline uint32_t _do_efsctui (uint32_t val)
1867 /* NaN are not treated the same way IEEE 754 does */
1868 if (unlikely(isnan(u.f)))
1871 return float32_to_uint32(u.f, &env->spe_status);
1874 static always_inline int32_t _do_efsctsiz (uint32_t val)
1879 /* NaN are not treated the same way IEEE 754 does */
1880 if (unlikely(isnan(u.f)))
1883 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1886 static always_inline uint32_t _do_efsctuiz (uint32_t val)
1891 /* NaN are not treated the same way IEEE 754 does */
1892 if (unlikely(isnan(u.f)))
1895 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1898 void do_efscfsi (void)
1900 T0_64 = _do_efscfsi(T0_64);
1903 void do_efscfui (void)
1905 T0_64 = _do_efscfui(T0_64);
1908 void do_efsctsi (void)
1910 T0_64 = _do_efsctsi(T0_64);
1913 void do_efsctui (void)
1915 T0_64 = _do_efsctui(T0_64);
1918 void do_efsctsiz (void)
1920 T0_64 = _do_efsctsiz(T0_64);
1923 void do_efsctuiz (void)
1925 T0_64 = _do_efsctuiz(T0_64);
1928 /* Single precision floating-point conversion to/from fractional */
1929 static always_inline uint32_t _do_efscfsf (uint32_t val)
1934 u.f = int32_to_float32(val, &env->spe_status);
1935 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1936 u.f = float32_div(u.f, tmp, &env->spe_status);
1941 static always_inline uint32_t _do_efscfuf (uint32_t val)
1946 u.f = uint32_to_float32(val, &env->spe_status);
1947 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1948 u.f = float32_div(u.f, tmp, &env->spe_status);
1953 static always_inline int32_t _do_efsctsf (uint32_t val)
1959 /* NaN are not treated the same way IEEE 754 does */
1960 if (unlikely(isnan(u.f)))
1962 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1963 u.f = float32_mul(u.f, tmp, &env->spe_status);
1965 return float32_to_int32(u.f, &env->spe_status);
1968 static always_inline uint32_t _do_efsctuf (uint32_t val)
1974 /* NaN are not treated the same way IEEE 754 does */
1975 if (unlikely(isnan(u.f)))
1977 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1978 u.f = float32_mul(u.f, tmp, &env->spe_status);
1980 return float32_to_uint32(u.f, &env->spe_status);
1983 static always_inline int32_t _do_efsctsfz (uint32_t val)
1989 /* NaN are not treated the same way IEEE 754 does */
1990 if (unlikely(isnan(u.f)))
1992 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1993 u.f = float32_mul(u.f, tmp, &env->spe_status);
1995 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1998 static always_inline uint32_t _do_efsctufz (uint32_t val)
2004 /* NaN are not treated the same way IEEE 754 does */
2005 if (unlikely(isnan(u.f)))
2007 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2008 u.f = float32_mul(u.f, tmp, &env->spe_status);
2010 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2013 void do_efscfsf (void)
2015 T0_64 = _do_efscfsf(T0_64);
2018 void do_efscfuf (void)
2020 T0_64 = _do_efscfuf(T0_64);
2023 void do_efsctsf (void)
2025 T0_64 = _do_efsctsf(T0_64);
2028 void do_efsctuf (void)
2030 T0_64 = _do_efsctuf(T0_64);
2033 void do_efsctsfz (void)
2035 T0_64 = _do_efsctsfz(T0_64);
2038 void do_efsctufz (void)
2040 T0_64 = _do_efsctufz(T0_64);
2043 /* Double precision floating point helpers */
2044 static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
2046 /* XXX: TODO: test special values (NaN, infinites, ...) */
2047 return _do_efdtstlt(op1, op2);
2050 static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
2052 /* XXX: TODO: test special values (NaN, infinites, ...) */
2053 return _do_efdtstgt(op1, op2);
2056 static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
2058 /* XXX: TODO: test special values (NaN, infinites, ...) */
2059 return _do_efdtsteq(op1, op2);
2062 void do_efdcmplt (void)
2064 T0 = _do_efdcmplt(T0_64, T1_64);
2067 void do_efdcmpgt (void)
2069 T0 = _do_efdcmpgt(T0_64, T1_64);
2072 void do_efdcmpeq (void)
2074 T0 = _do_efdcmpeq(T0_64, T1_64);
2077 /* Double precision floating-point conversion to/from integer */
2078 static always_inline uint64_t _do_efdcfsi (int64_t val)
2082 u.d = int64_to_float64(val, &env->spe_status);
2087 static always_inline uint64_t _do_efdcfui (uint64_t val)
2091 u.d = uint64_to_float64(val, &env->spe_status);
2096 static always_inline int64_t _do_efdctsi (uint64_t val)
2101 /* NaN are not treated the same way IEEE 754 does */
2102 if (unlikely(isnan(u.d)))
2105 return float64_to_int64(u.d, &env->spe_status);
2108 static always_inline uint64_t _do_efdctui (uint64_t val)
2113 /* NaN are not treated the same way IEEE 754 does */
2114 if (unlikely(isnan(u.d)))
2117 return float64_to_uint64(u.d, &env->spe_status);
2120 static always_inline int64_t _do_efdctsiz (uint64_t val)
2125 /* NaN are not treated the same way IEEE 754 does */
2126 if (unlikely(isnan(u.d)))
2129 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2132 static always_inline uint64_t _do_efdctuiz (uint64_t val)
2137 /* NaN are not treated the same way IEEE 754 does */
2138 if (unlikely(isnan(u.d)))
2141 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2144 void do_efdcfsi (void)
2146 T0_64 = _do_efdcfsi(T0_64);
2149 void do_efdcfui (void)
2151 T0_64 = _do_efdcfui(T0_64);
2154 void do_efdctsi (void)
2156 T0_64 = _do_efdctsi(T0_64);
2159 void do_efdctui (void)
2161 T0_64 = _do_efdctui(T0_64);
2164 void do_efdctsiz (void)
2166 T0_64 = _do_efdctsiz(T0_64);
2169 void do_efdctuiz (void)
2171 T0_64 = _do_efdctuiz(T0_64);
2174 /* Double precision floating-point conversion to/from fractional */
2175 static always_inline uint64_t _do_efdcfsf (int64_t val)
2180 u.d = int32_to_float64(val, &env->spe_status);
2181 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2182 u.d = float64_div(u.d, tmp, &env->spe_status);
2187 static always_inline uint64_t _do_efdcfuf (uint64_t val)
2192 u.d = uint32_to_float64(val, &env->spe_status);
2193 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2194 u.d = float64_div(u.d, tmp, &env->spe_status);
2199 static always_inline int64_t _do_efdctsf (uint64_t val)
2205 /* NaN are not treated the same way IEEE 754 does */
2206 if (unlikely(isnan(u.d)))
2208 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2209 u.d = float64_mul(u.d, tmp, &env->spe_status);
2211 return float64_to_int32(u.d, &env->spe_status);
2214 static always_inline uint64_t _do_efdctuf (uint64_t val)
2220 /* NaN are not treated the same way IEEE 754 does */
2221 if (unlikely(isnan(u.d)))
2223 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2224 u.d = float64_mul(u.d, tmp, &env->spe_status);
2226 return float64_to_uint32(u.d, &env->spe_status);
2229 static always_inline int64_t _do_efdctsfz (uint64_t val)
2235 /* NaN are not treated the same way IEEE 754 does */
2236 if (unlikely(isnan(u.d)))
2238 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2239 u.d = float64_mul(u.d, tmp, &env->spe_status);
2241 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2244 static always_inline uint64_t _do_efdctufz (uint64_t val)
2250 /* NaN are not treated the same way IEEE 754 does */
2251 if (unlikely(isnan(u.d)))
2253 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2254 u.d = float64_mul(u.d, tmp, &env->spe_status);
2256 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2259 void do_efdcfsf (void)
2261 T0_64 = _do_efdcfsf(T0_64);
2264 void do_efdcfuf (void)
2266 T0_64 = _do_efdcfuf(T0_64);
2269 void do_efdctsf (void)
2271 T0_64 = _do_efdctsf(T0_64);
2274 void do_efdctuf (void)
2276 T0_64 = _do_efdctuf(T0_64);
2279 void do_efdctsfz (void)
2281 T0_64 = _do_efdctsfz(T0_64);
2284 void do_efdctufz (void)
2286 T0_64 = _do_efdctufz(T0_64);
2289 /* Floating point conversion between single and double precision */
2290 static always_inline uint32_t _do_efscfd (uint64_t val)
2296 u2.f = float64_to_float32(u1.d, &env->spe_status);
2301 static always_inline uint64_t _do_efdcfs (uint32_t val)
2307 u2.d = float32_to_float64(u1.f, &env->spe_status);
2312 void do_efscfd (void)
2314 T0_64 = _do_efscfd(T0_64);
2317 void do_efdcfs (void)
2319 T0_64 = _do_efdcfs(T0_64);
2322 /* Single precision fixed-point vector arithmetic */
2338 /* Single-precision floating-point comparisons */
2339 static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2341 /* XXX: TODO: test special values (NaN, infinites, ...) */
2342 return _do_efststlt(op1, op2);
2345 static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2347 /* XXX: TODO: test special values (NaN, infinites, ...) */
2348 return _do_efststgt(op1, op2);
2351 static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2353 /* XXX: TODO: test special values (NaN, infinites, ...) */
2354 return _do_efststeq(op1, op2);
2357 void do_efscmplt (void)
2359 T0 = _do_efscmplt(T0_64, T1_64);
2362 void do_efscmpgt (void)
2364 T0 = _do_efscmpgt(T0_64, T1_64);
2367 void do_efscmpeq (void)
2369 T0 = _do_efscmpeq(T0_64, T1_64);
2372 /* Single-precision floating-point vector comparisons */
2374 DO_SPE_CMP(fscmplt);
2376 DO_SPE_CMP(fscmpgt);
2378 DO_SPE_CMP(fscmpeq);
2380 DO_SPE_CMP(fststlt);
2382 DO_SPE_CMP(fststgt);
2384 DO_SPE_CMP(fststeq);
2386 /* Single-precision floating-point vector conversions */
2400 DO_SPE_OP1(fsctsiz);
2402 DO_SPE_OP1(fsctuiz);
2408 /*****************************************************************************/
2409 /* Softmmu support */
2410 #if !defined (CONFIG_USER_ONLY)
2412 #define MMUSUFFIX _mmu
2415 #include "softmmu_template.h"
2418 #include "softmmu_template.h"
2421 #include "softmmu_template.h"
2424 #include "softmmu_template.h"
2426 /* try to fill the TLB and return an exception if error. If retaddr is
2427 NULL, it means that the function was called in C code (i.e. not
2428 from generated code or from helper.c) */
2429 /* XXX: fix it to restore all registers */
2430 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2432 TranslationBlock *tb;
2433 CPUState *saved_env;
2437 /* XXX: hack to restore env in all cases, even if not called from
2440 env = cpu_single_env;
2441 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2442 if (unlikely(ret != 0)) {
2443 if (likely(retaddr)) {
2444 /* now we have a real cpu fault */
2445 pc = (unsigned long)retaddr;
2446 tb = tb_find_pc(pc);
2448 /* the PC is inside the translated code. It means that we have
2449 a virtual CPU fault */
2450 cpu_restore_state(tb, env, pc, NULL);
2453 raise_exception_err(env, env->exception_index, env->error_code);
2458 /* Software driven TLBs management */
2459 /* PowerPC 602/603 software TLB load instructions helpers */
2460 void do_load_6xx_tlb (int is_code)
2462 target_ulong RPN, CMP, EPN;
2465 RPN = env->spr[SPR_RPA];
2467 CMP = env->spr[SPR_ICMP];
2468 EPN = env->spr[SPR_IMISS];
2470 CMP = env->spr[SPR_DCMP];
2471 EPN = env->spr[SPR_DMISS];
2473 way = (env->spr[SPR_SRR1] >> 17) & 1;
2474 #if defined (DEBUG_SOFTWARE_TLB)
2475 if (loglevel != 0) {
2476 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2477 " PTE1 " ADDRX " way %d\n",
2478 __func__, T0, EPN, CMP, RPN, way);
2481 /* Store this TLB */
2482 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2483 way, is_code, CMP, RPN);
2486 void do_load_74xx_tlb (int is_code)
2488 target_ulong RPN, CMP, EPN;
2491 RPN = env->spr[SPR_PTELO];
2492 CMP = env->spr[SPR_PTEHI];
2493 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2494 way = env->spr[SPR_TLBMISS] & 0x3;
2495 #if defined (DEBUG_SOFTWARE_TLB)
2496 if (loglevel != 0) {
2497 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2498 " PTE1 " ADDRX " way %d\n",
2499 __func__, T0, EPN, CMP, RPN, way);
2502 /* Store this TLB */
2503 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2504 way, is_code, CMP, RPN);
2507 static always_inline target_ulong booke_tlb_to_page_size (int size)
2509 return 1024 << (2 * size);
2512 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2516 switch (page_size) {
2550 #if defined (TARGET_PPC64)
2551 case 0x000100000000ULL:
2554 case 0x000400000000ULL:
2557 case 0x001000000000ULL:
2560 case 0x004000000000ULL:
2563 case 0x010000000000ULL:
2575 /* Helpers for 4xx TLB management */
2576 void do_4xx_tlbre_lo (void)
2582 tlb = &env->tlb[T0].tlbe;
2584 if (tlb->prot & PAGE_VALID)
2586 size = booke_page_size_to_tlb(tlb->size);
2587 if (size < 0 || size > 0x7)
2590 env->spr[SPR_40x_PID] = tlb->PID;
2593 void do_4xx_tlbre_hi (void)
2598 tlb = &env->tlb[T0].tlbe;
2600 if (tlb->prot & PAGE_EXEC)
2602 if (tlb->prot & PAGE_WRITE)
2606 void do_4xx_tlbwe_hi (void)
2609 target_ulong page, end;
2611 #if defined (DEBUG_SOFTWARE_TLB)
2612 if (loglevel != 0) {
2613 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2617 tlb = &env->tlb[T0].tlbe;
2618 /* Invalidate previous TLB (if it's valid) */
2619 if (tlb->prot & PAGE_VALID) {
2620 end = tlb->EPN + tlb->size;
2621 #if defined (DEBUG_SOFTWARE_TLB)
2622 if (loglevel != 0) {
2623 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2624 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2627 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2628 tlb_flush_page(env, page);
2630 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2631 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2632 * If this ever occurs, one should use the ppcemb target instead
2633 * of the ppc or ppc64 one
2635 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2636 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2637 "are not supported (%d)\n",
2638 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2640 tlb->EPN = T1 & ~(tlb->size - 1);
2642 tlb->prot |= PAGE_VALID;
2644 tlb->prot &= ~PAGE_VALID;
2646 /* XXX: TO BE FIXED */
2647 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2649 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2650 tlb->attr = T1 & 0xFF;
2651 #if defined (DEBUG_SOFTWARE_TLB)
2652 if (loglevel != 0) {
2653 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2654 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2655 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2656 tlb->prot & PAGE_READ ? 'r' : '-',
2657 tlb->prot & PAGE_WRITE ? 'w' : '-',
2658 tlb->prot & PAGE_EXEC ? 'x' : '-',
2659 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2662 /* Invalidate new TLB (if valid) */
2663 if (tlb->prot & PAGE_VALID) {
2664 end = tlb->EPN + tlb->size;
2665 #if defined (DEBUG_SOFTWARE_TLB)
2666 if (loglevel != 0) {
2667 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2668 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2671 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2672 tlb_flush_page(env, page);
2676 void do_4xx_tlbwe_lo (void)
2680 #if defined (DEBUG_SOFTWARE_TLB)
2681 if (loglevel != 0) {
2682 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2686 tlb = &env->tlb[T0].tlbe;
2687 tlb->RPN = T1 & 0xFFFFFC00;
2688 tlb->prot = PAGE_READ;
2690 tlb->prot |= PAGE_EXEC;
2692 tlb->prot |= PAGE_WRITE;
2693 #if defined (DEBUG_SOFTWARE_TLB)
2694 if (loglevel != 0) {
2695 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2696 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2697 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2698 tlb->prot & PAGE_READ ? 'r' : '-',
2699 tlb->prot & PAGE_WRITE ? 'w' : '-',
2700 tlb->prot & PAGE_EXEC ? 'x' : '-',
2701 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2706 /* PowerPC 440 TLB management */
2707 void do_440_tlbwe (int word)
2710 target_ulong EPN, RPN, size;
2713 #if defined (DEBUG_SOFTWARE_TLB)
2714 if (loglevel != 0) {
2715 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2716 __func__, word, T0, T1);
2721 tlb = &env->tlb[T0].tlbe;
2724 /* Just here to please gcc */
2726 EPN = T1 & 0xFFFFFC00;
2727 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2730 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2731 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2735 tlb->attr |= (T1 >> 8) & 1;
2737 tlb->prot |= PAGE_VALID;
2739 if (tlb->prot & PAGE_VALID) {
2740 tlb->prot &= ~PAGE_VALID;
2744 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2749 RPN = T1 & 0xFFFFFC0F;
2750 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2755 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2756 tlb->prot = tlb->prot & PAGE_VALID;
2758 tlb->prot |= PAGE_READ << 4;
2760 tlb->prot |= PAGE_WRITE << 4;
2762 tlb->prot |= PAGE_EXEC << 4;
2764 tlb->prot |= PAGE_READ;
2766 tlb->prot |= PAGE_WRITE;
2768 tlb->prot |= PAGE_EXEC;
2773 void do_440_tlbre (int word)
2779 tlb = &env->tlb[T0].tlbe;
2782 /* Just here to please gcc */
2785 size = booke_page_size_to_tlb(tlb->size);
2786 if (size < 0 || size > 0xF)
2789 if (tlb->attr & 0x1)
2791 if (tlb->prot & PAGE_VALID)
2793 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2794 env->spr[SPR_440_MMUCR] |= tlb->PID;
2800 T0 = tlb->attr & ~0x1;
2801 if (tlb->prot & (PAGE_READ << 4))
2803 if (tlb->prot & (PAGE_WRITE << 4))
2805 if (tlb->prot & (PAGE_EXEC << 4))
2807 if (tlb->prot & PAGE_READ)
2809 if (tlb->prot & PAGE_WRITE)
2811 if (tlb->prot & PAGE_EXEC)
2816 #endif /* !CONFIG_USER_ONLY */