2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
36 printf("Raise exception %3x code : %d\n", exception, error_code);
38 env->exception_index = exception;
39 env->error_code = error_code;
43 void helper_raise_exception (uint32_t exception)
45 helper_raise_exception_err(exception, 0);
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
52 return (env->crf[0] << 28) |
62 void helper_store_cr (target_ulong val, uint32_t mask)
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
72 /*****************************************************************************/
74 void helper_load_dump_spr (uint32_t sprn)
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
82 void helper_store_dump_spr (uint32_t sprn)
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
90 target_ulong helper_load_tbl (void)
92 return cpu_ppc_load_tbl(env);
95 target_ulong helper_load_tbu (void)
97 return cpu_ppc_load_tbu(env);
100 target_ulong helper_load_atbl (void)
102 return cpu_ppc_load_atbl(env);
105 target_ulong helper_load_atbu (void)
107 return cpu_ppc_load_atbu(env);
110 target_ulong helper_load_601_rtcl (void)
112 return cpu_ppc601_load_rtcl(env);
115 target_ulong helper_load_601_rtcu (void)
117 return cpu_ppc601_load_rtcu(env);
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
124 ppc_store_asr(env, val);
128 void helper_store_sdr1 (target_ulong val)
130 ppc_store_sdr1(env, val);
133 void helper_store_tbl (target_ulong val)
135 cpu_ppc_store_tbl(env, val);
138 void helper_store_tbu (target_ulong val)
140 cpu_ppc_store_tbu(env, val);
143 void helper_store_atbl (target_ulong val)
145 cpu_ppc_store_atbl(env, val);
148 void helper_store_atbu (target_ulong val)
150 cpu_ppc_store_atbu(env, val);
153 void helper_store_601_rtcl (target_ulong val)
155 cpu_ppc601_store_rtcl(env, val);
158 void helper_store_601_rtcu (target_ulong val)
160 cpu_ppc601_store_rtcu(env, val);
163 target_ulong helper_load_decr (void)
165 return cpu_ppc_load_decr(env);
168 void helper_store_decr (target_ulong val)
170 cpu_ppc_store_decr(env, val);
173 void helper_store_hid0_601 (target_ulong val)
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
189 env->spr[SPR_HID0] = (uint32_t)val;
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
201 target_ulong helper_load_40x_pit (void)
203 return load_40x_pit(env);
206 void helper_store_40x_pit (target_ulong val)
208 store_40x_pit(env, val);
211 void helper_store_40x_dbcr0 (target_ulong val)
213 store_40x_dbcr0(env, val);
216 void helper_store_40x_sler (target_ulong val)
218 store_40x_sler(env, val);
221 void helper_store_booke_tcr (target_ulong val)
223 store_booke_tcr(env, val);
226 void helper_store_booke_tsr (target_ulong val)
228 store_booke_tsr(env, val);
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
233 ppc_store_ibatu(env, nr, val);
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
238 ppc_store_ibatl(env, nr, val);
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
243 ppc_store_dbatu(env, nr, val);
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
248 ppc_store_dbatl(env, nr, val);
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
253 ppc_store_ibatl_601(env, nr, val);
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
258 ppc_store_ibatu_601(env, nr, val);
262 /*****************************************************************************/
263 /* Memory load and stores */
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
267 #if defined(TARGET_PPC64)
269 return (uint32_t)(addr + arg);
275 void helper_lmw (target_ulong addr, uint32_t reg)
277 for (; reg < 32; reg++) {
279 env->gpr[reg] = bswap32(ldl(addr));
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
286 void helper_stmw (target_ulong addr, uint32_t reg)
288 for (; reg < 32; reg++) {
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
305 if (unlikely(nb > 0)) {
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
325 POWERPC_EXCP_INVAL_LSWX);
327 helper_lsw(addr, xer_bc, reg);
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
349 addr &= ~(dcache_line_size - 1);
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
358 void helper_dcbz(target_ulong addr)
360 do_dcbz(addr, env->dcache_line_size);
363 void helper_dcbz_970(target_ulong addr)
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
368 do_dcbz(addr, env->dcache_line_size);
371 void helper_icbi(target_ulong addr)
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
390 for (i = 0; i < xer_bc; i++) {
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
397 if (unlikely(c == xer_cmp))
399 if (likely(d != 0)) {
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
419 muls64(&tl, &th, arg1, arg2);
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
428 mulu64(&tl, &th, arg1, arg2);
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
448 target_ulong helper_cntlzw (target_ulong t)
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
472 env->xer |= (1 << XER_CA);
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
479 ret = (int32_t)value >> 31;
481 env->xer |= (1 << XER_CA);
483 env->xer &= ~(1 << XER_CA);
486 return (target_long)ret;
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
501 env->xer |= (1 << XER_CA);
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
508 ret = (int64_t)value >> 63;
510 env->xer |= (1 << XER_CA);
512 env->xer &= ~(1 << XER_CA);
519 target_ulong helper_popcntb (target_ulong val)
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
544 d.d = float32_to_float64(f.f, &env->fp_status);
548 uint32_t helper_float64_to_float32(uint64_t arg)
553 f.f = float64_to_float32(d.d, &env->fp_status);
557 static always_inline int isden (float64 d)
563 return ((u.ll >> 52) & 0x7FF) == 0;
566 #ifdef CONFIG_SOFTFLOAT
567 static always_inline int isnormal (float64 d)
573 uint32_t exp = (u.ll >> 52) & 0x7FF;
574 return ((0 < exp) && (exp < 0x7FF));
578 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
584 isneg = float64_is_neg(farg.d);
585 if (unlikely(float64_is_nan(farg.d))) {
586 if (float64_is_signaling_nan(farg.d)) {
587 /* Signaling NaN: flags are undefined */
593 } else if (unlikely(float64_is_infinity(farg.d))) {
600 if (float64_is_zero(farg.d)) {
608 /* Denormalized numbers */
611 /* Normalized numbers */
622 /* We update FPSCR_FPRF */
623 env->fpscr &= ~(0x1F << FPSCR_FPRF);
624 env->fpscr |= ret << FPSCR_FPRF;
626 /* We just need fpcc to update Rc1 */
630 /* Floating-point invalid operations exception */
631 static always_inline uint64_t fload_invalid_op_excp (int op)
638 case POWERPC_EXCP_FP_VXSNAN:
639 env->fpscr |= 1 << FPSCR_VXSNAN;
641 case POWERPC_EXCP_FP_VXSOFT:
642 env->fpscr |= 1 << FPSCR_VXSOFT;
644 case POWERPC_EXCP_FP_VXISI:
645 /* Magnitude subtraction of infinities */
646 env->fpscr |= 1 << FPSCR_VXISI;
648 case POWERPC_EXCP_FP_VXIDI:
649 /* Division of infinity by infinity */
650 env->fpscr |= 1 << FPSCR_VXIDI;
652 case POWERPC_EXCP_FP_VXZDZ:
653 /* Division of zero by zero */
654 env->fpscr |= 1 << FPSCR_VXZDZ;
656 case POWERPC_EXCP_FP_VXIMZ:
657 /* Multiplication of zero by infinity */
658 env->fpscr |= 1 << FPSCR_VXIMZ;
660 case POWERPC_EXCP_FP_VXVC:
661 /* Ordered comparison of NaN */
662 env->fpscr |= 1 << FPSCR_VXVC;
663 env->fpscr &= ~(0xF << FPSCR_FPCC);
664 env->fpscr |= 0x11 << FPSCR_FPCC;
665 /* We must update the target FPR before raising the exception */
667 env->exception_index = POWERPC_EXCP_PROGRAM;
668 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
669 /* Update the floating-point enabled exception summary */
670 env->fpscr |= 1 << FPSCR_FEX;
671 /* Exception is differed */
675 case POWERPC_EXCP_FP_VXSQRT:
676 /* Square root of a negative number */
677 env->fpscr |= 1 << FPSCR_VXSQRT;
679 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
681 /* Set the result to quiet NaN */
682 ret = 0xFFF8000000000000ULL;
683 env->fpscr &= ~(0xF << FPSCR_FPCC);
684 env->fpscr |= 0x11 << FPSCR_FPCC;
687 case POWERPC_EXCP_FP_VXCVI:
688 /* Invalid conversion */
689 env->fpscr |= 1 << FPSCR_VXCVI;
690 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
692 /* Set the result to quiet NaN */
693 ret = 0xFFF8000000000000ULL;
694 env->fpscr &= ~(0xF << FPSCR_FPCC);
695 env->fpscr |= 0x11 << FPSCR_FPCC;
699 /* Update the floating-point invalid operation summary */
700 env->fpscr |= 1 << FPSCR_VX;
701 /* Update the floating-point exception summary */
702 env->fpscr |= 1 << FPSCR_FX;
704 /* Update the floating-point enabled exception summary */
705 env->fpscr |= 1 << FPSCR_FEX;
706 if (msr_fe0 != 0 || msr_fe1 != 0)
707 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
712 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
714 env->fpscr |= 1 << FPSCR_ZX;
715 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
716 /* Update the floating-point exception summary */
717 env->fpscr |= 1 << FPSCR_FX;
719 /* Update the floating-point enabled exception summary */
720 env->fpscr |= 1 << FPSCR_FEX;
721 if (msr_fe0 != 0 || msr_fe1 != 0) {
722 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
723 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
726 /* Set the result to infinity */
727 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
728 arg1 |= 0x7FFULL << 52;
733 static always_inline void float_overflow_excp (void)
735 env->fpscr |= 1 << FPSCR_OX;
736 /* Update the floating-point exception summary */
737 env->fpscr |= 1 << FPSCR_FX;
739 /* XXX: should adjust the result */
740 /* Update the floating-point enabled exception summary */
741 env->fpscr |= 1 << FPSCR_FEX;
742 /* We must update the target FPR before raising the exception */
743 env->exception_index = POWERPC_EXCP_PROGRAM;
744 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
746 env->fpscr |= 1 << FPSCR_XX;
747 env->fpscr |= 1 << FPSCR_FI;
751 static always_inline void float_underflow_excp (void)
753 env->fpscr |= 1 << FPSCR_UX;
754 /* Update the floating-point exception summary */
755 env->fpscr |= 1 << FPSCR_FX;
757 /* XXX: should adjust the result */
758 /* Update the floating-point enabled exception summary */
759 env->fpscr |= 1 << FPSCR_FEX;
760 /* We must update the target FPR before raising the exception */
761 env->exception_index = POWERPC_EXCP_PROGRAM;
762 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
766 static always_inline void float_inexact_excp (void)
768 env->fpscr |= 1 << FPSCR_XX;
769 /* Update the floating-point exception summary */
770 env->fpscr |= 1 << FPSCR_FX;
772 /* Update the floating-point enabled exception summary */
773 env->fpscr |= 1 << FPSCR_FEX;
774 /* We must update the target FPR before raising the exception */
775 env->exception_index = POWERPC_EXCP_PROGRAM;
776 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
780 static always_inline void fpscr_set_rounding_mode (void)
784 /* Set rounding mode */
787 /* Best approximation (round to nearest) */
788 rnd_type = float_round_nearest_even;
791 /* Smaller magnitude (round toward zero) */
792 rnd_type = float_round_to_zero;
795 /* Round toward +infinite */
796 rnd_type = float_round_up;
800 /* Round toward -infinite */
801 rnd_type = float_round_down;
804 set_float_rounding_mode(rnd_type, &env->fp_status);
807 void helper_fpscr_clrbit (uint32_t bit)
811 prev = (env->fpscr >> bit) & 1;
812 env->fpscr &= ~(1 << bit);
817 fpscr_set_rounding_mode();
825 void helper_fpscr_setbit (uint32_t bit)
829 prev = (env->fpscr >> bit) & 1;
830 env->fpscr |= 1 << bit;
834 env->fpscr |= 1 << FPSCR_FX;
838 env->fpscr |= 1 << FPSCR_FX;
843 env->fpscr |= 1 << FPSCR_FX;
848 env->fpscr |= 1 << FPSCR_FX;
853 env->fpscr |= 1 << FPSCR_FX;
866 env->fpscr |= 1 << FPSCR_VX;
867 env->fpscr |= 1 << FPSCR_FX;
874 env->error_code = POWERPC_EXCP_FP;
876 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
878 env->error_code |= POWERPC_EXCP_FP_VXISI;
880 env->error_code |= POWERPC_EXCP_FP_VXIDI;
882 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
884 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
886 env->error_code |= POWERPC_EXCP_FP_VXVC;
888 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
890 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
892 env->error_code |= POWERPC_EXCP_FP_VXCVI;
899 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
906 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
913 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
920 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
926 fpscr_set_rounding_mode();
931 /* Update the floating-point enabled exception summary */
932 env->fpscr |= 1 << FPSCR_FEX;
933 /* We have to update Rc1 before raising the exception */
934 env->exception_index = POWERPC_EXCP_PROGRAM;
940 void helper_store_fpscr (uint64_t arg, uint32_t mask)
943 * We use only the 32 LSB of the incoming fpr
951 new |= prev & 0x60000000;
952 for (i = 0; i < 8; i++) {
953 if (mask & (1 << i)) {
954 env->fpscr &= ~(0xF << (4 * i));
955 env->fpscr |= new & (0xF << (4 * i));
958 /* Update VX and FEX */
960 env->fpscr |= 1 << FPSCR_VX;
962 env->fpscr &= ~(1 << FPSCR_VX);
963 if ((fpscr_ex & fpscr_eex) != 0) {
964 env->fpscr |= 1 << FPSCR_FEX;
965 env->exception_index = POWERPC_EXCP_PROGRAM;
966 /* XXX: we should compute it properly */
967 env->error_code = POWERPC_EXCP_FP;
970 env->fpscr &= ~(1 << FPSCR_FEX);
971 fpscr_set_rounding_mode();
974 void helper_float_check_status (void)
976 #ifdef CONFIG_SOFTFLOAT
977 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
978 (env->error_code & POWERPC_EXCP_FP)) {
979 /* Differred floating-point exception after target FPR update */
980 if (msr_fe0 != 0 || msr_fe1 != 0)
981 helper_raise_exception_err(env->exception_index, env->error_code);
983 int status = get_float_exception_flags(&env->fp_status);
984 if (status & float_flag_overflow) {
985 float_overflow_excp();
986 } else if (status & float_flag_underflow) {
987 float_underflow_excp();
988 } else if (status & float_flag_inexact) {
989 float_inexact_excp();
993 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
994 (env->error_code & POWERPC_EXCP_FP)) {
995 /* Differred floating-point exception after target FPR update */
996 if (msr_fe0 != 0 || msr_fe1 != 0)
997 helper_raise_exception_err(env->exception_index, env->error_code);
1002 #ifdef CONFIG_SOFTFLOAT
1003 void helper_reset_fpstatus (void)
1005 set_float_exception_flags(0, &env->fp_status);
1010 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1012 CPU_DoubleU farg1, farg2;
1016 #if USE_PRECISE_EMULATION
1017 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1018 float64_is_signaling_nan(farg2.d))) {
1020 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1021 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1022 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
1023 /* Magnitude subtraction of infinities */
1024 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1026 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1029 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1035 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1037 CPU_DoubleU farg1, farg2;
1041 #if USE_PRECISE_EMULATION
1043 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1044 float64_is_signaling_nan(farg2.d))) {
1045 /* sNaN subtraction */
1046 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1047 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1048 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
1049 /* Magnitude subtraction of infinities */
1050 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1052 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1056 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1062 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1064 CPU_DoubleU farg1, farg2;
1068 #if USE_PRECISE_EMULATION
1069 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1070 float64_is_signaling_nan(farg2.d))) {
1071 /* sNaN multiplication */
1072 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1073 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1074 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1075 /* Multiplication of zero by infinity */
1076 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1078 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1081 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1087 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1089 CPU_DoubleU farg1, farg2;
1093 #if USE_PRECISE_EMULATION
1094 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1095 float64_is_signaling_nan(farg2.d))) {
1097 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1098 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
1099 /* Division of infinity by infinity */
1100 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1101 } else if (unlikely(!float64_is_nan(farg1.d) && float64_is_zero(farg2.d))) {
1102 if (float64_is_zero(farg1.d)) {
1103 /* Division of zero by zero */
1104 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1106 /* Division by zero */
1107 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1110 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1113 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1119 uint64_t helper_fabs (uint64_t arg)
1124 farg.d = float64_abs(farg.d);
1129 uint64_t helper_fnabs (uint64_t arg)
1134 farg.d = float64_abs(farg.d);
1135 farg.d = float64_chs(farg.d);
1140 uint64_t helper_fneg (uint64_t arg)
1145 farg.d = float64_chs(farg.d);
1149 /* fctiw - fctiw. */
1150 uint64_t helper_fctiw (uint64_t arg)
1155 if (unlikely(float64_is_signaling_nan(farg.d))) {
1156 /* sNaN conversion */
1157 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1158 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1159 /* qNan / infinity conversion */
1160 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1162 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1163 #if USE_PRECISE_EMULATION
1164 /* XXX: higher bits are not supposed to be significant.
1165 * to make tests easier, return the same as a real PowerPC 750
1167 farg.ll |= 0xFFF80000ULL << 32;
1173 /* fctiwz - fctiwz. */
1174 uint64_t helper_fctiwz (uint64_t arg)
1179 if (unlikely(float64_is_signaling_nan(farg.d))) {
1180 /* sNaN conversion */
1181 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1182 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1183 /* qNan / infinity conversion */
1184 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1186 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1187 #if USE_PRECISE_EMULATION
1188 /* XXX: higher bits are not supposed to be significant.
1189 * to make tests easier, return the same as a real PowerPC 750
1191 farg.ll |= 0xFFF80000ULL << 32;
1197 #if defined(TARGET_PPC64)
1198 /* fcfid - fcfid. */
1199 uint64_t helper_fcfid (uint64_t arg)
1202 farg.d = int64_to_float64(arg, &env->fp_status);
1206 /* fctid - fctid. */
1207 uint64_t helper_fctid (uint64_t arg)
1212 if (unlikely(float64_is_signaling_nan(farg.d))) {
1213 /* sNaN conversion */
1214 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1215 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1216 /* qNan / infinity conversion */
1217 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1219 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1224 /* fctidz - fctidz. */
1225 uint64_t helper_fctidz (uint64_t arg)
1230 if (unlikely(float64_is_signaling_nan(farg.d))) {
1231 /* sNaN conversion */
1232 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1233 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1234 /* qNan / infinity conversion */
1235 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1237 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1244 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1249 if (unlikely(float64_is_signaling_nan(farg.d))) {
1251 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1252 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1253 /* qNan / infinity round */
1254 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1256 set_float_rounding_mode(rounding_mode, &env->fp_status);
1257 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1258 /* Restore rounding mode from FPSCR */
1259 fpscr_set_rounding_mode();
1264 uint64_t helper_frin (uint64_t arg)
1266 return do_fri(arg, float_round_nearest_even);
1269 uint64_t helper_friz (uint64_t arg)
1271 return do_fri(arg, float_round_to_zero);
1274 uint64_t helper_frip (uint64_t arg)
1276 return do_fri(arg, float_round_up);
1279 uint64_t helper_frim (uint64_t arg)
1281 return do_fri(arg, float_round_down);
1284 /* fmadd - fmadd. */
1285 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1287 CPU_DoubleU farg1, farg2, farg3;
1292 #if USE_PRECISE_EMULATION
1293 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1294 float64_is_signaling_nan(farg2.d) ||
1295 float64_is_signaling_nan(farg3.d))) {
1296 /* sNaN operation */
1297 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1300 /* This is the way the PowerPC specification defines it */
1301 float128 ft0_128, ft1_128;
1303 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1304 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1305 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1306 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1307 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1308 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1310 /* This is OK on x86 hosts */
1311 farg1.d = (farg1.d * farg2.d) + farg3.d;
1315 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1316 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1321 /* fmsub - fmsub. */
1322 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1324 CPU_DoubleU farg1, farg2, farg3;
1329 #if USE_PRECISE_EMULATION
1330 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1331 float64_is_signaling_nan(farg2.d) ||
1332 float64_is_signaling_nan(farg3.d))) {
1333 /* sNaN operation */
1334 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1337 /* This is the way the PowerPC specification defines it */
1338 float128 ft0_128, ft1_128;
1340 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1341 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1342 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1343 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1344 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1345 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1347 /* This is OK on x86 hosts */
1348 farg1.d = (farg1.d * farg2.d) - farg3.d;
1352 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1353 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1358 /* fnmadd - fnmadd. */
1359 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1361 CPU_DoubleU farg1, farg2, farg3;
1367 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1368 float64_is_signaling_nan(farg2.d) ||
1369 float64_is_signaling_nan(farg3.d))) {
1370 /* sNaN operation */
1371 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1373 #if USE_PRECISE_EMULATION
1375 /* This is the way the PowerPC specification defines it */
1376 float128 ft0_128, ft1_128;
1378 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1379 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1380 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1381 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1382 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1383 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1385 /* This is OK on x86 hosts */
1386 farg1.d = (farg1.d * farg2.d) + farg3.d;
1389 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1390 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1392 if (likely(!float64_is_nan(farg1.d)))
1393 farg1.d = float64_chs(farg1.d);
1398 /* fnmsub - fnmsub. */
1399 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1401 CPU_DoubleU farg1, farg2, farg3;
1407 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1408 float64_is_signaling_nan(farg2.d) ||
1409 float64_is_signaling_nan(farg3.d))) {
1410 /* sNaN operation */
1411 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1413 #if USE_PRECISE_EMULATION
1415 /* This is the way the PowerPC specification defines it */
1416 float128 ft0_128, ft1_128;
1418 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1419 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1420 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1421 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1422 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1423 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1425 /* This is OK on x86 hosts */
1426 farg1.d = (farg1.d * farg2.d) - farg3.d;
1429 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1430 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1432 if (likely(!float64_is_nan(farg1.d)))
1433 farg1.d = float64_chs(farg1.d);
1439 uint64_t helper_frsp (uint64_t arg)
1445 #if USE_PRECISE_EMULATION
1446 if (unlikely(float64_is_signaling_nan(farg.d))) {
1447 /* sNaN square root */
1448 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1450 f32 = float64_to_float32(farg.d, &env->fp_status);
1451 farg.d = float32_to_float64(f32, &env->fp_status);
1454 f32 = float64_to_float32(farg.d, &env->fp_status);
1455 farg.d = float32_to_float64(f32, &env->fp_status);
1460 /* fsqrt - fsqrt. */
1461 uint64_t helper_fsqrt (uint64_t arg)
1466 if (unlikely(float64_is_signaling_nan(farg.d))) {
1467 /* sNaN square root */
1468 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1469 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1470 /* Square root of a negative nonzero number */
1471 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1473 farg.d = float64_sqrt(farg.d, &env->fp_status);
1479 uint64_t helper_fre (uint64_t arg)
1481 CPU_DoubleU fone, farg;
1482 fone.ll = 0x3FF0000000000000ULL;
1485 if (unlikely(float64_is_signaling_nan(farg.d))) {
1486 /* sNaN reciprocal */
1487 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1488 } else if (unlikely(float64_is_zero(farg.d))) {
1489 /* Zero reciprocal */
1490 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1491 } else if (likely(isnormal(farg.d))) {
1492 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1494 if (farg.ll == 0x8000000000000000ULL) {
1495 farg.ll = 0xFFF0000000000000ULL;
1496 } else if (farg.ll == 0x0000000000000000ULL) {
1497 farg.ll = 0x7FF0000000000000ULL;
1498 } else if (float64_is_nan(farg.d)) {
1499 farg.ll = 0x7FF8000000000000ULL;
1500 } else if (float64_is_neg(farg.d)) {
1501 farg.ll = 0x8000000000000000ULL;
1503 farg.ll = 0x0000000000000000ULL;
1510 uint64_t helper_fres (uint64_t arg)
1512 CPU_DoubleU fone, farg;
1513 fone.ll = 0x3FF0000000000000ULL;
1516 if (unlikely(float64_is_signaling_nan(farg.d))) {
1517 /* sNaN reciprocal */
1518 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1519 } else if (unlikely(float64_is_zero(farg.d))) {
1520 /* Zero reciprocal */
1521 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1522 } else if (likely(isnormal(farg.d))) {
1523 #if USE_PRECISE_EMULATION
1524 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1525 farg.d = float64_to_float32(farg.d, &env->fp_status);
1527 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1530 if (farg.ll == 0x8000000000000000ULL) {
1531 farg.ll = 0xFFF0000000000000ULL;
1532 } else if (farg.ll == 0x0000000000000000ULL) {
1533 farg.ll = 0x7FF0000000000000ULL;
1534 } else if (float64_is_nan(farg.d)) {
1535 farg.ll = 0x7FF8000000000000ULL;
1536 } else if (float64_is_neg(farg.d)) {
1537 farg.ll = 0x8000000000000000ULL;
1539 farg.ll = 0x0000000000000000ULL;
1545 /* frsqrte - frsqrte. */
1546 uint64_t helper_frsqrte (uint64_t arg)
1548 CPU_DoubleU fone, farg;
1549 fone.ll = 0x3FF0000000000000ULL;
1552 if (unlikely(float64_is_signaling_nan(farg.d))) {
1553 /* sNaN reciprocal square root */
1554 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1555 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1556 /* Reciprocal square root of a negative nonzero number */
1557 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1558 } else if (likely(isnormal(farg.d))) {
1559 farg.d = float64_sqrt(farg.d, &env->fp_status);
1560 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1562 if (farg.ll == 0x8000000000000000ULL) {
1563 farg.ll = 0xFFF0000000000000ULL;
1564 } else if (farg.ll == 0x0000000000000000ULL) {
1565 farg.ll = 0x7FF0000000000000ULL;
1566 } else if (float64_is_nan(farg.d)) {
1567 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1568 } else if (float64_is_neg(farg.d)) {
1569 farg.ll = 0x7FF8000000000000ULL;
1571 farg.ll = 0x0000000000000000ULL;
1578 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1584 if (!float64_is_neg(farg1.d) || float64_is_zero(farg1.d))
1590 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1592 CPU_DoubleU farg1, farg2;
1597 if (unlikely(float64_is_nan(farg1.d) ||
1598 float64_is_nan(farg2.d))) {
1600 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1602 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1608 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1609 env->fpscr |= ret << FPSCR_FPRF;
1610 env->crf[crfD] = ret;
1611 if (unlikely(ret == 0x01UL
1612 && (float64_is_signaling_nan(farg1.d) ||
1613 float64_is_signaling_nan(farg2.d)))) {
1614 /* sNaN comparison */
1615 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1619 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1621 CPU_DoubleU farg1, farg2;
1626 if (unlikely(float64_is_nan(farg1.d) ||
1627 float64_is_nan(farg2.d))) {
1629 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1631 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1637 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1638 env->fpscr |= ret << FPSCR_FPRF;
1639 env->crf[crfD] = ret;
1640 if (unlikely (ret == 0x01UL)) {
1641 if (float64_is_signaling_nan(farg1.d) ||
1642 float64_is_signaling_nan(farg2.d)) {
1643 /* sNaN comparison */
1644 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1645 POWERPC_EXCP_FP_VXVC);
1647 /* qNaN comparison */
1648 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1653 #if !defined (CONFIG_USER_ONLY)
1654 void helper_store_msr (target_ulong val)
1656 val = hreg_store_msr(env, val, 0);
1658 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1659 helper_raise_exception(val);
1663 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1664 target_ulong msrm, int keep_msrh)
1666 #if defined(TARGET_PPC64)
1667 if (msr & (1ULL << MSR_SF)) {
1668 nip = (uint64_t)nip;
1669 msr &= (uint64_t)msrm;
1671 nip = (uint32_t)nip;
1672 msr = (uint32_t)(msr & msrm);
1674 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1677 nip = (uint32_t)nip;
1678 msr &= (uint32_t)msrm;
1680 /* XXX: beware: this is false if VLE is supported */
1681 env->nip = nip & ~((target_ulong)0x00000003);
1682 hreg_store_msr(env, msr, 1);
1683 #if defined (DEBUG_OP)
1684 cpu_dump_rfi(env->nip, env->msr);
1686 /* No need to raise an exception here,
1687 * as rfi is always the last insn of a TB
1689 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1692 void helper_rfi (void)
1694 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1695 ~((target_ulong)0xFFFF0000), 1);
1698 #if defined(TARGET_PPC64)
1699 void helper_rfid (void)
1701 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1702 ~((target_ulong)0xFFFF0000), 0);
1705 void helper_hrfid (void)
1707 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1708 ~((target_ulong)0xFFFF0000), 0);
1713 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1715 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1716 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1717 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1718 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1719 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1720 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1724 #if defined(TARGET_PPC64)
1725 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1727 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1728 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1729 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1730 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1731 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1732 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1736 /*****************************************************************************/
1737 /* PowerPC 601 specific instructions (POWER bridge) */
1739 target_ulong helper_clcs (uint32_t arg)
1743 /* Instruction cache line size */
1744 return env->icache_line_size;
1747 /* Data cache line size */
1748 return env->dcache_line_size;
1751 /* Minimum cache line size */
1752 return (env->icache_line_size < env->dcache_line_size) ?
1753 env->icache_line_size : env->dcache_line_size;
1756 /* Maximum cache line size */
1757 return (env->icache_line_size > env->dcache_line_size) ?
1758 env->icache_line_size : env->dcache_line_size;
1767 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1769 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1771 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1772 (int32_t)arg2 == 0) {
1773 env->spr[SPR_MQ] = 0;
1776 env->spr[SPR_MQ] = tmp % arg2;
1777 return tmp / (int32_t)arg2;
1781 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1783 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1785 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1786 (int32_t)arg2 == 0) {
1787 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1788 env->spr[SPR_MQ] = 0;
1791 env->spr[SPR_MQ] = tmp % arg2;
1792 tmp /= (int32_t)arg2;
1793 if ((int32_t)tmp != tmp) {
1794 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1796 env->xer &= ~(1 << XER_OV);
1802 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1804 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1805 (int32_t)arg2 == 0) {
1806 env->spr[SPR_MQ] = 0;
1809 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1810 return (int32_t)arg1 / (int32_t)arg2;
1814 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1816 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1817 (int32_t)arg2 == 0) {
1818 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1819 env->spr[SPR_MQ] = 0;
1822 env->xer &= ~(1 << XER_OV);
1823 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1824 return (int32_t)arg1 / (int32_t)arg2;
1828 #if !defined (CONFIG_USER_ONLY)
1829 target_ulong helper_rac (target_ulong addr)
1833 target_ulong ret = 0;
1835 /* We don't have to generate many instances of this instruction,
1836 * as rac is supervisor only.
1838 /* XXX: FIX THIS: Pretend we have no BAT */
1839 nb_BATs = env->nb_BATs;
1841 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1843 env->nb_BATs = nb_BATs;
1847 void helper_rfsvc (void)
1849 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1853 /*****************************************************************************/
1854 /* 602 specific instructions */
1855 /* mfrom is the most crazy instruction ever seen, imho ! */
1856 /* Real implementation uses a ROM table. Do the same */
1857 /* Extremly decomposed:
1859 * return 256 * log10(10 + 1.0) + 0.5
1861 #if !defined (CONFIG_USER_ONLY)
1862 target_ulong helper_602_mfrom (target_ulong arg)
1864 if (likely(arg < 602)) {
1865 #include "mfrom_table.c"
1866 return mfrom_ROM_table[arg];
1873 /*****************************************************************************/
1874 /* Embedded PowerPC specific helpers */
1876 /* XXX: to be improved to check access rights when in user-mode */
1877 target_ulong helper_load_dcr (target_ulong dcrn)
1879 target_ulong val = 0;
1881 if (unlikely(env->dcr_env == NULL)) {
1882 if (loglevel != 0) {
1883 fprintf(logfile, "No DCR environment\n");
1885 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1886 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1887 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1888 if (loglevel != 0) {
1889 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1891 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1892 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1897 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1899 if (unlikely(env->dcr_env == NULL)) {
1900 if (loglevel != 0) {
1901 fprintf(logfile, "No DCR environment\n");
1903 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1904 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1905 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1906 if (loglevel != 0) {
1907 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1909 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1910 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1914 #if !defined(CONFIG_USER_ONLY)
1915 void helper_40x_rfci (void)
1917 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1918 ~((target_ulong)0xFFFF0000), 0);
1921 void helper_rfci (void)
1923 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1924 ~((target_ulong)0x3FFF0000), 0);
1927 void helper_rfdi (void)
1929 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1930 ~((target_ulong)0x3FFF0000), 0);
1933 void helper_rfmci (void)
1935 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1936 ~((target_ulong)0x3FFF0000), 0);
1941 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1947 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1948 if ((high & mask) == 0) {
1956 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1957 if ((low & mask) == 0) {
1969 env->xer = (env->xer & ~0x7F) | i;
1971 env->crf[0] |= xer_so;
1976 /*****************************************************************************/
1977 /* SPE extension helpers */
1978 /* Use a table to make this quicker */
1979 static uint8_t hbrev[16] = {
1980 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1981 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1984 static always_inline uint8_t byte_reverse (uint8_t val)
1986 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1989 static always_inline uint32_t word_reverse (uint32_t val)
1991 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1992 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1995 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1996 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
1998 uint32_t a, b, d, mask;
2000 mask = UINT32_MAX >> (32 - MASKBITS);
2003 d = word_reverse(1 + word_reverse(a | ~b));
2004 return (arg1 & ~mask) | (d & b);
2007 uint32_t helper_cntlsw32 (uint32_t val)
2009 if (val & 0x80000000)
2015 uint32_t helper_cntlzw32 (uint32_t val)
2020 /* Single-precision floating-point conversions */
2021 static always_inline uint32_t efscfsi (uint32_t val)
2025 u.f = int32_to_float32(val, &env->spe_status);
2030 static always_inline uint32_t efscfui (uint32_t val)
2034 u.f = uint32_to_float32(val, &env->spe_status);
2039 static always_inline int32_t efsctsi (uint32_t val)
2044 /* NaN are not treated the same way IEEE 754 does */
2045 if (unlikely(float32_is_nan(u.f)))
2048 return float32_to_int32(u.f, &env->spe_status);
2051 static always_inline uint32_t efsctui (uint32_t val)
2056 /* NaN are not treated the same way IEEE 754 does */
2057 if (unlikely(float32_is_nan(u.f)))
2060 return float32_to_uint32(u.f, &env->spe_status);
2063 static always_inline uint32_t efsctsiz (uint32_t val)
2068 /* NaN are not treated the same way IEEE 754 does */
2069 if (unlikely(float32_is_nan(u.f)))
2072 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2075 static always_inline uint32_t efsctuiz (uint32_t val)
2080 /* NaN are not treated the same way IEEE 754 does */
2081 if (unlikely(float32_is_nan(u.f)))
2084 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2087 static always_inline uint32_t efscfsf (uint32_t val)
2092 u.f = int32_to_float32(val, &env->spe_status);
2093 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2094 u.f = float32_div(u.f, tmp, &env->spe_status);
2099 static always_inline uint32_t efscfuf (uint32_t val)
2104 u.f = uint32_to_float32(val, &env->spe_status);
2105 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2106 u.f = float32_div(u.f, tmp, &env->spe_status);
2111 static always_inline uint32_t efsctsf (uint32_t val)
2117 /* NaN are not treated the same way IEEE 754 does */
2118 if (unlikely(float32_is_nan(u.f)))
2120 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2121 u.f = float32_mul(u.f, tmp, &env->spe_status);
2123 return float32_to_int32(u.f, &env->spe_status);
2126 static always_inline uint32_t efsctuf (uint32_t val)
2132 /* NaN are not treated the same way IEEE 754 does */
2133 if (unlikely(float32_is_nan(u.f)))
2135 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2136 u.f = float32_mul(u.f, tmp, &env->spe_status);
2138 return float32_to_uint32(u.f, &env->spe_status);
2141 #define HELPER_SPE_SINGLE_CONV(name) \
2142 uint32_t helper_e##name (uint32_t val) \
2144 return e##name(val); \
2147 HELPER_SPE_SINGLE_CONV(fscfsi);
2149 HELPER_SPE_SINGLE_CONV(fscfui);
2151 HELPER_SPE_SINGLE_CONV(fscfuf);
2153 HELPER_SPE_SINGLE_CONV(fscfsf);
2155 HELPER_SPE_SINGLE_CONV(fsctsi);
2157 HELPER_SPE_SINGLE_CONV(fsctui);
2159 HELPER_SPE_SINGLE_CONV(fsctsiz);
2161 HELPER_SPE_SINGLE_CONV(fsctuiz);
2163 HELPER_SPE_SINGLE_CONV(fsctsf);
2165 HELPER_SPE_SINGLE_CONV(fsctuf);
2167 #define HELPER_SPE_VECTOR_CONV(name) \
2168 uint64_t helper_ev##name (uint64_t val) \
2170 return ((uint64_t)e##name(val >> 32) << 32) | \
2171 (uint64_t)e##name(val); \
2174 HELPER_SPE_VECTOR_CONV(fscfsi);
2176 HELPER_SPE_VECTOR_CONV(fscfui);
2178 HELPER_SPE_VECTOR_CONV(fscfuf);
2180 HELPER_SPE_VECTOR_CONV(fscfsf);
2182 HELPER_SPE_VECTOR_CONV(fsctsi);
2184 HELPER_SPE_VECTOR_CONV(fsctui);
2186 HELPER_SPE_VECTOR_CONV(fsctsiz);
2188 HELPER_SPE_VECTOR_CONV(fsctuiz);
2190 HELPER_SPE_VECTOR_CONV(fsctsf);
2192 HELPER_SPE_VECTOR_CONV(fsctuf);
2194 /* Single-precision floating-point arithmetic */
2195 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2200 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2204 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2209 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2213 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2218 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2222 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2227 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2231 #define HELPER_SPE_SINGLE_ARITH(name) \
2232 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2234 return e##name(op1, op2); \
2237 HELPER_SPE_SINGLE_ARITH(fsadd);
2239 HELPER_SPE_SINGLE_ARITH(fssub);
2241 HELPER_SPE_SINGLE_ARITH(fsmul);
2243 HELPER_SPE_SINGLE_ARITH(fsdiv);
2245 #define HELPER_SPE_VECTOR_ARITH(name) \
2246 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2248 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2249 (uint64_t)e##name(op1, op2); \
2252 HELPER_SPE_VECTOR_ARITH(fsadd);
2254 HELPER_SPE_VECTOR_ARITH(fssub);
2256 HELPER_SPE_VECTOR_ARITH(fsmul);
2258 HELPER_SPE_VECTOR_ARITH(fsdiv);
2260 /* Single-precision floating-point comparisons */
2261 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2266 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2269 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2274 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2277 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2282 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2285 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2287 /* XXX: TODO: test special values (NaN, infinites, ...) */
2288 return efststlt(op1, op2);
2291 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2293 /* XXX: TODO: test special values (NaN, infinites, ...) */
2294 return efststgt(op1, op2);
2297 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2299 /* XXX: TODO: test special values (NaN, infinites, ...) */
2300 return efststeq(op1, op2);
2303 #define HELPER_SINGLE_SPE_CMP(name) \
2304 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2306 return e##name(op1, op2) << 2; \
2309 HELPER_SINGLE_SPE_CMP(fststlt);
2311 HELPER_SINGLE_SPE_CMP(fststgt);
2313 HELPER_SINGLE_SPE_CMP(fststeq);
2315 HELPER_SINGLE_SPE_CMP(fscmplt);
2317 HELPER_SINGLE_SPE_CMP(fscmpgt);
2319 HELPER_SINGLE_SPE_CMP(fscmpeq);
2321 static always_inline uint32_t evcmp_merge (int t0, int t1)
2323 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2326 #define HELPER_VECTOR_SPE_CMP(name) \
2327 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2329 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2332 HELPER_VECTOR_SPE_CMP(fststlt);
2334 HELPER_VECTOR_SPE_CMP(fststgt);
2336 HELPER_VECTOR_SPE_CMP(fststeq);
2338 HELPER_VECTOR_SPE_CMP(fscmplt);
2340 HELPER_VECTOR_SPE_CMP(fscmpgt);
2342 HELPER_VECTOR_SPE_CMP(fscmpeq);
2344 /* Double-precision floating-point conversion */
2345 uint64_t helper_efdcfsi (uint32_t val)
2349 u.d = int32_to_float64(val, &env->spe_status);
2354 uint64_t helper_efdcfsid (uint64_t val)
2358 u.d = int64_to_float64(val, &env->spe_status);
2363 uint64_t helper_efdcfui (uint32_t val)
2367 u.d = uint32_to_float64(val, &env->spe_status);
2372 uint64_t helper_efdcfuid (uint64_t val)
2376 u.d = uint64_to_float64(val, &env->spe_status);
2381 uint32_t helper_efdctsi (uint64_t val)
2386 /* NaN are not treated the same way IEEE 754 does */
2387 if (unlikely(float64_is_nan(u.d)))
2390 return float64_to_int32(u.d, &env->spe_status);
2393 uint32_t helper_efdctui (uint64_t val)
2398 /* NaN are not treated the same way IEEE 754 does */
2399 if (unlikely(float64_is_nan(u.d)))
2402 return float64_to_uint32(u.d, &env->spe_status);
2405 uint32_t helper_efdctsiz (uint64_t val)
2410 /* NaN are not treated the same way IEEE 754 does */
2411 if (unlikely(float64_is_nan(u.d)))
2414 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2417 uint64_t helper_efdctsidz (uint64_t val)
2422 /* NaN are not treated the same way IEEE 754 does */
2423 if (unlikely(float64_is_nan(u.d)))
2426 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2429 uint32_t helper_efdctuiz (uint64_t val)
2434 /* NaN are not treated the same way IEEE 754 does */
2435 if (unlikely(float64_is_nan(u.d)))
2438 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2441 uint64_t helper_efdctuidz (uint64_t val)
2446 /* NaN are not treated the same way IEEE 754 does */
2447 if (unlikely(float64_is_nan(u.d)))
2450 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2453 uint64_t helper_efdcfsf (uint32_t val)
2458 u.d = int32_to_float64(val, &env->spe_status);
2459 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2460 u.d = float64_div(u.d, tmp, &env->spe_status);
2465 uint64_t helper_efdcfuf (uint32_t val)
2470 u.d = uint32_to_float64(val, &env->spe_status);
2471 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2472 u.d = float64_div(u.d, tmp, &env->spe_status);
2477 uint32_t helper_efdctsf (uint64_t val)
2483 /* NaN are not treated the same way IEEE 754 does */
2484 if (unlikely(float64_is_nan(u.d)))
2486 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2487 u.d = float64_mul(u.d, tmp, &env->spe_status);
2489 return float64_to_int32(u.d, &env->spe_status);
2492 uint32_t helper_efdctuf (uint64_t val)
2498 /* NaN are not treated the same way IEEE 754 does */
2499 if (unlikely(float64_is_nan(u.d)))
2501 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2502 u.d = float64_mul(u.d, tmp, &env->spe_status);
2504 return float64_to_uint32(u.d, &env->spe_status);
2507 uint32_t helper_efscfd (uint64_t val)
2513 u2.f = float64_to_float32(u1.d, &env->spe_status);
2518 uint64_t helper_efdcfs (uint32_t val)
2524 u2.d = float32_to_float64(u1.f, &env->spe_status);
2529 /* Double precision fixed-point arithmetic */
2530 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2535 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2539 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2544 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2548 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2553 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2557 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2562 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2566 /* Double precision floating point helpers */
2567 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2572 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2575 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2580 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2583 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2588 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2591 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2593 /* XXX: TODO: test special values (NaN, infinites, ...) */
2594 return helper_efdtstlt(op1, op2);
2597 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2599 /* XXX: TODO: test special values (NaN, infinites, ...) */
2600 return helper_efdtstgt(op1, op2);
2603 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2605 /* XXX: TODO: test special values (NaN, infinites, ...) */
2606 return helper_efdtsteq(op1, op2);
2609 /*****************************************************************************/
2610 /* Softmmu support */
2611 #if !defined (CONFIG_USER_ONLY)
2613 #define MMUSUFFIX _mmu
2616 #include "softmmu_template.h"
2619 #include "softmmu_template.h"
2622 #include "softmmu_template.h"
2625 #include "softmmu_template.h"
2627 /* try to fill the TLB and return an exception if error. If retaddr is
2628 NULL, it means that the function was called in C code (i.e. not
2629 from generated code or from helper.c) */
2630 /* XXX: fix it to restore all registers */
2631 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2633 TranslationBlock *tb;
2634 CPUState *saved_env;
2638 /* XXX: hack to restore env in all cases, even if not called from
2641 env = cpu_single_env;
2642 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2643 if (unlikely(ret != 0)) {
2644 if (likely(retaddr)) {
2645 /* now we have a real cpu fault */
2646 pc = (unsigned long)retaddr;
2647 tb = tb_find_pc(pc);
2649 /* the PC is inside the translated code. It means that we have
2650 a virtual CPU fault */
2651 cpu_restore_state(tb, env, pc, NULL);
2654 helper_raise_exception_err(env->exception_index, env->error_code);
2659 /* Segment registers load and store */
2660 target_ulong helper_load_sr (target_ulong sr_num)
2662 return env->sr[sr_num];
2665 void helper_store_sr (target_ulong sr_num, target_ulong val)
2667 ppc_store_sr(env, sr_num, val);
2670 /* SLB management */
2671 #if defined(TARGET_PPC64)
2672 target_ulong helper_load_slb (target_ulong slb_nr)
2674 return ppc_load_slb(env, slb_nr);
2677 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2679 ppc_store_slb(env, slb_nr, rs);
2682 void helper_slbia (void)
2684 ppc_slb_invalidate_all(env);
2687 void helper_slbie (target_ulong addr)
2689 ppc_slb_invalidate_one(env, addr);
2692 #endif /* defined(TARGET_PPC64) */
2694 /* TLB management */
2695 void helper_tlbia (void)
2697 ppc_tlb_invalidate_all(env);
2700 void helper_tlbie (target_ulong addr)
2702 ppc_tlb_invalidate_one(env, addr);
2705 /* Software driven TLBs management */
2706 /* PowerPC 602/603 software TLB load instructions helpers */
2707 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2709 target_ulong RPN, CMP, EPN;
2712 RPN = env->spr[SPR_RPA];
2714 CMP = env->spr[SPR_ICMP];
2715 EPN = env->spr[SPR_IMISS];
2717 CMP = env->spr[SPR_DCMP];
2718 EPN = env->spr[SPR_DMISS];
2720 way = (env->spr[SPR_SRR1] >> 17) & 1;
2721 #if defined (DEBUG_SOFTWARE_TLB)
2722 if (loglevel != 0) {
2723 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2724 " PTE1 " ADDRX " way %d\n",
2725 __func__, new_EPN, EPN, CMP, RPN, way);
2728 /* Store this TLB */
2729 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2730 way, is_code, CMP, RPN);
2733 void helper_6xx_tlbd (target_ulong EPN)
2738 void helper_6xx_tlbi (target_ulong EPN)
2743 /* PowerPC 74xx software TLB load instructions helpers */
2744 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2746 target_ulong RPN, CMP, EPN;
2749 RPN = env->spr[SPR_PTELO];
2750 CMP = env->spr[SPR_PTEHI];
2751 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2752 way = env->spr[SPR_TLBMISS] & 0x3;
2753 #if defined (DEBUG_SOFTWARE_TLB)
2754 if (loglevel != 0) {
2755 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2756 " PTE1 " ADDRX " way %d\n",
2757 __func__, new_EPN, EPN, CMP, RPN, way);
2760 /* Store this TLB */
2761 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2762 way, is_code, CMP, RPN);
2765 void helper_74xx_tlbd (target_ulong EPN)
2767 do_74xx_tlb(EPN, 0);
2770 void helper_74xx_tlbi (target_ulong EPN)
2772 do_74xx_tlb(EPN, 1);
2775 static always_inline target_ulong booke_tlb_to_page_size (int size)
2777 return 1024 << (2 * size);
2780 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2784 switch (page_size) {
2818 #if defined (TARGET_PPC64)
2819 case 0x000100000000ULL:
2822 case 0x000400000000ULL:
2825 case 0x001000000000ULL:
2828 case 0x004000000000ULL:
2831 case 0x010000000000ULL:
2843 /* Helpers for 4xx TLB management */
2844 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2851 tlb = &env->tlb[entry].tlbe;
2853 if (tlb->prot & PAGE_VALID)
2855 size = booke_page_size_to_tlb(tlb->size);
2856 if (size < 0 || size > 0x7)
2859 env->spr[SPR_40x_PID] = tlb->PID;
2863 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2869 tlb = &env->tlb[entry].tlbe;
2871 if (tlb->prot & PAGE_EXEC)
2873 if (tlb->prot & PAGE_WRITE)
2878 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2881 target_ulong page, end;
2883 #if defined (DEBUG_SOFTWARE_TLB)
2884 if (loglevel != 0) {
2885 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2889 tlb = &env->tlb[entry].tlbe;
2890 /* Invalidate previous TLB (if it's valid) */
2891 if (tlb->prot & PAGE_VALID) {
2892 end = tlb->EPN + tlb->size;
2893 #if defined (DEBUG_SOFTWARE_TLB)
2894 if (loglevel != 0) {
2895 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2896 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2899 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2900 tlb_flush_page(env, page);
2902 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2903 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2904 * If this ever occurs, one should use the ppcemb target instead
2905 * of the ppc or ppc64 one
2907 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2908 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2909 "are not supported (%d)\n",
2910 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2912 tlb->EPN = val & ~(tlb->size - 1);
2914 tlb->prot |= PAGE_VALID;
2916 tlb->prot &= ~PAGE_VALID;
2918 /* XXX: TO BE FIXED */
2919 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2921 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2922 tlb->attr = val & 0xFF;
2923 #if defined (DEBUG_SOFTWARE_TLB)
2924 if (loglevel != 0) {
2925 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2926 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2927 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2928 tlb->prot & PAGE_READ ? 'r' : '-',
2929 tlb->prot & PAGE_WRITE ? 'w' : '-',
2930 tlb->prot & PAGE_EXEC ? 'x' : '-',
2931 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2934 /* Invalidate new TLB (if valid) */
2935 if (tlb->prot & PAGE_VALID) {
2936 end = tlb->EPN + tlb->size;
2937 #if defined (DEBUG_SOFTWARE_TLB)
2938 if (loglevel != 0) {
2939 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2940 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2943 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2944 tlb_flush_page(env, page);
2948 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2952 #if defined (DEBUG_SOFTWARE_TLB)
2953 if (loglevel != 0) {
2954 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2958 tlb = &env->tlb[entry].tlbe;
2959 tlb->RPN = val & 0xFFFFFC00;
2960 tlb->prot = PAGE_READ;
2962 tlb->prot |= PAGE_EXEC;
2964 tlb->prot |= PAGE_WRITE;
2965 #if defined (DEBUG_SOFTWARE_TLB)
2966 if (loglevel != 0) {
2967 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2968 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2969 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2970 tlb->prot & PAGE_READ ? 'r' : '-',
2971 tlb->prot & PAGE_WRITE ? 'w' : '-',
2972 tlb->prot & PAGE_EXEC ? 'x' : '-',
2973 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2978 target_ulong helper_4xx_tlbsx (target_ulong address)
2980 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
2983 /* PowerPC 440 TLB management */
2984 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
2987 target_ulong EPN, RPN, size;
2990 #if defined (DEBUG_SOFTWARE_TLB)
2991 if (loglevel != 0) {
2992 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
2993 __func__, word, (int)entry, value);
2998 tlb = &env->tlb[entry].tlbe;
3001 /* Just here to please gcc */
3003 EPN = value & 0xFFFFFC00;
3004 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3007 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3008 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3012 tlb->attr |= (value >> 8) & 1;
3013 if (value & 0x200) {
3014 tlb->prot |= PAGE_VALID;
3016 if (tlb->prot & PAGE_VALID) {
3017 tlb->prot &= ~PAGE_VALID;
3021 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3026 RPN = value & 0xFFFFFC0F;
3027 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3032 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3033 tlb->prot = tlb->prot & PAGE_VALID;
3035 tlb->prot |= PAGE_READ << 4;
3037 tlb->prot |= PAGE_WRITE << 4;
3039 tlb->prot |= PAGE_EXEC << 4;
3041 tlb->prot |= PAGE_READ;
3043 tlb->prot |= PAGE_WRITE;
3045 tlb->prot |= PAGE_EXEC;
3050 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3057 tlb = &env->tlb[entry].tlbe;
3060 /* Just here to please gcc */
3063 size = booke_page_size_to_tlb(tlb->size);
3064 if (size < 0 || size > 0xF)
3067 if (tlb->attr & 0x1)
3069 if (tlb->prot & PAGE_VALID)
3071 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3072 env->spr[SPR_440_MMUCR] |= tlb->PID;
3078 ret = tlb->attr & ~0x1;
3079 if (tlb->prot & (PAGE_READ << 4))
3081 if (tlb->prot & (PAGE_WRITE << 4))
3083 if (tlb->prot & (PAGE_EXEC << 4))
3085 if (tlb->prot & PAGE_READ)
3087 if (tlb->prot & PAGE_WRITE)
3089 if (tlb->prot & PAGE_EXEC)
3096 target_ulong helper_440_tlbsx (target_ulong address)
3098 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3101 #endif /* !CONFIG_USER_ONLY */