2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
23 #include "helper_regs.h"
24 #include "op_helper.h"
26 #define MEMSUFFIX _raw
27 #include "op_helper.h"
28 #include "op_helper_mem.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #define MEMSUFFIX _user
31 #include "op_helper.h"
32 #include "op_helper_mem.h"
33 #define MEMSUFFIX _kernel
34 #include "op_helper.h"
35 #include "op_helper_mem.h"
36 #if defined(TARGET_PPC64H)
37 #define MEMSUFFIX _hypv
38 #include "op_helper.h"
39 #include "op_helper_mem.h"
44 //#define DEBUG_EXCEPTIONS
45 //#define DEBUG_SOFTWARE_TLB
47 /*****************************************************************************/
48 /* Exceptions processing helpers */
50 void do_raise_exception_err (uint32_t exception, int error_code)
53 printf("Raise exception %3x code : %d\n", exception, error_code);
55 env->exception_index = exception;
56 env->error_code = error_code;
60 void do_raise_exception (uint32_t exception)
62 do_raise_exception_err(exception, 0);
65 void cpu_dump_EA (target_ulong EA);
66 void do_print_mem_EA (target_ulong EA)
71 /*****************************************************************************/
72 /* Registers load and stores */
73 void do_load_cr (void)
75 T0 = (env->crf[0] << 28) |
85 void do_store_cr (uint32_t mask)
89 for (i = 0, sh = 7; i < 8; i++, sh--) {
91 env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
95 #if defined(TARGET_PPC64)
96 void do_store_pri (int prio)
98 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
99 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
103 target_ulong ppc_load_dump_spr (int sprn)
106 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
107 sprn, sprn, env->spr[sprn]);
110 return env->spr[sprn];
113 void ppc_store_dump_spr (int sprn, target_ulong val)
116 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
117 sprn, sprn, env->spr[sprn], val);
119 env->spr[sprn] = val;
122 /*****************************************************************************/
123 /* Fixed point operations helpers */
128 if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
129 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
136 #if defined(TARGET_PPC64)
137 void do_adde_64 (void)
141 if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
142 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
150 void do_addmeo (void)
154 xer_ov = ((uint32_t)T1 & ((uint32_t)T1 ^ (uint32_t)T0)) >> 31;
162 #if defined(TARGET_PPC64)
163 void do_addmeo_64 (void)
167 xer_ov = ((uint64_t)T1 & ((uint64_t)T1 ^ (uint64_t)T0)) >> 63;
178 if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
179 (int32_t)T1 == 0))) {
181 T0 = (int32_t)T0 / (int32_t)T1;
185 T0 = (-1) * ((uint32_t)T0 >> 31);
189 #if defined(TARGET_PPC64)
192 if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
193 (int64_t)T1 == 0))) {
195 T0 = (int64_t)T0 / (int64_t)T1;
199 T0 = (-1ULL) * ((uint64_t)T0 >> 63);
204 void do_divwuo (void)
206 if (likely((uint32_t)T1 != 0)) {
208 T0 = (uint32_t)T0 / (uint32_t)T1;
216 #if defined(TARGET_PPC64)
217 void do_divduo (void)
219 if (likely((uint64_t)T1 != 0)) {
221 T0 = (uint64_t)T0 / (uint64_t)T1;
230 void do_mullwo (void)
232 int64_t res = (int64_t)T0 * (int64_t)T1;
234 if (likely((int32_t)res == res)) {
243 #if defined(TARGET_PPC64)
244 void do_mulldo (void)
249 muls64(&tl, &th, T0, T1);
250 /* If th != 0 && th != -1, then we had an overflow */
251 if (likely((th + 1) <= 1)) {
263 if (likely((int32_t)T0 != INT32_MIN)) {
272 #if defined(TARGET_PPC64)
273 void do_nego_64 (void)
275 if (likely((int64_t)T0 != INT64_MIN)) {
287 T0 = T1 + ~T0 + xer_ca;
288 if (likely((uint32_t)T0 >= (uint32_t)T1 &&
289 (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
296 #if defined(TARGET_PPC64)
297 void do_subfe_64 (void)
299 T0 = T1 + ~T0 + xer_ca;
300 if (likely((uint64_t)T0 >= (uint64_t)T1 &&
301 (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
309 void do_subfmeo (void)
312 T0 = ~T0 + xer_ca - 1;
313 xer_ov = ((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0)) >> 31;
315 if (likely((uint32_t)T1 != UINT32_MAX))
321 #if defined(TARGET_PPC64)
322 void do_subfmeo_64 (void)
325 T0 = ~T0 + xer_ca - 1;
326 xer_ov = ((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0)) >> 63;
328 if (likely((uint64_t)T1 != UINT64_MAX))
335 void do_subfzeo (void)
339 xer_ov = (((uint32_t)~T1 ^ UINT32_MAX) &
340 ((uint32_t)(~T1) ^ (uint32_t)T0)) >> 31;
342 if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
349 #if defined(TARGET_PPC64)
350 void do_subfzeo_64 (void)
354 xer_ov = (((uint64_t)~T1 ^ UINT64_MAX) &
355 ((uint64_t)(~T1) ^ (uint64_t)T0)) >> 63;
357 if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
365 void do_cntlzw (void)
370 #if defined(TARGET_PPC64)
371 void do_cntlzd (void)
377 /* shift right arithmetic helper */
382 if (likely(!(T1 & 0x20UL))) {
383 if (likely((uint32_t)T1 != 0)) {
384 ret = (int32_t)T0 >> (T1 & 0x1fUL);
385 if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
395 ret = (-1) * ((uint32_t)T0 >> 31);
396 if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
405 #if defined(TARGET_PPC64)
410 if (likely(!(T1 & 0x40UL))) {
411 if (likely((uint64_t)T1 != 0)) {
412 ret = (int64_t)T0 >> (T1 & 0x3FUL);
413 if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
423 ret = (-1) * ((uint64_t)T0 >> 63);
424 if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
434 void do_popcntb (void)
440 for (i = 0; i < 32; i += 8)
441 ret |= ctpop8((T0 >> i) & 0xFF) << i;
445 #if defined(TARGET_PPC64)
446 void do_popcntb_64 (void)
452 for (i = 0; i < 64; i += 8)
453 ret |= ctpop8((T0 >> i) & 0xFF) << i;
458 /*****************************************************************************/
459 /* Floating point operations helpers */
460 static always_inline int fpisneg (float64 f)
469 return u.u >> 63 != 0;
472 static always_inline int isden (float f)
481 return ((u.u >> 52) & 0x7FF) == 0;
484 static always_inline int iszero (float64 f)
493 return (u.u & ~0x8000000000000000ULL) == 0;
496 static always_inline int isinfinity (float64 f)
505 return ((u.u >> 52) & 0x7FF) == 0x7FF &&
506 (u.u & 0x000FFFFFFFFFFFFFULL) == 0;
509 void do_compute_fprf (int set_fprf)
513 isneg = fpisneg(FT0);
514 if (unlikely(float64_is_nan(FT0))) {
515 if (float64_is_signaling_nan(FT0)) {
516 /* Signaling NaN: flags are undefined */
522 } else if (unlikely(isinfinity(FT0))) {
537 /* Denormalized numbers */
540 /* Normalized numbers */
551 /* We update FPSCR_FPRF */
552 env->fpscr &= ~(0x1F << FPSCR_FPRF);
553 env->fpscr |= T0 << FPSCR_FPRF;
555 /* We just need fpcc to update Rc1 */
559 /* Floating-point invalid operations exception */
560 static always_inline void fload_invalid_op_excp (int op)
565 if (op & POWERPC_EXCP_FP_VXSNAN) {
566 /* Operation on signaling NaN */
567 env->fpscr |= 1 << FPSCR_VXSNAN;
569 if (op & POWERPC_EXCP_FP_VXSOFT) {
570 /* Software-defined condition */
571 env->fpscr |= 1 << FPSCR_VXSOFT;
573 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
574 case POWERPC_EXCP_FP_VXISI:
575 /* Magnitude subtraction of infinities */
576 env->fpscr |= 1 << FPSCR_VXISI;
578 case POWERPC_EXCP_FP_VXIDI:
579 /* Division of infinity by infinity */
580 env->fpscr |= 1 << FPSCR_VXIDI;
582 case POWERPC_EXCP_FP_VXZDZ:
583 /* Division of zero by zero */
584 env->fpscr |= 1 << FPSCR_VXZDZ;
586 case POWERPC_EXCP_FP_VXIMZ:
587 /* Multiplication of zero by infinity */
588 env->fpscr |= 1 << FPSCR_VXIMZ;
590 case POWERPC_EXCP_FP_VXVC:
591 /* Ordered comparison of NaN */
592 env->fpscr |= 1 << FPSCR_VXVC;
593 env->fpscr &= ~(0xF << FPSCR_FPCC);
594 env->fpscr |= 0x11 << FPSCR_FPCC;
595 /* We must update the target FPR before raising the exception */
597 env->exception_index = POWERPC_EXCP_PROGRAM;
598 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
599 /* Update the floating-point enabled exception summary */
600 env->fpscr |= 1 << FPSCR_FEX;
601 /* Exception is differed */
605 case POWERPC_EXCP_FP_VXSQRT:
606 /* Square root of a negative number */
607 env->fpscr |= 1 << FPSCR_VXSQRT;
609 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
611 /* Set the result to quiet NaN */
613 env->fpscr &= ~(0xF << FPSCR_FPCC);
614 env->fpscr |= 0x11 << FPSCR_FPCC;
617 case POWERPC_EXCP_FP_VXCVI:
618 /* Invalid conversion */
619 env->fpscr |= 1 << FPSCR_VXCVI;
620 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
622 /* Set the result to quiet NaN */
624 env->fpscr &= ~(0xF << FPSCR_FPCC);
625 env->fpscr |= 0x11 << FPSCR_FPCC;
629 /* Update the floating-point invalid operation summary */
630 env->fpscr |= 1 << FPSCR_VX;
631 /* Update the floating-point exception summary */
632 env->fpscr |= 1 << FPSCR_FX;
634 /* Update the floating-point enabled exception summary */
635 env->fpscr |= 1 << FPSCR_FEX;
636 if (msr_fe0 != 0 || msr_fe1 != 0)
637 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
641 static always_inline void float_zero_divide_excp (void)
648 env->fpscr |= 1 << FPSCR_ZX;
649 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
650 /* Update the floating-point exception summary */
651 env->fpscr |= 1 << FPSCR_FX;
653 /* Update the floating-point enabled exception summary */
654 env->fpscr |= 1 << FPSCR_FEX;
655 if (msr_fe0 != 0 || msr_fe1 != 0) {
656 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
657 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
660 /* Set the result to infinity */
663 u0.u = ((u0.u ^ u1.u) & 0x8000000000000000ULL);
664 u0.u |= 0x7FFULL << 52;
669 static always_inline void float_overflow_excp (void)
671 env->fpscr |= 1 << FPSCR_OX;
672 /* Update the floating-point exception summary */
673 env->fpscr |= 1 << FPSCR_FX;
675 /* XXX: should adjust the result */
676 /* Update the floating-point enabled exception summary */
677 env->fpscr |= 1 << FPSCR_FEX;
678 /* We must update the target FPR before raising the exception */
679 env->exception_index = POWERPC_EXCP_PROGRAM;
680 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
682 env->fpscr |= 1 << FPSCR_XX;
683 env->fpscr |= 1 << FPSCR_FI;
687 static always_inline void float_underflow_excp (void)
689 env->fpscr |= 1 << FPSCR_UX;
690 /* Update the floating-point exception summary */
691 env->fpscr |= 1 << FPSCR_FX;
693 /* XXX: should adjust the result */
694 /* Update the floating-point enabled exception summary */
695 env->fpscr |= 1 << FPSCR_FEX;
696 /* We must update the target FPR before raising the exception */
697 env->exception_index = POWERPC_EXCP_PROGRAM;
698 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
702 static always_inline void float_inexact_excp (void)
704 env->fpscr |= 1 << FPSCR_XX;
705 /* Update the floating-point exception summary */
706 env->fpscr |= 1 << FPSCR_FX;
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 /* We must update the target FPR before raising the exception */
711 env->exception_index = POWERPC_EXCP_PROGRAM;
712 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
716 static always_inline void fpscr_set_rounding_mode (void)
720 /* Set rounding mode */
723 /* Best approximation (round to nearest) */
724 rnd_type = float_round_nearest_even;
727 /* Smaller magnitude (round toward zero) */
728 rnd_type = float_round_to_zero;
731 /* Round toward +infinite */
732 rnd_type = float_round_up;
736 /* Round toward -infinite */
737 rnd_type = float_round_down;
740 set_float_rounding_mode(rnd_type, &env->fp_status);
743 void do_fpscr_setbit (int bit)
747 prev = (env->fpscr >> bit) & 1;
748 env->fpscr |= 1 << bit;
752 env->fpscr |= 1 << FPSCR_FX;
756 env->fpscr |= 1 << FPSCR_FX;
761 env->fpscr |= 1 << FPSCR_FX;
766 env->fpscr |= 1 << FPSCR_FX;
771 env->fpscr |= 1 << FPSCR_FX;
784 env->fpscr |= 1 << FPSCR_VX;
785 env->fpscr |= 1 << FPSCR_FX;
792 env->error_code = POWERPC_EXCP_FP;
794 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
796 env->error_code |= POWERPC_EXCP_FP_VXISI;
798 env->error_code |= POWERPC_EXCP_FP_VXIDI;
800 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
802 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
804 env->error_code |= POWERPC_EXCP_FP_VXVC;
806 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
808 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
810 env->error_code |= POWERPC_EXCP_FP_VXCVI;
817 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
824 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
831 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
838 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
844 fpscr_set_rounding_mode();
849 /* Update the floating-point enabled exception summary */
850 env->fpscr |= 1 << FPSCR_FEX;
851 /* We have to update Rc1 before raising the exception */
852 env->exception_index = POWERPC_EXCP_PROGRAM;
858 #if defined(WORDS_BIGENDIAN)
865 void do_store_fpscr (uint32_t mask)
868 * We use only the 32 LSB of the incoming fpr
883 new |= prev & 0x90000000;
884 for (i = 0; i < 7; i++) {
885 if (mask & (1 << i)) {
886 env->fpscr &= ~(0xF << (4 * i));
887 env->fpscr |= new & (0xF << (4 * i));
890 /* Update VX and FEX */
892 env->fpscr |= 1 << FPSCR_VX;
893 if ((fpscr_ex & fpscr_eex) != 0) {
894 env->fpscr |= 1 << FPSCR_FEX;
895 env->exception_index = POWERPC_EXCP_PROGRAM;
896 /* XXX: we should compute it properly */
897 env->error_code = POWERPC_EXCP_FP;
899 fpscr_set_rounding_mode();
904 #ifdef CONFIG_SOFTFLOAT
905 void do_float_check_status (void)
907 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
908 (env->error_code & POWERPC_EXCP_FP)) {
909 /* Differred floating-point exception after target FPR update */
910 if (msr_fe0 != 0 || msr_fe1 != 0)
911 do_raise_exception_err(env->exception_index, env->error_code);
912 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
913 float_overflow_excp();
914 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
915 float_underflow_excp();
916 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
917 float_inexact_excp();
922 #if USE_PRECISE_EMULATION
925 if (unlikely(float64_is_signaling_nan(FT0) ||
926 float64_is_signaling_nan(FT1))) {
928 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
929 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
930 fpisneg(FT0) == fpisneg(FT1))) {
931 FT0 = float64_add(FT0, FT1, &env->fp_status);
933 /* Magnitude subtraction of infinities */
934 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
940 if (unlikely(float64_is_signaling_nan(FT0) ||
941 float64_is_signaling_nan(FT1))) {
942 /* sNaN subtraction */
943 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
944 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
945 fpisneg(FT0) != fpisneg(FT1))) {
946 FT0 = float64_sub(FT0, FT1, &env->fp_status);
948 /* Magnitude subtraction of infinities */
949 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
955 if (unlikely(float64_is_signaling_nan(FT0) ||
956 float64_is_signaling_nan(FT1))) {
957 /* sNaN multiplication */
958 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
959 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
960 (iszero(FT0) && isinfinity(FT1)))) {
961 /* Multiplication of zero by infinity */
962 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
964 FT0 = float64_mul(FT0, FT1, &env->fp_status);
970 if (unlikely(float64_is_signaling_nan(FT0) ||
971 float64_is_signaling_nan(FT1))) {
973 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
974 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
975 /* Division of infinity by infinity */
976 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
977 } else if (unlikely(iszero(FT1))) {
979 /* Division of zero by zero */
980 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
982 /* Division by zero */
983 float_zero_divide_excp();
986 FT0 = float64_div(FT0, FT1, &env->fp_status);
989 #endif /* USE_PRECISE_EMULATION */
998 if (unlikely(float64_is_signaling_nan(FT0))) {
999 /* sNaN conversion */
1000 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1001 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1002 /* qNan / infinity conversion */
1003 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1005 p.i = float64_to_int32(FT0, &env->fp_status);
1006 #if USE_PRECISE_EMULATION
1007 /* XXX: higher bits are not supposed to be significant.
1008 * to make tests easier, return the same as a real PowerPC 750
1010 p.i |= 0xFFF80000ULL << 32;
1016 void do_fctiwz (void)
1023 if (unlikely(float64_is_signaling_nan(FT0))) {
1024 /* sNaN conversion */
1025 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1026 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1027 /* qNan / infinity conversion */
1028 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1030 p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
1031 #if USE_PRECISE_EMULATION
1032 /* XXX: higher bits are not supposed to be significant.
1033 * to make tests easier, return the same as a real PowerPC 750
1035 p.i |= 0xFFF80000ULL << 32;
1041 #if defined(TARGET_PPC64)
1042 void do_fcfid (void)
1050 FT0 = int64_to_float64(p.i, &env->fp_status);
1053 void do_fctid (void)
1060 if (unlikely(float64_is_signaling_nan(FT0))) {
1061 /* sNaN conversion */
1062 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1063 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1064 /* qNan / infinity conversion */
1065 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1067 p.i = float64_to_int64(FT0, &env->fp_status);
1072 void do_fctidz (void)
1079 if (unlikely(float64_is_signaling_nan(FT0))) {
1080 /* sNaN conversion */
1081 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1082 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1083 /* qNan / infinity conversion */
1084 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1086 p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
1093 static always_inline void do_fri (int rounding_mode)
1095 if (unlikely(float64_is_signaling_nan(FT0))) {
1097 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1098 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1099 /* qNan / infinity round */
1100 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1102 set_float_rounding_mode(rounding_mode, &env->fp_status);
1103 FT0 = float64_round_to_int(FT0, &env->fp_status);
1104 /* Restore rounding mode from FPSCR */
1105 fpscr_set_rounding_mode();
1111 do_fri(float_round_nearest_even);
1116 do_fri(float_round_to_zero);
1121 do_fri(float_round_up);
1126 do_fri(float_round_down);
1129 #if USE_PRECISE_EMULATION
1130 void do_fmadd (void)
1132 if (unlikely(float64_is_signaling_nan(FT0) ||
1133 float64_is_signaling_nan(FT1) ||
1134 float64_is_signaling_nan(FT2))) {
1135 /* sNaN operation */
1136 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1139 /* This is the way the PowerPC specification defines it */
1140 float128 ft0_128, ft1_128;
1142 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1143 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1144 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1145 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1146 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1147 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1149 /* This is OK on x86 hosts */
1150 FT0 = (FT0 * FT1) + FT2;
1155 void do_fmsub (void)
1157 if (unlikely(float64_is_signaling_nan(FT0) ||
1158 float64_is_signaling_nan(FT1) ||
1159 float64_is_signaling_nan(FT2))) {
1160 /* sNaN operation */
1161 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1164 /* This is the way the PowerPC specification defines it */
1165 float128 ft0_128, ft1_128;
1167 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1168 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1169 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1170 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1171 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1172 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1174 /* This is OK on x86 hosts */
1175 FT0 = (FT0 * FT1) - FT2;
1179 #endif /* USE_PRECISE_EMULATION */
1181 void do_fnmadd (void)
1183 if (unlikely(float64_is_signaling_nan(FT0) ||
1184 float64_is_signaling_nan(FT1) ||
1185 float64_is_signaling_nan(FT2))) {
1186 /* sNaN operation */
1187 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1189 #if USE_PRECISE_EMULATION
1191 /* This is the way the PowerPC specification defines it */
1192 float128 ft0_128, ft1_128;
1194 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1195 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1196 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1197 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1198 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1199 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1201 /* This is OK on x86 hosts */
1202 FT0 = (FT0 * FT1) + FT2;
1205 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1206 FT0 = float64_add(FT0, FT2, &env->fp_status);
1208 if (likely(!isnan(FT0)))
1209 FT0 = float64_chs(FT0);
1213 void do_fnmsub (void)
1215 if (unlikely(float64_is_signaling_nan(FT0) ||
1216 float64_is_signaling_nan(FT1) ||
1217 float64_is_signaling_nan(FT2))) {
1218 /* sNaN operation */
1219 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1221 #if USE_PRECISE_EMULATION
1223 /* This is the way the PowerPC specification defines it */
1224 float128 ft0_128, ft1_128;
1226 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1227 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1228 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1229 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1230 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1231 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1233 /* This is OK on x86 hosts */
1234 FT0 = (FT0 * FT1) - FT2;
1237 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1238 FT0 = float64_sub(FT0, FT2, &env->fp_status);
1240 if (likely(!isnan(FT0)))
1241 FT0 = float64_chs(FT0);
1245 #if USE_PRECISE_EMULATION
1248 if (unlikely(float64_is_signaling_nan(FT0))) {
1249 /* sNaN square root */
1250 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1252 FT0 = float64_to_float32(FT0, &env->fp_status);
1255 #endif /* USE_PRECISE_EMULATION */
1257 void do_fsqrt (void)
1259 if (unlikely(float64_is_signaling_nan(FT0))) {
1260 /* sNaN square root */
1261 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1262 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1263 /* Square root of a negative nonzero number */
1264 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1266 FT0 = float64_sqrt(FT0, &env->fp_status);
1277 if (unlikely(float64_is_signaling_nan(FT0))) {
1278 /* sNaN reciprocal */
1279 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1280 } else if (unlikely(iszero(FT0))) {
1281 /* Zero reciprocal */
1282 float_zero_divide_excp();
1283 } else if (likely(isnormal(FT0))) {
1284 FT0 = float64_div(1.0, FT0, &env->fp_status);
1287 if (p.i == 0x8000000000000000ULL) {
1288 p.i = 0xFFF0000000000000ULL;
1289 } else if (p.i == 0x0000000000000000ULL) {
1290 p.i = 0x7FF0000000000000ULL;
1291 } else if (isnan(FT0)) {
1292 p.i = 0x7FF8000000000000ULL;
1293 } else if (fpisneg(FT0)) {
1294 p.i = 0x8000000000000000ULL;
1296 p.i = 0x0000000000000000ULL;
1309 if (unlikely(float64_is_signaling_nan(FT0))) {
1310 /* sNaN reciprocal */
1311 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1312 } else if (unlikely(iszero(FT0))) {
1313 /* Zero reciprocal */
1314 float_zero_divide_excp();
1315 } else if (likely(isnormal(FT0))) {
1316 #if USE_PRECISE_EMULATION
1317 FT0 = float64_div(1.0, FT0, &env->fp_status);
1318 FT0 = float64_to_float32(FT0, &env->fp_status);
1320 FT0 = float32_div(1.0, FT0, &env->fp_status);
1324 if (p.i == 0x8000000000000000ULL) {
1325 p.i = 0xFFF0000000000000ULL;
1326 } else if (p.i == 0x0000000000000000ULL) {
1327 p.i = 0x7FF0000000000000ULL;
1328 } else if (isnan(FT0)) {
1329 p.i = 0x7FF8000000000000ULL;
1330 } else if (fpisneg(FT0)) {
1331 p.i = 0x8000000000000000ULL;
1333 p.i = 0x0000000000000000ULL;
1339 void do_frsqrte (void)
1346 if (unlikely(float64_is_signaling_nan(FT0))) {
1347 /* sNaN reciprocal square root */
1348 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1349 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1350 /* Reciprocal square root of a negative nonzero number */
1351 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1352 } else if (likely(isnormal(FT0))) {
1353 FT0 = float64_sqrt(FT0, &env->fp_status);
1354 FT0 = float32_div(1.0, FT0, &env->fp_status);
1357 if (p.i == 0x8000000000000000ULL) {
1358 p.i = 0xFFF0000000000000ULL;
1359 } else if (p.i == 0x0000000000000000ULL) {
1360 p.i = 0x7FF0000000000000ULL;
1361 } else if (isnan(FT0)) {
1362 p.i |= 0x000FFFFFFFFFFFFFULL;
1363 } else if (fpisneg(FT0)) {
1364 p.i = 0x7FF8000000000000ULL;
1366 p.i = 0x0000000000000000ULL;
1374 if (!fpisneg(FT0) || iszero(FT0))
1380 void do_fcmpu (void)
1382 if (unlikely(float64_is_signaling_nan(FT0) ||
1383 float64_is_signaling_nan(FT1))) {
1384 /* sNaN comparison */
1385 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1387 if (float64_lt(FT0, FT1, &env->fp_status)) {
1389 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1395 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1396 env->fpscr |= T0 << FPSCR_FPRF;
1399 void do_fcmpo (void)
1401 if (unlikely(float64_is_nan(FT0) ||
1402 float64_is_nan(FT1))) {
1403 if (float64_is_signaling_nan(FT0) ||
1404 float64_is_signaling_nan(FT1)) {
1405 /* sNaN comparison */
1406 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1407 POWERPC_EXCP_FP_VXVC);
1409 /* qNaN comparison */
1410 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1413 if (float64_lt(FT0, FT1, &env->fp_status)) {
1415 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1421 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1422 env->fpscr |= T0 << FPSCR_FPRF;
1425 #if !defined (CONFIG_USER_ONLY)
1426 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1428 void do_store_msr (void)
1430 T0 = hreg_store_msr(env, T0);
1432 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1433 do_raise_exception(T0);
1437 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1438 target_ulong msrm, int keep_msrh)
1440 #if defined(TARGET_PPC64)
1441 if (msr & (1ULL << MSR_SF)) {
1442 nip = (uint64_t)nip;
1443 msr &= (uint64_t)msrm;
1445 nip = (uint32_t)nip;
1446 msr = (uint32_t)(msr & msrm);
1448 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1451 nip = (uint32_t)nip;
1452 msr &= (uint32_t)msrm;
1454 /* XXX: beware: this is false if VLE is supported */
1455 env->nip = nip & ~((target_ulong)0x00000003);
1456 hreg_store_msr(env, msr);
1457 #if defined (DEBUG_OP)
1458 cpu_dump_rfi(env->nip, env->msr);
1460 /* No need to raise an exception here,
1461 * as rfi is always the last insn of a TB
1463 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1468 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1469 ~((target_ulong)0xFFFF0000), 1);
1472 #if defined(TARGET_PPC64)
1475 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1476 ~((target_ulong)0xFFFF0000), 0);
1479 #if defined(TARGET_PPC64H)
1480 void do_hrfid (void)
1482 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1483 ~((target_ulong)0xFFFF0000), 0);
1488 void do_tw (int flags)
1490 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1491 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1492 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1493 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
1494 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
1495 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1499 #if defined(TARGET_PPC64)
1500 void do_td (int flags)
1502 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1503 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1504 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1505 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1506 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
1507 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1511 /*****************************************************************************/
1512 /* PowerPC 601 specific instructions (POWER bridge) */
1513 void do_POWER_abso (void)
1515 if ((int32_t)T0 == INT32_MIN) {
1518 } else if ((int32_t)T0 < 0) {
1527 void do_POWER_clcs (void)
1531 /* Instruction cache line size */
1532 T0 = env->icache_line_size;
1535 /* Data cache line size */
1536 T0 = env->dcache_line_size;
1539 /* Minimum cache line size */
1540 T0 = env->icache_line_size < env->dcache_line_size ?
1541 env->icache_line_size : env->dcache_line_size;
1544 /* Maximum cache line size */
1545 T0 = env->icache_line_size > env->dcache_line_size ?
1546 env->icache_line_size : env->dcache_line_size;
1554 void do_POWER_div (void)
1558 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1559 T0 = (long)((-1) * (T0 >> 31));
1560 env->spr[SPR_MQ] = 0;
1562 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1563 env->spr[SPR_MQ] = tmp % T1;
1564 T0 = tmp / (int32_t)T1;
1568 void do_POWER_divo (void)
1572 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1573 T0 = (long)((-1) * (T0 >> 31));
1574 env->spr[SPR_MQ] = 0;
1578 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1579 env->spr[SPR_MQ] = tmp % T1;
1581 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1591 void do_POWER_divs (void)
1593 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1594 T0 = (long)((-1) * (T0 >> 31));
1595 env->spr[SPR_MQ] = 0;
1597 env->spr[SPR_MQ] = T0 % T1;
1598 T0 = (int32_t)T0 / (int32_t)T1;
1602 void do_POWER_divso (void)
1604 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
1605 T0 = (long)((-1) * (T0 >> 31));
1606 env->spr[SPR_MQ] = 0;
1610 T0 = (int32_t)T0 / (int32_t)T1;
1611 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1616 void do_POWER_dozo (void)
1618 if ((int32_t)T1 > (int32_t)T0) {
1621 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1622 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1634 void do_POWER_maskg (void)
1638 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1641 ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
1642 (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
1643 if ((uint32_t)T0 > (uint32_t)T1)
1649 void do_POWER_mulo (void)
1653 tmp = (uint64_t)T0 * (uint64_t)T1;
1654 env->spr[SPR_MQ] = tmp >> 32;
1656 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1664 #if !defined (CONFIG_USER_ONLY)
1665 void do_POWER_rac (void)
1670 /* We don't have to generate many instances of this instruction,
1671 * as rac is supervisor only.
1673 /* XXX: FIX THIS: Pretend we have no BAT */
1674 nb_BATs = env->nb_BATs;
1676 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1678 env->nb_BATs = nb_BATs;
1681 void do_POWER_rfsvc (void)
1683 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1686 void do_store_hid0_601 (void)
1690 hid0 = env->spr[SPR_HID0];
1691 if ((T0 ^ hid0) & 0x00000008) {
1692 /* Change current endianness */
1693 env->hflags &= ~(1 << MSR_LE);
1694 env->hflags_nmsr &= ~(1 << MSR_LE);
1695 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1696 env->hflags |= env->hflags_nmsr;
1697 if (loglevel != 0) {
1698 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1699 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1702 env->spr[SPR_HID0] = T0;
1706 /*****************************************************************************/
1707 /* 602 specific instructions */
1708 /* mfrom is the most crazy instruction ever seen, imho ! */
1709 /* Real implementation uses a ROM table. Do the same */
1710 #define USE_MFROM_ROM_TABLE
1711 void do_op_602_mfrom (void)
1713 if (likely(T0 < 602)) {
1714 #if defined(USE_MFROM_ROM_TABLE)
1715 #include "mfrom_table.c"
1716 T0 = mfrom_ROM_table[T0];
1719 /* Extremly decomposed:
1721 * T0 = 256 * log10(10 + 1.0) + 0.5
1724 d = float64_div(d, 256, &env->fp_status);
1726 d = exp10(d); // XXX: use float emulation function
1727 d = float64_add(d, 1.0, &env->fp_status);
1728 d = log10(d); // XXX: use float emulation function
1729 d = float64_mul(d, 256, &env->fp_status);
1730 d = float64_add(d, 0.5, &env->fp_status);
1731 T0 = float64_round_to_int(d, &env->fp_status);
1738 /*****************************************************************************/
1739 /* Embedded PowerPC specific helpers */
1740 void do_405_check_sat (void)
1742 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1743 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1744 /* Saturate result */
1753 /* XXX: to be improved to check access rights when in user-mode */
1754 void do_load_dcr (void)
1758 if (unlikely(env->dcr_env == NULL)) {
1759 if (loglevel != 0) {
1760 fprintf(logfile, "No DCR environment\n");
1762 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1763 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1764 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1765 if (loglevel != 0) {
1766 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1768 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1769 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1775 void do_store_dcr (void)
1777 if (unlikely(env->dcr_env == NULL)) {
1778 if (loglevel != 0) {
1779 fprintf(logfile, "No DCR environment\n");
1781 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1782 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1783 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1784 if (loglevel != 0) {
1785 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1787 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1788 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1792 #if !defined(CONFIG_USER_ONLY)
1793 void do_40x_rfci (void)
1795 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1796 ~((target_ulong)0xFFFF0000), 0);
1801 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1802 ~((target_ulong)0x3FFF0000), 0);
1807 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1808 ~((target_ulong)0x3FFF0000), 0);
1811 void do_rfmci (void)
1813 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1814 ~((target_ulong)0x3FFF0000), 0);
1817 void do_load_403_pb (int num)
1822 void do_store_403_pb (int num)
1824 if (likely(env->pb[num] != T0)) {
1826 /* Should be optimized */
1833 void do_440_dlmzb (void)
1839 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1840 if ((T0 & mask) == 0)
1844 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1845 if ((T1 & mask) == 0)
1853 #if defined(TARGET_PPCEMB)
1854 /* SPE extension helpers */
1855 /* Use a table to make this quicker */
1856 static uint8_t hbrev[16] = {
1857 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1858 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1861 static always_inline uint8_t byte_reverse (uint8_t val)
1863 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1866 static always_inline uint32_t word_reverse (uint32_t val)
1868 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1869 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1872 #define MASKBITS 16 // Random value - to be fixed
1873 void do_brinc (void)
1875 uint32_t a, b, d, mask;
1877 mask = (uint32_t)(-1UL) >> MASKBITS;
1880 d = word_reverse(1 + word_reverse(a | ~mask));
1881 T0_64 = (T0_64 & ~mask) | (d & mask);
1884 #define DO_SPE_OP2(name) \
1885 void do_ev##name (void) \
1887 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1888 (uint64_t)_do_e##name(T0_64, T1_64); \
1891 #define DO_SPE_OP1(name) \
1892 void do_ev##name (void) \
1894 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1895 (uint64_t)_do_e##name(T0_64); \
1898 /* Fixed-point vector arithmetic */
1899 static always_inline uint32_t _do_eabs (uint32_t val)
1901 if ((val & 0x80000000) && val != 0x80000000)
1907 static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1912 static always_inline int _do_ecntlsw (uint32_t val)
1914 if (val & 0x80000000)
1920 static always_inline int _do_ecntlzw (uint32_t val)
1925 static always_inline uint32_t _do_eneg (uint32_t val)
1927 if (val != 0x80000000)
1933 static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1935 return rotl32(op1, op2);
1938 static always_inline uint32_t _do_erndw (uint32_t val)
1940 return (val + 0x000080000000) & 0xFFFF0000;
1943 static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1945 /* No error here: 6 bits are used */
1946 return op1 << (op2 & 0x3F);
1949 static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1951 /* No error here: 6 bits are used */
1952 return op1 >> (op2 & 0x3F);
1955 static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1957 /* No error here: 6 bits are used */
1958 return op1 >> (op2 & 0x3F);
1961 static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1989 /* evsel is a little bit more complicated... */
1990 static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1998 void do_evsel (void)
2000 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
2001 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
2004 /* Fixed-point vector comparisons */
2005 #define DO_SPE_CMP(name) \
2006 void do_ev##name (void) \
2008 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
2009 T1_64 >> 32) << 32, \
2010 _do_e##name(T0_64, T1_64)); \
2013 static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
2015 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2017 static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
2019 return op1 == op2 ? 1 : 0;
2022 static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
2024 return op1 > op2 ? 1 : 0;
2027 static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
2029 return op1 > op2 ? 1 : 0;
2032 static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
2034 return op1 < op2 ? 1 : 0;
2037 static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
2039 return op1 < op2 ? 1 : 0;
2053 /* Single precision floating-point conversions from/to integer */
2054 static always_inline uint32_t _do_efscfsi (int32_t val)
2061 u.f = int32_to_float32(val, &env->spe_status);
2066 static always_inline uint32_t _do_efscfui (uint32_t val)
2073 u.f = uint32_to_float32(val, &env->spe_status);
2078 static always_inline int32_t _do_efsctsi (uint32_t val)
2086 /* NaN are not treated the same way IEEE 754 does */
2087 if (unlikely(isnan(u.f)))
2090 return float32_to_int32(u.f, &env->spe_status);
2093 static always_inline uint32_t _do_efsctui (uint32_t val)
2101 /* NaN are not treated the same way IEEE 754 does */
2102 if (unlikely(isnan(u.f)))
2105 return float32_to_uint32(u.f, &env->spe_status);
2108 static always_inline int32_t _do_efsctsiz (uint32_t val)
2116 /* NaN are not treated the same way IEEE 754 does */
2117 if (unlikely(isnan(u.f)))
2120 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2123 static always_inline uint32_t _do_efsctuiz (uint32_t val)
2131 /* NaN are not treated the same way IEEE 754 does */
2132 if (unlikely(isnan(u.f)))
2135 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2138 void do_efscfsi (void)
2140 T0_64 = _do_efscfsi(T0_64);
2143 void do_efscfui (void)
2145 T0_64 = _do_efscfui(T0_64);
2148 void do_efsctsi (void)
2150 T0_64 = _do_efsctsi(T0_64);
2153 void do_efsctui (void)
2155 T0_64 = _do_efsctui(T0_64);
2158 void do_efsctsiz (void)
2160 T0_64 = _do_efsctsiz(T0_64);
2163 void do_efsctuiz (void)
2165 T0_64 = _do_efsctuiz(T0_64);
2168 /* Single precision floating-point conversion to/from fractional */
2169 static always_inline uint32_t _do_efscfsf (uint32_t val)
2177 u.f = int32_to_float32(val, &env->spe_status);
2178 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2179 u.f = float32_div(u.f, tmp, &env->spe_status);
2184 static always_inline uint32_t _do_efscfuf (uint32_t val)
2192 u.f = uint32_to_float32(val, &env->spe_status);
2193 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2194 u.f = float32_div(u.f, tmp, &env->spe_status);
2199 static always_inline int32_t _do_efsctsf (uint32_t val)
2208 /* NaN are not treated the same way IEEE 754 does */
2209 if (unlikely(isnan(u.f)))
2211 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2212 u.f = float32_mul(u.f, tmp, &env->spe_status);
2214 return float32_to_int32(u.f, &env->spe_status);
2217 static always_inline uint32_t _do_efsctuf (uint32_t val)
2226 /* NaN are not treated the same way IEEE 754 does */
2227 if (unlikely(isnan(u.f)))
2229 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2230 u.f = float32_mul(u.f, tmp, &env->spe_status);
2232 return float32_to_uint32(u.f, &env->spe_status);
2235 static always_inline int32_t _do_efsctsfz (uint32_t val)
2244 /* NaN are not treated the same way IEEE 754 does */
2245 if (unlikely(isnan(u.f)))
2247 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2248 u.f = float32_mul(u.f, tmp, &env->spe_status);
2250 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2253 static always_inline uint32_t _do_efsctufz (uint32_t val)
2262 /* NaN are not treated the same way IEEE 754 does */
2263 if (unlikely(isnan(u.f)))
2265 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2266 u.f = float32_mul(u.f, tmp, &env->spe_status);
2268 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2271 void do_efscfsf (void)
2273 T0_64 = _do_efscfsf(T0_64);
2276 void do_efscfuf (void)
2278 T0_64 = _do_efscfuf(T0_64);
2281 void do_efsctsf (void)
2283 T0_64 = _do_efsctsf(T0_64);
2286 void do_efsctuf (void)
2288 T0_64 = _do_efsctuf(T0_64);
2291 void do_efsctsfz (void)
2293 T0_64 = _do_efsctsfz(T0_64);
2296 void do_efsctufz (void)
2298 T0_64 = _do_efsctufz(T0_64);
2301 /* Double precision floating point helpers */
2302 static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
2304 /* XXX: TODO: test special values (NaN, infinites, ...) */
2305 return _do_efdtstlt(op1, op2);
2308 static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
2310 /* XXX: TODO: test special values (NaN, infinites, ...) */
2311 return _do_efdtstgt(op1, op2);
2314 static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
2316 /* XXX: TODO: test special values (NaN, infinites, ...) */
2317 return _do_efdtsteq(op1, op2);
2320 void do_efdcmplt (void)
2322 T0 = _do_efdcmplt(T0_64, T1_64);
2325 void do_efdcmpgt (void)
2327 T0 = _do_efdcmpgt(T0_64, T1_64);
2330 void do_efdcmpeq (void)
2332 T0 = _do_efdcmpeq(T0_64, T1_64);
2335 /* Double precision floating-point conversion to/from integer */
2336 static always_inline uint64_t _do_efdcfsi (int64_t val)
2343 u.f = int64_to_float64(val, &env->spe_status);
2348 static always_inline uint64_t _do_efdcfui (uint64_t val)
2355 u.f = uint64_to_float64(val, &env->spe_status);
2360 static always_inline int64_t _do_efdctsi (uint64_t val)
2368 /* NaN are not treated the same way IEEE 754 does */
2369 if (unlikely(isnan(u.f)))
2372 return float64_to_int64(u.f, &env->spe_status);
2375 static always_inline uint64_t _do_efdctui (uint64_t val)
2383 /* NaN are not treated the same way IEEE 754 does */
2384 if (unlikely(isnan(u.f)))
2387 return float64_to_uint64(u.f, &env->spe_status);
2390 static always_inline int64_t _do_efdctsiz (uint64_t val)
2398 /* NaN are not treated the same way IEEE 754 does */
2399 if (unlikely(isnan(u.f)))
2402 return float64_to_int64_round_to_zero(u.f, &env->spe_status);
2405 static always_inline uint64_t _do_efdctuiz (uint64_t val)
2413 /* NaN are not treated the same way IEEE 754 does */
2414 if (unlikely(isnan(u.f)))
2417 return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
2420 void do_efdcfsi (void)
2422 T0_64 = _do_efdcfsi(T0_64);
2425 void do_efdcfui (void)
2427 T0_64 = _do_efdcfui(T0_64);
2430 void do_efdctsi (void)
2432 T0_64 = _do_efdctsi(T0_64);
2435 void do_efdctui (void)
2437 T0_64 = _do_efdctui(T0_64);
2440 void do_efdctsiz (void)
2442 T0_64 = _do_efdctsiz(T0_64);
2445 void do_efdctuiz (void)
2447 T0_64 = _do_efdctuiz(T0_64);
2450 /* Double precision floating-point conversion to/from fractional */
2451 static always_inline uint64_t _do_efdcfsf (int64_t val)
2459 u.f = int32_to_float64(val, &env->spe_status);
2460 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2461 u.f = float64_div(u.f, tmp, &env->spe_status);
2466 static always_inline uint64_t _do_efdcfuf (uint64_t val)
2474 u.f = uint32_to_float64(val, &env->spe_status);
2475 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2476 u.f = float64_div(u.f, tmp, &env->spe_status);
2481 static always_inline int64_t _do_efdctsf (uint64_t val)
2490 /* NaN are not treated the same way IEEE 754 does */
2491 if (unlikely(isnan(u.f)))
2493 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2494 u.f = float64_mul(u.f, tmp, &env->spe_status);
2496 return float64_to_int32(u.f, &env->spe_status);
2499 static always_inline uint64_t _do_efdctuf (uint64_t val)
2508 /* NaN are not treated the same way IEEE 754 does */
2509 if (unlikely(isnan(u.f)))
2511 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2512 u.f = float64_mul(u.f, tmp, &env->spe_status);
2514 return float64_to_uint32(u.f, &env->spe_status);
2517 static always_inline int64_t _do_efdctsfz (uint64_t val)
2526 /* NaN are not treated the same way IEEE 754 does */
2527 if (unlikely(isnan(u.f)))
2529 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2530 u.f = float64_mul(u.f, tmp, &env->spe_status);
2532 return float64_to_int32_round_to_zero(u.f, &env->spe_status);
2535 static always_inline uint64_t _do_efdctufz (uint64_t val)
2544 /* NaN are not treated the same way IEEE 754 does */
2545 if (unlikely(isnan(u.f)))
2547 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2548 u.f = float64_mul(u.f, tmp, &env->spe_status);
2550 return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
2553 void do_efdcfsf (void)
2555 T0_64 = _do_efdcfsf(T0_64);
2558 void do_efdcfuf (void)
2560 T0_64 = _do_efdcfuf(T0_64);
2563 void do_efdctsf (void)
2565 T0_64 = _do_efdctsf(T0_64);
2568 void do_efdctuf (void)
2570 T0_64 = _do_efdctuf(T0_64);
2573 void do_efdctsfz (void)
2575 T0_64 = _do_efdctsfz(T0_64);
2578 void do_efdctufz (void)
2580 T0_64 = _do_efdctufz(T0_64);
2583 /* Floating point conversion between single and double precision */
2584 static always_inline uint32_t _do_efscfd (uint64_t val)
2596 u2.f = float64_to_float32(u1.f, &env->spe_status);
2601 static always_inline uint64_t _do_efdcfs (uint32_t val)
2613 u2.f = float32_to_float64(u1.f, &env->spe_status);
2618 void do_efscfd (void)
2620 T0_64 = _do_efscfd(T0_64);
2623 void do_efdcfs (void)
2625 T0_64 = _do_efdcfs(T0_64);
2628 /* Single precision fixed-point vector arithmetic */
2644 /* Single-precision floating-point comparisons */
2645 static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2647 /* XXX: TODO: test special values (NaN, infinites, ...) */
2648 return _do_efststlt(op1, op2);
2651 static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2653 /* XXX: TODO: test special values (NaN, infinites, ...) */
2654 return _do_efststgt(op1, op2);
2657 static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2659 /* XXX: TODO: test special values (NaN, infinites, ...) */
2660 return _do_efststeq(op1, op2);
2663 void do_efscmplt (void)
2665 T0 = _do_efscmplt(T0_64, T1_64);
2668 void do_efscmpgt (void)
2670 T0 = _do_efscmpgt(T0_64, T1_64);
2673 void do_efscmpeq (void)
2675 T0 = _do_efscmpeq(T0_64, T1_64);
2678 /* Single-precision floating-point vector comparisons */
2680 DO_SPE_CMP(fscmplt);
2682 DO_SPE_CMP(fscmpgt);
2684 DO_SPE_CMP(fscmpeq);
2686 DO_SPE_CMP(fststlt);
2688 DO_SPE_CMP(fststgt);
2690 DO_SPE_CMP(fststeq);
2692 /* Single-precision floating-point vector conversions */
2706 DO_SPE_OP1(fsctsiz);
2708 DO_SPE_OP1(fsctuiz);
2713 #endif /* defined(TARGET_PPCEMB) */
2715 /*****************************************************************************/
2716 /* Softmmu support */
2717 #if !defined (CONFIG_USER_ONLY)
2719 #define MMUSUFFIX _mmu
2721 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
2723 # define GETPC() (__builtin_return_address(0))
2727 #include "softmmu_template.h"
2730 #include "softmmu_template.h"
2733 #include "softmmu_template.h"
2736 #include "softmmu_template.h"
2738 /* try to fill the TLB and return an exception if error. If retaddr is
2739 NULL, it means that the function was called in C code (i.e. not
2740 from generated code or from helper.c) */
2741 /* XXX: fix it to restore all registers */
2742 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2744 TranslationBlock *tb;
2745 CPUState *saved_env;
2746 target_phys_addr_t pc;
2749 /* XXX: hack to restore env in all cases, even if not called from
2752 env = cpu_single_env;
2753 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2754 if (unlikely(ret != 0)) {
2755 if (likely(retaddr)) {
2756 /* now we have a real cpu fault */
2757 pc = (target_phys_addr_t)(unsigned long)retaddr;
2758 tb = tb_find_pc(pc);
2760 /* the PC is inside the translated code. It means that we have
2761 a virtual CPU fault */
2762 cpu_restore_state(tb, env, pc, NULL);
2765 do_raise_exception_err(env->exception_index, env->error_code);
2770 /* Software driven TLBs management */
2771 /* PowerPC 602/603 software TLB load instructions helpers */
2772 void do_load_6xx_tlb (int is_code)
2774 target_ulong RPN, CMP, EPN;
2777 RPN = env->spr[SPR_RPA];
2779 CMP = env->spr[SPR_ICMP];
2780 EPN = env->spr[SPR_IMISS];
2782 CMP = env->spr[SPR_DCMP];
2783 EPN = env->spr[SPR_DMISS];
2785 way = (env->spr[SPR_SRR1] >> 17) & 1;
2786 #if defined (DEBUG_SOFTWARE_TLB)
2787 if (loglevel != 0) {
2788 fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2789 __func__, (unsigned long)T0, (unsigned long)EPN,
2790 (unsigned long)CMP, (unsigned long)RPN, way);
2793 /* Store this TLB */
2794 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2795 way, is_code, CMP, RPN);
2798 void do_load_74xx_tlb (int is_code)
2800 target_ulong RPN, CMP, EPN;
2803 RPN = env->spr[SPR_PTELO];
2804 CMP = env->spr[SPR_PTEHI];
2805 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2806 way = env->spr[SPR_TLBMISS] & 0x3;
2807 #if defined (DEBUG_SOFTWARE_TLB)
2808 if (loglevel != 0) {
2809 fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2810 __func__, (unsigned long)T0, (unsigned long)EPN,
2811 (unsigned long)CMP, (unsigned long)RPN, way);
2814 /* Store this TLB */
2815 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2816 way, is_code, CMP, RPN);
2819 static always_inline target_ulong booke_tlb_to_page_size (int size)
2821 return 1024 << (2 * size);
2824 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2828 switch (page_size) {
2862 #if defined (TARGET_PPC64)
2863 case 0x000100000000ULL:
2866 case 0x000400000000ULL:
2869 case 0x001000000000ULL:
2872 case 0x004000000000ULL:
2875 case 0x010000000000ULL:
2887 /* Helpers for 4xx TLB management */
2888 void do_4xx_tlbre_lo (void)
2894 tlb = &env->tlb[T0].tlbe;
2896 if (tlb->prot & PAGE_VALID)
2898 size = booke_page_size_to_tlb(tlb->size);
2899 if (size < 0 || size > 0x7)
2902 env->spr[SPR_40x_PID] = tlb->PID;
2905 void do_4xx_tlbre_hi (void)
2910 tlb = &env->tlb[T0].tlbe;
2912 if (tlb->prot & PAGE_EXEC)
2914 if (tlb->prot & PAGE_WRITE)
2918 void do_4xx_tlbwe_hi (void)
2921 target_ulong page, end;
2923 #if defined (DEBUG_SOFTWARE_TLB)
2924 if (loglevel != 0) {
2925 fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
2929 tlb = &env->tlb[T0].tlbe;
2930 /* Invalidate previous TLB (if it's valid) */
2931 if (tlb->prot & PAGE_VALID) {
2932 end = tlb->EPN + tlb->size;
2933 #if defined (DEBUG_SOFTWARE_TLB)
2934 if (loglevel != 0) {
2935 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2936 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2939 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2940 tlb_flush_page(env, page);
2942 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2943 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2944 * If this ever occurs, one should use the ppcemb target instead
2945 * of the ppc or ppc64 one
2947 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2948 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2949 "are not supported (%d)\n",
2950 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2952 tlb->EPN = T1 & ~(tlb->size - 1);
2954 tlb->prot |= PAGE_VALID;
2956 tlb->prot &= ~PAGE_VALID;
2958 /* XXX: TO BE FIXED */
2959 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2961 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2962 tlb->attr = T1 & 0xFF;
2963 #if defined (DEBUG_SOFTWARE_TLB)
2964 if (loglevel != 0) {
2965 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2966 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2967 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2968 tlb->prot & PAGE_READ ? 'r' : '-',
2969 tlb->prot & PAGE_WRITE ? 'w' : '-',
2970 tlb->prot & PAGE_EXEC ? 'x' : '-',
2971 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2974 /* Invalidate new TLB (if valid) */
2975 if (tlb->prot & PAGE_VALID) {
2976 end = tlb->EPN + tlb->size;
2977 #if defined (DEBUG_SOFTWARE_TLB)
2978 if (loglevel != 0) {
2979 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2980 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2983 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2984 tlb_flush_page(env, page);
2988 void do_4xx_tlbwe_lo (void)
2992 #if defined (DEBUG_SOFTWARE_TLB)
2993 if (loglevel != 0) {
2994 fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
2998 tlb = &env->tlb[T0].tlbe;
2999 tlb->RPN = T1 & 0xFFFFFC00;
3000 tlb->prot = PAGE_READ;
3002 tlb->prot |= PAGE_EXEC;
3004 tlb->prot |= PAGE_WRITE;
3005 #if defined (DEBUG_SOFTWARE_TLB)
3006 if (loglevel != 0) {
3007 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3008 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3009 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
3010 tlb->prot & PAGE_READ ? 'r' : '-',
3011 tlb->prot & PAGE_WRITE ? 'w' : '-',
3012 tlb->prot & PAGE_EXEC ? 'x' : '-',
3013 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3018 /* PowerPC 440 TLB management */
3019 void do_440_tlbwe (int word)
3022 target_ulong EPN, RPN, size;
3025 #if defined (DEBUG_SOFTWARE_TLB)
3026 if (loglevel != 0) {
3027 fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n",
3028 __func__, word, T0, T1);
3033 tlb = &env->tlb[T0].tlbe;
3036 /* Just here to please gcc */
3038 EPN = T1 & 0xFFFFFC00;
3039 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3042 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
3043 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3047 tlb->attr |= (T1 >> 8) & 1;
3049 tlb->prot |= PAGE_VALID;
3051 if (tlb->prot & PAGE_VALID) {
3052 tlb->prot &= ~PAGE_VALID;
3056 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3061 RPN = T1 & 0xFFFFFC0F;
3062 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3067 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
3068 tlb->prot = tlb->prot & PAGE_VALID;
3070 tlb->prot |= PAGE_READ << 4;
3072 tlb->prot |= PAGE_WRITE << 4;
3074 tlb->prot |= PAGE_EXEC << 4;
3076 tlb->prot |= PAGE_READ;
3078 tlb->prot |= PAGE_WRITE;
3080 tlb->prot |= PAGE_EXEC;
3085 void do_440_tlbre (int word)
3091 tlb = &env->tlb[T0].tlbe;
3094 /* Just here to please gcc */
3097 size = booke_page_size_to_tlb(tlb->size);
3098 if (size < 0 || size > 0xF)
3101 if (tlb->attr & 0x1)
3103 if (tlb->prot & PAGE_VALID)
3105 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3106 env->spr[SPR_440_MMUCR] |= tlb->PID;
3112 T0 = tlb->attr & ~0x1;
3113 if (tlb->prot & (PAGE_READ << 4))
3115 if (tlb->prot & (PAGE_WRITE << 4))
3117 if (tlb->prot & (PAGE_EXEC << 4))
3119 if (tlb->prot & PAGE_READ)
3121 if (tlb->prot & PAGE_WRITE)
3123 if (tlb->prot & PAGE_EXEC)
3128 #endif /* !CONFIG_USER_ONLY */