2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #if defined(CONFIG_USER_ONLY)
24 #define MEMSUFFIX _raw
25 #include "op_helper_mem.h"
27 #define MEMSUFFIX _user
28 #include "op_helper_mem.h"
29 #define MEMSUFFIX _kernel
30 #include "op_helper_mem.h"
33 /*****************************************************************************/
34 /* Exceptions processing helpers */
35 void do_queue_exception_err (uint32_t exception, int error_code)
37 /* Queue real PPC exceptions */
38 if (exception < EXCP_PPC_MAX) {
39 env->exceptions |= 1 << exception;
40 env->errors[exception] = error_code;
42 /* Preserve compatibility with qemu core */
44 env->exception_index = exception;
45 env->error_code = error_code;
49 void do_queue_exception (uint32_t exception)
51 do_queue_exception_err(exception, 0);
54 void do_check_exception_state (void)
56 if ((env->exceptions & 1) == 1 || check_exception_state(env)) {
57 env->exceptions &= ~1;
62 /*****************************************************************************/
63 /* Helpers for "fat" micro operations */
64 /* Special registers load and store */
65 void do_load_cr (void)
67 T0 = (env->crf[0] << 28) |
77 void do_store_cr (uint32_t mask)
81 for (i = 0, sh = 7; i < 8; i++, sh --) {
83 env->crf[i] = (T0 >> (sh * 4)) & 0xF;
87 void do_load_xer (void)
89 T0 = (xer_so << XER_SO) |
95 void do_store_xer (void)
97 xer_so = (T0 >> XER_SO) & 0x01;
98 xer_ov = (T0 >> XER_OV) & 0x01;
99 xer_ca = (T0 >> XER_CA) & 0x01;
100 xer_bc = (T0 >> XER_BC) & 0x1f;
103 void do_load_msr (void)
105 T0 = (msr_pow << MSR_POW) |
106 (msr_ile << MSR_ILE) |
111 (msr_fe0 << MSR_FE0) |
114 (msr_fe1 << MSR_FE1) |
122 void do_store_msr (void)
124 if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
125 ((T0 >> MSR_DR) & 0x01) != msr_dr ||
126 ((T0 >> MSR_PR) & 0x01) != msr_pr) {
127 /* Flush all tlb when changing translation mode or privilege level */
131 if ((T0 >> MSR_IP) & 0x01) {
132 printf("Halting CPU. Stop emulation\n");
133 do_queue_exception(EXCP_HLT);
137 msr_pow = (T0 >> MSR_POW) & 0x03;
138 msr_ile = (T0 >> MSR_ILE) & 0x01;
139 msr_ee = (T0 >> MSR_EE) & 0x01;
140 msr_pr = (T0 >> MSR_PR) & 0x01;
141 msr_fp = (T0 >> MSR_FP) & 0x01;
142 msr_me = (T0 >> MSR_ME) & 0x01;
143 msr_fe0 = (T0 >> MSR_FE0) & 0x01;
144 msr_se = (T0 >> MSR_SE) & 0x01;
145 msr_be = (T0 >> MSR_BE) & 0x01;
146 msr_fe1 = (T0 >> MSR_FE1) & 0x01;
147 msr_ip = (T0 >> MSR_IP) & 0x01;
148 msr_ir = (T0 >> MSR_IR) & 0x01;
149 msr_dr = (T0 >> MSR_DR) & 0x01;
150 msr_ri = (T0 >> MSR_RI) & 0x01;
151 msr_le = (T0 >> MSR_LE) & 0x01;
154 /* shift right arithmetic helper */
161 ret = (-1) * (T0 >> 31);
165 ret = (int32_t)T0 >> (T1 & 0x1f);
166 if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
172 /* Floating point operations helpers */
173 void do_load_fpscr (void)
175 /* The 32 MSB of the target fpr are undefined.
188 for (i = 0; i < 8; i++)
189 u.s.u[1] |= env->fpscr[i] << (4 * i);
193 void do_store_fpscr (uint32_t mask)
196 * We use only the 32 LSB of the incoming fpr
208 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9);
209 for (i = 1; i < 7; i++) {
210 if (mask & (1 << (7 - i)))
211 env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF;
213 /* TODO: update FEX & VX */
214 /* Set rounding mode */
215 switch (env->fpscr[0] & 0x3) {
217 /* Best approximation (round to nearest) */
218 fesetround(FE_TONEAREST);
221 /* Smaller magnitude (round toward zero) */
222 fesetround(FE_TOWARDZERO);
225 /* Round toward +infinite */
226 fesetround(FE_UPWARD);
229 /* Round toward -infinite */
230 fesetround(FE_DOWNWARD);
242 if (FT0 > (double)0x7FFFFFFF)
243 p->i = 0x7FFFFFFFULL << 32;
244 else if (FT0 < -(double)0x80000000)
245 p->i = 0x80000000ULL << 32;
248 p->i |= (uint32_t)FT0;
252 void do_fctiwz (void)
258 int cround = fegetround();
260 fesetround(FE_TOWARDZERO);
261 if (FT0 > (double)0x7FFFFFFF)
262 p->i = 0x7FFFFFFFULL << 32;
263 else if (FT0 < -(double)0x80000000)
264 p->i = 0x80000000ULL << 32;
267 p->i |= (uint32_t)FT0;
277 void do_fsqrts (void)
279 FT0 = (float)sqrt((float)FT0);
287 void do_fsqrte (void)
289 FT0 = 1.0 / sqrt(FT0);
302 env->fpscr[4] &= ~0x1;
303 if (isnan(FT0) || isnan(FT1)) {
305 env->fpscr[4] |= 0x1;
306 env->fpscr[6] |= 0x1;
307 } else if (FT0 < FT1) {
309 } else if (FT0 > FT1) {
319 env->fpscr[4] &= ~0x1;
320 if (isnan(FT0) || isnan(FT1)) {
322 env->fpscr[4] |= 0x1;
323 /* I don't know how to test "quiet" nan... */
324 if (0 /* || ! quiet_nan(...) */) {
325 env->fpscr[6] |= 0x1;
326 if (!(env->fpscr[1] & 0x8))
327 env->fpscr[4] |= 0x8;
329 env->fpscr[4] |= 0x8;
331 } else if (FT0 < FT1) {
333 } else if (FT0 > FT1) {
351 /* Instruction cache invalidation helper */
352 #define ICACHE_LINE_SIZE 32
356 /* Invalidate one cache line */
357 T0 &= ~(ICACHE_LINE_SIZE - 1);
358 tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE);
361 /* TLB invalidation helpers */
369 tlb_flush_page(env, T0);
372 /*****************************************************************************/
373 /* Special helpers for debug */
377 printf("Return from interrupt\n");
378 printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x\n",
379 env->nip, env->lr, env->ctr,
380 (msr_pow << MSR_POW) | (msr_ile << MSR_ILE) | (msr_ee << MSR_EE) |
381 (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_me << MSR_ME) |
382 (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) | (msr_be << MSR_BE) |
383 (msr_fe1 << MSR_FE1) | (msr_ip << MSR_IP) | (msr_ir << MSR_IR) |
384 (msr_dr << MSR_DR) | (msr_ri << MSR_RI) | (msr_le << MSR_LE));
387 for (i = 0; i < 32; i++) {
389 printf("GPR%02d:", i);
390 printf(" %08x", env->gpr[i]);
395 for (i = 0; i < 8; i++)
396 printf("%01x", env->crf[i]);
398 for (i = 0; i < 8; i++) {
400 if (env->crf[i] & 0x08)
402 else if (env->crf[i] & 0x04)
404 else if (env->crf[i] & 0x02)
406 printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
410 printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
411 printf("SRR0 0x%08x SRR1 0x%08x\n", env->spr[SRR0], env->spr[SRR1]);
415 void dump_store_sr (int srnum)
418 printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
422 static void _dump_store_bat (char ID, int ul, int nr)
424 printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
425 ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
428 void dump_store_ibat (int ul, int nr)
430 _dump_store_bat('I', ul, nr);
433 void dump_store_dbat (int ul, int nr)
435 _dump_store_bat('D', ul, nr);
438 void dump_store_tb (int ul)
440 printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
443 void dump_update_tb(uint32_t param)
446 printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);