2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #if defined (USE_OPEN_FIRMWARE)
29 //#define DEBUG_EXCEPTIONS
31 extern FILE *logfile, *stderr;
35 void cpu_loop_exit(void)
37 longjmp(env->jmp_env, 1);
40 void do_process_exceptions (void)
45 int check_exception_state (CPUState *env)
49 /* Process PPC exceptions */
50 for (i = 1; i < EXCP_PPC_MAX; i++) {
51 if (env->exceptions & (1 << i)) {
59 if (env->errors[EXCP_PROGRAM] == EXCP_FP &&
60 msr_fe0 == 0 && msr_fe1 == 0)
66 env->exception_index = i;
67 env->error_code = env->errors[i];
75 /*****************************************************************************/
76 /* PPC MMU emulation */
77 /* Perform BAT hit & translation */
78 static int get_bat (CPUState *env, uint32_t *real, int *prot,
79 uint32_t virtual, int rw, int type)
81 uint32_t *BATlt, *BATut, *BATu, *BATl;
82 uint32_t base, BEPIl, BEPIu, bl;
86 #if defined (DEBUG_BATS)
88 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
89 type == ACCESS_CODE ? 'I' : 'D', virtual);
91 printf("%s: %cBAT v 0x%08x\n", __func__,
92 type == ACCESS_CODE ? 'I' : 'D', virtual);
100 BATlt = env->DBAT[1];
101 BATut = env->DBAT[0];
104 #if defined (DEBUG_BATS)
106 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
107 type == ACCESS_CODE ? 'I' : 'D', virtual);
109 printf("%s...: %cBAT v 0x%08x\n", __func__,
110 type == ACCESS_CODE ? 'I' : 'D', virtual);
112 base = virtual & 0xFFFC0000;
113 for (i = 0; i < 4; i++) {
116 BEPIu = *BATu & 0xF0000000;
117 BEPIl = *BATu & 0x0FFE0000;
118 bl = (*BATu & 0x00001FFC) << 15;
119 #if defined (DEBUG_BATS)
121 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
122 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
125 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
126 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
130 if ((virtual & 0xF0000000) == BEPIu &&
131 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
133 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
134 (msr_pr == 1 && (*BATu & 0x00000001))) {
135 /* Get physical address */
136 *real = (*BATl & 0xF0000000) |
137 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
138 (virtual & 0x0001FFFF);
139 if (*BATl & 0x00000001)
141 if (*BATl & 0x00000002)
142 *prot = PROT_WRITE | PROT_READ;
143 #if defined (DEBUG_BATS)
145 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
146 i, *real, *prot & PROT_READ ? 'R' : '-',
147 *prot & PROT_WRITE ? 'W' : '-');
149 printf("BAT %d match: 0x%08x => 0x%08x prot=%c%c\n",
150 i, virtual, *real, *prot & PROT_READ ? 'R' : '-',
151 *prot & PROT_WRITE ? 'W' : '-');
160 #if defined (DEBUG_BATS)
161 printf("no BAT match for 0x%08x:\n", virtual);
162 for (i = 0; i < 4; i++) {
165 BEPIu = *BATu & 0xF0000000;
166 BEPIl = *BATu & 0x0FFE0000;
167 bl = (*BATu & 0x00001FFC) << 15;
168 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
169 "0x%08x 0x%08x 0x%08x\n",
170 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
171 *BATu, *BATl, BEPIu, BEPIl, bl);
174 env->spr[DAR] = virtual;
180 /* PTE table lookup */
181 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
182 int h, int key, int rw)
184 uint32_t pte0, pte1, keep = 0;
185 int i, good = -1, store = 0;
186 int ret = -1; /* No entry found */
188 for (i = 0; i < 8; i++) {
189 pte0 = ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8)));
190 pte1 = ldl_raw((void *)((uint32_t)phys_ram_base + base + (i * 8) + 4));
191 #if defined (DEBUG_MMU)
192 printf("Load pte from 0x%08x => 0x%08x 0x%08x\n", base + (i * 8),
195 /* Check validity and table match */
196 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
197 #if defined (DEBUG_MMU)
198 printf("PTE is valid and table matches... compare 0x%08x:%08x\n",
199 pte0 & 0x7FFFFFBF, va);
201 /* Check vsid & api */
202 if ((pte0 & 0x7FFFFFBF) == va) {
203 #if defined (DEBUG_MMU)
204 printf("PTE match !\n");
210 /* All matches should have equal RPN, WIMG & PP */
211 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
212 printf("Bad RPN/WIMG/PP\n");
216 /* Check access rights */
219 if ((pte1 & 0x00000003) != 0x3)
222 switch (pte1 & 0x00000003) {
231 *prot = PROT_READ | PROT_WRITE;
235 if ((rw == 0 && *prot != 0) ||
236 (rw == 1 && (*prot & PROT_WRITE))) {
237 #if defined (DEBUG_MMU)
238 printf("PTE access granted !\n");
243 } else if (ret == -1) {
244 ret = -2; /* Access right violation */
245 #if defined (DEBUG_MMU)
246 printf("PTE access rejected\n");
253 *RPN = keep & 0xFFFFF000;
254 #if defined (DEBUG_MMU)
255 printf("found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
258 /* Update page flags */
259 if (!(keep & 0x00000100)) {
264 if (!(keep & 0x00000080)) {
270 stl_raw((void *)(base + (good * 2) + 1), keep);
276 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
278 return (sdr1 & 0xFFFF0000) | (hash & mask);
281 /* Perform segment based translation */
282 static int get_segment (CPUState *env, uint32_t *real, int *prot,
283 uint32_t virtual, int rw, int type)
285 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
291 sr = env->sr[virtual >> 28];
292 #if defined (DEBUG_MMU)
293 printf("Check segment v=0x%08x %d 0x%08x nip=0x%08x lr=0x%08x ir=%d dr=%d "
294 "pr=%d t=%d\n", virtual, virtual >> 28, sr, env->nip,
295 env->lr, msr_ir, msr_dr, msr_pr, type);
297 key = ((sr & 0x20000000) && msr_pr == 1) ||
298 ((sr & 0x40000000) && msr_pr == 0) ? 1 : 0;
299 if ((sr & 0x80000000) == 0) {
300 #if defined (DEBUG_MMU)
301 printf("pte segment: key=%d n=0x%08x\n", key, sr & 0x10000000);
303 /* Check if instruction fetch is allowed, if needed */
304 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
305 /* Page address translation */
306 vsid = sr & 0x00FFFFFF;
307 pgidx = (virtual >> 12) & 0xFFFF;
308 sdr = env->spr[SDR1];
309 hash = ((vsid ^ pgidx) & 0x07FFFF) << 6;
310 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
311 pg_addr = get_pgaddr(sdr, hash, mask);
312 ptem = (vsid << 7) | (pgidx >> 10);
313 #if defined (DEBUG_MMU)
314 printf("0 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%07x "
315 "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
317 /* Primary table lookup */
318 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
320 /* Secondary table lookup */
321 hash = (~hash) & 0x01FFFFC0;
322 pg_addr = get_pgaddr(sdr, hash, mask);
323 #if defined (DEBUG_MMU)
324 printf("1 sdr1=0x%08x vsid=0x%06x api=0x%04x hash=0x%05x "
325 "pg_addr=0x%08x\n", sdr, vsid, pgidx, hash, pg_addr);
327 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
332 *real |= (virtual & 0x00000FFF);
333 if (ret == -2 && type == ACCESS_CODE && (sr & 0x10000000))
336 #if defined (DEBUG_MMU)
337 printf("No access allowed\n");
341 #if defined (DEBUG_MMU)
342 printf("direct store...\n");
344 /* Direct-store segment : absolutely *BUGGY* for now */
347 /* Integer load/store : only access allowed */
350 /* No code fetch is allowed in direct-store areas */
353 /* Floating point load/store */
356 /* lwarx, ldarx or srwcx. */
359 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
360 /* Should make the instruction do no-op.
361 * As it already do no-op, it's quite easy :-)
370 fprintf(logfile, "ERROR: instruction should not need "
371 "address translation\n");
373 printf("ERROR: instruction should not need "
374 "address translation\n");
377 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
388 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
389 uint32_t address, int rw, int access_type)
394 fprintf(logfile, "%s\n", __func__);
396 if ((access_type == ACCESS_CODE && msr_ir == 0) || msr_dr == 0) {
397 /* No address translation */
399 *prot = PROT_READ | PROT_WRITE;
402 /* Try to find a BAT */
403 ret = get_bat(env, physical, prot, address, rw, access_type);
405 /* We didn't match any BAT entry */
406 ret = get_segment(env, physical, prot, address, rw, access_type);
413 #if defined(CONFIG_USER_ONLY)
414 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
419 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
424 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
430 #if !defined(CONFIG_USER_ONLY)
432 #define MMUSUFFIX _mmu
433 #define GETPC() (__builtin_return_address(0))
436 #include "softmmu_template.h"
439 #include "softmmu_template.h"
442 #include "softmmu_template.h"
445 #include "softmmu_template.h"
447 /* try to fill the TLB and return an exception if error. If retaddr is
448 NULL, it means that the function was called in C code (i.e. not
449 from generated code or from helper.c) */
450 /* XXX: fix it to restore all registers */
451 void tlb_fill(unsigned long addr, int is_write, int flags, void *retaddr)
453 TranslationBlock *tb;
458 /* XXX: hack to restore env in all cases, even if not called from
461 env = cpu_single_env;
462 is_user = flags & 0x01;
464 unsigned long tlb_addrr, tlb_addrw;
466 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
467 tlb_addrr = env->tlb_read[is_user][index].address;
468 tlb_addrw = env->tlb_write[is_user][index].address;
470 printf("%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
471 "(0x%08lx 0x%08lx)\n", __func__, env,
472 &env->tlb_read[is_user][index], index, addr,
473 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
474 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
477 ret = cpu_handle_mmu_fault(env, addr, is_write, flags, 1);
480 /* now we have a real cpu fault */
481 pc = (unsigned long)retaddr;
484 /* the PC is inside the translated code. It means that we have
485 a virtual CPU fault */
486 cpu_restore_state(tb, env, pc, NULL);
489 do_queue_exception_err(env->exception_index, env->error_code);
490 do_process_exceptions();
493 unsigned long tlb_addrr, tlb_addrw;
495 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
496 tlb_addrr = env->tlb_read[is_user][index].address;
497 tlb_addrw = env->tlb_write[is_user][index].address;
499 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
500 "(0x%08lx 0x%08lx)\n", __func__, env,
501 &env->tlb_read[is_user][index], index, addr,
502 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
503 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
509 void cpu_ppc_init_mmu(CPUPPCState *env)
511 /* Nothing to do: all translation are disabled */
515 /* Perform address translation */
516 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
517 int flags, int is_softmmu)
521 int exception = 0, error_code = 0;
522 int is_user, access_type;
525 // printf("%s 0\n", __func__);
526 is_user = flags & 0x01;
527 access_type = env->access_type;
528 if (env->user_mode_only) {
529 /* user mode only emulation */
533 ret = get_physical_address(env, &physical, &prot,
534 address, rw, access_type);
536 ret = tlb_set_page(env, address, physical, prot, is_user, is_softmmu);
537 } else if (ret < 0) {
539 #if defined (DEBUG_MMU)
540 printf("%s 5\n", __func__);
541 printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x TBL=0x%08x\n",
542 env->nip, env->lr, env->ctr, /*msr*/0, env->tb[0]);
545 for (i = 0; i < 32; i++) {
547 printf("GPR%02d:", i);
548 printf(" %08x", env->gpr[i]);
553 for (i = 0; i < 8; i++)
554 printf("%01x", env->crf[i]);
556 for (i = 0; i < 8; i++) {
558 if (env->crf[i] & 0x08)
560 else if (env->crf[i] & 0x04)
562 else if (env->crf[i] & 0x02)
564 printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
568 printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
569 printf("SRR0 0x%08x SRR1 0x%08x\n", env->spr[SRR0], env->spr[SRR1]);
571 if (access_type == ACCESS_CODE) {
572 exception = EXCP_ISI;
575 /* No matches in page tables */
576 error_code = EXCP_ISI_TRANSLATE;
579 /* Access rights violation */
580 error_code = EXCP_ISI_PROT;
583 error_code = EXCP_ISI_NOEXEC;
586 /* Direct store exception */
587 /* No code fetch is allowed in direct-store areas */
588 exception = EXCP_ISI;
589 error_code = EXCP_ISI_NOEXEC;
593 exception = EXCP_DSI;
596 /* No matches in page tables */
597 error_code = EXCP_DSI_TRANSLATE;
600 /* Access rights violation */
601 error_code = EXCP_DSI_PROT;
604 /* Direct store exception */
605 switch (access_type) {
607 /* Floating point load/store */
608 exception = EXCP_ALIGN;
609 error_code = EXCP_ALIGN_FP;
612 /* lwarx, ldarx or srwcx. */
613 exception = EXCP_DSI;
614 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
616 error_code |= EXCP_DSI_STORE;
620 exception = EXCP_DSI;
621 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | EXCP_ECXW;
624 exception = EXCP_PROGRAM;
625 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
630 error_code |= EXCP_DSI_STORE;
631 /* Should find a better solution:
632 * this will be invalid for some exception if more than one
633 * exception occurs for one instruction
636 if (error_code & EXCP_DSI_DIRECT) {
637 env->spr[DSISR] |= 0x80000000;
638 if (access_type == ACCESS_EXT ||
639 access_type == ACCESS_RES)
640 env->spr[DSISR] |= 0x04000000;
642 if ((error_code & 0xF) == EXCP_DSI_TRANSLATE)
643 env->spr[DSISR] |= 0x40000000;
644 if (error_code & EXCP_DSI_PROT)
645 env->spr[DSISR] |= 0x08000000;
646 if (error_code & EXCP_DSI_STORE)
647 env->spr[DSISR] |= 0x02000000;
648 if ((error_code & 0xF) == EXCP_DSI_DABR)
649 env->spr[DSISR] |= 0x00400000;
650 if (access_type == ACCESS_EXT)
651 env->spr[DSISR] |= 0x00100000;
654 printf("%s: set exception to %d %02x\n",
655 __func__, exception, error_code);
657 env->exception_index = exception;
658 env->error_code = error_code;
659 /* Store fault address */
660 env->spr[DAR] = address;
667 uint32_t _load_xer (void)
669 return (xer_so << XER_SO) |
675 void _store_xer (uint32_t value)
677 xer_so = (value >> XER_SO) & 0x01;
678 xer_ov = (value >> XER_OV) & 0x01;
679 xer_ca = (value >> XER_CA) & 0x01;
680 xer_bc = (value >> XER_BC) & 0x1f;
683 uint32_t _load_msr (void)
685 return (msr_pow << MSR_POW) |
686 (msr_ile << MSR_ILE) |
691 (msr_fe0 << MSR_FE0) |
694 (msr_fe1 << MSR_FE1) |
702 void _store_msr (uint32_t value)
704 msr_pow = (value >> MSR_POW) & 0x03;
705 msr_ile = (value >> MSR_ILE) & 0x01;
706 msr_ee = (value >> MSR_EE) & 0x01;
707 msr_pr = (value >> MSR_PR) & 0x01;
708 msr_fp = (value >> MSR_FP) & 0x01;
709 msr_me = (value >> MSR_ME) & 0x01;
710 msr_fe0 = (value >> MSR_FE0) & 0x01;
711 msr_se = (value >> MSR_SE) & 0x01;
712 msr_be = (value >> MSR_BE) & 0x01;
713 msr_fe1 = (value >> MSR_FE1) & 0x01;
714 msr_ip = (value >> MSR_IP) & 0x01;
715 msr_ir = (value >> MSR_IR) & 0x01;
716 msr_dr = (value >> MSR_DR) & 0x01;
717 msr_ri = (value >> MSR_RI) & 0x01;
718 msr_le = (value >> MSR_LE) & 0x01;
721 void do_interrupt (CPUState *env)
723 #if defined (CONFIG_USER_ONLY)
724 env->exception_index |= 0x100;
727 int excp = env->exception_index;
729 /* Dequeue PPC exceptions */
730 if (excp < EXCP_PPC_MAX)
731 env->exceptions &= ~(1 << excp);
733 #if defined (DEBUG_EXCEPTIONS)
734 if (excp != EXCP_DECR && excp == EXCP_PROGRAM && excp < EXCP_PPC_MAX)
737 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
738 env->nip, excp << 8, env->error_code);
740 printf("Raise exception at 0x%08x => 0x%08x (%02x)\n",
741 env->nip, excp << 8, env->error_code);
743 printf("nip=0x%08x LR=0x%08x CTR=0x%08x MSR=0x%08x DECR=0x%08x\n",
744 env->nip, env->lr, env->ctr, msr, env->decr);
747 for (i = 0; i < 32; i++) {
749 printf("GPR%02d:", i);
750 printf(" %08x", env->gpr[i]);
755 for (i = 0; i < 8; i++)
756 printf("%01x", env->crf[i]);
758 for (i = 0; i < 8; i++) {
760 if (env->crf[i] & 0x08)
762 else if (env->crf[i] & 0x04)
764 else if (env->crf[i] & 0x02)
766 printf(" %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
770 printf("TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
771 printf("XER 0x%08x SRR0 0x%08x SRR1 0x%08x\n",
772 _load_xer(), env->spr[SRR0], env->spr[SRR1]);
775 /* Generate informations in save/restore registers */
778 #if defined (USE_OPEN_FIRMWARE)
779 env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
783 #if defined (USE_OPEN_FIRMWARE)
784 printf("RTAS call !\n");
785 env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
786 printf("RTAS call done\n");
791 #if defined (DEBUG_EXCEPTIONS)
792 printf("%s: escape EXCP_NONE\n", __func__);
799 case EXCP_MACHINE_CHECK:
801 printf("Machine check exception while not allowed !\n");
804 "Machine check exception while not allowed !\n");
811 /* Store exception cause */
812 /* data location address has been stored
813 * when the fault has been detected
817 /* Store exception cause */
818 if (env->error_code == EXCP_ISI_TRANSLATE)
820 else if (env->error_code == EXCP_ISI_NOEXEC ||
821 env->error_code == EXCP_ISI_GUARD)
828 #if defined (DEBUG_EXCEPTIONS)
830 fprintf(logfile, "Skipping hardware interrupt\n");
832 printf("Skipping hardware interrupt\n");
839 /* Store exception cause */
840 /* Get rS/rD and rA from faulting opcode */
842 (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
843 /* data location address has been stored
844 * when the fault has been detected
849 switch (env->error_code & ~0xF) {
851 if (msr_fe0 == 0 && msr_fe1 == 0) {
852 #if defined (DEBUG_EXCEPTIONS)
853 printf("Ignore floating point exception\n");
859 env->fpscr[7] |= 0x8;
860 /* Finally, update FEX */
861 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
862 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
863 env->fpscr[7] |= 0x4;
875 /* Should never occur */
885 do_queue_exception(EXCP_DECR);
890 #if defined (DEBUG_EXCEPTIONS)
891 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
892 env->gpr[0], env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
901 #if defined (DEBUG_EXCEPTIONS)
902 printf("%s: escape EXCP_MTMSR\n", __func__);
907 #if defined (DEBUG_EXCEPTIONS)
908 printf("%s: escape EXCP_BRANCH\n", __func__);
912 /* Restore user-mode state */
913 #if defined (DEBUG_EXCEPTIONS)
914 printf("%s: escape EXCP_RFI\n", __func__);
918 /* SRR0 is set to current instruction */
919 env->spr[SRR0] = (uint32_t)env->nip - 4;
922 /* SRR0 is set to next instruction */
923 env->spr[SRR0] = (uint32_t)env->nip;
926 env->spr[SRR1] = msr;
927 /* reload MSR with correct bits */
940 /* Jump to handler */
941 env->nip = excp << 8;
942 env->exception_index = EXCP_NONE;
943 /* Invalidate all TLB as we may have changed translation mode */
945 /* ensure that no TB jump will be modified as
946 the program flow was changed */