2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 //#define DEBUG_EXCEPTIONS
25 /* accurate but slower TLB flush in exceptions */
26 //#define ACCURATE_TLB_FLUSH
28 /*****************************************************************************/
29 /* PowerPC MMU emulation */
31 /* Perform BAT hit & translation */
32 static int get_bat (CPUState *env, uint32_t *real, int *prot,
33 uint32_t virtual, int rw, int type)
35 uint32_t *BATlt, *BATut, *BATu, *BATl;
36 uint32_t base, BEPIl, BEPIu, bl;
40 #if defined (DEBUG_BATS)
42 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
43 type == ACCESS_CODE ? 'I' : 'D', virtual);
56 #if defined (DEBUG_BATS)
58 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
59 type == ACCESS_CODE ? 'I' : 'D', virtual);
62 base = virtual & 0xFFFC0000;
63 for (i = 0; i < 4; i++) {
66 BEPIu = *BATu & 0xF0000000;
67 BEPIl = *BATu & 0x0FFE0000;
68 bl = (*BATu & 0x00001FFC) << 15;
69 #if defined (DEBUG_BATS)
71 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
72 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
76 if ((virtual & 0xF0000000) == BEPIu &&
77 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
79 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
80 (msr_pr == 1 && (*BATu & 0x00000001))) {
81 /* Get physical address */
82 *real = (*BATl & 0xF0000000) |
83 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
84 (virtual & 0x0001F000);
85 if (*BATl & 0x00000001)
87 if (*BATl & 0x00000002)
88 *prot = PAGE_WRITE | PAGE_READ;
89 #if defined (DEBUG_BATS)
91 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
92 i, *real, *prot & PAGE_READ ? 'R' : '-',
93 *prot & PAGE_WRITE ? 'W' : '-');
102 #if defined (DEBUG_BATS)
103 printf("no BAT match for 0x%08x:\n", virtual);
104 for (i = 0; i < 4; i++) {
107 BEPIu = *BATu & 0xF0000000;
108 BEPIl = *BATu & 0x0FFE0000;
109 bl = (*BATu & 0x00001FFC) << 15;
110 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
111 "0x%08x 0x%08x 0x%08x\n",
112 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
113 *BATu, *BATl, BEPIu, BEPIl, bl);
121 /* PTE table lookup */
122 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
123 int h, int key, int rw)
125 uint32_t pte0, pte1, keep = 0, access = 0;
126 int i, good = -1, store = 0;
127 int ret = -1; /* No entry found */
129 for (i = 0; i < 8; i++) {
130 pte0 = ldl_phys(base + (i * 8));
131 pte1 = ldl_phys(base + (i * 8) + 4);
132 #if defined (DEBUG_MMU)
134 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
135 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
136 pte0 >> 31, h, (pte0 >> 6) & 1, va);
139 /* Check validity and table match */
140 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
141 /* Check vsid & api */
142 if ((pte0 & 0x7FFFFFBF) == va) {
147 /* All matches should have equal RPN, WIMG & PP */
148 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
150 fprintf(logfile, "Bad RPN/WIMG/PP\n");
154 /* Check access rights */
157 if ((pte1 & 0x00000003) != 0x3)
158 access |= PAGE_WRITE;
160 switch (pte1 & 0x00000003) {
169 access = PAGE_READ | PAGE_WRITE;
174 if ((rw == 0 && (access & PAGE_READ)) ||
175 (rw == 1 && (access & PAGE_WRITE))) {
176 #if defined (DEBUG_MMU)
178 fprintf(logfile, "PTE access granted !\n");
184 /* Access right violation */
186 #if defined (DEBUG_MMU)
188 fprintf(logfile, "PTE access rejected\n");
197 *RPN = keep & 0xFFFFF000;
198 #if defined (DEBUG_MMU)
200 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
204 /* Update page flags */
205 if (!(keep & 0x00000100)) {
210 if (!(keep & 0x00000080)) {
211 if (rw && ret == 0) {
216 /* Force page fault for first write access */
217 *prot &= ~PAGE_WRITE;
221 stl_phys_notdirty(base + (good * 8) + 4, keep);
228 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
230 return (sdr1 & 0xFFFF0000) | (hash & mask);
233 /* Perform segment based translation */
234 static int get_segment (CPUState *env, uint32_t *real, int *prot,
235 uint32_t virtual, int rw, int type)
237 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
243 sr = env->sr[virtual >> 28];
244 #if defined (DEBUG_MMU)
246 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
247 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
248 virtual, virtual >> 28, sr, env->nip,
249 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
252 key = (((sr & 0x20000000) && msr_pr == 1) ||
253 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
254 if ((sr & 0x80000000) == 0) {
255 #if defined (DEBUG_MMU)
257 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
258 key, sr & 0x10000000);
260 /* Check if instruction fetch is allowed, if needed */
261 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
262 /* Page address translation */
263 vsid = sr & 0x00FFFFFF;
264 pgidx = (virtual >> 12) & 0xFFFF;
266 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
267 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
268 pg_addr = get_pgaddr(sdr, hash, mask);
269 ptem = (vsid << 7) | (pgidx >> 10);
270 #if defined (DEBUG_MMU)
272 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
273 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
277 /* Primary table lookup */
278 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
280 /* Secondary table lookup */
281 hash = (~hash) & 0x01FFFFC0;
282 pg_addr = get_pgaddr(sdr, hash, mask);
283 #if defined (DEBUG_MMU)
284 if (virtual != 0xEFFFFFFF && loglevel > 0) {
285 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
286 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
290 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
295 #if defined (DEBUG_MMU)
297 fprintf(logfile, "No access allowed\n");
302 #if defined (DEBUG_MMU)
304 fprintf(logfile, "direct store...\n");
306 /* Direct-store segment : absolutely *BUGGY* for now */
309 /* Integer load/store : only access allowed */
312 /* No code fetch is allowed in direct-store areas */
315 /* Floating point load/store */
318 /* lwarx, ldarx or srwcx. */
321 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
322 /* Should make the instruction do no-op.
323 * As it already do no-op, it's quite easy :-)
332 fprintf(logfile, "ERROR: instruction should not need "
333 "address translation\n");
335 printf("ERROR: instruction should not need "
336 "address translation\n");
339 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
350 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
351 uint32_t address, int rw, int access_type)
356 fprintf(logfile, "%s\n", __func__);
359 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
360 (access_type != ACCESS_CODE && msr_dr == 0)) {
361 /* No address translation */
362 *physical = address & ~0xFFF;
363 *prot = PAGE_READ | PAGE_WRITE;
366 /* Try to find a BAT */
367 ret = get_bat(env, physical, prot, address, rw, access_type);
369 /* We didn't match any BAT entry */
370 ret = get_segment(env, physical, prot, address, rw, access_type);
375 fprintf(logfile, "%s address %08x => %08x\n",
376 __func__, address, *physical);
382 #if defined(CONFIG_USER_ONLY)
383 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
388 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
393 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
399 #if !defined(CONFIG_USER_ONLY)
401 #define MMUSUFFIX _mmu
402 #define GETPC() (__builtin_return_address(0))
405 #include "softmmu_template.h"
408 #include "softmmu_template.h"
411 #include "softmmu_template.h"
414 #include "softmmu_template.h"
416 /* try to fill the TLB and return an exception if error. If retaddr is
417 NULL, it means that the function was called in C code (i.e. not
418 from generated code or from helper.c) */
419 /* XXX: fix it to restore all registers */
420 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
422 TranslationBlock *tb;
427 /* XXX: hack to restore env in all cases, even if not called from
430 env = cpu_single_env;
433 unsigned long tlb_addrr, tlb_addrw;
435 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
436 tlb_addrr = env->tlb_read[is_user][index].address;
437 tlb_addrw = env->tlb_write[is_user][index].address;
440 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
441 "(0x%08lx 0x%08lx)\n", __func__, env,
442 &env->tlb_read[is_user][index], index, addr,
443 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
444 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
448 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
451 /* now we have a real cpu fault */
452 pc = (unsigned long)retaddr;
455 /* the PC is inside the translated code. It means that we have
456 a virtual CPU fault */
457 cpu_restore_state(tb, env, pc, NULL);
460 do_raise_exception_err(env->exception_index, env->error_code);
464 unsigned long tlb_addrr, tlb_addrw;
466 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
467 tlb_addrr = env->tlb_read[is_user][index].address;
468 tlb_addrw = env->tlb_write[is_user][index].address;
469 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
470 "(0x%08lx 0x%08lx)\n", __func__, env,
471 &env->tlb_read[is_user][index], index, addr,
472 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
473 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
479 void cpu_ppc_init_mmu(CPUState *env)
481 /* Nothing to do: all translation are disabled */
485 /* Perform address translation */
486 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
487 int is_user, int is_softmmu)
491 int exception = 0, error_code = 0;
498 access_type = ACCESS_CODE;
501 /* XXX: put correct access by using cpu_restore_state()
503 access_type = ACCESS_INT;
504 // access_type = env->access_type;
506 if (env->user_mode_only) {
507 /* user mode only emulation */
511 ret = get_physical_address(env, &physical, &prot,
512 address, rw, access_type);
514 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
515 is_user, is_softmmu);
516 } else if (ret < 0) {
518 #if defined (DEBUG_MMU)
520 cpu_dump_state(env, logfile, fprintf, 0);
522 if (access_type == ACCESS_CODE) {
523 exception = EXCP_ISI;
526 /* No matches in page tables */
527 error_code = EXCP_ISI_TRANSLATE;
530 /* Access rights violation */
531 error_code = EXCP_ISI_PROT;
534 /* No execute protection violation */
535 error_code = EXCP_ISI_NOEXEC;
538 /* Direct store exception */
539 /* No code fetch is allowed in direct-store areas */
540 error_code = EXCP_ISI_DIRECT;
544 exception = EXCP_DSI;
547 /* No matches in page tables */
548 error_code = EXCP_DSI_TRANSLATE;
551 /* Access rights violation */
552 error_code = EXCP_DSI_PROT;
555 /* Direct store exception */
556 switch (access_type) {
558 /* Floating point load/store */
559 exception = EXCP_ALIGN;
560 error_code = EXCP_ALIGN_FP;
563 /* lwarx, ldarx or srwcx. */
564 exception = EXCP_DSI;
565 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
569 exception = EXCP_DSI;
570 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
574 printf("DSI: invalid exception (%d)\n", ret);
575 exception = EXCP_PROGRAM;
576 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
581 error_code |= EXCP_DSI_STORE;
582 /* Store fault address */
583 env->spr[SPR_DAR] = address;
586 printf("%s: set exception to %d %02x\n",
587 __func__, exception, error_code);
589 env->exception_index = exception;
590 env->error_code = error_code;
596 /*****************************************************************************/
597 /* BATs management */
598 #if !defined(FLUSH_ALL_TLBS)
599 static inline void do_invalidate_BAT (CPUPPCState *env,
600 target_ulong BATu, target_ulong mask)
602 target_ulong base, end, page;
603 base = BATu & ~0x0001FFFF;
604 end = base + mask + 0x00020000;
605 #if defined (DEBUG_BATS)
607 fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n", base, end, mask);
609 for (page = base; page != end; page += TARGET_PAGE_SIZE)
610 tlb_flush_page(env, page);
611 #if defined (DEBUG_BATS)
613 fprintf(logfile, "Flush done\n");
618 static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
621 #if defined (DEBUG_BATS)
623 fprintf(logfile, "Set %cBAT%d%c to 0x%08lx (0x%08lx)\n",
624 ID, nr, ul == 0 ? 'u' : 'l', (unsigned long)value,
625 (unsigned long)env->nip);
630 target_ulong do_load_ibatu (CPUPPCState *env, int nr)
632 return env->IBAT[0][nr];
635 target_ulong do_load_ibatl (CPUPPCState *env, int nr)
637 return env->IBAT[1][nr];
640 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
644 dump_store_bat(env, 'I', 0, nr, value);
645 if (env->IBAT[0][nr] != value) {
646 mask = (value << 15) & 0x0FFE0000UL;
647 #if !defined(FLUSH_ALL_TLBS)
648 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
650 /* When storing valid upper BAT, mask BEPI and BRPN
651 * and invalidate all TLBs covered by this BAT
653 mask = (value << 15) & 0x0FFE0000UL;
654 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
655 (value & ~0x0001FFFFUL & ~mask);
656 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
657 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
658 #if !defined(FLUSH_ALL_TLBS)
659 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
661 #if defined(FLUSH_ALL_TLBS)
667 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
669 dump_store_bat(env, 'I', 1, nr, value);
670 env->IBAT[1][nr] = value;
673 target_ulong do_load_dbatu (CPUPPCState *env, int nr)
675 return env->DBAT[0][nr];
678 target_ulong do_load_dbatl (CPUPPCState *env, int nr)
680 return env->DBAT[1][nr];
683 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
687 dump_store_bat(env, 'D', 0, nr, value);
688 if (env->DBAT[0][nr] != value) {
689 /* When storing valid upper BAT, mask BEPI and BRPN
690 * and invalidate all TLBs covered by this BAT
692 mask = (value << 15) & 0x0FFE0000UL;
693 #if !defined(FLUSH_ALL_TLBS)
694 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
696 mask = (value << 15) & 0x0FFE0000UL;
697 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
698 (value & ~0x0001FFFFUL & ~mask);
699 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
700 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
701 #if !defined(FLUSH_ALL_TLBS)
702 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
709 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
711 dump_store_bat(env, 'D', 1, nr, value);
712 env->DBAT[1][nr] = value;
715 static inline void invalidate_all_tlbs (CPUPPCState *env)
717 /* XXX: this needs to be completed for sotware driven TLB support */
721 /*****************************************************************************/
722 /* Special registers manipulation */
723 target_ulong do_load_nip (CPUPPCState *env)
728 void do_store_nip (CPUPPCState *env, target_ulong value)
733 target_ulong do_load_sdr1 (CPUPPCState *env)
738 void do_store_sdr1 (CPUPPCState *env, target_ulong value)
740 #if defined (DEBUG_MMU)
742 fprintf(logfile, "%s: 0x%08lx\n", __func__, (unsigned long)value);
745 if (env->sdr1 != value) {
747 invalidate_all_tlbs(env);
751 target_ulong do_load_sr (CPUPPCState *env, int srnum)
753 return env->sr[srnum];
756 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
758 #if defined (DEBUG_MMU)
760 fprintf(logfile, "%s: reg=%d 0x%08lx %08lx\n",
761 __func__, srnum, (unsigned long)value, env->sr[srnum]);
764 if (env->sr[srnum] != value) {
765 env->sr[srnum] = value;
766 #if !defined(FLUSH_ALL_TLBS) && 0
768 target_ulong page, end;
769 /* Invalidate 256 MB of virtual memory */
770 page = (16 << 20) * srnum;
771 end = page + (16 << 20);
772 for (; page != end; page += TARGET_PAGE_SIZE)
773 tlb_flush_page(env, page);
776 invalidate_all_tlbs(env);
781 uint32_t do_load_cr (CPUPPCState *env)
783 return (env->crf[0] << 28) |
784 (env->crf[1] << 24) |
785 (env->crf[2] << 20) |
786 (env->crf[3] << 16) |
787 (env->crf[4] << 12) |
793 void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask)
797 for (i = 0, sh = 7; i < 8; i++, sh --) {
798 if (mask & (1 << sh))
799 env->crf[i] = (value >> (sh * 4)) & 0xFUL;
803 uint32_t do_load_xer (CPUPPCState *env)
805 return (xer_so << XER_SO) |
809 (xer_cmp << XER_CMP);
812 void do_store_xer (CPUPPCState *env, uint32_t value)
814 xer_so = (value >> XER_SO) & 0x01;
815 xer_ov = (value >> XER_OV) & 0x01;
816 xer_ca = (value >> XER_CA) & 0x01;
817 xer_cmp = (value >> XER_CMP) & 0xFF;
818 xer_bc = (value >> XER_BC) & 0x3F;
821 target_ulong do_load_msr (CPUPPCState *env)
823 return (msr_vr << MSR_VR) |
826 (msr_key << MSR_KEY) |
827 (msr_pow << MSR_POW) |
828 (msr_tlb << MSR_TLB) |
829 (msr_ile << MSR_ILE) |
834 (msr_fe0 << MSR_FE0) |
837 (msr_fe1 << MSR_FE1) |
848 void do_compute_hflags (CPUPPCState *env)
850 /* Compute current hflags */
851 env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
852 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
853 (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
854 (msr_se << MSR_SE) | (msr_be << MSR_BE);
857 void do_store_msr (CPUPPCState *env, target_ulong value)
859 value &= env->msr_mask;
860 if (((value >> MSR_IR) & 1) != msr_ir ||
861 ((value >> MSR_DR) & 1) != msr_dr) {
862 /* Flush all tlb when changing translation mode
863 * When using software driven TLB, we may also need to reload
867 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
871 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
874 msr_vr = (value >> MSR_VR) & 1;
875 msr_ap = (value >> MSR_AP) & 1;
876 msr_sa = (value >> MSR_SA) & 1;
877 msr_key = (value >> MSR_KEY) & 1;
878 msr_pow = (value >> MSR_POW) & 1;
879 msr_tlb = (value >> MSR_TLB) & 1;
880 msr_ile = (value >> MSR_ILE) & 1;
881 msr_ee = (value >> MSR_EE) & 1;
882 msr_pr = (value >> MSR_PR) & 1;
883 msr_fp = (value >> MSR_FP) & 1;
884 msr_me = (value >> MSR_ME) & 1;
885 msr_fe0 = (value >> MSR_FE0) & 1;
886 msr_se = (value >> MSR_SE) & 1;
887 msr_be = (value >> MSR_BE) & 1;
888 msr_fe1 = (value >> MSR_FE1) & 1;
889 msr_al = (value >> MSR_AL) & 1;
890 msr_ip = (value >> MSR_IP) & 1;
891 msr_ir = (value >> MSR_IR) & 1;
892 msr_dr = (value >> MSR_DR) & 1;
893 msr_pe = (value >> MSR_PE) & 1;
894 msr_px = (value >> MSR_PX) & 1;
895 msr_ri = (value >> MSR_RI) & 1;
896 msr_le = (value >> MSR_LE) & 1;
897 do_compute_hflags(env);
900 float64 do_load_fpscr (CPUPPCState *env)
902 /* The 32 MSB of the target fpr are undefined.
913 #ifdef WORDS_BIGENDIAN
922 for (i = 0; i < 8; i++)
923 u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
927 void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask)
930 * We use only the 32 LSB of the incoming fpr
942 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
943 for (i = 1; i < 7; i++) {
944 if (mask & (1 << (7 - i)))
945 env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
947 /* TODO: update FEX & VX */
948 /* Set rounding mode */
949 switch (env->fpscr[0] & 0x3) {
951 /* Best approximation (round to nearest) */
952 rnd_type = float_round_nearest_even;
955 /* Smaller magnitude (round toward zero) */
956 rnd_type = float_round_to_zero;
959 /* Round toward +infinite */
960 rnd_type = float_round_up;
964 /* Round toward -infinite */
965 rnd_type = float_round_down;
968 set_float_rounding_mode(rnd_type, &env->fp_status);
971 /*****************************************************************************/
972 /* Exception processing */
973 #if defined (CONFIG_USER_ONLY)
974 void do_interrupt (CPUState *env)
976 env->exception_index = -1;
979 static void dump_syscall(CPUState *env)
981 fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
982 env->gpr[0], env->gpr[3], env->gpr[4],
983 env->gpr[5], env->gpr[6], env->nip);
986 void do_interrupt (CPUState *env)
991 excp = env->exception_index;
992 msr = do_load_msr(env);
993 #if defined (DEBUG_EXCEPTIONS)
994 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
997 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
998 env->nip, excp << 8, env->error_code);
1001 cpu_dump_state(env, logfile, fprintf, 0);
1004 if (loglevel & CPU_LOG_INT) {
1005 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
1006 env->nip, excp << 8, env->error_code);
1008 /* Generate informations in save/restore registers */
1012 #if defined (DEBUG_EXCEPTIONS)
1013 printf("%s: escape EXCP_NONE\n", __func__);
1020 case EXCP_MACHINE_CHECK:
1022 cpu_abort(env, "Machine check exception while not allowed\n");
1027 /* Store exception cause */
1028 /* data location address has been stored
1029 * when the fault has been detected
1032 env->spr[SPR_DSISR] = 0;
1033 if ((env->error_code & 0x0f) == EXCP_DSI_TRANSLATE)
1034 env->spr[SPR_DSISR] |= 0x40000000;
1035 else if ((env->error_code & 0x0f) == EXCP_DSI_PROT)
1036 env->spr[SPR_DSISR] |= 0x08000000;
1037 else if ((env->error_code & 0x0f) == EXCP_DSI_NOTSUP) {
1038 env->spr[SPR_DSISR] |= 0x80000000;
1039 if (env->error_code & EXCP_DSI_DIRECT)
1040 env->spr[SPR_DSISR] |= 0x04000000;
1042 if (env->error_code & EXCP_DSI_STORE)
1043 env->spr[SPR_DSISR] |= 0x02000000;
1044 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
1045 env->spr[SPR_DSISR] |= 0x00400000;
1046 if (env->error_code & EXCP_DSI_ECXW)
1047 env->spr[SPR_DSISR] |= 0x00100000;
1048 #if defined (DEBUG_EXCEPTIONS)
1050 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
1051 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1053 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
1054 env->spr[SPR_DSISR], env->spr[SPR_DAR], env->nip);
1059 /* Store exception cause */
1061 if (env->error_code == EXCP_ISI_TRANSLATE)
1063 else if (env->error_code == EXCP_ISI_NOEXEC ||
1064 env->error_code == EXCP_ISI_GUARD ||
1065 env->error_code == EXCP_ISI_DIRECT)
1069 #if defined (DEBUG_EXCEPTIONS)
1071 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
1074 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
1075 msr, env->nip, env->spr[V_TBL]);
1081 #if defined (DEBUG_EXCEPTIONS)
1083 fprintf(logfile, "Skipping hardware interrupt\n");
1087 do_raise_exception(EXCP_EXTERNAL);
1092 /* Store exception cause */
1093 /* Get rS/rD and rA from faulting opcode */
1094 env->spr[SPR_DSISR] |=
1095 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1096 /* data location address has been stored
1097 * when the fault has been detected
1102 switch (env->error_code & ~0xF) {
1104 if (msr_fe0 == 0 && msr_fe1 == 0) {
1105 #if defined (DEBUG_EXCEPTIONS)
1106 printf("Ignore floating point exception\n");
1112 env->fpscr[7] |= 0x8;
1113 /* Finally, update FEX */
1114 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1115 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1116 env->fpscr[7] |= 0x4;
1119 // printf("Invalid instruction at 0x%08x\n", env->nip);
1129 /* Should never occur */
1140 do_raise_exception(EXCP_DECR);
1145 /* NOTE: this is a temporary hack to support graphics OSI
1146 calls from the MOL driver */
1147 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1149 if (env->osi_call(env) != 0)
1152 if (loglevel & CPU_LOG_INT) {
1158 case EXCP_FP_ASSIST:
1167 /* Restore user-mode state */
1168 #if defined (DEBUG_EXCEPTIONS)
1170 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
1174 /* SRR0 is set to current instruction */
1175 env->spr[SPR_SRR0] = (uint32_t)env->nip - 4;
1178 /* SRR0 is set to next instruction */
1179 env->spr[SPR_SRR0] = (uint32_t)env->nip;
1182 env->spr[SPR_SRR1] = msr;
1183 /* reload MSR with correct bits */
1196 do_compute_hflags(env);
1197 /* Jump to handler */
1198 env->nip = excp << 8;
1199 env->exception_index = EXCP_NONE;
1200 /* Invalidate all TLB as we may have changed translation mode */
1201 #ifdef ACCURATE_TLB_FLUSH
1204 /* ensure that no TB jump will be modified as
1205 the program flow was changed */
1211 env->exception_index = -1;
1213 #endif /* !CONFIG_USER_ONLY */