2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 //#define DEBUG_EXCEPTIONS
26 /*****************************************************************************/
27 /* PowerPC MMU emulation */
29 /* Perform BAT hit & translation */
30 static int get_bat (CPUState *env, uint32_t *real, int *prot,
31 uint32_t virtual, int rw, int type)
33 uint32_t *BATlt, *BATut, *BATu, *BATl;
34 uint32_t base, BEPIl, BEPIu, bl;
38 #if defined (DEBUG_BATS)
40 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
41 type == ACCESS_CODE ? 'I' : 'D', virtual);
54 #if defined (DEBUG_BATS)
56 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
57 type == ACCESS_CODE ? 'I' : 'D', virtual);
60 base = virtual & 0xFFFC0000;
61 for (i = 0; i < 4; i++) {
64 BEPIu = *BATu & 0xF0000000;
65 BEPIl = *BATu & 0x0FFE0000;
66 bl = (*BATu & 0x00001FFC) << 15;
67 #if defined (DEBUG_BATS)
69 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
70 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
74 if ((virtual & 0xF0000000) == BEPIu &&
75 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
77 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
78 (msr_pr == 1 && (*BATu & 0x00000001))) {
79 /* Get physical address */
80 *real = (*BATl & 0xF0000000) |
81 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
82 (virtual & 0x0001F000);
83 if (*BATl & 0x00000001)
85 if (*BATl & 0x00000002)
86 *prot = PAGE_WRITE | PAGE_READ;
87 #if defined (DEBUG_BATS)
89 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
90 i, *real, *prot & PAGE_READ ? 'R' : '-',
91 *prot & PAGE_WRITE ? 'W' : '-');
100 #if defined (DEBUG_BATS)
101 printf("no BAT match for 0x%08x:\n", virtual);
102 for (i = 0; i < 4; i++) {
105 BEPIu = *BATu & 0xF0000000;
106 BEPIl = *BATu & 0x0FFE0000;
107 bl = (*BATu & 0x00001FFC) << 15;
108 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
109 "0x%08x 0x%08x 0x%08x\n",
110 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
111 *BATu, *BATl, BEPIu, BEPIl, bl);
119 /* PTE table lookup */
120 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
121 int h, int key, int rw)
123 uint32_t pte0, pte1, keep = 0, access = 0;
124 int i, good = -1, store = 0;
125 int ret = -1; /* No entry found */
127 for (i = 0; i < 8; i++) {
128 pte0 = ldl_phys(base + (i * 8));
129 pte1 = ldl_phys(base + (i * 8) + 4);
130 #if defined (DEBUG_MMU)
132 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
133 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
134 pte0 >> 31, h, (pte0 >> 6) & 1, va);
137 /* Check validity and table match */
138 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
139 /* Check vsid & api */
140 if ((pte0 & 0x7FFFFFBF) == va) {
145 /* All matches should have equal RPN, WIMG & PP */
146 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
148 fprintf(logfile, "Bad RPN/WIMG/PP\n");
152 /* Check access rights */
155 if ((pte1 & 0x00000003) != 0x3)
156 access |= PAGE_WRITE;
158 switch (pte1 & 0x00000003) {
167 access = PAGE_READ | PAGE_WRITE;
172 if ((rw == 0 && (access & PAGE_READ)) ||
173 (rw == 1 && (access & PAGE_WRITE))) {
174 #if defined (DEBUG_MMU)
176 fprintf(logfile, "PTE access granted !\n");
182 /* Access right violation */
184 #if defined (DEBUG_MMU)
186 fprintf(logfile, "PTE access rejected\n");
195 *RPN = keep & 0xFFFFF000;
196 #if defined (DEBUG_MMU)
198 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
202 /* Update page flags */
203 if (!(keep & 0x00000100)) {
208 if (!(keep & 0x00000080)) {
209 if (rw && ret == 0) {
214 /* Force page fault for first write access */
215 *prot &= ~PAGE_WRITE;
219 stl_phys_notdirty(base + (good * 8) + 4, keep);
226 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
228 return (sdr1 & 0xFFFF0000) | (hash & mask);
231 /* Perform segment based translation */
232 static int get_segment (CPUState *env, uint32_t *real, int *prot,
233 uint32_t virtual, int rw, int type)
235 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
241 sr = env->sr[virtual >> 28];
242 #if defined (DEBUG_MMU)
244 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
245 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
246 virtual, virtual >> 28, sr, env->nip,
247 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
250 key = (((sr & 0x20000000) && msr_pr == 1) ||
251 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
252 if ((sr & 0x80000000) == 0) {
253 #if defined (DEBUG_MMU)
255 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
256 key, sr & 0x10000000);
258 /* Check if instruction fetch is allowed, if needed */
259 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
260 /* Page address translation */
261 vsid = sr & 0x00FFFFFF;
262 pgidx = (virtual >> 12) & 0xFFFF;
264 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
265 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
266 pg_addr = get_pgaddr(sdr, hash, mask);
267 ptem = (vsid << 7) | (pgidx >> 10);
268 #if defined (DEBUG_MMU)
270 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
271 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
275 /* Primary table lookup */
276 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
278 /* Secondary table lookup */
279 hash = (~hash) & 0x01FFFFC0;
280 pg_addr = get_pgaddr(sdr, hash, mask);
281 #if defined (DEBUG_MMU)
282 if (virtual != 0xEFFFFFFF && loglevel > 0) {
283 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
284 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
288 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
293 #if defined (DEBUG_MMU)
295 fprintf(logfile, "No access allowed\n");
300 #if defined (DEBUG_MMU)
302 fprintf(logfile, "direct store...\n");
304 /* Direct-store segment : absolutely *BUGGY* for now */
307 /* Integer load/store : only access allowed */
310 /* No code fetch is allowed in direct-store areas */
313 /* Floating point load/store */
316 /* lwarx, ldarx or srwcx. */
319 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
320 /* Should make the instruction do no-op.
321 * As it already do no-op, it's quite easy :-)
330 fprintf(logfile, "ERROR: instruction should not need "
331 "address translation\n");
333 printf("ERROR: instruction should not need "
334 "address translation\n");
337 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
348 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
349 uint32_t address, int rw, int access_type)
354 fprintf(logfile, "%s\n", __func__);
357 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
358 (access_type != ACCESS_CODE && msr_dr == 0)) {
359 /* No address translation */
360 *physical = address & ~0xFFF;
361 *prot = PAGE_READ | PAGE_WRITE;
364 /* Try to find a BAT */
365 ret = get_bat(env, physical, prot, address, rw, access_type);
367 /* We didn't match any BAT entry */
368 ret = get_segment(env, physical, prot, address, rw, access_type);
373 fprintf(logfile, "%s address %08x => %08x\n",
374 __func__, address, *physical);
380 #if defined(CONFIG_USER_ONLY)
381 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
386 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
391 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
397 #if !defined(CONFIG_USER_ONLY)
399 #define MMUSUFFIX _mmu
400 #define GETPC() (__builtin_return_address(0))
403 #include "softmmu_template.h"
406 #include "softmmu_template.h"
409 #include "softmmu_template.h"
412 #include "softmmu_template.h"
414 /* try to fill the TLB and return an exception if error. If retaddr is
415 NULL, it means that the function was called in C code (i.e. not
416 from generated code or from helper.c) */
417 /* XXX: fix it to restore all registers */
418 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
420 TranslationBlock *tb;
425 /* XXX: hack to restore env in all cases, even if not called from
428 env = cpu_single_env;
431 unsigned long tlb_addrr, tlb_addrw;
433 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
434 tlb_addrr = env->tlb_read[is_user][index].address;
435 tlb_addrw = env->tlb_write[is_user][index].address;
438 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
439 "(0x%08lx 0x%08lx)\n", __func__, env,
440 &env->tlb_read[is_user][index], index, addr,
441 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
442 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
446 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
449 /* now we have a real cpu fault */
450 pc = (unsigned long)retaddr;
453 /* the PC is inside the translated code. It means that we have
454 a virtual CPU fault */
455 cpu_restore_state(tb, env, pc, NULL);
458 do_raise_exception_err(env->exception_index, env->error_code);
462 unsigned long tlb_addrr, tlb_addrw;
464 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
465 tlb_addrr = env->tlb_read[is_user][index].address;
466 tlb_addrw = env->tlb_write[is_user][index].address;
467 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
468 "(0x%08lx 0x%08lx)\n", __func__, env,
469 &env->tlb_read[is_user][index], index, addr,
470 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
471 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
477 void cpu_ppc_init_mmu(CPUState *env)
479 /* Nothing to do: all translation are disabled */
483 /* Perform address translation */
484 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
485 int is_user, int is_softmmu)
489 int exception = 0, error_code = 0;
496 access_type = ACCESS_CODE;
499 /* XXX: put correct access by using cpu_restore_state()
501 access_type = ACCESS_INT;
502 // access_type = env->access_type;
504 if (env->user_mode_only) {
505 /* user mode only emulation */
509 ret = get_physical_address(env, &physical, &prot,
510 address, rw, access_type);
512 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
513 is_user, is_softmmu);
514 } else if (ret < 0) {
516 #if defined (DEBUG_MMU)
518 cpu_dump_state(env, logfile, fprintf, 0);
520 if (access_type == ACCESS_CODE) {
521 exception = EXCP_ISI;
524 /* No matches in page tables */
525 error_code = 0x40000000;
528 /* Access rights violation */
529 error_code = 0x08000000;
532 /* No execute protection violation */
533 error_code = 0x10000000;
536 /* Direct store exception */
537 /* No code fetch is allowed in direct-store areas */
538 error_code = 0x10000000;
541 /* No match in segment table */
542 exception = EXCP_ISEG;
547 exception = EXCP_DSI;
550 /* No matches in page tables */
551 error_code = 0x40000000;
554 /* Access rights violation */
555 error_code = 0x08000000;
558 /* Direct store exception */
559 switch (access_type) {
561 /* Floating point load/store */
562 exception = EXCP_ALIGN;
563 error_code = EXCP_ALIGN_FP;
566 /* lwarx, ldarx or srwcx. */
567 error_code = 0x04000000;
571 error_code = 0x04100000;
574 printf("DSI: invalid exception (%d)\n", ret);
575 exception = EXCP_PROGRAM;
576 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
580 /* No match in segment table */
581 exception = EXCP_DSEG;
586 error_code |= 0x02000000;
587 /* Store fault address */
588 env->spr[SPR_DAR] = address;
589 env->spr[SPR_DSISR] = error_code;
592 printf("%s: set exception to %d %02x\n",
593 __func__, exception, error_code);
595 env->exception_index = exception;
596 env->error_code = error_code;
602 /*****************************************************************************/
603 /* BATs management */
604 #if !defined(FLUSH_ALL_TLBS)
605 static inline void do_invalidate_BAT (CPUPPCState *env,
606 target_ulong BATu, target_ulong mask)
608 target_ulong base, end, page;
609 base = BATu & ~0x0001FFFF;
610 end = base + mask + 0x00020000;
611 #if defined (DEBUG_BATS)
613 fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n", base, end, mask);
615 for (page = base; page != end; page += TARGET_PAGE_SIZE)
616 tlb_flush_page(env, page);
617 #if defined (DEBUG_BATS)
619 fprintf(logfile, "Flush done\n");
624 static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
627 #if defined (DEBUG_BATS)
629 fprintf(logfile, "Set %cBAT%d%c to 0x%08lx (0x%08lx)\n",
630 ID, nr, ul == 0 ? 'u' : 'l', (unsigned long)value,
631 (unsigned long)env->nip);
636 target_ulong do_load_ibatu (CPUPPCState *env, int nr)
638 return env->IBAT[0][nr];
641 target_ulong do_load_ibatl (CPUPPCState *env, int nr)
643 return env->IBAT[1][nr];
646 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
650 dump_store_bat(env, 'I', 0, nr, value);
651 if (env->IBAT[0][nr] != value) {
652 mask = (value << 15) & 0x0FFE0000UL;
653 #if !defined(FLUSH_ALL_TLBS)
654 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
656 /* When storing valid upper BAT, mask BEPI and BRPN
657 * and invalidate all TLBs covered by this BAT
659 mask = (value << 15) & 0x0FFE0000UL;
660 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
661 (value & ~0x0001FFFFUL & ~mask);
662 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
663 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
664 #if !defined(FLUSH_ALL_TLBS)
665 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
667 #if defined(FLUSH_ALL_TLBS)
673 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
675 dump_store_bat(env, 'I', 1, nr, value);
676 env->IBAT[1][nr] = value;
679 target_ulong do_load_dbatu (CPUPPCState *env, int nr)
681 return env->DBAT[0][nr];
684 target_ulong do_load_dbatl (CPUPPCState *env, int nr)
686 return env->DBAT[1][nr];
689 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
693 dump_store_bat(env, 'D', 0, nr, value);
694 if (env->DBAT[0][nr] != value) {
695 /* When storing valid upper BAT, mask BEPI and BRPN
696 * and invalidate all TLBs covered by this BAT
698 mask = (value << 15) & 0x0FFE0000UL;
699 #if !defined(FLUSH_ALL_TLBS)
700 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
702 mask = (value << 15) & 0x0FFE0000UL;
703 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
704 (value & ~0x0001FFFFUL & ~mask);
705 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
706 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
707 #if !defined(FLUSH_ALL_TLBS)
708 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
715 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
717 dump_store_bat(env, 'D', 1, nr, value);
718 env->DBAT[1][nr] = value;
721 static inline void invalidate_all_tlbs (CPUPPCState *env)
723 /* XXX: this needs to be completed for sotware driven TLB support */
727 /*****************************************************************************/
728 /* Special registers manipulation */
729 target_ulong do_load_nip (CPUPPCState *env)
734 void do_store_nip (CPUPPCState *env, target_ulong value)
739 target_ulong do_load_sdr1 (CPUPPCState *env)
744 void do_store_sdr1 (CPUPPCState *env, target_ulong value)
746 #if defined (DEBUG_MMU)
748 fprintf(logfile, "%s: 0x%08lx\n", __func__, (unsigned long)value);
751 if (env->sdr1 != value) {
753 invalidate_all_tlbs(env);
757 target_ulong do_load_sr (CPUPPCState *env, int srnum)
759 return env->sr[srnum];
762 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
764 #if defined (DEBUG_MMU)
766 fprintf(logfile, "%s: reg=%d 0x%08lx %08lx\n",
767 __func__, srnum, (unsigned long)value, env->sr[srnum]);
770 if (env->sr[srnum] != value) {
771 env->sr[srnum] = value;
772 #if !defined(FLUSH_ALL_TLBS) && 0
774 target_ulong page, end;
775 /* Invalidate 256 MB of virtual memory */
776 page = (16 << 20) * srnum;
777 end = page + (16 << 20);
778 for (; page != end; page += TARGET_PAGE_SIZE)
779 tlb_flush_page(env, page);
782 invalidate_all_tlbs(env);
787 uint32_t do_load_cr (CPUPPCState *env)
789 return (env->crf[0] << 28) |
790 (env->crf[1] << 24) |
791 (env->crf[2] << 20) |
792 (env->crf[3] << 16) |
793 (env->crf[4] << 12) |
799 void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask)
803 for (i = 0, sh = 7; i < 8; i++, sh --) {
804 if (mask & (1 << sh))
805 env->crf[i] = (value >> (sh * 4)) & 0xFUL;
809 uint32_t do_load_xer (CPUPPCState *env)
811 return (xer_so << XER_SO) |
815 (xer_cmp << XER_CMP);
818 void do_store_xer (CPUPPCState *env, uint32_t value)
820 xer_so = (value >> XER_SO) & 0x01;
821 xer_ov = (value >> XER_OV) & 0x01;
822 xer_ca = (value >> XER_CA) & 0x01;
823 xer_cmp = (value >> XER_CMP) & 0xFF;
824 xer_bc = (value >> XER_BC) & 0x3F;
827 target_ulong do_load_msr (CPUPPCState *env)
829 return (msr_vr << MSR_VR) |
832 (msr_key << MSR_KEY) |
833 (msr_pow << MSR_POW) |
834 (msr_tlb << MSR_TLB) |
835 (msr_ile << MSR_ILE) |
840 (msr_fe0 << MSR_FE0) |
843 (msr_fe1 << MSR_FE1) |
854 void do_compute_hflags (CPUPPCState *env)
856 /* Compute current hflags */
857 env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
858 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
859 (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
860 (msr_se << MSR_SE) | (msr_be << MSR_BE);
863 void do_store_msr (CPUPPCState *env, target_ulong value)
865 value &= env->msr_mask;
866 if (((value >> MSR_IR) & 1) != msr_ir ||
867 ((value >> MSR_DR) & 1) != msr_dr) {
868 /* Flush all tlb when changing translation mode
869 * When using software driven TLB, we may also need to reload
873 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
877 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
880 msr_vr = (value >> MSR_VR) & 1;
881 msr_ap = (value >> MSR_AP) & 1;
882 msr_sa = (value >> MSR_SA) & 1;
883 msr_key = (value >> MSR_KEY) & 1;
884 msr_pow = (value >> MSR_POW) & 1;
885 msr_tlb = (value >> MSR_TLB) & 1;
886 msr_ile = (value >> MSR_ILE) & 1;
887 msr_ee = (value >> MSR_EE) & 1;
888 msr_pr = (value >> MSR_PR) & 1;
889 msr_fp = (value >> MSR_FP) & 1;
890 msr_me = (value >> MSR_ME) & 1;
891 msr_fe0 = (value >> MSR_FE0) & 1;
892 msr_se = (value >> MSR_SE) & 1;
893 msr_be = (value >> MSR_BE) & 1;
894 msr_fe1 = (value >> MSR_FE1) & 1;
895 msr_al = (value >> MSR_AL) & 1;
896 msr_ip = (value >> MSR_IP) & 1;
897 msr_ir = (value >> MSR_IR) & 1;
898 msr_dr = (value >> MSR_DR) & 1;
899 msr_pe = (value >> MSR_PE) & 1;
900 msr_px = (value >> MSR_PX) & 1;
901 msr_ri = (value >> MSR_RI) & 1;
902 msr_le = (value >> MSR_LE) & 1;
903 do_compute_hflags(env);
906 float64 do_load_fpscr (CPUPPCState *env)
908 /* The 32 MSB of the target fpr are undefined.
919 #ifdef WORDS_BIGENDIAN
928 for (i = 0; i < 8; i++)
929 u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
933 void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask)
936 * We use only the 32 LSB of the incoming fpr
948 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
949 for (i = 1; i < 7; i++) {
950 if (mask & (1 << (7 - i)))
951 env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
953 /* TODO: update FEX & VX */
954 /* Set rounding mode */
955 switch (env->fpscr[0] & 0x3) {
957 /* Best approximation (round to nearest) */
958 rnd_type = float_round_nearest_even;
961 /* Smaller magnitude (round toward zero) */
962 rnd_type = float_round_to_zero;
965 /* Round toward +infinite */
966 rnd_type = float_round_up;
970 /* Round toward -infinite */
971 rnd_type = float_round_down;
974 set_float_rounding_mode(rnd_type, &env->fp_status);
977 /*****************************************************************************/
978 /* Exception processing */
979 #if defined (CONFIG_USER_ONLY)
980 void do_interrupt (CPUState *env)
982 env->exception_index = -1;
985 static void dump_syscall(CPUState *env)
987 fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
988 env->gpr[0], env->gpr[3], env->gpr[4],
989 env->gpr[5], env->gpr[6], env->nip);
992 void do_interrupt (CPUState *env)
994 target_ulong msr, *srr_0, *srr_1, tmp;
997 excp = env->exception_index;
998 msr = do_load_msr(env);
999 /* The default is to use SRR0 & SRR1 to save the exception context */
1000 srr_0 = &env->spr[SPR_SRR0];
1001 srr_1 = &env->spr[SPR_SRR1];
1002 #if defined (DEBUG_EXCEPTIONS)
1003 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1004 if (loglevel != 0) {
1005 fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
1006 (unsigned long)env->nip, excp, env->error_code);
1007 cpu_dump_state(env, logfile, fprintf, 0);
1011 if (loglevel & CPU_LOG_INT) {
1012 fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
1013 (unsigned long)env->nip, excp, env->error_code);
1016 /* Generate informations in save/restore registers */
1018 /* Generic PowerPC exceptions */
1019 case EXCP_RESET: /* 0x0100 */
1020 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
1025 srr_0 = &env->spr[SPR_40x_SRR2];
1026 srr_1 = &env->spr[SPR_40x_SRR3];
1029 case EXCP_MACHINE_CHECK: /* 0x0200 */
1031 cpu_abort(env, "Machine check exception while not allowed\n");
1033 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_40x) {
1034 srr_0 = &env->spr[SPR_40x_SRR2];
1035 srr_1 = &env->spr[SPR_40x_SRR3];
1039 case EXCP_DSI: /* 0x0300 */
1040 /* Store exception cause */
1041 /* data location address has been stored
1042 * when the fault has been detected
1045 #if defined (DEBUG_EXCEPTIONS)
1047 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
1048 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1050 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
1051 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1055 case EXCP_ISI: /* 0x0400 */
1056 /* Store exception cause */
1058 msr |= env->error_code;
1059 #if defined (DEBUG_EXCEPTIONS)
1060 if (loglevel != 0) {
1061 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
1066 case EXCP_EXTERNAL: /* 0x0500 */
1068 #if defined (DEBUG_EXCEPTIONS)
1070 fprintf(logfile, "Skipping hardware interrupt\n");
1074 env->interrupt_request |= CPU_INTERRUPT_HARD;
1078 case EXCP_ALIGN: /* 0x0600 */
1079 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_601) {
1080 /* Store exception cause */
1081 /* Get rS/rD and rA from faulting opcode */
1082 env->spr[SPR_DSISR] |=
1083 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1084 /* data location address has been stored
1085 * when the fault has been detected
1088 /* IO error exception on PowerPC 601 */
1091 "601 IO error exception is not implemented yet !\n");
1094 case EXCP_PROGRAM: /* 0x0700 */
1096 switch (env->error_code & ~0xF) {
1098 if (msr_fe0 == 0 && msr_fe1 == 0) {
1099 #if defined (DEBUG_EXCEPTIONS)
1100 printf("Ignore floating point exception\n");
1106 env->fpscr[7] |= 0x8;
1107 /* Finally, update FEX */
1108 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1109 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1110 env->fpscr[7] |= 0x4;
1113 // printf("Invalid instruction at 0x%08x\n", env->nip);
1123 /* Should never occur */
1128 case EXCP_NO_FP: /* 0x0800 */
1135 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1140 case EXCP_SYSCALL: /* 0x0C00 */
1141 /* NOTE: this is a temporary hack to support graphics OSI
1142 calls from the MOL driver */
1143 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1145 if (env->osi_call(env) != 0)
1148 if (loglevel & CPU_LOG_INT) {
1152 case EXCP_TRACE: /* 0x0D00 */
1154 cpu_abort(env, "Trace exception is not implemented yet !\n");
1156 case EXCP_PERF: /* 0x0F00 */
1159 "Performance counter exception is not implemented yet !\n");
1161 /* 32 bits PowerPC specific exceptions */
1162 case EXCP_FP_ASSIST: /* 0x0E00 */
1164 cpu_abort(env, "Floating point assist exception "
1165 "is not implemented yet !\n");
1167 /* 64 bits PowerPC exceptions */
1168 case EXCP_DSEG: /* 0x0380 */
1170 cpu_abort(env, "Data segment exception is not implemented yet !\n");
1172 case EXCP_ISEG: /* 0x0480 */
1175 "Instruction segment exception is not implemented yet !\n");
1177 case EXCP_HDECR: /* 0x0980 */
1181 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1186 "Hypervisor decrementer exception is not implemented yet !\n");
1188 /* Implementation specific exceptions */
1190 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_602) {
1191 /* Critical interrupt on G2 */
1193 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1196 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1200 switch (PPC_EXCP(env)) {
1201 case PPC_FLAGS_EXCP_40x:
1202 /* APU unavailable on 405 */
1205 "APU unavailable exception is not implemented yet !\n");
1207 case PPC_FLAGS_EXCP_74xx:
1208 /* Altivec unavailable */
1210 cpu_abort(env, "Altivec unavailable exception "
1211 "is not implemented yet !\n");
1214 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1219 switch (PPC_EXCP(env)) {
1220 case PPC_FLAGS_EXCP_40x:
1223 cpu_abort(env, "40x PIT exception is not implemented yet !\n");
1225 case PPC_FLAGS_EXCP_602:
1226 case PPC_FLAGS_EXCP_603:
1227 /* ITLBMISS on 602/603 */
1232 cpu_abort(env, "Invalid exception 0x1000 !\n");
1237 switch (PPC_EXCP(env)) {
1238 case PPC_FLAGS_EXCP_40x:
1240 cpu_abort(env, "40x FIT exception is not implemented yet !\n");
1244 cpu_abort(env, "Invalid exception 0x1010 !\n");
1249 switch (PPC_EXCP(env)) {
1250 case PPC_FLAGS_EXCP_40x:
1251 /* Watchdog on 4xx */
1254 "40x watchdog exception is not implemented yet !\n");
1257 cpu_abort(env, "Invalid exception 0x1020 !\n");
1262 switch (PPC_EXCP(env)) {
1263 case PPC_FLAGS_EXCP_40x:
1264 /* DTLBMISS on 4xx */
1267 "40x DTLBMISS exception is not implemented yet !\n");
1269 case PPC_FLAGS_EXCP_602:
1270 case PPC_FLAGS_EXCP_603:
1271 /* DLTLBMISS on 602/603 */
1276 cpu_abort(env, "Invalid exception 0x1100 !\n");
1281 switch (PPC_EXCP(env)) {
1282 case PPC_FLAGS_EXCP_40x:
1283 /* ITLBMISS on 4xx */
1286 "40x ITLBMISS exception is not implemented yet !\n");
1288 case PPC_FLAGS_EXCP_602:
1289 case PPC_FLAGS_EXCP_603:
1290 /* DSTLBMISS on 602/603 */
1294 #if defined (DEBUG_SOFTWARE_TLB)
1295 if (loglevel != 0) {
1296 fprintf(logfile, "6xx %sTLB miss: IM %08x DM %08x IC %08x "
1297 "DC %08x H1 %08x H2 %08x %08x\n",
1298 excp == 0x1000 ? "I" : excp == 0x1100 ? "DL" : "DS",
1299 env->spr[SPR_IMISS], env->spr[SPR_DMISS],
1300 env->spr[SPR_ICMP], env->spr[SPR_DCMP],
1301 env->spr[SPR_DHASH1], env->spr[SPR_DHASH2],
1305 /* Swap temporary saved registers with GPRs */
1307 env->gpr[0] = env->tgpr[0];
1310 env->gpr[1] = env->tgpr[1];
1313 env->gpr[2] = env->tgpr[2];
1316 env->gpr[3] = env->tgpr[3];
1318 msr |= env->crf[0] << 28;
1319 msr |= env->error_code; /* key, D/I, S/L bits */
1320 /* Set way using a LRU mechanism */
1321 msr |= (env->last_way ^ 1) << 17;
1324 cpu_abort(env, "Invalid exception 0x1200 !\n");
1329 switch (PPC_EXCP(env)) {
1330 case PPC_FLAGS_EXCP_601:
1331 case PPC_FLAGS_EXCP_602:
1332 case PPC_FLAGS_EXCP_603:
1333 case PPC_FLAGS_EXCP_604:
1334 case PPC_FLAGS_EXCP_7x0:
1335 case PPC_FLAGS_EXCP_7x5:
1336 /* IABR on 6xx/7xx */
1338 cpu_abort(env, "IABR exception is not implemented yet !\n");
1341 cpu_abort(env, "Invalid exception 0x1300 !\n");
1346 switch (PPC_EXCP(env)) {
1347 case PPC_FLAGS_EXCP_601:
1348 case PPC_FLAGS_EXCP_602:
1349 case PPC_FLAGS_EXCP_603:
1350 case PPC_FLAGS_EXCP_604:
1351 case PPC_FLAGS_EXCP_7x0:
1352 case PPC_FLAGS_EXCP_7x5:
1353 /* SMI on 6xx/7xx */
1355 cpu_abort(env, "SMI exception is not implemented yet !\n");
1358 cpu_abort(env, "Invalid exception 0x1400 !\n");
1363 switch (PPC_EXCP(env)) {
1364 case PPC_FLAGS_EXCP_602:
1365 /* Watchdog on 602 */
1367 "602 watchdog exception is not implemented yet !\n");
1369 case PPC_FLAGS_EXCP_970:
1370 /* Soft patch exception on 970 */
1373 "970 soft-patch exception is not implemented yet !\n");
1375 case PPC_FLAGS_EXCP_74xx:
1376 /* VPU assist on 74xx */
1378 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1381 cpu_abort(env, "Invalid exception 0x1500 !\n");
1386 switch (PPC_EXCP(env)) {
1387 case PPC_FLAGS_EXCP_602:
1388 /* Emulation trap on 602 */
1390 cpu_abort(env, "602 emulation trap exception "
1391 "is not implemented yet !\n");
1393 case PPC_FLAGS_EXCP_970:
1394 /* Maintenance exception on 970 */
1397 "970 maintenance exception is not implemented yet !\n");
1400 cpu_abort(env, "Invalid exception 0x1600 !\n");
1405 switch (PPC_EXCP(env)) {
1406 case PPC_FLAGS_EXCP_7x0:
1407 case PPC_FLAGS_EXCP_7x5:
1408 /* Thermal management interrupt on G3 */
1410 cpu_abort(env, "G3 thermal management exception "
1411 "is not implemented yet !\n");
1413 case PPC_FLAGS_EXCP_970:
1414 /* VPU assist on 970 */
1417 "970 VPU assist exception is not implemented yet !\n");
1420 cpu_abort(env, "Invalid exception 0x1700 !\n");
1425 switch (PPC_EXCP(env)) {
1426 case PPC_FLAGS_EXCP_970:
1427 /* Thermal exception on 970 */
1429 cpu_abort(env, "970 thermal management exception "
1430 "is not implemented yet !\n");
1433 cpu_abort(env, "Invalid exception 0x1800 !\n");
1438 switch (PPC_EXCP(env)) {
1439 case PPC_FLAGS_EXCP_40x:
1442 cpu_abort(env, "40x debug exception is not implemented yet !\n");
1444 case PPC_FLAGS_EXCP_601:
1445 /* Run mode exception on 601 */
1448 "601 run mode exception is not implemented yet !\n");
1451 cpu_abort(env, "Invalid exception 0x1800 !\n");
1455 /* Other exceptions */
1456 /* Qemu internal exceptions:
1457 * we should never come here with those values: abort execution
1460 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
1463 /* save current instruction location */
1464 *srr_0 = (env->nip - 4) & 0xFFFFFFFFULL;
1467 /* save next instruction location */
1468 *srr_0 = env->nip & 0xFFFFFFFFULL;
1473 /* If we disactivated any translation, flush TLBs */
1474 if (msr_ir || msr_dr) {
1477 /* reload MSR with correct bits */
1490 do_compute_hflags(env);
1491 /* Jump to handler */
1493 env->exception_index = EXCP_NONE;
1494 /* ensure that no TB jump will be modified as
1495 the program flow was changed */
1501 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1503 #endif /* !CONFIG_USER_ONLY */