2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #if defined (USE_OPEN_FIRMWARE)
28 //#define DEBUG_EXCEPTIONS
30 extern FILE *stdout, *stderr;
32 /*****************************************************************************/
33 /* PPC MMU emulation */
34 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
35 int is_user, int is_softmmu);
37 /* Perform BAT hit & translation */
38 static int get_bat (CPUState *env, uint32_t *real, int *prot,
39 uint32_t virtual, int rw, int type)
41 uint32_t *BATlt, *BATut, *BATu, *BATl;
42 uint32_t base, BEPIl, BEPIu, bl;
46 #if defined (DEBUG_BATS)
48 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
49 type == ACCESS_CODE ? 'I' : 'D', virtual);
62 #if defined (DEBUG_BATS)
64 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
65 type == ACCESS_CODE ? 'I' : 'D', virtual);
68 base = virtual & 0xFFFC0000;
69 for (i = 0; i < 4; i++) {
72 BEPIu = *BATu & 0xF0000000;
73 BEPIl = *BATu & 0x0FFE0000;
74 bl = (*BATu & 0x00001FFC) << 15;
75 #if defined (DEBUG_BATS)
77 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
78 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
82 if ((virtual & 0xF0000000) == BEPIu &&
83 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
85 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
86 (msr_pr == 1 && (*BATu & 0x00000001))) {
87 /* Get physical address */
88 *real = (*BATl & 0xF0000000) |
89 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
90 (virtual & 0x0001F000);
91 if (*BATl & 0x00000001)
93 if (*BATl & 0x00000002)
94 *prot = PAGE_WRITE | PAGE_READ;
95 #if defined (DEBUG_BATS)
97 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
98 i, *real, *prot & PAGE_READ ? 'R' : '-',
99 *prot & PAGE_WRITE ? 'W' : '-');
108 #if defined (DEBUG_BATS)
109 printf("no BAT match for 0x%08x:\n", virtual);
110 for (i = 0; i < 4; i++) {
113 BEPIu = *BATu & 0xF0000000;
114 BEPIl = *BATu & 0x0FFE0000;
115 bl = (*BATu & 0x00001FFC) << 15;
116 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
117 "0x%08x 0x%08x 0x%08x\n",
118 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
119 *BATu, *BATl, BEPIu, BEPIl, bl);
127 /* PTE table lookup */
128 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
129 int h, int key, int rw)
131 uint32_t pte0, pte1, keep = 0, access = 0;
132 int i, good = -1, store = 0;
133 int ret = -1; /* No entry found */
135 for (i = 0; i < 8; i++) {
136 pte0 = ldl_raw(phys_ram_base + base + (i * 8));
137 pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
138 #if defined (DEBUG_MMU)
140 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
141 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
142 pte0 >> 31, h, (pte0 >> 6) & 1, va);
145 /* Check validity and table match */
146 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
147 /* Check vsid & api */
148 if ((pte0 & 0x7FFFFFBF) == va) {
153 /* All matches should have equal RPN, WIMG & PP */
154 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
156 fprintf(logfile, "Bad RPN/WIMG/PP\n");
160 /* Check access rights */
163 if ((pte1 & 0x00000003) != 0x3)
164 access |= PAGE_WRITE;
166 switch (pte1 & 0x00000003) {
175 access = PAGE_READ | PAGE_WRITE;
180 if ((rw == 0 && (access & PAGE_READ)) ||
181 (rw == 1 && (access & PAGE_WRITE))) {
182 #if defined (DEBUG_MMU)
184 fprintf(logfile, "PTE access granted !\n");
190 /* Access right violation */
192 #if defined (DEBUG_MMU)
194 fprintf(logfile, "PTE access rejected\n");
203 *RPN = keep & 0xFFFFF000;
204 #if defined (DEBUG_MMU)
206 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
210 /* Update page flags */
211 if (!(keep & 0x00000100)) {
216 if (!(keep & 0x00000080)) {
217 if (rw && ret == 0) {
222 /* Force page fault for first write access */
223 *prot &= ~PAGE_WRITE;
227 stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
234 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
236 return (sdr1 & 0xFFFF0000) | (hash & mask);
239 /* Perform segment based translation */
240 static int get_segment (CPUState *env, uint32_t *real, int *prot,
241 uint32_t virtual, int rw, int type)
243 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
249 sr = env->sr[virtual >> 28];
250 #if defined (DEBUG_MMU)
252 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
253 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
254 virtual, virtual >> 28, sr, env->nip,
255 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
258 key = (((sr & 0x20000000) && msr_pr == 1) ||
259 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
260 if ((sr & 0x80000000) == 0) {
261 #if defined (DEBUG_MMU)
263 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
264 key, sr & 0x10000000);
266 /* Check if instruction fetch is allowed, if needed */
267 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
268 /* Page address translation */
269 vsid = sr & 0x00FFFFFF;
270 pgidx = (virtual >> 12) & 0xFFFF;
272 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
273 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
274 pg_addr = get_pgaddr(sdr, hash, mask);
275 ptem = (vsid << 7) | (pgidx >> 10);
276 #if defined (DEBUG_MMU)
278 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
279 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
283 /* Primary table lookup */
284 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
286 /* Secondary table lookup */
287 hash = (~hash) & 0x01FFFFC0;
288 pg_addr = get_pgaddr(sdr, hash, mask);
289 #if defined (DEBUG_MMU)
290 if (virtual != 0xEFFFFFFF && loglevel > 0) {
291 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
292 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
296 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
301 #if defined (DEBUG_MMU)
303 fprintf(logfile, "No access allowed\n");
308 #if defined (DEBUG_MMU)
310 fprintf(logfile, "direct store...\n");
312 /* Direct-store segment : absolutely *BUGGY* for now */
315 /* Integer load/store : only access allowed */
318 /* No code fetch is allowed in direct-store areas */
321 /* Floating point load/store */
324 /* lwarx, ldarx or srwcx. */
327 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
328 /* Should make the instruction do no-op.
329 * As it already do no-op, it's quite easy :-)
338 fprintf(logfile, "ERROR: instruction should not need "
339 "address translation\n");
341 printf("ERROR: instruction should not need "
342 "address translation\n");
345 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
356 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
357 uint32_t address, int rw, int access_type)
362 fprintf(logfile, "%s\n", __func__);
365 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
366 (access_type != ACCESS_CODE && msr_dr == 0)) {
367 /* No address translation */
368 *physical = address & ~0xFFF;
369 *prot = PAGE_READ | PAGE_WRITE;
372 /* Try to find a BAT */
373 ret = get_bat(env, physical, prot, address, rw, access_type);
375 /* We didn't match any BAT entry */
376 ret = get_segment(env, physical, prot, address, rw, access_type);
380 fprintf(logfile, "%s address %08x => %08x\n",
381 __func__, address, *physical);
387 #if defined(CONFIG_USER_ONLY)
388 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
393 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
398 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
404 #if !defined(CONFIG_USER_ONLY)
406 #define MMUSUFFIX _mmu
407 #define GETPC() (__builtin_return_address(0))
410 #include "softmmu_template.h"
413 #include "softmmu_template.h"
416 #include "softmmu_template.h"
419 #include "softmmu_template.h"
421 /* try to fill the TLB and return an exception if error. If retaddr is
422 NULL, it means that the function was called in C code (i.e. not
423 from generated code or from helper.c) */
424 /* XXX: fix it to restore all registers */
425 void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
427 TranslationBlock *tb;
432 /* XXX: hack to restore env in all cases, even if not called from
435 env = cpu_single_env;
437 unsigned long tlb_addrr, tlb_addrw;
439 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
440 tlb_addrr = env->tlb_read[is_user][index].address;
441 tlb_addrw = env->tlb_write[is_user][index].address;
445 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
446 "(0x%08lx 0x%08lx)\n", __func__, env,
447 &env->tlb_read[is_user][index], index, addr,
448 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
449 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
453 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
456 /* now we have a real cpu fault */
457 pc = (unsigned long)retaddr;
460 /* the PC is inside the translated code. It means that we have
461 a virtual CPU fault */
462 cpu_restore_state(tb, env, pc, NULL);
465 do_raise_exception_err(env->exception_index, env->error_code);
468 unsigned long tlb_addrr, tlb_addrw;
470 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
471 tlb_addrr = env->tlb_read[is_user][index].address;
472 tlb_addrw = env->tlb_write[is_user][index].address;
474 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
475 "(0x%08lx 0x%08lx)\n", __func__, env,
476 &env->tlb_read[is_user][index], index, addr,
477 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
478 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
484 void cpu_ppc_init_mmu(CPUState *env)
486 /* Nothing to do: all translation are disabled */
490 /* Perform address translation */
491 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
492 int is_user, int is_softmmu)
496 int exception = 0, error_code = 0;
500 // printf("%s 0\n", __func__);
501 access_type = env->access_type;
502 if (env->user_mode_only) {
503 /* user mode only emulation */
507 /* NASTY BUG workaround */
508 if (access_type == ACCESS_CODE && rw) {
509 printf("%s: ERROR WRITE CODE ACCESS\n", __func__);
510 access_type = ACCESS_INT;
512 ret = get_physical_address(env, &physical, &prot,
513 address, rw, access_type);
515 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
516 is_user, is_softmmu);
517 } else if (ret < 0) {
519 #if defined (DEBUG_MMU)
521 cpu_ppc_dump_state(env, logfile, 0);
523 if (access_type == ACCESS_CODE) {
524 exception = EXCP_ISI;
527 /* No matches in page tables */
528 error_code = EXCP_ISI_TRANSLATE;
531 /* Access rights violation */
532 error_code = EXCP_ISI_PROT;
535 /* No execute protection violation */
536 error_code = EXCP_ISI_NOEXEC;
539 /* Direct store exception */
540 /* No code fetch is allowed in direct-store areas */
541 error_code = EXCP_ISI_DIRECT;
545 exception = EXCP_DSI;
548 /* No matches in page tables */
549 error_code = EXCP_DSI_TRANSLATE;
552 /* Access rights violation */
553 error_code = EXCP_DSI_PROT;
556 /* Direct store exception */
557 switch (access_type) {
559 /* Floating point load/store */
560 exception = EXCP_ALIGN;
561 error_code = EXCP_ALIGN_FP;
564 /* lwarx, ldarx or srwcx. */
565 exception = EXCP_DSI;
566 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
570 exception = EXCP_DSI;
571 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
575 printf("DSI: invalid exception (%d)\n", ret);
576 exception = EXCP_PROGRAM;
577 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
582 error_code |= EXCP_DSI_STORE;
583 /* Store fault address */
584 env->spr[DAR] = address;
587 printf("%s: set exception to %d %02x\n",
588 __func__, exception, error_code);
590 env->exception_index = exception;
591 env->error_code = error_code;
598 uint32_t _load_xer (CPUState *env)
600 return (xer_so << XER_SO) |
606 void _store_xer (CPUState *env, uint32_t value)
608 xer_so = (value >> XER_SO) & 0x01;
609 xer_ov = (value >> XER_OV) & 0x01;
610 xer_ca = (value >> XER_CA) & 0x01;
611 xer_bc = (value >> XER_BC) & 0x1f;
614 uint32_t _load_msr (CPUState *env)
616 return (msr_pow << MSR_POW) |
617 (msr_ile << MSR_ILE) |
622 (msr_fe0 << MSR_FE0) |
625 (msr_fe1 << MSR_FE1) |
633 void _store_msr (CPUState *env, uint32_t value)
636 if (((value >> MSR_IR) & 0x01) != msr_ir ||
637 ((value >> MSR_DR) & 0x01) != msr_dr)
639 /* Flush all tlb when changing translation mode or privilege level */
643 msr_pow = (value >> MSR_POW) & 0x03;
644 msr_ile = (value >> MSR_ILE) & 0x01;
645 msr_ee = (value >> MSR_EE) & 0x01;
646 msr_pr = (value >> MSR_PR) & 0x01;
647 msr_fp = (value >> MSR_FP) & 0x01;
648 msr_me = (value >> MSR_ME) & 0x01;
649 msr_fe0 = (value >> MSR_FE0) & 0x01;
650 msr_se = (value >> MSR_SE) & 0x01;
651 msr_be = (value >> MSR_BE) & 0x01;
652 msr_fe1 = (value >> MSR_FE1) & 0x01;
653 msr_ip = (value >> MSR_IP) & 0x01;
654 msr_ir = (value >> MSR_IR) & 0x01;
655 msr_dr = (value >> MSR_DR) & 0x01;
656 msr_ri = (value >> MSR_RI) & 0x01;
657 msr_le = (value >> MSR_LE) & 0x01;
660 void do_interrupt (CPUState *env)
662 #if defined (CONFIG_USER_ONLY)
663 env->exception_index |= 0x100;
666 int excp = env->exception_index;
668 msr = _load_msr(env);
669 #if defined (DEBUG_EXCEPTIONS)
670 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
673 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
674 env->nip, excp << 8, env->error_code);
677 cpu_ppc_dump_state(env, logfile, 0);
680 /* Generate informations in save/restore registers */
683 #if defined (USE_OPEN_FIRMWARE)
684 env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
688 #if defined (USE_OPEN_FIRMWARE)
689 printf("RTAS call !\n");
690 env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
691 printf("RTAS call done\n");
696 #if defined (DEBUG_EXCEPTIONS)
697 printf("%s: escape EXCP_NONE\n", __func__);
704 case EXCP_MACHINE_CHECK:
706 cpu_abort(env, "Machine check exception while not allowed\n");
711 /* Store exception cause */
712 /* data location address has been stored
713 * when the fault has been detected
717 if (env->error_code & EXCP_DSI_TRANSLATE)
718 env->spr[DSISR] |= 0x40000000;
719 else if (env->error_code & EXCP_DSI_PROT)
720 env->spr[DSISR] |= 0x08000000;
721 else if (env->error_code & EXCP_DSI_NOTSUP) {
722 env->spr[DSISR] |= 0x80000000;
723 if (env->error_code & EXCP_DSI_DIRECT)
724 env->spr[DSISR] |= 0x04000000;
726 if (env->error_code & EXCP_DSI_STORE)
727 env->spr[DSISR] |= 0x02000000;
728 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
729 env->spr[DSISR] |= 0x00400000;
730 if (env->error_code & EXCP_DSI_ECXW)
731 env->spr[DSISR] |= 0x00100000;
732 #if defined (DEBUG_EXCEPTIONS)
734 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
735 env->spr[DSISR], env->spr[DAR]);
737 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
738 env->spr[DSISR], env->spr[DAR], env->nip);
743 /* Store exception cause */
745 if (env->error_code == EXCP_ISI_TRANSLATE)
747 else if (env->error_code == EXCP_ISI_NOEXEC ||
748 env->error_code == EXCP_ISI_GUARD ||
749 env->error_code == EXCP_ISI_DIRECT)
753 #if defined (DEBUG_EXCEPTIONS)
755 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
758 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
759 msr, env->nip, env->spr[V_TBL]);
765 #if defined (DEBUG_EXCEPTIONS)
767 fprintf(logfile, "Skipping hardware interrupt\n");
771 do_raise_exception(EXCP_EXTERNAL);
776 /* Store exception cause */
777 /* Get rS/rD and rA from faulting opcode */
779 (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
780 /* data location address has been stored
781 * when the fault has been detected
786 switch (env->error_code & ~0xF) {
788 if (msr_fe0 == 0 && msr_fe1 == 0) {
789 #if defined (DEBUG_EXCEPTIONS)
790 printf("Ignore floating point exception\n");
796 env->fpscr[7] |= 0x8;
797 /* Finally, update FEX */
798 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
799 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
800 env->fpscr[7] |= 0x4;
803 // printf("Invalid instruction at 0x%08x\n", env->nip);
813 /* Should never occur */
823 do_raise_exception(EXCP_DECR);
828 #if defined (DEBUG_EXCEPTIONS)
831 fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
832 env->gpr[0], env->gpr[3], env->gpr[4],
833 env->gpr[5], env->gpr[6]);
835 printf("syscall %d from 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
836 env->gpr[0], env->nip, env->gpr[3], env->gpr[4],
837 env->gpr[5], env->gpr[6]);
853 /* Restore user-mode state */
855 #if defined (DEBUG_EXCEPTIONS)
857 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
861 /* SRR0 is set to current instruction */
862 env->spr[SRR0] = (uint32_t)env->nip - 4;
865 /* SRR0 is set to next instruction */
866 env->spr[SRR0] = (uint32_t)env->nip;
869 env->spr[SRR1] = msr;
870 /* reload MSR with correct bits */
883 /* Jump to handler */
884 env->nip = excp << 8;
885 env->exception_index = EXCP_NONE;
886 /* Invalidate all TLB as we may have changed translation mode */
888 /* ensure that no TB jump will be modified as
889 the program flow was changed */
896 env->exception_index = -1;