2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #if defined (USE_OPEN_FIRMWARE)
28 //#define DEBUG_EXCEPTIONS
30 /*****************************************************************************/
31 /* PPC MMU emulation */
32 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
33 int is_user, int is_softmmu);
35 /* Perform BAT hit & translation */
36 static int get_bat (CPUState *env, uint32_t *real, int *prot,
37 uint32_t virtual, int rw, int type)
39 uint32_t *BATlt, *BATut, *BATu, *BATl;
40 uint32_t base, BEPIl, BEPIu, bl;
44 #if defined (DEBUG_BATS)
46 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
47 type == ACCESS_CODE ? 'I' : 'D', virtual);
60 #if defined (DEBUG_BATS)
62 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
63 type == ACCESS_CODE ? 'I' : 'D', virtual);
66 base = virtual & 0xFFFC0000;
67 for (i = 0; i < 4; i++) {
70 BEPIu = *BATu & 0xF0000000;
71 BEPIl = *BATu & 0x0FFE0000;
72 bl = (*BATu & 0x00001FFC) << 15;
73 #if defined (DEBUG_BATS)
75 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
76 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
80 if ((virtual & 0xF0000000) == BEPIu &&
81 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
83 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
84 (msr_pr == 1 && (*BATu & 0x00000001))) {
85 /* Get physical address */
86 *real = (*BATl & 0xF0000000) |
87 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
88 (virtual & 0x0001F000);
89 if (*BATl & 0x00000001)
91 if (*BATl & 0x00000002)
92 *prot = PAGE_WRITE | PAGE_READ;
93 #if defined (DEBUG_BATS)
95 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
96 i, *real, *prot & PAGE_READ ? 'R' : '-',
97 *prot & PAGE_WRITE ? 'W' : '-');
106 #if defined (DEBUG_BATS)
107 printf("no BAT match for 0x%08x:\n", virtual);
108 for (i = 0; i < 4; i++) {
111 BEPIu = *BATu & 0xF0000000;
112 BEPIl = *BATu & 0x0FFE0000;
113 bl = (*BATu & 0x00001FFC) << 15;
114 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
115 "0x%08x 0x%08x 0x%08x\n",
116 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
117 *BATu, *BATl, BEPIu, BEPIl, bl);
125 /* PTE table lookup */
126 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
127 int h, int key, int rw)
129 uint32_t pte0, pte1, keep = 0, access = 0;
130 int i, good = -1, store = 0;
131 int ret = -1; /* No entry found */
133 for (i = 0; i < 8; i++) {
134 pte0 = ldl_raw(phys_ram_base + base + (i * 8));
135 pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
136 #if defined (DEBUG_MMU)
138 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
139 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
140 pte0 >> 31, h, (pte0 >> 6) & 1, va);
143 /* Check validity and table match */
144 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
145 /* Check vsid & api */
146 if ((pte0 & 0x7FFFFFBF) == va) {
151 /* All matches should have equal RPN, WIMG & PP */
152 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
154 fprintf(logfile, "Bad RPN/WIMG/PP\n");
158 /* Check access rights */
161 if ((pte1 & 0x00000003) != 0x3)
162 access |= PAGE_WRITE;
164 switch (pte1 & 0x00000003) {
173 access = PAGE_READ | PAGE_WRITE;
178 if ((rw == 0 && (access & PAGE_READ)) ||
179 (rw == 1 && (access & PAGE_WRITE))) {
180 #if defined (DEBUG_MMU)
182 fprintf(logfile, "PTE access granted !\n");
188 /* Access right violation */
190 #if defined (DEBUG_MMU)
192 fprintf(logfile, "PTE access rejected\n");
201 *RPN = keep & 0xFFFFF000;
202 #if defined (DEBUG_MMU)
204 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
208 /* Update page flags */
209 if (!(keep & 0x00000100)) {
214 if (!(keep & 0x00000080)) {
215 if (rw && ret == 0) {
220 /* Force page fault for first write access */
221 *prot &= ~PAGE_WRITE;
225 stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
232 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
234 return (sdr1 & 0xFFFF0000) | (hash & mask);
237 /* Perform segment based translation */
238 static int get_segment (CPUState *env, uint32_t *real, int *prot,
239 uint32_t virtual, int rw, int type)
241 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
247 sr = env->sr[virtual >> 28];
248 #if defined (DEBUG_MMU)
250 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
251 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
252 virtual, virtual >> 28, sr, env->nip,
253 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
256 key = (((sr & 0x20000000) && msr_pr == 1) ||
257 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
258 if ((sr & 0x80000000) == 0) {
259 #if defined (DEBUG_MMU)
261 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
262 key, sr & 0x10000000);
264 /* Check if instruction fetch is allowed, if needed */
265 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
266 /* Page address translation */
267 vsid = sr & 0x00FFFFFF;
268 pgidx = (virtual >> 12) & 0xFFFF;
270 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
271 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
272 pg_addr = get_pgaddr(sdr, hash, mask);
273 ptem = (vsid << 7) | (pgidx >> 10);
274 #if defined (DEBUG_MMU)
276 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
277 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
281 /* Primary table lookup */
282 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
284 /* Secondary table lookup */
285 hash = (~hash) & 0x01FFFFC0;
286 pg_addr = get_pgaddr(sdr, hash, mask);
287 #if defined (DEBUG_MMU)
288 if (virtual != 0xEFFFFFFF && loglevel > 0) {
289 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
290 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
294 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
299 #if defined (DEBUG_MMU)
301 fprintf(logfile, "No access allowed\n");
306 #if defined (DEBUG_MMU)
308 fprintf(logfile, "direct store...\n");
310 /* Direct-store segment : absolutely *BUGGY* for now */
313 /* Integer load/store : only access allowed */
316 /* No code fetch is allowed in direct-store areas */
319 /* Floating point load/store */
322 /* lwarx, ldarx or srwcx. */
325 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
326 /* Should make the instruction do no-op.
327 * As it already do no-op, it's quite easy :-)
336 fprintf(logfile, "ERROR: instruction should not need "
337 "address translation\n");
339 printf("ERROR: instruction should not need "
340 "address translation\n");
343 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
354 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
355 uint32_t address, int rw, int access_type)
360 fprintf(logfile, "%s\n", __func__);
363 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
364 (access_type != ACCESS_CODE && msr_dr == 0)) {
365 /* No address translation */
366 *physical = address & ~0xFFF;
367 *prot = PAGE_READ | PAGE_WRITE;
370 /* Try to find a BAT */
371 ret = get_bat(env, physical, prot, address, rw, access_type);
373 /* We didn't match any BAT entry */
374 ret = get_segment(env, physical, prot, address, rw, access_type);
379 fprintf(logfile, "%s address %08x => %08x\n",
380 __func__, address, *physical);
386 #if defined(CONFIG_USER_ONLY)
387 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
392 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
397 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
403 #if !defined(CONFIG_USER_ONLY)
405 #define MMUSUFFIX _mmu
406 #define GETPC() (__builtin_return_address(0))
409 #include "softmmu_template.h"
412 #include "softmmu_template.h"
415 #include "softmmu_template.h"
418 #include "softmmu_template.h"
420 /* try to fill the TLB and return an exception if error. If retaddr is
421 NULL, it means that the function was called in C code (i.e. not
422 from generated code or from helper.c) */
423 /* XXX: fix it to restore all registers */
424 void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
426 TranslationBlock *tb;
431 /* XXX: hack to restore env in all cases, even if not called from
434 env = cpu_single_env;
437 unsigned long tlb_addrr, tlb_addrw;
439 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
440 tlb_addrr = env->tlb_read[is_user][index].address;
441 tlb_addrw = env->tlb_write[is_user][index].address;
444 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
445 "(0x%08lx 0x%08lx)\n", __func__, env,
446 &env->tlb_read[is_user][index], index, addr,
447 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
448 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
452 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
455 /* now we have a real cpu fault */
456 pc = (unsigned long)retaddr;
459 /* the PC is inside the translated code. It means that we have
460 a virtual CPU fault */
461 cpu_restore_state(tb, env, pc, NULL);
464 do_raise_exception_err(env->exception_index, env->error_code);
468 unsigned long tlb_addrr, tlb_addrw;
470 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
471 tlb_addrr = env->tlb_read[is_user][index].address;
472 tlb_addrw = env->tlb_write[is_user][index].address;
473 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
474 "(0x%08lx 0x%08lx)\n", __func__, env,
475 &env->tlb_read[is_user][index], index, addr,
476 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
477 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
483 void cpu_ppc_init_mmu(CPUState *env)
485 /* Nothing to do: all translation are disabled */
489 /* Perform address translation */
490 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
491 int is_user, int is_softmmu)
495 int exception = 0, error_code = 0;
502 access_type = ACCESS_CODE;
505 /* XXX: put correct access by using cpu_restore_state()
507 access_type = ACCESS_INT;
508 // access_type = env->access_type;
510 if (env->user_mode_only) {
511 /* user mode only emulation */
515 ret = get_physical_address(env, &physical, &prot,
516 address, rw, access_type);
518 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
519 is_user, is_softmmu);
520 } else if (ret < 0) {
522 #if defined (DEBUG_MMU)
524 cpu_dump_state(env, logfile, fprintf, 0);
526 if (access_type == ACCESS_CODE) {
527 exception = EXCP_ISI;
530 /* No matches in page tables */
531 error_code = EXCP_ISI_TRANSLATE;
534 /* Access rights violation */
535 error_code = EXCP_ISI_PROT;
538 /* No execute protection violation */
539 error_code = EXCP_ISI_NOEXEC;
542 /* Direct store exception */
543 /* No code fetch is allowed in direct-store areas */
544 error_code = EXCP_ISI_DIRECT;
548 exception = EXCP_DSI;
551 /* No matches in page tables */
552 error_code = EXCP_DSI_TRANSLATE;
555 /* Access rights violation */
556 error_code = EXCP_DSI_PROT;
559 /* Direct store exception */
560 switch (access_type) {
562 /* Floating point load/store */
563 exception = EXCP_ALIGN;
564 error_code = EXCP_ALIGN_FP;
567 /* lwarx, ldarx or srwcx. */
568 exception = EXCP_DSI;
569 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
573 exception = EXCP_DSI;
574 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
578 printf("DSI: invalid exception (%d)\n", ret);
579 exception = EXCP_PROGRAM;
580 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
585 error_code |= EXCP_DSI_STORE;
586 /* Store fault address */
587 env->spr[DAR] = address;
590 printf("%s: set exception to %d %02x\n",
591 __func__, exception, error_code);
593 env->exception_index = exception;
594 env->error_code = error_code;
600 uint32_t _load_xer (CPUState *env)
602 return (xer_so << XER_SO) |
608 void _store_xer (CPUState *env, uint32_t value)
610 xer_so = (value >> XER_SO) & 0x01;
611 xer_ov = (value >> XER_OV) & 0x01;
612 xer_ca = (value >> XER_CA) & 0x01;
613 xer_bc = (value >> XER_BC) & 0x1f;
616 uint32_t _load_msr (CPUState *env)
618 return (msr_pow << MSR_POW) |
619 (msr_ile << MSR_ILE) |
624 (msr_fe0 << MSR_FE0) |
627 (msr_fe1 << MSR_FE1) |
635 void _store_msr (CPUState *env, uint32_t value)
638 if (((value >> MSR_IR) & 0x01) != msr_ir ||
639 ((value >> MSR_DR) & 0x01) != msr_dr)
641 /* Flush all tlb when changing translation mode or privilege level */
645 msr_pow = (value >> MSR_POW) & 0x03;
646 msr_ile = (value >> MSR_ILE) & 0x01;
647 msr_ee = (value >> MSR_EE) & 0x01;
648 msr_pr = (value >> MSR_PR) & 0x01;
649 msr_fp = (value >> MSR_FP) & 0x01;
650 msr_me = (value >> MSR_ME) & 0x01;
651 msr_fe0 = (value >> MSR_FE0) & 0x01;
652 msr_se = (value >> MSR_SE) & 0x01;
653 msr_be = (value >> MSR_BE) & 0x01;
654 msr_fe1 = (value >> MSR_FE1) & 0x01;
655 msr_ip = (value >> MSR_IP) & 0x01;
656 msr_ir = (value >> MSR_IR) & 0x01;
657 msr_dr = (value >> MSR_DR) & 0x01;
658 msr_ri = (value >> MSR_RI) & 0x01;
659 msr_le = (value >> MSR_LE) & 0x01;
662 void do_interrupt (CPUState *env)
664 #if defined (CONFIG_USER_ONLY)
665 env->exception_index |= 0x100;
668 int excp = env->exception_index;
670 msr = _load_msr(env);
671 #if defined (DEBUG_EXCEPTIONS)
672 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
675 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
676 env->nip, excp << 8, env->error_code);
679 cpu_dump_state(env, logfile, fprintf, 0);
682 if (loglevel & CPU_LOG_INT) {
683 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
684 env->nip, excp << 8, env->error_code);
686 /* Generate informations in save/restore registers */
689 #if defined (USE_OPEN_FIRMWARE)
690 env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
694 #if defined (USE_OPEN_FIRMWARE)
695 printf("RTAS call !\n");
696 env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
697 printf("RTAS call done\n");
702 #if defined (DEBUG_EXCEPTIONS)
703 printf("%s: escape EXCP_NONE\n", __func__);
710 case EXCP_MACHINE_CHECK:
712 cpu_abort(env, "Machine check exception while not allowed\n");
717 /* Store exception cause */
718 /* data location address has been stored
719 * when the fault has been detected
723 if (env->error_code & EXCP_DSI_TRANSLATE)
724 env->spr[DSISR] |= 0x40000000;
725 else if (env->error_code & EXCP_DSI_PROT)
726 env->spr[DSISR] |= 0x08000000;
727 else if (env->error_code & EXCP_DSI_NOTSUP) {
728 env->spr[DSISR] |= 0x80000000;
729 if (env->error_code & EXCP_DSI_DIRECT)
730 env->spr[DSISR] |= 0x04000000;
732 if (env->error_code & EXCP_DSI_STORE)
733 env->spr[DSISR] |= 0x02000000;
734 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
735 env->spr[DSISR] |= 0x00400000;
736 if (env->error_code & EXCP_DSI_ECXW)
737 env->spr[DSISR] |= 0x00100000;
738 #if defined (DEBUG_EXCEPTIONS)
740 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
741 env->spr[DSISR], env->spr[DAR]);
743 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
744 env->spr[DSISR], env->spr[DAR], env->nip);
749 /* Store exception cause */
751 if (env->error_code == EXCP_ISI_TRANSLATE)
753 else if (env->error_code == EXCP_ISI_NOEXEC ||
754 env->error_code == EXCP_ISI_GUARD ||
755 env->error_code == EXCP_ISI_DIRECT)
759 #if defined (DEBUG_EXCEPTIONS)
761 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
764 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
765 msr, env->nip, env->spr[V_TBL]);
771 #if defined (DEBUG_EXCEPTIONS)
773 fprintf(logfile, "Skipping hardware interrupt\n");
777 do_raise_exception(EXCP_EXTERNAL);
782 /* Store exception cause */
783 /* Get rS/rD and rA from faulting opcode */
785 (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
786 /* data location address has been stored
787 * when the fault has been detected
792 switch (env->error_code & ~0xF) {
794 if (msr_fe0 == 0 && msr_fe1 == 0) {
795 #if defined (DEBUG_EXCEPTIONS)
796 printf("Ignore floating point exception\n");
802 env->fpscr[7] |= 0x8;
803 /* Finally, update FEX */
804 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
805 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
806 env->fpscr[7] |= 0x4;
809 // printf("Invalid instruction at 0x%08x\n", env->nip);
819 /* Should never occur */
829 do_raise_exception(EXCP_DECR);
834 if (loglevel & CPU_LOG_INT) {
835 fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
836 env->gpr[0], env->gpr[3], env->gpr[4],
837 env->gpr[5], env->gpr[6]);
838 if (env->gpr[0] == 4 && env->gpr[3] == 1) {
842 fprintf(logfile, "write: ");
847 for(i = 0; i < len; i++) {
849 cpu_memory_rw_debug(env, addr + i, &c, 1, 0);
850 if (c < 32 || c > 126)
852 fprintf(logfile, "%c", c);
854 fprintf(logfile, "\n");
869 /* Restore user-mode state */
871 #if defined (DEBUG_EXCEPTIONS)
873 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
877 /* SRR0 is set to current instruction */
878 env->spr[SRR0] = (uint32_t)env->nip - 4;
881 /* SRR0 is set to next instruction */
882 env->spr[SRR0] = (uint32_t)env->nip;
885 env->spr[SRR1] = msr;
886 /* reload MSR with correct bits */
899 /* Jump to handler */
900 env->nip = excp << 8;
901 env->exception_index = EXCP_NONE;
902 /* Invalidate all TLB as we may have changed translation mode */
904 /* ensure that no TB jump will be modified as
905 the program flow was changed */
912 env->exception_index = -1;