2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #if defined (USE_OPEN_FIRMWARE)
30 //#define DEBUG_EXCEPTIONS
32 extern FILE *logfile, *stdout, *stderr;
36 void cpu_loop_exit(void)
38 longjmp(env->jmp_env, 1);
41 void do_process_exceptions (void)
46 int check_exception_state (CPUState *env)
50 /* Process PPC exceptions */
51 for (i = 1; i < EXCP_PPC_MAX; i++) {
52 if (env->exceptions & (1 << i)) {
60 if (env->errors[EXCP_PROGRAM] == EXCP_FP &&
61 msr_fe0 == 0 && msr_fe1 == 0)
67 env->exception_index = i;
68 env->error_code = env->errors[i];
76 /*****************************************************************************/
77 /* PPC MMU emulation */
78 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
79 int is_user, int is_softmmu);
81 /* Perform BAT hit & translation */
82 static int get_bat (CPUState *env, uint32_t *real, int *prot,
83 uint32_t virtual, int rw, int type)
85 uint32_t *BATlt, *BATut, *BATu, *BATl;
86 uint32_t base, BEPIl, BEPIu, bl;
90 #if defined (DEBUG_BATS)
92 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
93 type == ACCESS_CODE ? 'I' : 'D', virtual);
102 BATlt = env->DBAT[1];
103 BATut = env->DBAT[0];
106 #if defined (DEBUG_BATS)
108 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
109 type == ACCESS_CODE ? 'I' : 'D', virtual);
112 base = virtual & 0xFFFC0000;
113 for (i = 0; i < 4; i++) {
116 BEPIu = *BATu & 0xF0000000;
117 BEPIl = *BATu & 0x0FFE0000;
118 bl = (*BATu & 0x00001FFC) << 15;
119 #if defined (DEBUG_BATS)
121 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
122 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
126 if ((virtual & 0xF0000000) == BEPIu &&
127 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
129 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
130 (msr_pr == 1 && (*BATu & 0x00000001))) {
131 /* Get physical address */
132 *real = (*BATl & 0xF0000000) |
133 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
134 (virtual & 0x0001F000);
135 if (*BATl & 0x00000001)
137 if (*BATl & 0x00000002)
138 *prot = PROT_WRITE | PROT_READ;
139 #if defined (DEBUG_BATS)
141 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
142 i, *real, *prot & PROT_READ ? 'R' : '-',
143 *prot & PROT_WRITE ? 'W' : '-');
152 #if defined (DEBUG_BATS)
153 printf("no BAT match for 0x%08x:\n", virtual);
154 for (i = 0; i < 4; i++) {
157 BEPIu = *BATu & 0xF0000000;
158 BEPIl = *BATu & 0x0FFE0000;
159 bl = (*BATu & 0x00001FFC) << 15;
160 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
161 "0x%08x 0x%08x 0x%08x\n",
162 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
163 *BATu, *BATl, BEPIu, BEPIl, bl);
166 env->spr[DAR] = virtual;
172 /* PTE table lookup */
173 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
174 int h, int key, int rw)
176 uint32_t pte0, pte1, keep = 0, access = 0;
177 int i, good = -1, store = 0;
178 int ret = -1; /* No entry found */
180 for (i = 0; i < 8; i++) {
181 pte0 = ldl_raw(phys_ram_base + base + (i * 8));
182 pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
183 #if defined (DEBUG_MMU)
185 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
186 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
187 pte0 >> 31, h, (pte0 >> 6) & 1, va);
190 /* Check validity and table match */
191 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
192 /* Check vsid & api */
193 if ((pte0 & 0x7FFFFFBF) == va) {
198 /* All matches should have equal RPN, WIMG & PP */
199 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
201 fprintf(logfile, "Bad RPN/WIMG/PP\n");
205 /* Check access rights */
208 if ((pte1 & 0x00000003) != 0x3)
209 access |= PROT_WRITE;
211 switch (pte1 & 0x00000003) {
220 access = PROT_READ | PROT_WRITE;
225 if ((rw == 0 && (access & PROT_READ)) ||
226 (rw == 1 && (access & PROT_WRITE))) {
227 #if defined (DEBUG_MMU)
229 fprintf(logfile, "PTE access granted !\n");
235 /* Access right violation */
237 #if defined (DEBUG_MMU)
239 fprintf(logfile, "PTE access rejected\n");
248 *RPN = keep & 0xFFFFF000;
249 #if defined (DEBUG_MMU)
251 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
255 /* Update page flags */
256 if (!(keep & 0x00000100)) {
261 if (!(keep & 0x00000080)) {
262 if (rw && ret == 0) {
267 /* Force page fault for first write access */
268 *prot &= ~PROT_WRITE;
272 stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
279 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
281 return (sdr1 & 0xFFFF0000) | (hash & mask);
284 /* Perform segment based translation */
285 static int get_segment (CPUState *env, uint32_t *real, int *prot,
286 uint32_t virtual, int rw, int type)
288 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
294 sr = env->sr[virtual >> 28];
295 #if defined (DEBUG_MMU)
297 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
298 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
299 virtual, virtual >> 28, sr, env->nip,
300 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
303 key = (((sr & 0x20000000) && msr_pr == 1) ||
304 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
305 if ((sr & 0x80000000) == 0) {
306 #if defined (DEBUG_MMU)
308 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
309 key, sr & 0x10000000);
311 /* Check if instruction fetch is allowed, if needed */
312 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
313 /* Page address translation */
314 vsid = sr & 0x00FFFFFF;
315 pgidx = (virtual >> 12) & 0xFFFF;
317 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
318 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
319 pg_addr = get_pgaddr(sdr, hash, mask);
320 ptem = (vsid << 7) | (pgidx >> 10);
321 #if defined (DEBUG_MMU)
323 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
324 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
328 /* Primary table lookup */
329 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
331 /* Secondary table lookup */
332 hash = (~hash) & 0x01FFFFC0;
333 pg_addr = get_pgaddr(sdr, hash, mask);
334 #if defined (DEBUG_MMU)
335 if (virtual != 0xEFFFFFFF && loglevel > 0) {
336 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
337 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
341 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
346 #if defined (DEBUG_MMU)
348 fprintf(logfile, "No access allowed\n");
353 #if defined (DEBUG_MMU)
355 fprintf(logfile, "direct store...\n");
357 /* Direct-store segment : absolutely *BUGGY* for now */
360 /* Integer load/store : only access allowed */
363 /* No code fetch is allowed in direct-store areas */
366 /* Floating point load/store */
369 /* lwarx, ldarx or srwcx. */
372 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
373 /* Should make the instruction do no-op.
374 * As it already do no-op, it's quite easy :-)
383 fprintf(logfile, "ERROR: instruction should not need "
384 "address translation\n");
386 printf("ERROR: instruction should not need "
387 "address translation\n");
390 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
401 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
402 uint32_t address, int rw, int access_type)
407 fprintf(logfile, "%s\n", __func__);
410 if ((access_type == ACCESS_CODE && msr_ir == 0) || msr_dr == 0) {
411 /* No address translation */
412 *physical = address & ~0xFFF;
413 *prot = PROT_READ | PROT_WRITE;
416 /* Try to find a BAT */
417 ret = get_bat(env, physical, prot, address, rw, access_type);
419 /* We didn't match any BAT entry */
420 ret = get_segment(env, physical, prot, address, rw, access_type);
424 fprintf(logfile, "%s address %08x => %08x\n",
425 __func__, address, *physical);
431 #if defined(CONFIG_USER_ONLY)
432 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
437 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
442 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
448 #if !defined(CONFIG_USER_ONLY)
450 #define MMUSUFFIX _mmu
451 #define GETPC() (__builtin_return_address(0))
454 #include "softmmu_template.h"
457 #include "softmmu_template.h"
460 #include "softmmu_template.h"
463 #include "softmmu_template.h"
465 /* try to fill the TLB and return an exception if error. If retaddr is
466 NULL, it means that the function was called in C code (i.e. not
467 from generated code or from helper.c) */
468 /* XXX: fix it to restore all registers */
469 void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
471 TranslationBlock *tb;
476 /* XXX: hack to restore env in all cases, even if not called from
479 env = cpu_single_env;
481 unsigned long tlb_addrr, tlb_addrw;
483 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
484 tlb_addrr = env->tlb_read[is_user][index].address;
485 tlb_addrw = env->tlb_write[is_user][index].address;
487 printf("%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
488 "(0x%08lx 0x%08lx)\n", __func__, env,
489 &env->tlb_read[is_user][index], index, addr,
490 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
491 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
494 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
497 /* now we have a real cpu fault */
498 pc = (unsigned long)retaddr;
501 /* the PC is inside the translated code. It means that we have
502 a virtual CPU fault */
503 cpu_restore_state(tb, env, pc, NULL);
506 do_queue_exception_err(env->exception_index, env->error_code);
507 do_process_exceptions();
510 unsigned long tlb_addrr, tlb_addrw;
512 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
513 tlb_addrr = env->tlb_read[is_user][index].address;
514 tlb_addrw = env->tlb_write[is_user][index].address;
516 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
517 "(0x%08lx 0x%08lx)\n", __func__, env,
518 &env->tlb_read[is_user][index], index, addr,
519 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
520 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
526 void cpu_ppc_init_mmu(CPUState *env)
528 /* Nothing to do: all translation are disabled */
532 /* Perform address translation */
533 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
534 int is_user, int is_softmmu)
538 int exception = 0, error_code = 0;
542 // printf("%s 0\n", __func__);
543 access_type = env->access_type;
544 if (env->user_mode_only) {
545 /* user mode only emulation */
549 /* NASTY BUG workaround */
550 if (access_type == ACCESS_CODE && rw) {
551 // printf("%s: ERROR WRITE CODE ACCESS\n", __func__);
552 access_type = ACCESS_INT;
554 ret = get_physical_address(env, &physical, &prot,
555 address, rw, access_type);
557 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
558 is_user, is_softmmu);
559 } else if (ret < 0) {
561 #if defined (DEBUG_MMU)
563 cpu_ppc_dump_state(env, logfile, 0);
565 if (access_type == ACCESS_CODE) {
566 exception = EXCP_ISI;
569 /* No matches in page tables */
570 error_code = EXCP_ISI_TRANSLATE;
573 /* Access rights violation */
574 error_code = EXCP_ISI_PROT;
577 /* No execute protection violation */
578 error_code = EXCP_ISI_NOEXEC;
581 /* Direct store exception */
582 /* No code fetch is allowed in direct-store areas */
583 error_code = EXCP_ISI_DIRECT;
587 exception = EXCP_DSI;
590 /* No matches in page tables */
591 error_code = EXCP_DSI_TRANSLATE;
594 /* Access rights violation */
595 error_code = EXCP_DSI_PROT;
598 /* Direct store exception */
599 switch (access_type) {
601 /* Floating point load/store */
602 exception = EXCP_ALIGN;
603 error_code = EXCP_ALIGN_FP;
606 /* lwarx, ldarx or srwcx. */
607 exception = EXCP_DSI;
608 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
612 exception = EXCP_DSI;
613 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
617 printf("DSI: invalid exception (%d)\n", ret);
618 exception = EXCP_PROGRAM;
619 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
624 error_code |= EXCP_DSI_STORE;
625 /* Store fault address */
626 env->spr[DAR] = address;
629 printf("%s: set exception to %d %02x\n",
630 __func__, exception, error_code);
632 env->exception_index = exception;
633 env->error_code = error_code;
640 uint32_t _load_xer (CPUState *env)
642 return (xer_so << XER_SO) |
648 void _store_xer (CPUState *env, uint32_t value)
650 xer_so = (value >> XER_SO) & 0x01;
651 xer_ov = (value >> XER_OV) & 0x01;
652 xer_ca = (value >> XER_CA) & 0x01;
653 xer_bc = (value >> XER_BC) & 0x1f;
656 uint32_t _load_msr (CPUState *env)
658 return (msr_pow << MSR_POW) |
659 (msr_ile << MSR_ILE) |
664 (msr_fe0 << MSR_FE0) |
667 (msr_fe1 << MSR_FE1) |
675 void _store_msr (CPUState *env, uint32_t value)
677 if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
678 ((T0 >> MSR_DR) & 0x01) != msr_dr) {
679 /* Flush all tlb when changing translation mode or privilege level */
682 msr_pow = (value >> MSR_POW) & 0x03;
683 msr_ile = (value >> MSR_ILE) & 0x01;
684 msr_ee = (value >> MSR_EE) & 0x01;
685 msr_pr = (value >> MSR_PR) & 0x01;
686 msr_fp = (value >> MSR_FP) & 0x01;
687 msr_me = (value >> MSR_ME) & 0x01;
688 msr_fe0 = (value >> MSR_FE0) & 0x01;
689 msr_se = (value >> MSR_SE) & 0x01;
690 msr_be = (value >> MSR_BE) & 0x01;
691 msr_fe1 = (value >> MSR_FE1) & 0x01;
692 msr_ip = (value >> MSR_IP) & 0x01;
693 msr_ir = (value >> MSR_IR) & 0x01;
694 msr_dr = (value >> MSR_DR) & 0x01;
695 msr_ri = (value >> MSR_RI) & 0x01;
696 msr_le = (value >> MSR_LE) & 0x01;
699 void do_interrupt (CPUState *env)
701 #if defined (CONFIG_USER_ONLY)
702 env->exception_index |= 0x100;
705 int excp = env->exception_index;
707 /* Dequeue PPC exceptions */
708 if (excp < EXCP_PPC_MAX)
709 env->exceptions &= ~(1 << excp);
710 msr = _load_msr(env);
711 #if defined (DEBUG_EXCEPTIONS)
712 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
715 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
716 env->nip, excp << 8, env->error_code);
719 cpu_ppc_dump_state(env, logfile, 0);
722 /* Generate informations in save/restore registers */
725 #if defined (USE_OPEN_FIRMWARE)
726 env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
730 #if defined (USE_OPEN_FIRMWARE)
731 printf("RTAS call !\n");
732 env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
733 printf("RTAS call done\n");
738 #if defined (DEBUG_EXCEPTIONS)
739 printf("%s: escape EXCP_NONE\n", __func__);
746 case EXCP_MACHINE_CHECK:
748 printf("Machine check exception while not allowed !\n");
751 "Machine check exception while not allowed !\n");
758 /* Store exception cause */
759 /* data location address has been stored
760 * when the fault has been detected
764 if (env->error_code & EXCP_DSI_TRANSLATE)
765 env->spr[DSISR] |= 0x40000000;
766 else if (env->error_code & EXCP_DSI_PROT)
767 env->spr[DSISR] |= 0x08000000;
768 else if (env->error_code & EXCP_DSI_NOTSUP) {
769 env->spr[DSISR] |= 0x80000000;
770 if (env->error_code & EXCP_DSI_DIRECT)
771 env->spr[DSISR] |= 0x04000000;
773 if (env->error_code & EXCP_DSI_STORE)
774 env->spr[DSISR] |= 0x02000000;
775 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
776 env->spr[DSISR] |= 0x00400000;
777 if (env->error_code & EXCP_DSI_ECXW)
778 env->spr[DSISR] |= 0x00100000;
779 #if defined (DEBUG_EXCEPTIONS)
781 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
782 env->spr[DSISR], env->spr[DAR]);
784 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
785 env->spr[DSISR], env->spr[DAR], env->nip);
790 /* Store exception cause */
792 if (env->error_code == EXCP_ISI_TRANSLATE)
794 else if (env->error_code == EXCP_ISI_NOEXEC ||
795 env->error_code == EXCP_ISI_GUARD ||
796 env->error_code == EXCP_ISI_DIRECT)
800 #if defined (DEBUG_EXCEPTIONS)
802 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
805 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
806 msr, env->nip, env->spr[V_TBL]);
812 #if defined (DEBUG_EXCEPTIONS)
814 fprintf(logfile, "Skipping hardware interrupt\n");
818 do_queue_exception(EXCP_EXTERNAL);
823 /* Store exception cause */
824 /* Get rS/rD and rA from faulting opcode */
826 (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
827 /* data location address has been stored
828 * when the fault has been detected
833 switch (env->error_code & ~0xF) {
835 if (msr_fe0 == 0 && msr_fe1 == 0) {
836 #if defined (DEBUG_EXCEPTIONS)
837 printf("Ignore floating point exception\n");
843 env->fpscr[7] |= 0x8;
844 /* Finally, update FEX */
845 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
846 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
847 env->fpscr[7] |= 0x4;
850 printf("Invalid instruction at 0x%08x\n", env->nip);
860 /* Should never occur */
870 do_queue_exception(EXCP_DECR);
875 #if defined (DEBUG_EXCEPTIONS)
878 fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
879 env->gpr[0], env->gpr[3], env->gpr[4],
880 env->gpr[5], env->gpr[6]);
882 printf("syscall %d from 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
883 env->gpr[0], env->nip, env->gpr[3], env->gpr[4],
884 env->gpr[5], env->gpr[6]);
900 /* Restore user-mode state */
902 #if defined (DEBUG_EXCEPTIONS)
904 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
908 /* SRR0 is set to current instruction */
909 env->spr[SRR0] = (uint32_t)env->nip - 4;
912 /* SRR0 is set to next instruction */
913 env->spr[SRR0] = (uint32_t)env->nip;
916 env->spr[SRR1] = msr;
917 /* reload MSR with correct bits */
930 /* Jump to handler */
931 env->nip = excp << 8;
932 env->exception_index = EXCP_NONE;
933 /* Invalidate all TLB as we may have changed translation mode */
935 /* ensure that no TB jump will be modified as
936 the program flow was changed */