2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define DEBUG_EXCEPTIONS
34 //#define FLUSH_ALL_TLBS
36 /*****************************************************************************/
37 /* PowerPC MMU emulation */
39 /* Perform BAT hit & translation */
40 static int get_bat (CPUState *env, uint32_t *real, int *prot,
41 uint32_t virtual, int rw, int type)
43 uint32_t *BATlt, *BATut, *BATu, *BATl;
44 uint32_t base, BEPIl, BEPIu, bl;
48 #if defined (DEBUG_BATS)
50 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
51 type == ACCESS_CODE ? 'I' : 'D', virtual);
64 #if defined (DEBUG_BATS)
66 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
67 type == ACCESS_CODE ? 'I' : 'D', virtual);
70 base = virtual & 0xFFFC0000;
71 for (i = 0; i < 4; i++) {
74 BEPIu = *BATu & 0xF0000000;
75 BEPIl = *BATu & 0x0FFE0000;
76 bl = (*BATu & 0x00001FFC) << 15;
77 #if defined (DEBUG_BATS)
79 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
80 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
84 if ((virtual & 0xF0000000) == BEPIu &&
85 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
87 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
88 (msr_pr == 1 && (*BATu & 0x00000001))) {
89 /* Get physical address */
90 *real = (*BATl & 0xF0000000) |
91 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
92 (virtual & 0x0001F000);
93 if (*BATl & 0x00000001)
95 if (*BATl & 0x00000002)
96 *prot = PAGE_WRITE | PAGE_READ;
97 #if defined (DEBUG_BATS)
99 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
100 i, *real, *prot & PAGE_READ ? 'R' : '-',
101 *prot & PAGE_WRITE ? 'W' : '-');
110 #if defined (DEBUG_BATS)
111 printf("no BAT match for 0x%08x:\n", virtual);
112 for (i = 0; i < 4; i++) {
115 BEPIu = *BATu & 0xF0000000;
116 BEPIl = *BATu & 0x0FFE0000;
117 bl = (*BATu & 0x00001FFC) << 15;
118 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
119 "0x%08x 0x%08x 0x%08x\n",
120 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
121 *BATu, *BATl, BEPIu, BEPIl, bl);
129 /* PTE table lookup */
130 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
131 int h, int key, int rw)
133 uint32_t pte0, pte1, keep = 0, access = 0;
134 int i, good = -1, store = 0;
135 int ret = -1; /* No entry found */
137 for (i = 0; i < 8; i++) {
138 pte0 = ldl_phys(base + (i * 8));
139 pte1 = ldl_phys(base + (i * 8) + 4);
140 #if defined (DEBUG_MMU)
142 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
143 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
144 pte0 >> 31, h, (pte0 >> 6) & 1, va);
147 /* Check validity and table match */
148 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
149 /* Check vsid & api */
150 if ((pte0 & 0x7FFFFFBF) == va) {
155 /* All matches should have equal RPN, WIMG & PP */
156 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
158 fprintf(logfile, "Bad RPN/WIMG/PP\n");
162 /* Check access rights */
165 if ((pte1 & 0x00000003) != 0x3)
166 access |= PAGE_WRITE;
168 switch (pte1 & 0x00000003) {
177 access = PAGE_READ | PAGE_WRITE;
182 if ((rw == 0 && (access & PAGE_READ)) ||
183 (rw == 1 && (access & PAGE_WRITE))) {
184 #if defined (DEBUG_MMU)
186 fprintf(logfile, "PTE access granted !\n");
192 /* Access right violation */
194 #if defined (DEBUG_MMU)
196 fprintf(logfile, "PTE access rejected\n");
205 *RPN = keep & 0xFFFFF000;
206 #if defined (DEBUG_MMU)
208 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
212 /* Update page flags */
213 if (!(keep & 0x00000100)) {
218 if (!(keep & 0x00000080)) {
219 if (rw && ret == 0) {
224 /* Force page fault for first write access */
225 *prot &= ~PAGE_WRITE;
229 stl_phys_notdirty(base + (good * 8) + 4, keep);
236 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
238 return (sdr1 & 0xFFFF0000) | (hash & mask);
241 /* Perform segment based translation */
242 static int get_segment (CPUState *env, uint32_t *real, int *prot,
243 uint32_t virtual, int rw, int type)
245 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
251 sr = env->sr[virtual >> 28];
252 #if defined (DEBUG_MMU)
254 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
255 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
256 virtual, virtual >> 28, sr, env->nip,
257 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
260 key = (((sr & 0x20000000) && msr_pr == 1) ||
261 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
262 if ((sr & 0x80000000) == 0) {
263 #if defined (DEBUG_MMU)
265 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
266 key, sr & 0x10000000);
268 /* Check if instruction fetch is allowed, if needed */
269 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
270 /* Page address translation */
271 vsid = sr & 0x00FFFFFF;
272 pgidx = (virtual >> 12) & 0xFFFF;
274 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
275 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
276 pg_addr = get_pgaddr(sdr, hash, mask);
277 ptem = (vsid << 7) | (pgidx >> 10);
278 #if defined (DEBUG_MMU)
280 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
281 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
285 /* Primary table lookup */
286 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
288 /* Secondary table lookup */
289 hash = (~hash) & 0x01FFFFC0;
290 pg_addr = get_pgaddr(sdr, hash, mask);
291 #if defined (DEBUG_MMU)
292 if (virtual != 0xEFFFFFFF && loglevel > 0) {
293 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
294 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
298 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
303 #if defined (DEBUG_MMU)
305 fprintf(logfile, "No access allowed\n");
310 #if defined (DEBUG_MMU)
312 fprintf(logfile, "direct store...\n");
314 /* Direct-store segment : absolutely *BUGGY* for now */
317 /* Integer load/store : only access allowed */
320 /* No code fetch is allowed in direct-store areas */
323 /* Floating point load/store */
326 /* lwarx, ldarx or srwcx. */
329 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
330 /* Should make the instruction do no-op.
331 * As it already do no-op, it's quite easy :-)
340 fprintf(logfile, "ERROR: instruction should not need "
341 "address translation\n");
343 printf("ERROR: instruction should not need "
344 "address translation\n");
347 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
358 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
359 uint32_t address, int rw, int access_type)
364 fprintf(logfile, "%s\n", __func__);
367 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
368 (access_type != ACCESS_CODE && msr_dr == 0)) {
369 /* No address translation */
370 *physical = address & ~0xFFF;
371 *prot = PAGE_READ | PAGE_WRITE;
374 /* Try to find a BAT */
375 ret = get_bat(env, physical, prot, address, rw, access_type);
377 /* We didn't match any BAT entry */
378 ret = get_segment(env, physical, prot, address, rw, access_type);
383 fprintf(logfile, "%s address %08x => %08x\n",
384 __func__, address, *physical);
390 #if defined(CONFIG_USER_ONLY)
391 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
396 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
401 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
407 /* Perform address translation */
408 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
409 int is_user, int is_softmmu)
413 int exception = 0, error_code = 0;
420 access_type = ACCESS_CODE;
423 /* XXX: put correct access by using cpu_restore_state()
425 access_type = ACCESS_INT;
426 // access_type = env->access_type;
428 if (env->user_mode_only) {
429 /* user mode only emulation */
433 ret = get_physical_address(env, &physical, &prot,
434 address, rw, access_type);
436 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
437 is_user, is_softmmu);
438 } else if (ret < 0) {
440 #if defined (DEBUG_MMU)
442 cpu_dump_state(env, logfile, fprintf, 0);
444 if (access_type == ACCESS_CODE) {
445 exception = EXCP_ISI;
448 /* No matches in page tables */
449 error_code = 0x40000000;
452 /* Access rights violation */
453 error_code = 0x08000000;
456 /* No execute protection violation */
457 error_code = 0x10000000;
460 /* Direct store exception */
461 /* No code fetch is allowed in direct-store areas */
462 error_code = 0x10000000;
465 /* No match in segment table */
466 exception = EXCP_ISEG;
471 exception = EXCP_DSI;
474 /* No matches in page tables */
475 error_code = 0x40000000;
478 /* Access rights violation */
479 error_code = 0x08000000;
482 /* Direct store exception */
483 switch (access_type) {
485 /* Floating point load/store */
486 exception = EXCP_ALIGN;
487 error_code = EXCP_ALIGN_FP;
490 /* lwarx, ldarx or srwcx. */
491 error_code = 0x04000000;
495 error_code = 0x04100000;
498 printf("DSI: invalid exception (%d)\n", ret);
499 exception = EXCP_PROGRAM;
500 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
505 /* No match in segment table */
506 exception = EXCP_DSEG;
510 if (exception == EXCP_DSI && rw == 1)
511 error_code |= 0x02000000;
512 /* Store fault address */
513 env->spr[SPR_DAR] = address;
514 env->spr[SPR_DSISR] = error_code;
517 printf("%s: set exception to %d %02x\n",
518 __func__, exception, error_code);
520 env->exception_index = exception;
521 env->error_code = error_code;
527 /*****************************************************************************/
528 /* BATs management */
529 #if !defined(FLUSH_ALL_TLBS)
530 static inline void do_invalidate_BAT (CPUPPCState *env,
531 target_ulong BATu, target_ulong mask)
533 target_ulong base, end, page;
534 base = BATu & ~0x0001FFFF;
535 end = base + mask + 0x00020000;
536 #if defined (DEBUG_BATS)
538 fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n", base, end, mask);
540 for (page = base; page != end; page += TARGET_PAGE_SIZE)
541 tlb_flush_page(env, page);
542 #if defined (DEBUG_BATS)
544 fprintf(logfile, "Flush done\n");
549 static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
552 #if defined (DEBUG_BATS)
554 fprintf(logfile, "Set %cBAT%d%c to 0x%08lx (0x%08lx)\n",
555 ID, nr, ul == 0 ? 'u' : 'l', (unsigned long)value,
556 (unsigned long)env->nip);
561 target_ulong do_load_ibatu (CPUPPCState *env, int nr)
563 return env->IBAT[0][nr];
566 target_ulong do_load_ibatl (CPUPPCState *env, int nr)
568 return env->IBAT[1][nr];
571 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
575 dump_store_bat(env, 'I', 0, nr, value);
576 if (env->IBAT[0][nr] != value) {
577 mask = (value << 15) & 0x0FFE0000UL;
578 #if !defined(FLUSH_ALL_TLBS)
579 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
581 /* When storing valid upper BAT, mask BEPI and BRPN
582 * and invalidate all TLBs covered by this BAT
584 mask = (value << 15) & 0x0FFE0000UL;
585 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
586 (value & ~0x0001FFFFUL & ~mask);
587 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
588 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
589 #if !defined(FLUSH_ALL_TLBS)
590 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
592 #if defined(FLUSH_ALL_TLBS)
598 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
600 dump_store_bat(env, 'I', 1, nr, value);
601 env->IBAT[1][nr] = value;
604 target_ulong do_load_dbatu (CPUPPCState *env, int nr)
606 return env->DBAT[0][nr];
609 target_ulong do_load_dbatl (CPUPPCState *env, int nr)
611 return env->DBAT[1][nr];
614 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
618 dump_store_bat(env, 'D', 0, nr, value);
619 if (env->DBAT[0][nr] != value) {
620 /* When storing valid upper BAT, mask BEPI and BRPN
621 * and invalidate all TLBs covered by this BAT
623 mask = (value << 15) & 0x0FFE0000UL;
624 #if !defined(FLUSH_ALL_TLBS)
625 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
627 mask = (value << 15) & 0x0FFE0000UL;
628 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
629 (value & ~0x0001FFFFUL & ~mask);
630 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
631 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
632 #if !defined(FLUSH_ALL_TLBS)
633 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
640 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
642 dump_store_bat(env, 'D', 1, nr, value);
643 env->DBAT[1][nr] = value;
646 static inline void invalidate_all_tlbs (CPUPPCState *env)
648 /* XXX: this needs to be completed for sotware driven TLB support */
652 /*****************************************************************************/
653 /* Special registers manipulation */
654 target_ulong do_load_nip (CPUPPCState *env)
659 void do_store_nip (CPUPPCState *env, target_ulong value)
664 target_ulong do_load_sdr1 (CPUPPCState *env)
669 void do_store_sdr1 (CPUPPCState *env, target_ulong value)
671 #if defined (DEBUG_MMU)
673 fprintf(logfile, "%s: 0x%08lx\n", __func__, (unsigned long)value);
676 if (env->sdr1 != value) {
678 invalidate_all_tlbs(env);
682 target_ulong do_load_sr (CPUPPCState *env, int srnum)
684 return env->sr[srnum];
687 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
689 #if defined (DEBUG_MMU)
691 fprintf(logfile, "%s: reg=%d 0x%08lx %08lx\n",
692 __func__, srnum, (unsigned long)value, env->sr[srnum]);
695 if (env->sr[srnum] != value) {
696 env->sr[srnum] = value;
697 #if !defined(FLUSH_ALL_TLBS) && 0
699 target_ulong page, end;
700 /* Invalidate 256 MB of virtual memory */
701 page = (16 << 20) * srnum;
702 end = page + (16 << 20);
703 for (; page != end; page += TARGET_PAGE_SIZE)
704 tlb_flush_page(env, page);
707 invalidate_all_tlbs(env);
712 uint32_t do_load_cr (CPUPPCState *env)
714 return (env->crf[0] << 28) |
715 (env->crf[1] << 24) |
716 (env->crf[2] << 20) |
717 (env->crf[3] << 16) |
718 (env->crf[4] << 12) |
724 void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask)
728 for (i = 0, sh = 7; i < 8; i++, sh --) {
729 if (mask & (1 << sh))
730 env->crf[i] = (value >> (sh * 4)) & 0xFUL;
734 uint32_t do_load_xer (CPUPPCState *env)
736 return (xer_so << XER_SO) |
740 (xer_cmp << XER_CMP);
743 void do_store_xer (CPUPPCState *env, uint32_t value)
745 xer_so = (value >> XER_SO) & 0x01;
746 xer_ov = (value >> XER_OV) & 0x01;
747 xer_ca = (value >> XER_CA) & 0x01;
748 xer_cmp = (value >> XER_CMP) & 0xFF;
749 xer_bc = (value >> XER_BC) & 0x3F;
752 target_ulong do_load_msr (CPUPPCState *env)
754 return (msr_vr << MSR_VR) |
757 (msr_key << MSR_KEY) |
758 (msr_pow << MSR_POW) |
759 (msr_tlb << MSR_TLB) |
760 (msr_ile << MSR_ILE) |
765 (msr_fe0 << MSR_FE0) |
768 (msr_fe1 << MSR_FE1) |
779 void do_compute_hflags (CPUPPCState *env)
781 /* Compute current hflags */
782 env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
783 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
784 (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
785 (msr_se << MSR_SE) | (msr_be << MSR_BE);
788 void do_store_msr (CPUPPCState *env, target_ulong value)
790 value &= env->msr_mask;
791 if (((value >> MSR_IR) & 1) != msr_ir ||
792 ((value >> MSR_DR) & 1) != msr_dr) {
793 /* Flush all tlb when changing translation mode
794 * When using software driven TLB, we may also need to reload
798 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
802 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
805 msr_vr = (value >> MSR_VR) & 1;
806 msr_ap = (value >> MSR_AP) & 1;
807 msr_sa = (value >> MSR_SA) & 1;
808 msr_key = (value >> MSR_KEY) & 1;
809 msr_pow = (value >> MSR_POW) & 1;
810 msr_tlb = (value >> MSR_TLB) & 1;
811 msr_ile = (value >> MSR_ILE) & 1;
812 msr_ee = (value >> MSR_EE) & 1;
813 msr_pr = (value >> MSR_PR) & 1;
814 msr_fp = (value >> MSR_FP) & 1;
815 msr_me = (value >> MSR_ME) & 1;
816 msr_fe0 = (value >> MSR_FE0) & 1;
817 msr_se = (value >> MSR_SE) & 1;
818 msr_be = (value >> MSR_BE) & 1;
819 msr_fe1 = (value >> MSR_FE1) & 1;
820 msr_al = (value >> MSR_AL) & 1;
821 msr_ip = (value >> MSR_IP) & 1;
822 msr_ir = (value >> MSR_IR) & 1;
823 msr_dr = (value >> MSR_DR) & 1;
824 msr_pe = (value >> MSR_PE) & 1;
825 msr_px = (value >> MSR_PX) & 1;
826 msr_ri = (value >> MSR_RI) & 1;
827 msr_le = (value >> MSR_LE) & 1;
828 do_compute_hflags(env);
831 float64 do_load_fpscr (CPUPPCState *env)
833 /* The 32 MSB of the target fpr are undefined.
844 #ifdef WORDS_BIGENDIAN
853 for (i = 0; i < 8; i++)
854 u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
858 void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask)
861 * We use only the 32 LSB of the incoming fpr
873 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
874 for (i = 1; i < 7; i++) {
875 if (mask & (1 << (7 - i)))
876 env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
878 /* TODO: update FEX & VX */
879 /* Set rounding mode */
880 switch (env->fpscr[0] & 0x3) {
882 /* Best approximation (round to nearest) */
883 rnd_type = float_round_nearest_even;
886 /* Smaller magnitude (round toward zero) */
887 rnd_type = float_round_to_zero;
890 /* Round toward +infinite */
891 rnd_type = float_round_up;
895 /* Round toward -infinite */
896 rnd_type = float_round_down;
899 set_float_rounding_mode(rnd_type, &env->fp_status);
902 /*****************************************************************************/
903 /* Exception processing */
904 #if defined (CONFIG_USER_ONLY)
905 void do_interrupt (CPUState *env)
907 env->exception_index = -1;
910 static void dump_syscall(CPUState *env)
912 fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
913 env->gpr[0], env->gpr[3], env->gpr[4],
914 env->gpr[5], env->gpr[6], env->nip);
917 void do_interrupt (CPUState *env)
919 target_ulong msr, *srr_0, *srr_1, tmp;
922 excp = env->exception_index;
923 msr = do_load_msr(env);
924 /* The default is to use SRR0 & SRR1 to save the exception context */
925 srr_0 = &env->spr[SPR_SRR0];
926 srr_1 = &env->spr[SPR_SRR1];
927 #if defined (DEBUG_EXCEPTIONS)
928 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
930 fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
931 (unsigned long)env->nip, excp, env->error_code);
932 cpu_dump_state(env, logfile, fprintf, 0);
936 if (loglevel & CPU_LOG_INT) {
937 fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
938 (unsigned long)env->nip, excp, env->error_code);
941 /* Generate informations in save/restore registers */
943 /* Generic PowerPC exceptions */
944 case EXCP_RESET: /* 0x0100 */
945 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
950 srr_0 = &env->spr[SPR_40x_SRR2];
951 srr_1 = &env->spr[SPR_40x_SRR3];
954 case EXCP_MACHINE_CHECK: /* 0x0200 */
956 cpu_abort(env, "Machine check exception while not allowed\n");
958 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_40x) {
959 srr_0 = &env->spr[SPR_40x_SRR2];
960 srr_1 = &env->spr[SPR_40x_SRR3];
964 case EXCP_DSI: /* 0x0300 */
965 /* Store exception cause */
966 /* data location address has been stored
967 * when the fault has been detected
970 #if defined (DEBUG_EXCEPTIONS)
972 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
973 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
975 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
976 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
980 case EXCP_ISI: /* 0x0400 */
981 /* Store exception cause */
983 msr |= env->error_code;
984 #if defined (DEBUG_EXCEPTIONS)
986 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
991 case EXCP_EXTERNAL: /* 0x0500 */
993 #if defined (DEBUG_EXCEPTIONS)
995 fprintf(logfile, "Skipping hardware interrupt\n");
999 env->interrupt_request |= CPU_INTERRUPT_HARD;
1003 case EXCP_ALIGN: /* 0x0600 */
1004 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_601) {
1005 /* Store exception cause */
1006 /* Get rS/rD and rA from faulting opcode */
1007 env->spr[SPR_DSISR] |=
1008 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1009 /* data location address has been stored
1010 * when the fault has been detected
1013 /* IO error exception on PowerPC 601 */
1016 "601 IO error exception is not implemented yet !\n");
1019 case EXCP_PROGRAM: /* 0x0700 */
1021 switch (env->error_code & ~0xF) {
1023 if (msr_fe0 == 0 && msr_fe1 == 0) {
1024 #if defined (DEBUG_EXCEPTIONS)
1025 printf("Ignore floating point exception\n");
1031 env->fpscr[7] |= 0x8;
1032 /* Finally, update FEX */
1033 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1034 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1035 env->fpscr[7] |= 0x4;
1038 // printf("Invalid instruction at 0x%08x\n", env->nip);
1048 /* Should never occur */
1053 case EXCP_NO_FP: /* 0x0800 */
1060 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1065 case EXCP_SYSCALL: /* 0x0C00 */
1066 /* NOTE: this is a temporary hack to support graphics OSI
1067 calls from the MOL driver */
1068 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1070 if (env->osi_call(env) != 0)
1073 if (loglevel & CPU_LOG_INT) {
1077 case EXCP_TRACE: /* 0x0D00 */
1079 cpu_abort(env, "Trace exception is not implemented yet !\n");
1081 case EXCP_PERF: /* 0x0F00 */
1084 "Performance counter exception is not implemented yet !\n");
1086 /* 32 bits PowerPC specific exceptions */
1087 case EXCP_FP_ASSIST: /* 0x0E00 */
1089 cpu_abort(env, "Floating point assist exception "
1090 "is not implemented yet !\n");
1092 /* 64 bits PowerPC exceptions */
1093 case EXCP_DSEG: /* 0x0380 */
1095 cpu_abort(env, "Data segment exception is not implemented yet !\n");
1097 case EXCP_ISEG: /* 0x0480 */
1100 "Instruction segment exception is not implemented yet !\n");
1102 case EXCP_HDECR: /* 0x0980 */
1106 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1111 "Hypervisor decrementer exception is not implemented yet !\n");
1113 /* Implementation specific exceptions */
1115 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_602) {
1116 /* Critical interrupt on G2 */
1118 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1121 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1125 switch (PPC_EXCP(env)) {
1126 case PPC_FLAGS_EXCP_40x:
1127 /* APU unavailable on 405 */
1130 "APU unavailable exception is not implemented yet !\n");
1132 case PPC_FLAGS_EXCP_74xx:
1133 /* Altivec unavailable */
1135 cpu_abort(env, "Altivec unavailable exception "
1136 "is not implemented yet !\n");
1139 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1144 switch (PPC_EXCP(env)) {
1145 case PPC_FLAGS_EXCP_40x:
1148 cpu_abort(env, "40x PIT exception is not implemented yet !\n");
1150 case PPC_FLAGS_EXCP_602:
1151 case PPC_FLAGS_EXCP_603:
1152 /* ITLBMISS on 602/603 */
1157 cpu_abort(env, "Invalid exception 0x1000 !\n");
1162 switch (PPC_EXCP(env)) {
1163 case PPC_FLAGS_EXCP_40x:
1165 cpu_abort(env, "40x FIT exception is not implemented yet !\n");
1169 cpu_abort(env, "Invalid exception 0x1010 !\n");
1174 switch (PPC_EXCP(env)) {
1175 case PPC_FLAGS_EXCP_40x:
1176 /* Watchdog on 4xx */
1179 "40x watchdog exception is not implemented yet !\n");
1182 cpu_abort(env, "Invalid exception 0x1020 !\n");
1187 switch (PPC_EXCP(env)) {
1188 case PPC_FLAGS_EXCP_40x:
1189 /* DTLBMISS on 4xx */
1192 "40x DTLBMISS exception is not implemented yet !\n");
1194 case PPC_FLAGS_EXCP_602:
1195 case PPC_FLAGS_EXCP_603:
1196 /* DLTLBMISS on 602/603 */
1201 cpu_abort(env, "Invalid exception 0x1100 !\n");
1206 switch (PPC_EXCP(env)) {
1207 case PPC_FLAGS_EXCP_40x:
1208 /* ITLBMISS on 4xx */
1211 "40x ITLBMISS exception is not implemented yet !\n");
1213 case PPC_FLAGS_EXCP_602:
1214 case PPC_FLAGS_EXCP_603:
1215 /* DSTLBMISS on 602/603 */
1219 #if defined (DEBUG_SOFTWARE_TLB)
1220 if (loglevel != 0) {
1221 fprintf(logfile, "6xx %sTLB miss: IM %08x DM %08x IC %08x "
1222 "DC %08x H1 %08x H2 %08x %08x\n",
1223 excp == 0x1000 ? "I" : excp == 0x1100 ? "DL" : "DS",
1224 env->spr[SPR_IMISS], env->spr[SPR_DMISS],
1225 env->spr[SPR_ICMP], env->spr[SPR_DCMP],
1226 env->spr[SPR_DHASH1], env->spr[SPR_DHASH2],
1230 /* Swap temporary saved registers with GPRs */
1232 env->gpr[0] = env->tgpr[0];
1235 env->gpr[1] = env->tgpr[1];
1238 env->gpr[2] = env->tgpr[2];
1241 env->gpr[3] = env->tgpr[3];
1243 msr |= env->crf[0] << 28;
1244 msr |= env->error_code; /* key, D/I, S/L bits */
1245 /* Set way using a LRU mechanism */
1246 msr |= (env->last_way ^ 1) << 17;
1249 cpu_abort(env, "Invalid exception 0x1200 !\n");
1254 switch (PPC_EXCP(env)) {
1255 case PPC_FLAGS_EXCP_601:
1256 case PPC_FLAGS_EXCP_602:
1257 case PPC_FLAGS_EXCP_603:
1258 case PPC_FLAGS_EXCP_604:
1259 case PPC_FLAGS_EXCP_7x0:
1260 case PPC_FLAGS_EXCP_7x5:
1261 /* IABR on 6xx/7xx */
1263 cpu_abort(env, "IABR exception is not implemented yet !\n");
1266 cpu_abort(env, "Invalid exception 0x1300 !\n");
1271 switch (PPC_EXCP(env)) {
1272 case PPC_FLAGS_EXCP_601:
1273 case PPC_FLAGS_EXCP_602:
1274 case PPC_FLAGS_EXCP_603:
1275 case PPC_FLAGS_EXCP_604:
1276 case PPC_FLAGS_EXCP_7x0:
1277 case PPC_FLAGS_EXCP_7x5:
1278 /* SMI on 6xx/7xx */
1280 cpu_abort(env, "SMI exception is not implemented yet !\n");
1283 cpu_abort(env, "Invalid exception 0x1400 !\n");
1288 switch (PPC_EXCP(env)) {
1289 case PPC_FLAGS_EXCP_602:
1290 /* Watchdog on 602 */
1292 "602 watchdog exception is not implemented yet !\n");
1294 case PPC_FLAGS_EXCP_970:
1295 /* Soft patch exception on 970 */
1298 "970 soft-patch exception is not implemented yet !\n");
1300 case PPC_FLAGS_EXCP_74xx:
1301 /* VPU assist on 74xx */
1303 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1306 cpu_abort(env, "Invalid exception 0x1500 !\n");
1311 switch (PPC_EXCP(env)) {
1312 case PPC_FLAGS_EXCP_602:
1313 /* Emulation trap on 602 */
1315 cpu_abort(env, "602 emulation trap exception "
1316 "is not implemented yet !\n");
1318 case PPC_FLAGS_EXCP_970:
1319 /* Maintenance exception on 970 */
1322 "970 maintenance exception is not implemented yet !\n");
1325 cpu_abort(env, "Invalid exception 0x1600 !\n");
1330 switch (PPC_EXCP(env)) {
1331 case PPC_FLAGS_EXCP_7x0:
1332 case PPC_FLAGS_EXCP_7x5:
1333 /* Thermal management interrupt on G3 */
1335 cpu_abort(env, "G3 thermal management exception "
1336 "is not implemented yet !\n");
1338 case PPC_FLAGS_EXCP_970:
1339 /* VPU assist on 970 */
1342 "970 VPU assist exception is not implemented yet !\n");
1345 cpu_abort(env, "Invalid exception 0x1700 !\n");
1350 switch (PPC_EXCP(env)) {
1351 case PPC_FLAGS_EXCP_970:
1352 /* Thermal exception on 970 */
1354 cpu_abort(env, "970 thermal management exception "
1355 "is not implemented yet !\n");
1358 cpu_abort(env, "Invalid exception 0x1800 !\n");
1363 switch (PPC_EXCP(env)) {
1364 case PPC_FLAGS_EXCP_40x:
1367 cpu_abort(env, "40x debug exception is not implemented yet !\n");
1369 case PPC_FLAGS_EXCP_601:
1370 /* Run mode exception on 601 */
1373 "601 run mode exception is not implemented yet !\n");
1376 cpu_abort(env, "Invalid exception 0x1800 !\n");
1380 /* Other exceptions */
1381 /* Qemu internal exceptions:
1382 * we should never come here with those values: abort execution
1385 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
1388 /* save current instruction location */
1389 *srr_0 = (env->nip - 4) & 0xFFFFFFFFULL;
1392 /* save next instruction location */
1393 *srr_0 = env->nip & 0xFFFFFFFFULL;
1398 /* If we disactivated any translation, flush TLBs */
1399 if (msr_ir || msr_dr) {
1402 /* reload MSR with correct bits */
1415 do_compute_hflags(env);
1416 /* Jump to handler */
1418 env->exception_index = EXCP_NONE;
1420 /* ensure that no TB jump will be modified as
1421 the program flow was changed */
1428 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1430 #endif /* !CONFIG_USER_ONLY */