2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 //#define DEBUG_EXCEPTIONS
25 /* accurate but slower TLB flush in exceptions */
26 //#define ACCURATE_TLB_FLUSH
28 /*****************************************************************************/
29 /* PPC MMU emulation */
31 /* Perform BAT hit & translation */
32 static int get_bat (CPUState *env, uint32_t *real, int *prot,
33 uint32_t virtual, int rw, int type)
35 uint32_t *BATlt, *BATut, *BATu, *BATl;
36 uint32_t base, BEPIl, BEPIu, bl;
40 #if defined (DEBUG_BATS)
42 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
43 type == ACCESS_CODE ? 'I' : 'D', virtual);
56 #if defined (DEBUG_BATS)
58 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
59 type == ACCESS_CODE ? 'I' : 'D', virtual);
62 base = virtual & 0xFFFC0000;
63 for (i = 0; i < 4; i++) {
66 BEPIu = *BATu & 0xF0000000;
67 BEPIl = *BATu & 0x0FFE0000;
68 bl = (*BATu & 0x00001FFC) << 15;
69 #if defined (DEBUG_BATS)
71 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
72 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
76 if ((virtual & 0xF0000000) == BEPIu &&
77 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
79 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
80 (msr_pr == 1 && (*BATu & 0x00000001))) {
81 /* Get physical address */
82 *real = (*BATl & 0xF0000000) |
83 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
84 (virtual & 0x0001F000);
85 if (*BATl & 0x00000001)
87 if (*BATl & 0x00000002)
88 *prot = PAGE_WRITE | PAGE_READ;
89 #if defined (DEBUG_BATS)
91 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
92 i, *real, *prot & PAGE_READ ? 'R' : '-',
93 *prot & PAGE_WRITE ? 'W' : '-');
102 #if defined (DEBUG_BATS)
103 printf("no BAT match for 0x%08x:\n", virtual);
104 for (i = 0; i < 4; i++) {
107 BEPIu = *BATu & 0xF0000000;
108 BEPIl = *BATu & 0x0FFE0000;
109 bl = (*BATu & 0x00001FFC) << 15;
110 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
111 "0x%08x 0x%08x 0x%08x\n",
112 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
113 *BATu, *BATl, BEPIu, BEPIl, bl);
121 /* PTE table lookup */
122 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
123 int h, int key, int rw)
125 uint32_t pte0, pte1, keep = 0, access = 0;
126 int i, good = -1, store = 0;
127 int ret = -1; /* No entry found */
129 for (i = 0; i < 8; i++) {
130 pte0 = ldl_phys(base + (i * 8));
131 pte1 = ldl_phys(base + (i * 8) + 4);
132 #if defined (DEBUG_MMU)
134 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
135 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
136 pte0 >> 31, h, (pte0 >> 6) & 1, va);
139 /* Check validity and table match */
140 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
141 /* Check vsid & api */
142 if ((pte0 & 0x7FFFFFBF) == va) {
147 /* All matches should have equal RPN, WIMG & PP */
148 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
150 fprintf(logfile, "Bad RPN/WIMG/PP\n");
154 /* Check access rights */
157 if ((pte1 & 0x00000003) != 0x3)
158 access |= PAGE_WRITE;
160 switch (pte1 & 0x00000003) {
169 access = PAGE_READ | PAGE_WRITE;
174 if ((rw == 0 && (access & PAGE_READ)) ||
175 (rw == 1 && (access & PAGE_WRITE))) {
176 #if defined (DEBUG_MMU)
178 fprintf(logfile, "PTE access granted !\n");
184 /* Access right violation */
186 #if defined (DEBUG_MMU)
188 fprintf(logfile, "PTE access rejected\n");
197 *RPN = keep & 0xFFFFF000;
198 #if defined (DEBUG_MMU)
200 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
204 /* Update page flags */
205 if (!(keep & 0x00000100)) {
210 if (!(keep & 0x00000080)) {
211 if (rw && ret == 0) {
216 /* Force page fault for first write access */
217 *prot &= ~PAGE_WRITE;
221 stl_phys_notdirty(base + (good * 8) + 4, keep);
228 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
230 return (sdr1 & 0xFFFF0000) | (hash & mask);
233 /* Perform segment based translation */
234 static int get_segment (CPUState *env, uint32_t *real, int *prot,
235 uint32_t virtual, int rw, int type)
237 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
243 sr = env->sr[virtual >> 28];
244 #if defined (DEBUG_MMU)
246 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
247 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
248 virtual, virtual >> 28, sr, env->nip,
249 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
252 key = (((sr & 0x20000000) && msr_pr == 1) ||
253 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
254 if ((sr & 0x80000000) == 0) {
255 #if defined (DEBUG_MMU)
257 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
258 key, sr & 0x10000000);
260 /* Check if instruction fetch is allowed, if needed */
261 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
262 /* Page address translation */
263 vsid = sr & 0x00FFFFFF;
264 pgidx = (virtual >> 12) & 0xFFFF;
266 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
267 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
268 pg_addr = get_pgaddr(sdr, hash, mask);
269 ptem = (vsid << 7) | (pgidx >> 10);
270 #if defined (DEBUG_MMU)
272 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
273 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
277 /* Primary table lookup */
278 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
280 /* Secondary table lookup */
281 hash = (~hash) & 0x01FFFFC0;
282 pg_addr = get_pgaddr(sdr, hash, mask);
283 #if defined (DEBUG_MMU)
284 if (virtual != 0xEFFFFFFF && loglevel > 0) {
285 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
286 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
290 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
295 #if defined (DEBUG_MMU)
297 fprintf(logfile, "No access allowed\n");
302 #if defined (DEBUG_MMU)
304 fprintf(logfile, "direct store...\n");
306 /* Direct-store segment : absolutely *BUGGY* for now */
309 /* Integer load/store : only access allowed */
312 /* No code fetch is allowed in direct-store areas */
315 /* Floating point load/store */
318 /* lwarx, ldarx or srwcx. */
321 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
322 /* Should make the instruction do no-op.
323 * As it already do no-op, it's quite easy :-)
332 fprintf(logfile, "ERROR: instruction should not need "
333 "address translation\n");
335 printf("ERROR: instruction should not need "
336 "address translation\n");
339 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
350 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
351 uint32_t address, int rw, int access_type)
356 fprintf(logfile, "%s\n", __func__);
359 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
360 (access_type != ACCESS_CODE && msr_dr == 0)) {
361 /* No address translation */
362 *physical = address & ~0xFFF;
363 *prot = PAGE_READ | PAGE_WRITE;
366 /* Try to find a BAT */
367 ret = get_bat(env, physical, prot, address, rw, access_type);
369 /* We didn't match any BAT entry */
370 ret = get_segment(env, physical, prot, address, rw, access_type);
375 fprintf(logfile, "%s address %08x => %08x\n",
376 __func__, address, *physical);
382 #if defined(CONFIG_USER_ONLY)
383 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
388 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
393 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
399 #if !defined(CONFIG_USER_ONLY)
401 #define MMUSUFFIX _mmu
402 #define GETPC() (__builtin_return_address(0))
405 #include "softmmu_template.h"
408 #include "softmmu_template.h"
411 #include "softmmu_template.h"
414 #include "softmmu_template.h"
416 /* try to fill the TLB and return an exception if error. If retaddr is
417 NULL, it means that the function was called in C code (i.e. not
418 from generated code or from helper.c) */
419 /* XXX: fix it to restore all registers */
420 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
422 TranslationBlock *tb;
427 /* XXX: hack to restore env in all cases, even if not called from
430 env = cpu_single_env;
433 unsigned long tlb_addrr, tlb_addrw;
435 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
436 tlb_addrr = env->tlb_read[is_user][index].address;
437 tlb_addrw = env->tlb_write[is_user][index].address;
440 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
441 "(0x%08lx 0x%08lx)\n", __func__, env,
442 &env->tlb_read[is_user][index], index, addr,
443 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
444 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
448 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
451 /* now we have a real cpu fault */
452 pc = (unsigned long)retaddr;
455 /* the PC is inside the translated code. It means that we have
456 a virtual CPU fault */
457 cpu_restore_state(tb, env, pc, NULL);
460 do_raise_exception_err(env->exception_index, env->error_code);
464 unsigned long tlb_addrr, tlb_addrw;
466 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
467 tlb_addrr = env->tlb_read[is_user][index].address;
468 tlb_addrw = env->tlb_write[is_user][index].address;
469 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
470 "(0x%08lx 0x%08lx)\n", __func__, env,
471 &env->tlb_read[is_user][index], index, addr,
472 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
473 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
479 void cpu_ppc_init_mmu(CPUState *env)
481 /* Nothing to do: all translation are disabled */
485 /* Perform address translation */
486 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
487 int is_user, int is_softmmu)
491 int exception = 0, error_code = 0;
498 access_type = ACCESS_CODE;
501 /* XXX: put correct access by using cpu_restore_state()
503 access_type = ACCESS_INT;
504 // access_type = env->access_type;
506 if (env->user_mode_only) {
507 /* user mode only emulation */
511 ret = get_physical_address(env, &physical, &prot,
512 address, rw, access_type);
514 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
515 is_user, is_softmmu);
516 } else if (ret < 0) {
518 #if defined (DEBUG_MMU)
520 cpu_dump_state(env, logfile, fprintf, 0);
522 if (access_type == ACCESS_CODE) {
523 exception = EXCP_ISI;
526 /* No matches in page tables */
527 error_code = EXCP_ISI_TRANSLATE;
530 /* Access rights violation */
531 error_code = EXCP_ISI_PROT;
534 /* No execute protection violation */
535 error_code = EXCP_ISI_NOEXEC;
538 /* Direct store exception */
539 /* No code fetch is allowed in direct-store areas */
540 error_code = EXCP_ISI_DIRECT;
544 exception = EXCP_DSI;
547 /* No matches in page tables */
548 error_code = EXCP_DSI_TRANSLATE;
551 /* Access rights violation */
552 error_code = EXCP_DSI_PROT;
555 /* Direct store exception */
556 switch (access_type) {
558 /* Floating point load/store */
559 exception = EXCP_ALIGN;
560 error_code = EXCP_ALIGN_FP;
563 /* lwarx, ldarx or srwcx. */
564 exception = EXCP_DSI;
565 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
569 exception = EXCP_DSI;
570 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
574 printf("DSI: invalid exception (%d)\n", ret);
575 exception = EXCP_PROGRAM;
576 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
581 error_code |= EXCP_DSI_STORE;
582 /* Store fault address */
583 env->spr[DAR] = address;
586 printf("%s: set exception to %d %02x\n",
587 __func__, exception, error_code);
589 env->exception_index = exception;
590 env->error_code = error_code;
596 uint32_t _load_xer (CPUState *env)
598 return (xer_so << XER_SO) |
604 void _store_xer (CPUState *env, uint32_t value)
606 xer_so = (value >> XER_SO) & 0x01;
607 xer_ov = (value >> XER_OV) & 0x01;
608 xer_ca = (value >> XER_CA) & 0x01;
609 xer_bc = (value >> XER_BC) & 0x3f;
612 uint32_t _load_msr (CPUState *env)
614 return (msr_pow << MSR_POW) |
615 (msr_ile << MSR_ILE) |
620 (msr_fe0 << MSR_FE0) |
623 (msr_fe1 << MSR_FE1) |
631 void _store_msr (CPUState *env, uint32_t value)
633 #ifdef ACCURATE_TLB_FLUSH
634 if (((value >> MSR_IR) & 0x01) != msr_ir ||
635 ((value >> MSR_DR) & 0x01) != msr_dr)
637 /* Flush all tlb when changing translation mode or privilege level */
641 msr_pow = (value >> MSR_POW) & 0x03;
642 msr_ile = (value >> MSR_ILE) & 0x01;
643 msr_ee = (value >> MSR_EE) & 0x01;
644 msr_pr = (value >> MSR_PR) & 0x01;
645 msr_fp = (value >> MSR_FP) & 0x01;
646 msr_me = (value >> MSR_ME) & 0x01;
647 msr_fe0 = (value >> MSR_FE0) & 0x01;
648 msr_se = (value >> MSR_SE) & 0x01;
649 msr_be = (value >> MSR_BE) & 0x01;
650 msr_fe1 = (value >> MSR_FE1) & 0x01;
651 msr_ip = (value >> MSR_IP) & 0x01;
652 msr_ir = (value >> MSR_IR) & 0x01;
653 msr_dr = (value >> MSR_DR) & 0x01;
654 msr_ri = (value >> MSR_RI) & 0x01;
655 msr_le = (value >> MSR_LE) & 0x01;
656 /* XXX: should enter PM state if msr_pow has been set */
659 #if defined (CONFIG_USER_ONLY)
660 void do_interrupt (CPUState *env)
662 env->exception_index = -1;
665 static void dump_syscall(CPUState *env)
667 fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
668 env->gpr[0], env->gpr[3], env->gpr[4],
669 env->gpr[5], env->gpr[6], env->nip);
672 void do_interrupt (CPUState *env)
677 excp = env->exception_index;
678 msr = _load_msr(env);
679 #if defined (DEBUG_EXCEPTIONS)
680 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
683 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
684 env->nip, excp << 8, env->error_code);
687 cpu_dump_state(env, logfile, fprintf, 0);
690 if (loglevel & CPU_LOG_INT) {
691 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
692 env->nip, excp << 8, env->error_code);
694 /* Generate informations in save/restore registers */
698 #if defined (DEBUG_EXCEPTIONS)
699 printf("%s: escape EXCP_NONE\n", __func__);
706 case EXCP_MACHINE_CHECK:
708 cpu_abort(env, "Machine check exception while not allowed\n");
713 /* Store exception cause */
714 /* data location address has been stored
715 * when the fault has been detected
719 if ((env->error_code & 0x0f) == EXCP_DSI_TRANSLATE)
720 env->spr[DSISR] |= 0x40000000;
721 else if ((env->error_code & 0x0f) == EXCP_DSI_PROT)
722 env->spr[DSISR] |= 0x08000000;
723 else if ((env->error_code & 0x0f) == EXCP_DSI_NOTSUP) {
724 env->spr[DSISR] |= 0x80000000;
725 if (env->error_code & EXCP_DSI_DIRECT)
726 env->spr[DSISR] |= 0x04000000;
728 if (env->error_code & EXCP_DSI_STORE)
729 env->spr[DSISR] |= 0x02000000;
730 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
731 env->spr[DSISR] |= 0x00400000;
732 if (env->error_code & EXCP_DSI_ECXW)
733 env->spr[DSISR] |= 0x00100000;
734 #if defined (DEBUG_EXCEPTIONS)
736 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
737 env->spr[DSISR], env->spr[DAR]);
739 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
740 env->spr[DSISR], env->spr[DAR], env->nip);
745 /* Store exception cause */
747 if (env->error_code == EXCP_ISI_TRANSLATE)
749 else if (env->error_code == EXCP_ISI_NOEXEC ||
750 env->error_code == EXCP_ISI_GUARD ||
751 env->error_code == EXCP_ISI_DIRECT)
755 #if defined (DEBUG_EXCEPTIONS)
757 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
760 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
761 msr, env->nip, env->spr[V_TBL]);
767 #if defined (DEBUG_EXCEPTIONS)
769 fprintf(logfile, "Skipping hardware interrupt\n");
773 do_raise_exception(EXCP_EXTERNAL);
778 /* Store exception cause */
779 /* Get rS/rD and rA from faulting opcode */
781 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
782 /* data location address has been stored
783 * when the fault has been detected
788 switch (env->error_code & ~0xF) {
790 if (msr_fe0 == 0 && msr_fe1 == 0) {
791 #if defined (DEBUG_EXCEPTIONS)
792 printf("Ignore floating point exception\n");
798 env->fpscr[7] |= 0x8;
799 /* Finally, update FEX */
800 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
801 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
802 env->fpscr[7] |= 0x4;
805 // printf("Invalid instruction at 0x%08x\n", env->nip);
815 /* Should never occur */
826 do_raise_exception(EXCP_DECR);
831 /* NOTE: this is a temporary hack to support graphics OSI
832 calls from the MOL driver */
833 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
835 if (env->osi_call(env) != 0)
838 if (loglevel & CPU_LOG_INT) {
853 /* Restore user-mode state */
854 #if defined (DEBUG_EXCEPTIONS)
856 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
860 /* SRR0 is set to current instruction */
861 env->spr[SRR0] = (uint32_t)env->nip - 4;
864 /* SRR0 is set to next instruction */
865 env->spr[SRR0] = (uint32_t)env->nip;
868 env->spr[SRR1] = msr;
869 /* reload MSR with correct bits */
882 /* Jump to handler */
883 env->nip = excp << 8;
884 env->exception_index = EXCP_NONE;
885 /* Invalidate all TLB as we may have changed translation mode */
886 #ifdef ACCURATE_TLB_FLUSH
889 /* ensure that no TB jump will be modified as
890 the program flow was changed */
896 env->exception_index = -1;
898 #endif /* !CONFIG_USER_ONLY */