2 * PPC emulation cpu definitions for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if !defined (__CPU_PPC_H__)
24 #include <asm/byteorder.h>
26 #define TARGET_LONG_BITS 32
30 //#define USE_OPEN_FIRMWARE
32 /*** Sign extend constants ***/
34 static inline int32_t s_ext8 (uint8_t value)
42 static inline int32_t s_ext16 (uint16_t value)
44 int16_t *tmp = &value;
50 static inline int32_t s_ext24 (uint32_t value)
52 uint16_t utmp = (value >> 8) & 0xFFFF;
55 return (*tmp << 8) | (value & 0xFF);
61 /* Instruction types */
64 PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */
65 PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */
66 PPC_FLOW = 0x0004, /* CPU has flow control instructions */
67 PPC_MEM = 0x0008, /* CPU has virtual memory instructions */
68 PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */
69 PPC_CACHE = 0x0020, /* CPU has cache control instructions */
70 PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */
71 PPC_EXTERN = 0x0080, /* CPU has external control instructions */
72 PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */
73 PPC_CACHE_OPT= 0x0200,
74 PPC_FLOAT_OPT= 0x0400,
78 #define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
79 PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
80 /* PPC 740/745/750/755 (aka G3) has external access instructions */
81 #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
82 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
84 /* Supervisor mode registers */
85 /* Machine state register */
101 #define msr_pow env->msr[MSR_POW]
102 #define msr_ile env->msr[MSR_ILE]
103 #define msr_ee env->msr[MSR_EE]
104 #define msr_pr env->msr[MSR_PR]
105 #define msr_fp env->msr[MSR_FP]
106 #define msr_me env->msr[MSR_ME]
107 #define msr_fe0 env->msr[MSR_FE0]
108 #define msr_se env->msr[MSR_SE]
109 #define msr_be env->msr[MSR_BE]
110 #define msr_fe1 env->msr[MSR_FE1]
111 #define msr_ip env->msr[MSR_IP]
112 #define msr_ir env->msr[MSR_IR]
113 #define msr_dr env->msr[MSR_DR]
114 #define msr_ri env->msr[MSR_RI]
115 #define msr_le env->msr[MSR_LE]
117 /* Segment registers */
118 typedef struct CPUPPCState {
119 /* general purpose registers */
121 /* floating point registers */
123 /* segment registers */
128 /* Reservation address */
130 /* machine state register */
132 /* condition register */
134 /* floating point status and control register */
137 /* special purpose registers */
150 /* temporary float registers */
154 int interrupt_request;
158 int access_type; /* when a memory exception occurs, the access
159 type is stored here */
160 uint32_t exceptions; /* exception queue */
162 int user_mode_only; /* user mode only simulation */
163 struct TranslationBlock *current_tb; /* currently executing TB */
164 /* soft mmu support */
165 /* 0 = kernel, 1 = user */
166 CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
167 CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
172 CPUPPCState *cpu_ppc_init(void);
173 int cpu_ppc_exec(CPUPPCState *s);
174 void cpu_ppc_close(CPUPPCState *s);
175 /* you can call this signal handler from your SIGBUS and SIGSEGV
176 signal handlers to inform the virtual CPU of exceptions. non zero
177 is returned if the signal was handled by the virtual CPU. */
179 int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
182 void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
183 void cpu_loop_exit(void);
184 void dump_stack (CPUPPCState *env);
185 uint32_t _load_xer (void);
186 void _store_xer (uint32_t value);
187 uint32_t _load_msr (void);
188 void _store_msr (uint32_t value);
189 void do_interrupt (CPUPPCState *env);
191 #define TARGET_PAGE_BITS 12
194 #define ugpr(n) (env->gpr[n])
195 #define fprd(n) (env->fpr[n])
196 #define fprs(n) ((float)env->fpr[n])
197 #define fpru(n) ((uint32_t)env->fpr[n])
198 #define fpri(n) ((int32_t)env->fpr[n])
200 #define SPR_ENCODE(sprn) \
201 (((sprn) >> 5) | (((sprn) & 0x1F) << 5))
204 #define spr(n) env->spr[n]
209 #define xer_so env->xer[3]
210 #define xer_ov env->xer[2]
211 #define xer_ca env->xer[1]
212 #define xer_bc env->xer[0]
214 #define XER SPR_ENCODE(1)
215 #define LR SPR_ENCODE(8)
216 #define CTR SPR_ENCODE(9)
218 #define V_TBL SPR_ENCODE(268)
219 #define V_TBU SPR_ENCODE(269)
220 /* supervisor mode SPR */
221 #define DSISR SPR_ENCODE(18)
222 #define DAR SPR_ENCODE(19)
223 #define DECR SPR_ENCODE(22)
224 #define SDR1 SPR_ENCODE(25)
225 #define SRR0 SPR_ENCODE(26)
226 #define SRR1 SPR_ENCODE(27)
227 #define SPRG0 SPR_ENCODE(272)
228 #define SPRG1 SPR_ENCODE(273)
229 #define SPRG2 SPR_ENCODE(274)
230 #define SPRG3 SPR_ENCODE(275)
231 #define SPRG4 SPR_ENCODE(276)
232 #define SPRG5 SPR_ENCODE(277)
233 #define SPRG6 SPR_ENCODE(278)
234 #define SPRG7 SPR_ENCODE(279)
235 #define ASR SPR_ENCODE(280)
236 #define EAR SPR_ENCODE(282)
237 #define O_TBL SPR_ENCODE(284)
238 #define O_TBU SPR_ENCODE(285)
239 #define PVR SPR_ENCODE(287)
240 #define IBAT0U SPR_ENCODE(528)
241 #define IBAT0L SPR_ENCODE(529)
242 #define IBAT1U SPR_ENCODE(530)
243 #define IBAT1L SPR_ENCODE(531)
244 #define IBAT2U SPR_ENCODE(532)
245 #define IBAT2L SPR_ENCODE(533)
246 #define IBAT3U SPR_ENCODE(534)
247 #define IBAT3L SPR_ENCODE(535)
248 #define DBAT0U SPR_ENCODE(536)
249 #define DBAT0L SPR_ENCODE(537)
250 #define DBAT1U SPR_ENCODE(538)
251 #define DBAT1L SPR_ENCODE(539)
252 #define DBAT2U SPR_ENCODE(540)
253 #define DBAT2L SPR_ENCODE(541)
254 #define DBAT3U SPR_ENCODE(542)
255 #define DBAT3L SPR_ENCODE(543)
256 #define IBAT4U SPR_ENCODE(560)
257 #define IBAT4L SPR_ENCODE(561)
258 #define IBAT5U SPR_ENCODE(562)
259 #define IBAT5L SPR_ENCODE(563)
260 #define IBAT6U SPR_ENCODE(564)
261 #define IBAT6L SPR_ENCODE(565)
262 #define IBAT7U SPR_ENCODE(566)
263 #define IBAT7L SPR_ENCODE(567)
264 #define DBAT4U SPR_ENCODE(568)
265 #define DBAT4L SPR_ENCODE(569)
266 #define DBAT5U SPR_ENCODE(570)
267 #define DBAT5L SPR_ENCODE(571)
268 #define DBAT6U SPR_ENCODE(572)
269 #define DBAT6L SPR_ENCODE(573)
270 #define DBAT7U SPR_ENCODE(574)
271 #define DBAT7L SPR_ENCODE(575)
272 #define DABR SPR_ENCODE(1013)
273 #define DABR_MASK 0xFFFFFFF8
274 #define FPECR SPR_ENCODE(1022)
275 #define PIR SPR_ENCODE(1023)
277 #define TARGET_PAGE_BITS 12
280 CPUPPCState *cpu_ppc_init(void);
281 int cpu_ppc_exec(CPUPPCState *s);
282 void cpu_ppc_close(CPUPPCState *s);
283 void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
284 void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
285 uint32_t kernel_addr, uint32_t kernel_size,
286 uint32_t stack_addr, int boot_device);
288 /* Memory access type :
289 * may be needed for precise access rights control and precise exceptions.
292 /* 1 bit to define user level / supervisor access */
295 /* Type of instruction that generated the access */
296 ACCESS_CODE = 0x10, /* Code fetch access */
297 ACCESS_INT = 0x20, /* Integer load/store access */
298 ACCESS_FLOAT = 0x30, /* floating point load/store access */
299 ACCESS_RES = 0x40, /* load/store with reservation */
300 ACCESS_EXT = 0x50, /* external access */
301 ACCESS_CACHE = 0x60, /* Cache manipulation */
304 /*****************************************************************************/
308 /* PPC hardware exceptions : exception vector / 0x100 */
309 EXCP_RESET = 0x01, /* System reset */
310 EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
311 EXCP_DSI = 0x03, /* Impossible memory access */
312 EXCP_ISI = 0x04, /* Impossible instruction fetch */
313 EXCP_EXTERNAL = 0x05, /* External interruption */
314 EXCP_ALIGN = 0x06, /* Alignment exception */
315 EXCP_PROGRAM = 0x07, /* Program exception */
316 EXCP_NO_FP = 0x08, /* No floating point */
317 EXCP_DECR = 0x09, /* Decrementer exception */
318 EXCP_RESA = 0x0A, /* Implementation specific */
319 EXCP_RESB = 0x0B, /* Implementation specific */
320 EXCP_SYSCALL = 0x0C, /* System call */
321 EXCP_TRACE = 0x0D, /* Trace exception (optional) */
322 EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
323 /* MPC740/745/750 & IBM 750 */
324 EXCP_PERF = 0x0F, /* Performance monitor */
325 EXCP_IABR = 0x13, /* Instruction address breakpoint */
326 EXCP_SMI = 0x14, /* System management interrupt */
327 EXCP_THRM = 0x15, /* Thermal management interrupt */
329 EXCP_TLBMISS = 0x10, /* Instruction TLB miss */
330 EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */
331 EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */
334 EXCP_OFCALL = 0x20, /* Call open-firmware emulator */
335 EXCP_RTASCALL = 0x21, /* Call RTAS emulator */
336 /* Special cases where we want to stop translation */
337 EXCP_MTMSR = 0x104, /* mtmsr instruction: */
338 /* may change privilege level */
339 EXCP_BRANCH = 0x108, /* branch instruction */
340 EXCP_RFI = 0x10C, /* return from interrupt */
341 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
345 /* Exception subtypes for EXCP_DSI */
346 EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */
347 EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */
348 EXCP_DSI_PROT = 0x03, /* Memory protection violation */
349 EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */
350 EXCP_DSI_DABR = 0x05, /* Data address breakpoint */
351 /* flags for EXCP_DSI */
352 EXCP_DSI_DIRECT = 0x10,
353 EXCP_DSI_STORE = 0x20,
355 /* Exception subtypes for EXCP_ISI */
356 EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
357 EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
358 EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
359 EXCP_ISI_PROT = 0x04, /* Memory protection violation */
360 /* Exception subtypes for EXCP_ALIGN */
361 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
362 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
363 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
364 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
365 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
366 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
367 /* Exception subtypes for EXCP_PROGRAM */
370 EXCP_FP_OX = 0x01, /* FP overflow */
371 EXCP_FP_UX = 0x02, /* FP underflow */
372 EXCP_FP_ZX = 0x03, /* FP divide by zero */
373 EXCP_FP_XX = 0x04, /* FP inexact */
374 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
375 EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
376 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
377 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
378 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
379 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
380 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
381 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
382 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
383 /* Invalid instruction */
385 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
386 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
387 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
388 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
389 /* Privileged instruction */
391 EXCP_PRIV_OPC = 0x01,
392 EXCP_PRIV_REG = 0x02,
397 /*****************************************************************************/
399 #endif /* !defined (__CPU_PPC_H__) */