2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #define MIPS_DEBUG_DISAS
32 //#define MIPS_SINGLE_STEP
35 #define DEF(s, n, copy_size) INDEX_op_ ## s,
41 static uint16_t *gen_opc_ptr;
42 static uint32_t *gen_opparam_ptr;
46 const unsigned char *regnames[] =
47 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
48 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
49 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
50 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
52 /* Warning: no function for r0 register (hard wired to zero) */
53 #define GEN32(func, NAME) \
54 static GenOpFunc *NAME ## _table [32] = { \
55 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
56 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
57 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
58 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
59 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
60 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
61 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
62 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
64 static inline void func(int n) \
66 NAME ## _table[n](); \
69 /* General purpose registers moves */
70 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
71 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
72 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
74 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
75 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
77 typedef struct DisasContext {
78 struct TranslationBlock *tb;
79 target_ulong pc, saved_pc;
81 /* Routine used to access memory */
83 uint32_t hflags, saved_hflags;
90 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
93 BS_STOP = 1, /* We want to stop translation for any reason */
94 BS_BRANCH = 2, /* We reached a branch condition */
95 BS_EXCP = 3, /* We reached an exception condition */
98 #if defined MIPS_DEBUG_DISAS
99 #define MIPS_DEBUG(fmt, args...) \
101 if (loglevel & CPU_LOG_TB_IN_ASM) { \
102 fprintf(logfile, "%08x: %08x " fmt "\n", \
103 ctx->pc, ctx->opcode , ##args); \
107 #define MIPS_DEBUG(fmt, args...) do { } while(0)
110 #define MIPS_INVAL(op) \
112 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
113 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
116 #define GEN_LOAD_REG_TN(Tn, Rn) \
119 glue(gen_op_reset_, Tn)(); \
121 glue(gen_op_load_gpr_, Tn)(Rn); \
125 #define GEN_LOAD_IMM_TN(Tn, Imm) \
128 glue(gen_op_reset_, Tn)(); \
130 glue(gen_op_set_, Tn)(Imm); \
134 #define GEN_STORE_TN_REG(Rn, Tn) \
137 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
141 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
143 #if defined MIPS_DEBUG_DISAS
144 if (loglevel & CPU_LOG_TB_IN_ASM) {
145 fprintf(logfile, "hflags %08x saved %08x\n",
146 ctx->hflags, ctx->saved_hflags);
149 if (do_save_pc && ctx->pc != ctx->saved_pc) {
150 gen_op_save_pc(ctx->pc);
151 ctx->saved_pc = ctx->pc;
153 if (ctx->hflags != ctx->saved_hflags) {
154 gen_op_save_state(ctx->hflags);
155 ctx->saved_hflags = ctx->hflags;
156 if (ctx->hflags & MIPS_HFLAG_BR) {
157 gen_op_save_breg_target();
158 } else if (ctx->hflags & MIPS_HFLAG_B) {
159 gen_op_save_btarget(ctx->btarget);
160 } else if (ctx->hflags & MIPS_HFLAG_BMASK) {
162 gen_op_save_btarget(ctx->btarget);
167 static inline void generate_exception (DisasContext *ctx, int excp)
169 #if defined MIPS_DEBUG_DISAS
170 if (loglevel & CPU_LOG_TB_IN_ASM)
171 fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
173 save_cpu_state(ctx, 1);
174 gen_op_raise_exception(excp);
175 ctx->bstate = BS_EXCP;
178 #if defined(CONFIG_USER_ONLY)
179 #define op_ldst(name) gen_op_##name##_raw()
180 #define OP_LD_TABLE(width)
181 #define OP_ST_TABLE(width)
183 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
184 #define OP_LD_TABLE(width) \
185 static GenOpFunc *gen_op_l##width[] = { \
186 &gen_op_l##width##_user, \
187 &gen_op_l##width##_kernel, \
189 #define OP_ST_TABLE(width) \
190 static GenOpFunc *gen_op_s##width[] = { \
191 &gen_op_s##width##_user, \
192 &gen_op_s##width##_kernel, \
220 static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt,
221 int base, int16_t offset)
223 const unsigned char *opn = "unk";
226 GEN_LOAD_IMM_TN(T0, offset);
227 } else if (offset == 0) {
228 gen_op_load_gpr_T0(base);
230 gen_op_load_gpr_T0(base);
231 gen_op_set_T1(offset);
234 /* Don't do NOP if destination is zero: we must perform the actual
238 #if defined(TARGET_MIPS64)
240 #if defined (MIPS_HAS_UNALIGNED_LS)
244 GEN_STORE_TN_REG(rt, T0);
248 #if defined (MIPS_HAS_UNALIGNED_LS)
251 GEN_LOAD_REG_TN(T1, rt);
257 GEN_STORE_TN_REG(rt, T0);
261 GEN_LOAD_REG_TN(T1, rt);
267 GEN_STORE_TN_REG(rt, T0);
271 GEN_LOAD_REG_TN(T1, rt);
277 #if defined (MIPS_HAS_UNALIGNED_LS)
281 GEN_STORE_TN_REG(rt, T0);
285 #if defined (MIPS_HAS_UNALIGNED_LS)
288 GEN_LOAD_REG_TN(T1, rt);
293 #if defined (MIPS_HAS_UNALIGNED_LS)
297 GEN_STORE_TN_REG(rt, T0);
301 #if defined (MIPS_HAS_UNALIGNED_LS)
304 GEN_LOAD_REG_TN(T1, rt);
309 #if defined (MIPS_HAS_UNALIGNED_LS)
313 GEN_STORE_TN_REG(rt, T0);
318 GEN_STORE_TN_REG(rt, T0);
322 GEN_LOAD_REG_TN(T1, rt);
328 GEN_STORE_TN_REG(rt, T0);
332 GEN_LOAD_REG_TN(T1, rt);
334 GEN_STORE_TN_REG(rt, T0);
338 GEN_LOAD_REG_TN(T1, rt);
343 GEN_LOAD_REG_TN(T1, rt);
345 GEN_STORE_TN_REG(rt, T0);
349 GEN_LOAD_REG_TN(T1, rt);
355 GEN_STORE_TN_REG(rt, T0);
359 GEN_LOAD_REG_TN(T1, rt);
361 GEN_STORE_TN_REG(rt, T0);
365 MIPS_INVAL("load/store");
366 generate_exception(ctx, EXCP_RI);
369 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
372 /* Arithmetic with immediate operand */
373 static void gen_arith_imm (DisasContext *ctx, uint16_t opc, int rt,
377 const unsigned char *opn = "unk";
379 if (rt == 0 && opc != OPC_ADDI) {
380 /* if no destination, treat it as a NOP
381 * For addi, we must generate the overflow exception when needed.
386 if (opc == OPC_ADDI || opc == OPC_ADDIU ||
387 opc == OPC_SLTI || opc == OPC_SLTIU)
388 uimm = (int32_t)imm; /* Sign extent to 32 bits */
390 uimm = (uint16_t)imm;
391 if (opc != OPC_LUI) {
392 GEN_LOAD_REG_TN(T0, rs);
393 GEN_LOAD_IMM_TN(T1, uimm);
396 GEN_LOAD_IMM_TN(T0, uimm);
400 save_cpu_state(ctx, 1);
444 MIPS_INVAL("imm arith");
445 generate_exception(ctx, EXCP_RI);
448 GEN_STORE_TN_REG(rt, T0);
449 MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
453 static void gen_arith (DisasContext *ctx, uint16_t opc,
454 int rd, int rs, int rt)
456 const unsigned char *opn = "unk";
458 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB) {
459 /* if no destination, treat it as a NOP
460 * For add & sub, we must generate the overflow exception when needed.
465 GEN_LOAD_REG_TN(T0, rs);
466 GEN_LOAD_REG_TN(T1, rt);
469 save_cpu_state(ctx, 1);
478 save_cpu_state(ctx, 1);
536 generate_exception(ctx, EXCP_RI);
539 GEN_STORE_TN_REG(rd, T0);
541 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
544 /* Arithmetic on HI/LO registers */
545 static void gen_HILO (DisasContext *ctx, uint16_t opc, int reg)
547 const unsigned char *opn = "unk";
549 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
557 GEN_STORE_TN_REG(reg, T0);
562 GEN_STORE_TN_REG(reg, T0);
566 GEN_LOAD_REG_TN(T0, reg);
571 GEN_LOAD_REG_TN(T0, reg);
577 generate_exception(ctx, EXCP_RI);
580 MIPS_DEBUG("%s %s", opn, regnames[reg]);
583 static void gen_muldiv (DisasContext *ctx, uint16_t opc,
586 const unsigned char *opn = "unk";
588 GEN_LOAD_REG_TN(T0, rs);
589 GEN_LOAD_REG_TN(T1, rt);
624 MIPS_INVAL("mul/div");
625 generate_exception(ctx, EXCP_RI);
628 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
631 static void gen_cl (DisasContext *ctx, uint16_t opc,
634 const unsigned char *opn = "unk";
640 GEN_LOAD_REG_TN(T0, rs);
654 generate_exception(ctx, EXCP_RI);
657 gen_op_store_T0_gpr(rd);
658 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
662 static void gen_trap (DisasContext *ctx, uint16_t opc,
663 int rs, int rt, int16_t imm)
668 /* Load needed operands */
676 /* Compare two registers */
678 GEN_LOAD_REG_TN(T0, rs);
679 GEN_LOAD_REG_TN(T1, rt);
688 /* Compare register to immediate */
689 if (rs != 0 || imm != 0) {
690 GEN_LOAD_REG_TN(T0, rs);
691 GEN_LOAD_IMM_TN(T1, (int32_t)imm);
698 case OPC_TEQ: /* rs == rs */
699 case OPC_TEQI: /* r0 == 0 */
700 case OPC_TGE: /* rs >= rs */
701 case OPC_TGEI: /* r0 >= 0 */
702 case OPC_TGEU: /* rs >= rs unsigned */
703 case OPC_TGEIU: /* r0 >= 0 unsigned */
707 case OPC_TLT: /* rs < rs */
708 case OPC_TLTI: /* r0 < 0 */
709 case OPC_TLTU: /* rs < rs unsigned */
710 case OPC_TLTIU: /* r0 < 0 unsigned */
711 case OPC_TNE: /* rs != rs */
712 case OPC_TNEI: /* r0 != 0 */
713 /* Never trap: treat as NOP */
717 generate_exception(ctx, EXCP_RI);
748 generate_exception(ctx, EXCP_RI);
752 save_cpu_state(ctx, 1);
754 ctx->bstate = BS_STOP;
757 /* Branches (before delay slot) */
758 static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
759 int rs, int rt, int32_t offset)
761 target_ulong btarget;
767 /* Load needed operands */
773 /* Compare two registers */
775 GEN_LOAD_REG_TN(T0, rs);
776 GEN_LOAD_REG_TN(T1, rt);
779 btarget = ctx->pc + 4 + offset;
793 /* Compare to zero */
795 gen_op_load_gpr_T0(rs);
798 btarget = ctx->pc + 4 + offset;
802 /* Jump to immediate */
803 btarget = ((ctx->pc + 4) & 0xF0000000) | offset;
807 /* Jump to register */
809 /* Only hint = 0 is valid */
810 generate_exception(ctx, EXCP_RI);
813 GEN_LOAD_REG_TN(T2, rs);
816 MIPS_INVAL("branch/jump");
817 generate_exception(ctx, EXCP_RI);
821 /* No condition to be computed */
823 case OPC_BEQ: /* rx == rx */
824 case OPC_BEQL: /* rx == rx likely */
825 case OPC_BGEZ: /* 0 >= 0 */
826 case OPC_BGEZL: /* 0 >= 0 likely */
827 case OPC_BLEZ: /* 0 <= 0 */
828 case OPC_BLEZL: /* 0 <= 0 likely */
830 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
831 MIPS_DEBUG("balways");
833 case OPC_BGEZAL: /* 0 >= 0 */
834 case OPC_BGEZALL: /* 0 >= 0 likely */
835 /* Always take and link */
837 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
838 MIPS_DEBUG("balways and link");
840 case OPC_BNE: /* rx != rx */
841 case OPC_BGTZ: /* 0 > 0 */
842 case OPC_BLTZ: /* 0 < 0 */
843 case OPC_BLTZAL: /* 0 < 0 */
845 MIPS_DEBUG("bnever (NOP)");
847 case OPC_BNEL: /* rx != rx likely */
848 case OPC_BGTZL: /* 0 > 0 likely */
849 case OPC_BLTZALL: /* 0 < 0 likely */
850 case OPC_BLTZL: /* 0 < 0 likely */
851 /* Skip the instruction in the delay slot */
852 MIPS_DEBUG("bnever and skip");
853 gen_op_branch((long)ctx->tb, ctx->pc + 4);
856 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
857 MIPS_DEBUG("j %08x", btarget);
861 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
862 MIPS_DEBUG("jal %08x", btarget);
865 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
866 MIPS_DEBUG("jr %s", regnames[rs]);
870 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
871 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
874 MIPS_INVAL("branch/jump");
875 generate_exception(ctx, EXCP_RI);
882 MIPS_DEBUG("beq %s, %s, %08x",
883 regnames[rs], regnames[rt], btarget);
887 MIPS_DEBUG("beql %s, %s, %08x",
888 regnames[rs], regnames[rt], btarget);
892 MIPS_DEBUG("bne %s, %s, %08x",
893 regnames[rs], regnames[rt], btarget);
897 MIPS_DEBUG("bnel %s, %s, %08x",
898 regnames[rs], regnames[rt], btarget);
902 MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
906 MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
910 MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
916 MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
920 MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
924 MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
928 MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
932 MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
936 MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
940 MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
945 MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
947 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BC;
952 MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
954 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BL;
959 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
960 blink, ctx->hflags, btarget);
961 ctx->btarget = btarget;
963 gen_op_set_T0(ctx->pc + 8);
964 gen_op_store_T0_gpr(blink);
969 /* CP0 (MMU and control) */
970 static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd)
972 const unsigned char *opn = "unk";
974 if (!(ctx->CP0_Status & (1 << CP0St_CU0)) &&
975 !(ctx->hflags & MIPS_HFLAG_UM) &&
976 !(ctx->hflags & MIPS_HFLAG_ERL) &&
977 !(ctx->hflags & MIPS_HFLAG_EXL)) {
978 if (loglevel & CPU_LOG_TB_IN_ASM) {
979 fprintf(logfile, "CP0 is not usable\n");
981 gen_op_raise_exception_err(EXCP_CpU, 0);
990 gen_op_mfc0(rd, ctx->opcode & 0x7);
991 gen_op_store_T0_gpr(rt);
995 /* If we get an exception, we want to restart at next instruction */
997 save_cpu_state(ctx, 1);
999 GEN_LOAD_REG_TN(T0, rt);
1000 gen_op_mtc0(rd, ctx->opcode & 0x7);
1001 /* Stop translation as we may have switched the execution mode */
1002 ctx->bstate = BS_STOP;
1005 #if defined(MIPS_USES_R4K_TLB)
1025 save_cpu_state(ctx, 0);
1027 ctx->bstate = BS_EXCP;
1031 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
1032 generate_exception(ctx, EXCP_RI);
1034 save_cpu_state(ctx, 0);
1036 ctx->bstate = BS_EXCP;
1039 /* XXX: TODO: WAIT */
1041 if (loglevel & CPU_LOG_TB_IN_ASM) {
1042 fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
1043 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
1044 ((ctx->opcode >> 16) & 0x1F));
1046 generate_exception(ctx, EXCP_RI);
1049 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
1052 /* Coprocessor 1 (FPU) */
1054 /* ISA extensions */
1055 /* MIPS16 extension to MIPS32 */
1056 /* SmartMIPS extension to MIPS32 */
1058 #ifdef TARGET_MIPS64
1059 static void gen_arith64 (DisasContext *ctx, uint16_t opc)
1061 if (func == 0x02 && rd == 0) {
1065 if (rs == 0 || rt == 0) {
1069 gen_op_load_gpr_T0(rs);
1070 gen_op_load_gpr_T1(rt);
1083 /* Coprocessor 3 (FPU) */
1085 /* MDMX extension to MIPS64 */
1086 /* MIPS-3D extension to MIPS64 */
1090 static void decode_opc (DisasContext *ctx)
1097 if ((ctx->hflags & MIPS_HFLAG_DS) &&
1098 (ctx->hflags & MIPS_HFLAG_BL)) {
1099 /* Handle blikely not taken case */
1100 MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
1101 gen_op_blikely((long)ctx->tb, ctx->pc + 4,
1102 ctx->hflags & ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS));
1104 op = ctx->opcode >> 26;
1105 rs = ((ctx->opcode >> 21) & 0x1F);
1106 rt = ((ctx->opcode >> 16) & 0x1F);
1107 rd = ((ctx->opcode >> 11) & 0x1F);
1108 sa = ((ctx->opcode >> 6) & 0x1F);
1109 imm = (int16_t)ctx->opcode;
1111 case 0x00: /* Special opcode */
1112 op1 = ctx->opcode & 0x3F;
1114 case 0x00: /* Arithmetic with immediate */
1116 gen_arith_imm(ctx, op1 | EXT_SPECIAL, rd, rt, sa);
1118 case 0x04: /* Arithmetic */
1123 gen_arith(ctx, op1 | EXT_SPECIAL, rd, rs, rt);
1125 case 0x18 ... 0x1B: /* MULT / DIV */
1126 gen_muldiv(ctx, op1 | EXT_SPECIAL, rs, rt);
1128 case 0x08 ... 0x09: /* Jumps */
1129 gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa);
1131 case 0x30 ... 0x34: /* Traps */
1133 gen_trap(ctx, op1 | EXT_SPECIAL, rs, rt, -1);
1135 case 0x10: /* Move from HI/LO */
1137 gen_HILO(ctx, op1 | EXT_SPECIAL, rd);
1140 case 0x13: /* Move to HI/LO */
1141 gen_HILO(ctx, op1 | EXT_SPECIAL, rs);
1143 case 0x0C: /* SYSCALL */
1144 generate_exception(ctx, EXCP_SYSCALL);
1146 case 0x0D: /* BREAK */
1147 generate_exception(ctx, EXCP_BREAK);
1149 case 0x0F: /* SYNC */
1150 /* Treat as a noop */
1152 case 0x05: /* Pmon entry point */
1153 gen_op_pmon((ctx->opcode >> 6) & 0x1F);
1155 #if defined (MIPS_HAS_MOVCI)
1156 case 0x01: /* MOVCI */
1158 #if defined (TARGET_MIPS64)
1159 case 0x14: /* MIPS64 specific opcodes */
1168 default: /* Invalid */
1169 MIPS_INVAL("special");
1170 generate_exception(ctx, EXCP_RI);
1174 case 0x1C: /* Special2 opcode */
1175 op1 = ctx->opcode & 0x3F;
1177 #if defined (MIPS_USES_R4K_EXT)
1178 /* Those instructions are not part of MIPS32 core */
1179 case 0x00 ... 0x01: /* Multiply and add/sub */
1181 gen_muldiv(ctx, op1 | EXT_SPECIAL2, rs, rt);
1183 case 0x02: /* MUL */
1184 gen_arith(ctx, op1 | EXT_SPECIAL2, rd, rs, rt);
1186 case 0x20 ... 0x21: /* CLO / CLZ */
1187 gen_cl(ctx, op1 | EXT_SPECIAL2, rd, rs);
1190 case 0x3F: /* SDBBP */
1191 /* XXX: not clear which exception should be raised
1192 * when in debug mode...
1194 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
1195 generate_exception(ctx, EXCP_DBp);
1197 generate_exception(ctx, EXCP_DBp);
1199 /* Treat as a noop */
1201 default: /* Invalid */
1202 MIPS_INVAL("special2");
1203 generate_exception(ctx, EXCP_RI);
1207 case 0x01: /* B REGIMM opcode */
1208 op1 = ((ctx->opcode >> 16) & 0x1F);
1210 case 0x00 ... 0x03: /* REGIMM branches */
1212 gen_compute_branch(ctx, op1 | EXT_REGIMM, rs, -1, imm << 2);
1214 case 0x08 ... 0x0C: /* Traps */
1216 gen_trap(ctx, op1 | EXT_REGIMM, rs, -1, imm);
1218 default: /* Invalid */
1219 MIPS_INVAL("REGIMM");
1220 generate_exception(ctx, EXCP_RI);
1224 case 0x10: /* CP0 opcode */
1225 op1 = ((ctx->opcode >> 21) & 0x1F);
1229 gen_cp0(ctx, op1 | EXT_CP0, rt, rd);
1232 gen_cp0(ctx, (ctx->opcode & 0x1F) | EXT_CP0, rt, rd);
1236 case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */
1237 gen_arith_imm(ctx, op, rt, rs, imm);
1239 case 0x02 ... 0x03: /* Jump */
1240 offset = (int32_t)(ctx->opcode & 0x03FFFFFF) << 2;
1241 gen_compute_branch(ctx, op, rs, rt, offset);
1243 case 0x04 ... 0x07: /* Branch */
1245 gen_compute_branch(ctx, op, rs, rt, imm << 2);
1247 case 0x20 ... 0x26: /* Load and stores */
1251 gen_ldst(ctx, op, rt, rs, imm);
1253 case 0x2F: /* Cache operation */
1254 /* Treat as a noop */
1256 case 0x33: /* Prefetch */
1257 /* Treat as a noop */
1259 case 0x3F: /* HACK */
1261 #if defined(MIPS_USES_FPU)
1262 case 0x31 ... 0x32: /* Floating point load/store */
1266 /* Not implemented */
1267 /* XXX: not correct */
1269 case 0x11: /* CP1 opcode */
1270 /* Not implemented */
1271 /* XXX: not correct */
1272 case 0x12: /* CP2 opcode */
1273 /* Not implemented */
1274 /* XXX: not correct */
1275 case 0x13: /* CP3 opcode */
1276 /* Not implemented */
1277 /* XXX: not correct */
1278 #if defined (TARGET_MIPS64)
1283 /* MIPS64 opcodes */
1285 #if defined (MIPS_HAS_JALX)
1287 /* JALX: not implemented */
1291 #if defined (MIPS_HAS_LSC)
1292 case 0x31: /* LWC1 */
1293 case 0x32: /* LWC2 */
1294 case 0x35: /* SDC1 */
1295 case 0x36: /* SDC2 */
1297 default: /* Invalid */
1299 generate_exception(ctx, EXCP_RI);
1302 if (ctx->hflags & MIPS_HFLAG_DS) {
1303 int hflags = ctx->hflags;
1304 /* Branches completion */
1305 ctx->hflags &= ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS);
1306 ctx->bstate = BS_BRANCH;
1307 save_cpu_state(ctx, 0);
1308 switch (hflags & MIPS_HFLAG_BMASK) {
1310 /* unconditional branch */
1311 MIPS_DEBUG("unconditional branch");
1312 gen_op_branch((long)ctx->tb, ctx->btarget);
1315 /* blikely taken case */
1316 MIPS_DEBUG("blikely branch taken");
1317 gen_op_branch((long)ctx->tb, ctx->btarget);
1320 /* Conditional branch */
1321 MIPS_DEBUG("conditional branch");
1322 gen_op_bcond((long)ctx->tb, ctx->btarget, ctx->pc + 4);
1325 /* unconditional branch to register */
1326 MIPS_DEBUG("branch to register");
1330 MIPS_DEBUG("unknown branch");
1336 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
1339 DisasContext ctx, *ctxp = &ctx;
1340 target_ulong pc_start;
1341 uint16_t *gen_opc_end;
1345 gen_opc_ptr = gen_opc_buf;
1346 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1347 gen_opparam_ptr = gen_opparam_buf;
1350 ctx.bstate = BS_NONE;
1351 /* Restore delay slot state */
1352 ctx.hflags = env->hflags;
1353 ctx.saved_hflags = ctx.hflags;
1354 if (ctx.hflags & MIPS_HFLAG_BR) {
1355 gen_op_restore_breg_target();
1356 } else if (ctx.hflags & MIPS_HFLAG_B) {
1357 ctx.btarget = env->btarget;
1358 } else if (ctx.hflags & MIPS_HFLAG_BMASK) {
1359 /* If we are in the delay slot of a conditional branch,
1360 * restore the branch condition from env->bcond to T2
1362 ctx.btarget = env->btarget;
1363 gen_op_restore_bcond();
1365 #if defined(CONFIG_USER_ONLY)
1368 ctx.mem_idx = (ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 0 : 1;
1370 ctx.CP0_Status = env->CP0_Status;
1372 if (loglevel & CPU_LOG_TB_CPU) {
1373 fprintf(logfile, "------------------------------------------------\n");
1374 cpu_dump_state(env, logfile, fprintf, 0);
1377 #if defined MIPS_DEBUG_DISAS
1378 if (loglevel & CPU_LOG_TB_IN_ASM)
1379 fprintf(logfile, "\ntb %p super %d cond %04x %04x\n",
1380 tb, ctx.mem_idx, ctx.hflags, env->hflags);
1382 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1384 j = gen_opc_ptr - gen_opc_buf;
1385 save_cpu_state(ctxp, 1);
1389 gen_opc_instr_start[lj++] = 0;
1390 gen_opc_pc[lj] = ctx.pc;
1391 gen_opc_instr_start[lj] = 1;
1394 ctx.opcode = ldl_code(ctx.pc);
1397 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1399 #if defined (MIPS_SINGLE_STEP)
1403 if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
1404 save_cpu_state(ctxp, 0);
1405 gen_op_branch((long)ctx.tb, ctx.pc);
1408 /* Generate the return instruction */
1410 *gen_opc_ptr = INDEX_op_end;
1412 j = gen_opc_ptr - gen_opc_buf;
1415 gen_opc_instr_start[lj++] = 0;
1418 tb->size = ctx.pc - pc_start;
1421 #if defined MIPS_DEBUG_DISAS
1422 if (loglevel & CPU_LOG_TB_IN_ASM)
1423 fprintf(logfile, "\n");
1425 if (loglevel & CPU_LOG_TB_IN_ASM) {
1426 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
1427 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
1428 fprintf(logfile, "\n");
1430 if (loglevel & CPU_LOG_TB_OP) {
1431 fprintf(logfile, "OP:\n");
1432 dump_ops(gen_opc_buf, gen_opparam_buf);
1433 fprintf(logfile, "\n");
1435 if (loglevel & CPU_LOG_TB_CPU) {
1436 fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
1443 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1445 return gen_intermediate_code_internal(env, tb, 0);
1448 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1450 return gen_intermediate_code_internal(env, tb, 1);
1453 void cpu_dump_state (CPUState *env, FILE *f,
1454 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1460 cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
1461 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
1462 for (i = 0; i < 32; i++) {
1464 cpu_fprintf(f, "GPR%02d:", i);
1465 cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]);
1467 cpu_fprintf(f, "\n");
1470 c0_status = env->CP0_Status;
1471 if (env->hflags & MIPS_HFLAG_UM)
1472 c0_status |= (1 << CP0St_UM);
1473 if (env->hflags & MIPS_HFLAG_ERL)
1474 c0_status |= (1 << CP0St_ERL);
1475 if (env->hflags & MIPS_HFLAG_EXL)
1476 c0_status |= (1 << CP0St_EXL);
1478 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
1479 c0_status, env->CP0_Cause, env->CP0_EPC);
1480 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
1481 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
1484 CPUMIPSState *cpu_mips_init (void)
1489 env = qemu_mallocz(sizeof(CPUMIPSState));
1494 env->PC = 0xBFC00000;
1495 #if defined (MIPS_USES_R4K_TLB)
1496 env->CP0_random = MIPS_TLB_NB - 1;
1499 env->CP0_Config0 = MIPS_CONFIG0;
1500 #if defined (MIPS_CONFIG1)
1501 env->CP0_Config1 = MIPS_CONFIG1;
1503 #if defined (MIPS_CONFIG2)
1504 env->CP0_Config2 = MIPS_CONFIG2;
1506 #if defined (MIPS_CONFIG3)
1507 env->CP0_Config3 = MIPS_CONFIG3;
1509 env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
1510 env->CP0_WatchLo = 0;
1511 env->hflags = MIPS_HFLAG_ERL;
1512 /* Count register increments in debug mode, EJTAG version 1 */
1513 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
1514 env->CP0_PRid = MIPS_CPU;
1515 env->exception_index = EXCP_NONE;
1517 cpu_single_env = env;