2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 //#define MIPS_DEBUG_DISAS
33 //#define MIPS_SINGLE_STEP
35 #ifdef USE_DIRECT_JUMP
38 #define TBPARAM(x) (long)(x)
42 #define DEF(s, n, copy_size) INDEX_op_ ## s,
48 static uint16_t *gen_opc_ptr;
49 static uint32_t *gen_opparam_ptr;
53 /* MIPS major opcodes */
54 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
57 /* indirect opcode tables */
58 OPC_SPECIAL = (0x00 << 26),
59 OPC_REGIMM = (0x01 << 26),
60 OPC_CP0 = (0x10 << 26),
61 OPC_CP1 = (0x11 << 26),
62 OPC_CP2 = (0x12 << 26),
63 OPC_CP3 = (0x13 << 26),
64 OPC_SPECIAL2 = (0x1C << 26),
65 OPC_SPECIAL3 = (0x1F << 26),
66 /* arithmetic with immediate */
67 OPC_ADDI = (0x08 << 26),
68 OPC_ADDIU = (0x09 << 26),
69 OPC_SLTI = (0x0A << 26),
70 OPC_SLTIU = (0x0B << 26),
71 OPC_ANDI = (0x0C << 26),
72 OPC_ORI = (0x0D << 26),
73 OPC_XORI = (0x0E << 26),
74 OPC_LUI = (0x0F << 26),
75 OPC_DADDI = (0x18 << 26),
76 OPC_DADDIU = (0x19 << 26),
77 /* Jump and branches */
79 OPC_JAL = (0x03 << 26),
80 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
81 OPC_BEQL = (0x14 << 26),
82 OPC_BNE = (0x05 << 26),
83 OPC_BNEL = (0x15 << 26),
84 OPC_BLEZ = (0x06 << 26),
85 OPC_BLEZL = (0x16 << 26),
86 OPC_BGTZ = (0x07 << 26),
87 OPC_BGTZL = (0x17 << 26),
88 OPC_JALX = (0x1D << 26), /* MIPS 16 only */
90 OPC_LDL = (0x1A << 26),
91 OPC_LDR = (0x1B << 26),
92 OPC_LB = (0x20 << 26),
93 OPC_LH = (0x21 << 26),
94 OPC_LWL = (0x22 << 26),
95 OPC_LW = (0x23 << 26),
96 OPC_LBU = (0x24 << 26),
97 OPC_LHU = (0x25 << 26),
98 OPC_LWR = (0x26 << 26),
99 OPC_LWU = (0x27 << 26),
100 OPC_SB = (0x28 << 26),
101 OPC_SH = (0x29 << 26),
102 OPC_SWL = (0x2A << 26),
103 OPC_SW = (0x2B << 26),
104 OPC_SDL = (0x2C << 26),
105 OPC_SDR = (0x2D << 26),
106 OPC_SWR = (0x2E << 26),
107 OPC_LL = (0x30 << 26),
108 OPC_LLD = (0x34 << 26),
109 OPC_LD = (0x37 << 26),
110 OPC_SC = (0x38 << 26),
111 OPC_SCD = (0x3C << 26),
112 OPC_SD = (0x3F << 26),
113 /* Floating point load/store */
114 OPC_LWC1 = (0x31 << 26),
115 OPC_LWC2 = (0x32 << 26),
116 OPC_LDC1 = (0x35 << 26),
117 OPC_LDC2 = (0x36 << 26),
118 OPC_SWC1 = (0x39 << 26),
119 OPC_SWC2 = (0x3A << 26),
120 OPC_SDC1 = (0x3D << 26),
121 OPC_SDC2 = (0x3E << 26),
122 /* MDMX ASE specific */
123 OPC_MDMX = (0x1E << 26),
124 /* Cache and prefetch */
125 OPC_CACHE = (0x2F << 26),
126 OPC_PREF = (0x33 << 26),
127 /* Reserved major opcode */
128 OPC_MAJOR3B_RESERVED = (0x3B << 26),
131 /* MIPS special opcodes */
132 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
136 OPC_SLL = 0x00 | OPC_SPECIAL,
137 /* NOP is SLL r0, r0, 0 */
138 /* SSNOP is SLL r0, r0, 1 */
139 /* EHB is SLL r0, r0, 3 */
140 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
141 OPC_SRA = 0x03 | OPC_SPECIAL,
142 OPC_SLLV = 0x04 | OPC_SPECIAL,
143 OPC_SRLV = 0x06 | OPC_SPECIAL,
144 OPC_SRAV = 0x07 | OPC_SPECIAL,
145 OPC_DSLLV = 0x14 | OPC_SPECIAL,
146 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
147 OPC_DSRAV = 0x17 | OPC_SPECIAL,
148 OPC_DSLL = 0x38 | OPC_SPECIAL,
149 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
150 OPC_DSRA = 0x3B | OPC_SPECIAL,
151 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
152 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
153 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
154 /* Multiplication / division */
155 OPC_MULT = 0x18 | OPC_SPECIAL,
156 OPC_MULTU = 0x19 | OPC_SPECIAL,
157 OPC_DIV = 0x1A | OPC_SPECIAL,
158 OPC_DIVU = 0x1B | OPC_SPECIAL,
159 OPC_DMULT = 0x1C | OPC_SPECIAL,
160 OPC_DMULTU = 0x1D | OPC_SPECIAL,
161 OPC_DDIV = 0x1E | OPC_SPECIAL,
162 OPC_DDIVU = 0x1F | OPC_SPECIAL,
163 /* 2 registers arithmetic / logic */
164 OPC_ADD = 0x20 | OPC_SPECIAL,
165 OPC_ADDU = 0x21 | OPC_SPECIAL,
166 OPC_SUB = 0x22 | OPC_SPECIAL,
167 OPC_SUBU = 0x23 | OPC_SPECIAL,
168 OPC_AND = 0x24 | OPC_SPECIAL,
169 OPC_OR = 0x25 | OPC_SPECIAL,
170 OPC_XOR = 0x26 | OPC_SPECIAL,
171 OPC_NOR = 0x27 | OPC_SPECIAL,
172 OPC_SLT = 0x2A | OPC_SPECIAL,
173 OPC_SLTU = 0x2B | OPC_SPECIAL,
174 OPC_DADD = 0x2C | OPC_SPECIAL,
175 OPC_DADDU = 0x2D | OPC_SPECIAL,
176 OPC_DSUB = 0x2E | OPC_SPECIAL,
177 OPC_DSUBU = 0x2F | OPC_SPECIAL,
179 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
180 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
182 OPC_TGE = 0x30 | OPC_SPECIAL,
183 OPC_TGEU = 0x31 | OPC_SPECIAL,
184 OPC_TLT = 0x32 | OPC_SPECIAL,
185 OPC_TLTU = 0x33 | OPC_SPECIAL,
186 OPC_TEQ = 0x34 | OPC_SPECIAL,
187 OPC_TNE = 0x36 | OPC_SPECIAL,
188 /* HI / LO registers load & stores */
189 OPC_MFHI = 0x10 | OPC_SPECIAL,
190 OPC_MTHI = 0x11 | OPC_SPECIAL,
191 OPC_MFLO = 0x12 | OPC_SPECIAL,
192 OPC_MTLO = 0x13 | OPC_SPECIAL,
193 /* Conditional moves */
194 OPC_MOVZ = 0x0A | OPC_SPECIAL,
195 OPC_MOVN = 0x0B | OPC_SPECIAL,
197 OPC_MOVCI = 0x01 | OPC_SPECIAL,
200 OPC_PMON = 0x05 | OPC_SPECIAL, /* inofficial */
201 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
202 OPC_BREAK = 0x0D | OPC_SPECIAL,
203 OPC_SPIM = 0x0E | OPC_SPECIAL, /* inofficial */
204 OPC_SYNC = 0x0F | OPC_SPECIAL,
206 OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
207 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
208 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
209 OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
210 OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
211 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
212 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
215 /* REGIMM (rt field) opcodes */
216 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
219 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
220 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
221 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
222 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
223 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
224 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
225 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
226 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
227 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
228 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
229 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
230 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
231 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
232 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
233 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
236 /* Special2 opcodes */
237 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
240 /* Multiply & xxx operations */
241 OPC_MADD = 0x00 | OPC_SPECIAL2,
242 OPC_MADDU = 0x01 | OPC_SPECIAL2,
243 OPC_MUL = 0x02 | OPC_SPECIAL2,
244 OPC_MSUB = 0x04 | OPC_SPECIAL2,
245 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
247 OPC_CLZ = 0x20 | OPC_SPECIAL2,
248 OPC_CLO = 0x21 | OPC_SPECIAL2,
249 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
250 OPC_DCLO = 0x25 | OPC_SPECIAL2,
252 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
255 /* Special3 opcodes */
256 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
259 OPC_EXT = 0x00 | OPC_SPECIAL3,
260 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
261 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
262 OPC_DEXT = 0x03 | OPC_SPECIAL3,
263 OPC_INS = 0x04 | OPC_SPECIAL3,
264 OPC_DINSM = 0x05 | OPC_SPECIAL3,
265 OPC_DINSU = 0x06 | OPC_SPECIAL3,
266 OPC_DINS = 0x07 | OPC_SPECIAL3,
267 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
268 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
269 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
273 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
276 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
277 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
278 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
282 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
285 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
286 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
289 /* Coprocessor 0 (rs field) */
290 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
293 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
294 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
295 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
296 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
297 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
298 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
299 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
300 OPC_C0 = (0x10 << 21) | OPC_CP0,
301 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
302 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
306 #define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5)))
309 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
310 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
313 /* Coprocessor 0 (with rs == C0) */
314 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
317 OPC_TLBR = 0x01 | OPC_C0,
318 OPC_TLBWI = 0x02 | OPC_C0,
319 OPC_TLBWR = 0x06 | OPC_C0,
320 OPC_TLBP = 0x08 | OPC_C0,
321 OPC_RFE = 0x10 | OPC_C0,
322 OPC_ERET = 0x18 | OPC_C0,
323 OPC_DERET = 0x1F | OPC_C0,
324 OPC_WAIT = 0x20 | OPC_C0,
327 /* Coprocessor 1 (rs field) */
328 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
331 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
332 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
333 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
334 OPC_MFHCI = (0x03 << 21) | OPC_CP1,
335 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
336 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
337 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
338 OPC_MTHCI = (0x07 << 21) | OPC_CP1,
339 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
340 OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */
341 OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */
342 OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */
343 OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */
344 OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
345 OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
349 OPC_BC1F = (0x00 << 16) | OPC_BC1,
350 OPC_BC1T = (0x01 << 16) | OPC_BC1,
351 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
352 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
355 #define MASK_CP1_BCOND(op) MASK_CP1(op) | (op & ((0x1F << 21) | (0x3 << 16)))
356 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & ((0x1F << 21) | 0x3F))
358 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
359 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
361 const unsigned char *regnames[] =
362 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
363 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
364 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
365 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
367 /* Warning: no function for r0 register (hard wired to zero) */
368 #define GEN32(func, NAME) \
369 static GenOpFunc *NAME ## _table [32] = { \
370 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
371 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
372 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
373 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
374 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
375 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
376 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
377 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
379 static inline void func(int n) \
381 NAME ## _table[n](); \
384 /* General purpose registers moves */
385 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
386 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
387 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
389 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
390 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
392 static const char *fregnames[] =
393 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
394 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
395 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
396 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
398 # define SFGEN32(func, NAME) \
399 static GenOpFunc *NAME ## _table [32] = { \
400 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
401 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
402 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
403 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
404 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
405 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
406 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
407 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
409 static inline void func(int n) \
411 NAME ## _table[n](); \
414 # define DFGEN32(func, NAME) \
415 static GenOpFunc *NAME ## _table [32] = { \
416 NAME ## 0, 0, NAME ## 2, 0, \
417 NAME ## 4, 0, NAME ## 6, 0, \
418 NAME ## 8, 0, NAME ## 10, 0, \
419 NAME ## 12, 0, NAME ## 14, 0, \
420 NAME ## 16, 0, NAME ## 18, 0, \
421 NAME ## 20, 0, NAME ## 22, 0, \
422 NAME ## 24, 0, NAME ## 26, 0, \
423 NAME ## 28, 0, NAME ## 30, 0, \
425 static inline void func(int n) \
427 NAME ## _table[n](); \
430 SFGEN32(gen_op_load_fpr_WT0, gen_op_load_fpr_WT0_fpr);
431 SFGEN32(gen_op_store_fpr_WT0, gen_op_store_fpr_WT0_fpr);
433 SFGEN32(gen_op_load_fpr_WT1, gen_op_load_fpr_WT1_fpr);
434 SFGEN32(gen_op_store_fpr_WT1, gen_op_store_fpr_WT1_fpr);
436 SFGEN32(gen_op_load_fpr_WT2, gen_op_load_fpr_WT2_fpr);
437 SFGEN32(gen_op_store_fpr_WT2, gen_op_store_fpr_WT2_fpr);
439 DFGEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fpr);
440 DFGEN32(gen_op_store_fpr_DT0, gen_op_store_fpr_DT0_fpr);
442 DFGEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fpr);
443 DFGEN32(gen_op_store_fpr_DT1, gen_op_store_fpr_DT1_fpr);
445 DFGEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fpr);
446 DFGEN32(gen_op_store_fpr_DT2, gen_op_store_fpr_DT2_fpr);
448 #define FOP_CONDS(fmt) \
449 static GenOpFunc * cond_ ## fmt ## _table[16] = { \
450 gen_op_cmp_ ## fmt ## _f, \
451 gen_op_cmp_ ## fmt ## _un, \
452 gen_op_cmp_ ## fmt ## _eq, \
453 gen_op_cmp_ ## fmt ## _ueq, \
454 gen_op_cmp_ ## fmt ## _olt, \
455 gen_op_cmp_ ## fmt ## _ult, \
456 gen_op_cmp_ ## fmt ## _ole, \
457 gen_op_cmp_ ## fmt ## _ule, \
458 gen_op_cmp_ ## fmt ## _sf, \
459 gen_op_cmp_ ## fmt ## _ngle, \
460 gen_op_cmp_ ## fmt ## _seq, \
461 gen_op_cmp_ ## fmt ## _ngl, \
462 gen_op_cmp_ ## fmt ## _lt, \
463 gen_op_cmp_ ## fmt ## _nge, \
464 gen_op_cmp_ ## fmt ## _le, \
465 gen_op_cmp_ ## fmt ## _ngt, \
467 static inline void gen_cmp_ ## fmt(int n) \
469 cond_ ## fmt ## _table[n](); \
475 typedef struct DisasContext {
476 struct TranslationBlock *tb;
477 target_ulong pc, saved_pc;
479 /* Routine used to access memory */
481 uint32_t hflags, saved_hflags;
484 target_ulong btarget;
488 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
489 * exception condition
491 BS_STOP = 1, /* We want to stop translation for any reason */
492 BS_BRANCH = 2, /* We reached a branch condition */
493 BS_EXCP = 3, /* We reached an exception condition */
496 #if defined MIPS_DEBUG_DISAS
497 #define MIPS_DEBUG(fmt, args...) \
499 if (loglevel & CPU_LOG_TB_IN_ASM) { \
500 fprintf(logfile, "%08x: %08x " fmt "\n", \
501 ctx->pc, ctx->opcode , ##args); \
505 #define MIPS_DEBUG(fmt, args...) do { } while(0)
508 #define MIPS_INVAL(op) \
510 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
511 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
514 #define GEN_LOAD_REG_TN(Tn, Rn) \
517 glue(gen_op_reset_, Tn)(); \
519 glue(gen_op_load_gpr_, Tn)(Rn); \
523 #define GEN_LOAD_IMM_TN(Tn, Imm) \
526 glue(gen_op_reset_, Tn)(); \
528 glue(gen_op_set_, Tn)(Imm); \
532 #define GEN_STORE_TN_REG(Rn, Tn) \
535 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
539 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
541 glue(gen_op_load_fpr_, FTn)(Fn); \
544 #define GEN_STORE_FTN_FREG(Fn, FTn) \
546 glue(gen_op_store_fpr_, FTn)(Fn); \
549 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
551 #if defined MIPS_DEBUG_DISAS
552 if (loglevel & CPU_LOG_TB_IN_ASM) {
553 fprintf(logfile, "hflags %08x saved %08x\n",
554 ctx->hflags, ctx->saved_hflags);
557 if (do_save_pc && ctx->pc != ctx->saved_pc) {
558 gen_op_save_pc(ctx->pc);
559 ctx->saved_pc = ctx->pc;
561 if (ctx->hflags != ctx->saved_hflags) {
562 gen_op_save_state(ctx->hflags);
563 ctx->saved_hflags = ctx->hflags;
564 if (ctx->hflags & MIPS_HFLAG_BR) {
565 gen_op_save_breg_target();
566 } else if (ctx->hflags & MIPS_HFLAG_B) {
567 gen_op_save_btarget(ctx->btarget);
568 } else if (ctx->hflags & MIPS_HFLAG_BMASK) {
570 gen_op_save_btarget(ctx->btarget);
575 static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
577 #if defined MIPS_DEBUG_DISAS
578 if (loglevel & CPU_LOG_TB_IN_ASM)
579 fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
581 save_cpu_state(ctx, 1);
583 gen_op_raise_exception(excp);
585 gen_op_raise_exception_err(excp, err);
586 ctx->bstate = BS_EXCP;
589 static inline void generate_exception (DisasContext *ctx, int excp)
591 generate_exception_err (ctx, excp, 0);
594 #if defined(CONFIG_USER_ONLY)
595 #define op_ldst(name) gen_op_##name##_raw()
596 #define OP_LD_TABLE(width)
597 #define OP_ST_TABLE(width)
599 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
600 #define OP_LD_TABLE(width) \
601 static GenOpFunc *gen_op_l##width[] = { \
602 &gen_op_l##width##_user, \
603 &gen_op_l##width##_kernel, \
605 #define OP_ST_TABLE(width) \
606 static GenOpFunc *gen_op_s##width[] = { \
607 &gen_op_s##width##_user, \
608 &gen_op_s##width##_kernel, \
612 #ifdef MIPS_HAS_MIPS64
641 static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
642 int base, int16_t offset)
644 const char *opn = "unk";
647 GEN_LOAD_IMM_TN(T0, offset);
648 } else if (offset == 0) {
649 gen_op_load_gpr_T0(base);
651 gen_op_load_gpr_T0(base);
652 gen_op_set_T1(offset);
655 /* Don't do NOP if destination is zero: we must perform the actual
659 #ifdef MIPS_HAS_MIPS64
662 GEN_STORE_TN_REG(rt, T0);
667 GEN_STORE_TN_REG(rt, T0);
671 GEN_LOAD_REG_TN(T1, rt);
676 GEN_LOAD_REG_TN(T1, rt);
682 GEN_STORE_TN_REG(rt, T0);
686 GEN_LOAD_REG_TN(T1, rt);
692 GEN_STORE_TN_REG(rt, T0);
696 GEN_LOAD_REG_TN(T1, rt);
703 GEN_STORE_TN_REG(rt, T0);
708 GEN_STORE_TN_REG(rt, T0);
712 GEN_LOAD_REG_TN(T1, rt);
718 GEN_STORE_TN_REG(rt, T0);
722 GEN_LOAD_REG_TN(T1, rt);
728 GEN_STORE_TN_REG(rt, T0);
733 GEN_STORE_TN_REG(rt, T0);
737 GEN_LOAD_REG_TN(T1, rt);
743 GEN_STORE_TN_REG(rt, T0);
747 GEN_LOAD_REG_TN(T1, rt);
749 GEN_STORE_TN_REG(rt, T0);
753 GEN_LOAD_REG_TN(T1, rt);
758 GEN_LOAD_REG_TN(T1, rt);
760 GEN_STORE_TN_REG(rt, T0);
764 GEN_LOAD_REG_TN(T1, rt);
770 GEN_STORE_TN_REG(rt, T0);
774 GEN_LOAD_REG_TN(T1, rt);
776 GEN_STORE_TN_REG(rt, T0);
780 MIPS_INVAL("load/store");
781 generate_exception(ctx, EXCP_RI);
784 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
788 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
789 int base, int16_t offset)
791 const char *opn = "unk";
794 GEN_LOAD_IMM_TN(T0, offset);
795 } else if (offset == 0) {
796 gen_op_load_gpr_T0(base);
798 gen_op_load_gpr_T0(base);
799 gen_op_set_T1(offset);
802 /* Don't do NOP if destination is zero: we must perform the actual
808 GEN_STORE_FTN_FREG(ft, WT0);
812 GEN_LOAD_FREG_FTN(WT0, ft);
818 GEN_STORE_FTN_FREG(ft, DT0);
822 GEN_LOAD_FREG_FTN(DT0, ft);
827 MIPS_INVAL("float load/store");
828 generate_exception_err(ctx, EXCP_CpU, 1);
831 MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
834 /* Arithmetic with immediate operand */
835 static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
839 const char *opn = "unk";
841 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
842 /* if no destination, treat it as a NOP
843 * For addi, we must generate the overflow exception when needed.
848 if (opc == OPC_ADDI || opc == OPC_ADDIU ||
849 opc == OPC_DADDI || opc == OPC_DADDIU ||
850 opc == OPC_SLTI || opc == OPC_SLTIU)
851 uimm = (int32_t)imm; /* Sign extend to 32 bits */
853 uimm = (uint16_t)imm;
854 if (opc != OPC_LUI) {
855 GEN_LOAD_REG_TN(T0, rs);
856 GEN_LOAD_IMM_TN(T1, uimm);
859 GEN_LOAD_IMM_TN(T0, uimm);
863 save_cpu_state(ctx, 1);
871 #ifdef MIPS_HAS_MIPS64
873 save_cpu_state(ctx, 1);
914 if ((ctx->opcode >> 21) & 1) {
922 #ifdef MIPS_HAS_MIPS64
932 if ((ctx->opcode >> 21) & 1) {
949 if ((ctx->opcode >> 21) & 1) {
959 MIPS_INVAL("imm arith");
960 generate_exception(ctx, EXCP_RI);
963 GEN_STORE_TN_REG(rt, T0);
964 MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
968 static void gen_arith (DisasContext *ctx, uint32_t opc,
969 int rd, int rs, int rt)
971 const char *opn = "unk";
973 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
974 && opc != OPC_DADD && opc != OPC_DSUB) {
975 /* if no destination, treat it as a NOP
976 * For add & sub, we must generate the overflow exception when needed.
981 GEN_LOAD_REG_TN(T0, rs);
982 GEN_LOAD_REG_TN(T1, rt);
985 save_cpu_state(ctx, 1);
994 save_cpu_state(ctx, 1);
1002 #ifdef MIPS_HAS_MIPS64
1004 save_cpu_state(ctx, 1);
1013 save_cpu_state(ctx, 1);
1067 if ((ctx->opcode >> 6) & 1) {
1075 #ifdef MIPS_HAS_MIPS64
1085 if ((ctx->opcode >> 6) & 1) {
1095 MIPS_INVAL("arith");
1096 generate_exception(ctx, EXCP_RI);
1099 GEN_STORE_TN_REG(rd, T0);
1101 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1104 /* Arithmetic on HI/LO registers */
1105 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1107 const char *opn = "unk";
1109 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1110 /* Treat as a NOP */
1117 GEN_STORE_TN_REG(reg, T0);
1122 GEN_STORE_TN_REG(reg, T0);
1126 GEN_LOAD_REG_TN(T0, reg);
1131 GEN_LOAD_REG_TN(T0, reg);
1137 generate_exception(ctx, EXCP_RI);
1140 MIPS_DEBUG("%s %s", opn, regnames[reg]);
1143 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1146 const char *opn = "unk";
1148 GEN_LOAD_REG_TN(T0, rs);
1149 GEN_LOAD_REG_TN(T1, rt);
1167 #ifdef MIPS_HAS_MIPS64
1202 MIPS_INVAL("mul/div");
1203 generate_exception(ctx, EXCP_RI);
1206 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
1209 static void gen_cl (DisasContext *ctx, uint32_t opc,
1212 const char *opn = "unk";
1214 /* Treat as a NOP */
1218 GEN_LOAD_REG_TN(T0, rs);
1228 #ifdef MIPS_HAS_MIPS64
1240 generate_exception(ctx, EXCP_RI);
1243 gen_op_store_T0_gpr(rd);
1244 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
1248 static void gen_trap (DisasContext *ctx, uint32_t opc,
1249 int rs, int rt, int16_t imm)
1254 /* Load needed operands */
1262 /* Compare two registers */
1264 GEN_LOAD_REG_TN(T0, rs);
1265 GEN_LOAD_REG_TN(T1, rt);
1274 /* Compare register to immediate */
1275 if (rs != 0 || imm != 0) {
1276 GEN_LOAD_REG_TN(T0, rs);
1277 GEN_LOAD_IMM_TN(T1, (int32_t)imm);
1284 case OPC_TEQ: /* rs == rs */
1285 case OPC_TEQI: /* r0 == 0 */
1286 case OPC_TGE: /* rs >= rs */
1287 case OPC_TGEI: /* r0 >= 0 */
1288 case OPC_TGEU: /* rs >= rs unsigned */
1289 case OPC_TGEIU: /* r0 >= 0 unsigned */
1293 case OPC_TLT: /* rs < rs */
1294 case OPC_TLTI: /* r0 < 0 */
1295 case OPC_TLTU: /* rs < rs unsigned */
1296 case OPC_TLTIU: /* r0 < 0 unsigned */
1297 case OPC_TNE: /* rs != rs */
1298 case OPC_TNEI: /* r0 != 0 */
1299 /* Never trap: treat as NOP */
1303 generate_exception(ctx, EXCP_RI);
1334 generate_exception(ctx, EXCP_RI);
1338 save_cpu_state(ctx, 1);
1340 ctx->bstate = BS_STOP;
1343 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1345 TranslationBlock *tb;
1347 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1349 gen_op_goto_tb0(TBPARAM(tb));
1351 gen_op_goto_tb1(TBPARAM(tb));
1352 gen_op_save_pc(dest);
1353 gen_op_set_T0((long)tb + n);
1356 gen_op_save_pc(dest);
1362 /* Branches (before delay slot) */
1363 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1364 int rs, int rt, int32_t offset)
1366 target_ulong btarget;
1372 /* Load needed operands */
1378 /* Compare two registers */
1380 GEN_LOAD_REG_TN(T0, rs);
1381 GEN_LOAD_REG_TN(T1, rt);
1384 btarget = ctx->pc + 4 + offset;
1398 /* Compare to zero */
1400 gen_op_load_gpr_T0(rs);
1403 btarget = ctx->pc + 4 + offset;
1407 /* Jump to immediate */
1408 btarget = ((ctx->pc + 4) & 0xF0000000) | offset;
1412 /* Jump to register */
1413 if (offset != 0 && offset != 16) {
1414 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1415 others are reserved. */
1416 generate_exception(ctx, EXCP_RI);
1419 GEN_LOAD_REG_TN(T2, rs);
1422 MIPS_INVAL("branch/jump");
1423 generate_exception(ctx, EXCP_RI);
1427 /* No condition to be computed */
1429 case OPC_BEQ: /* rx == rx */
1430 case OPC_BEQL: /* rx == rx likely */
1431 case OPC_BGEZ: /* 0 >= 0 */
1432 case OPC_BGEZL: /* 0 >= 0 likely */
1433 case OPC_BLEZ: /* 0 <= 0 */
1434 case OPC_BLEZL: /* 0 <= 0 likely */
1436 ctx->hflags |= MIPS_HFLAG_B;
1437 MIPS_DEBUG("balways");
1439 case OPC_BGEZAL: /* 0 >= 0 */
1440 case OPC_BGEZALL: /* 0 >= 0 likely */
1441 /* Always take and link */
1443 ctx->hflags |= MIPS_HFLAG_B;
1444 MIPS_DEBUG("balways and link");
1446 case OPC_BNE: /* rx != rx */
1447 case OPC_BGTZ: /* 0 > 0 */
1448 case OPC_BLTZ: /* 0 < 0 */
1449 /* Treated as NOP */
1450 MIPS_DEBUG("bnever (NOP)");
1452 case OPC_BLTZAL: /* 0 < 0 */
1453 gen_op_set_T0(ctx->pc + 8);
1454 gen_op_store_T0_gpr(31);
1456 case OPC_BLTZALL: /* 0 < 0 likely */
1457 gen_op_set_T0(ctx->pc + 8);
1458 gen_op_store_T0_gpr(31);
1459 gen_goto_tb(ctx, 0, ctx->pc + 4);
1461 case OPC_BNEL: /* rx != rx likely */
1462 case OPC_BGTZL: /* 0 > 0 likely */
1463 case OPC_BLTZL: /* 0 < 0 likely */
1464 /* Skip the instruction in the delay slot */
1465 MIPS_DEBUG("bnever and skip");
1466 gen_goto_tb(ctx, 0, ctx->pc + 4);
1469 ctx->hflags |= MIPS_HFLAG_B;
1470 MIPS_DEBUG("j %08x", btarget);
1474 ctx->hflags |= MIPS_HFLAG_B;
1475 MIPS_DEBUG("jal %08x", btarget);
1478 ctx->hflags |= MIPS_HFLAG_BR;
1479 MIPS_DEBUG("jr %s", regnames[rs]);
1483 ctx->hflags |= MIPS_HFLAG_BR;
1484 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
1487 MIPS_INVAL("branch/jump");
1488 generate_exception(ctx, EXCP_RI);
1495 MIPS_DEBUG("beq %s, %s, %08x",
1496 regnames[rs], regnames[rt], btarget);
1500 MIPS_DEBUG("beql %s, %s, %08x",
1501 regnames[rs], regnames[rt], btarget);
1505 MIPS_DEBUG("bne %s, %s, %08x",
1506 regnames[rs], regnames[rt], btarget);
1510 MIPS_DEBUG("bnel %s, %s, %08x",
1511 regnames[rs], regnames[rt], btarget);
1515 MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
1519 MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
1523 MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
1529 MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
1533 MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
1537 MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
1541 MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
1545 MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
1549 MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
1553 MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
1558 MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
1560 ctx->hflags |= MIPS_HFLAG_BC;
1565 MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
1567 ctx->hflags |= MIPS_HFLAG_BL;
1572 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
1573 blink, ctx->hflags, btarget);
1574 ctx->btarget = btarget;
1576 gen_op_set_T0(ctx->pc + 8);
1577 gen_op_store_T0_gpr(blink);
1582 /* special3 bitfield operations */
1583 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
1584 int rs, int lsb, int msb)
1586 GEN_LOAD_REG_TN(T1, rs);
1591 gen_op_ext(lsb, msb + 1);
1596 gen_op_ext(lsb, msb + 1 + 32);
1601 gen_op_ext(lsb + 32, msb + 1);
1604 gen_op_ext(lsb, msb + 1);
1609 GEN_LOAD_REG_TN(T2, rt);
1610 gen_op_ins(lsb, msb - lsb + 1);
1615 GEN_LOAD_REG_TN(T2, rt);
1616 gen_op_ins(lsb, msb - lsb + 1 + 32);
1621 GEN_LOAD_REG_TN(T2, rt);
1622 gen_op_ins(lsb + 32, msb - lsb + 1);
1627 GEN_LOAD_REG_TN(T2, rt);
1628 gen_op_ins(lsb, msb - lsb + 1);
1632 MIPS_INVAL("bitops");
1633 generate_exception(ctx, EXCP_RI);
1636 GEN_STORE_TN_REG(rt, T0);
1639 /* CP0 (MMU and control) */
1640 static void gen_mfc0 (DisasContext *ctx, int reg, int sel)
1642 const char *rn = "invalid";
1648 gen_op_mfc0_index();
1652 // gen_op_mfc0_mvpcontrol(); /* MT ASE */
1656 // gen_op_mfc0_mvpconf0(); /* MT ASE */
1660 // gen_op_mfc0_mvpconf1(); /* MT ASE */
1670 gen_op_mfc0_random();
1674 // gen_op_mfc0_vpecontrol(); /* MT ASE */
1678 // gen_op_mfc0_vpeconf0(); /* MT ASE */
1682 // gen_op_mfc0_vpeconf1(); /* MT ASE */
1686 // gen_op_mfc0_YQMask(); /* MT ASE */
1690 // gen_op_mfc0_vpeschedule(); /* MT ASE */
1694 // gen_op_mfc0_vpeschefback(); /* MT ASE */
1695 rn = "VPEScheFBack";
1698 // gen_op_mfc0_vpeopt(); /* MT ASE */
1708 gen_op_mfc0_entrylo0();
1712 // gen_op_mfc0_tcstatus(); /* MT ASE */
1716 // gen_op_mfc0_tcbind(); /* MT ASE */
1720 // gen_op_mfc0_tcrestart(); /* MT ASE */
1724 // gen_op_mfc0_tchalt(); /* MT ASE */
1728 // gen_op_mfc0_tccontext(); /* MT ASE */
1732 // gen_op_mfc0_tcschedule(); /* MT ASE */
1736 // gen_op_mfc0_tcschefback(); /* MT ASE */
1746 gen_op_mfc0_entrylo1();
1756 gen_op_mfc0_context();
1760 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1761 rn = "ContextConfig";
1770 gen_op_mfc0_pagemask();
1774 gen_op_mfc0_pagegrain();
1784 gen_op_mfc0_wired();
1788 // gen_op_mfc0_srsconf0(); /* shadow registers */
1792 // gen_op_mfc0_srsconf1(); /* shadow registers */
1796 // gen_op_mfc0_srsconf2(); /* shadow registers */
1800 // gen_op_mfc0_srsconf3(); /* shadow registers */
1804 // gen_op_mfc0_srsconf4(); /* shadow registers */
1814 gen_op_mfc0_hwrena();
1824 gen_op_mfc0_badvaddr();
1834 gen_op_mfc0_count();
1837 /* 6,7 are implementation dependent */
1845 gen_op_mfc0_entryhi();
1855 gen_op_mfc0_compare();
1858 /* 6,7 are implementation dependent */
1866 gen_op_mfc0_status();
1870 gen_op_mfc0_intctl();
1874 gen_op_mfc0_srsctl();
1878 // gen_op_mfc0_srsmap(); /* shadow registers */
1888 gen_op_mfc0_cause();
1912 gen_op_mfc0_ebase();
1922 gen_op_mfc0_config0();
1926 gen_op_mfc0_config1();
1930 gen_op_mfc0_config2();
1934 gen_op_mfc0_config3();
1937 /* 6,7 are implementation dependent */
1945 gen_op_mfc0_lladdr();
1955 gen_op_mfc0_watchlo0();
1959 // gen_op_mfc0_watchlo1();
1963 // gen_op_mfc0_watchlo2();
1967 // gen_op_mfc0_watchlo3();
1971 // gen_op_mfc0_watchlo4();
1975 // gen_op_mfc0_watchlo5();
1979 // gen_op_mfc0_watchlo6();
1983 // gen_op_mfc0_watchlo7();
1993 gen_op_mfc0_watchhi0();
1997 // gen_op_mfc0_watchhi1();
2001 // gen_op_mfc0_watchhi2();
2005 // gen_op_mfc0_watchhi3();
2009 // gen_op_mfc0_watchhi4();
2013 // gen_op_mfc0_watchhi5();
2017 // gen_op_mfc0_watchhi6();
2021 // gen_op_mfc0_watchhi7();
2031 /* 64 bit MMU only */
2032 gen_op_mfc0_xcontext();
2040 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2043 gen_op_mfc0_framemask();
2052 rn = "'Diagnostic"; /* implementation dependent */
2057 gen_op_mfc0_debug(); /* EJTAG support */
2061 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2062 rn = "TraceControl";
2065 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2066 rn = "TraceControl2";
2069 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2070 rn = "UserTraceData";
2073 // gen_op_mfc0_debug(); /* PDtrace support */
2083 gen_op_mfc0_depc(); /* EJTAG support */
2093 gen_op_mfc0_performance0();
2094 rn = "Performance0";
2097 // gen_op_mfc0_performance1();
2098 rn = "Performance1";
2101 // gen_op_mfc0_performance2();
2102 rn = "Performance2";
2105 // gen_op_mfc0_performance3();
2106 rn = "Performance3";
2109 // gen_op_mfc0_performance4();
2110 rn = "Performance4";
2113 // gen_op_mfc0_performance5();
2114 rn = "Performance5";
2117 // gen_op_mfc0_performance6();
2118 rn = "Performance6";
2121 // gen_op_mfc0_performance7();
2122 rn = "Performance7";
2147 gen_op_mfc0_taglo();
2154 gen_op_mfc0_datalo();
2167 gen_op_mfc0_taghi();
2174 gen_op_mfc0_datahi();
2184 gen_op_mfc0_errorepc();
2194 gen_op_mfc0_desave(); /* EJTAG support */
2204 #if defined MIPS_DEBUG_DISAS
2205 if (loglevel & CPU_LOG_TB_IN_ASM) {
2206 fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
2213 #if defined MIPS_DEBUG_DISAS
2214 if (loglevel & CPU_LOG_TB_IN_ASM) {
2215 fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
2219 generate_exception(ctx, EXCP_RI);
2222 static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
2224 const char *rn = "invalid";
2230 gen_op_mtc0_index();
2234 // gen_op_mtc0_mvpcontrol(); /* MT ASE */
2238 // gen_op_mtc0_mvpconf0(); /* MT ASE */
2242 // gen_op_mtc0_mvpconf1(); /* MT ASE */
2256 // gen_op_mtc0_vpecontrol(); /* MT ASE */
2260 // gen_op_mtc0_vpeconf0(); /* MT ASE */
2264 // gen_op_mtc0_vpeconf1(); /* MT ASE */
2268 // gen_op_mtc0_YQMask(); /* MT ASE */
2272 // gen_op_mtc0_vpeschedule(); /* MT ASE */
2276 // gen_op_mtc0_vpeschefback(); /* MT ASE */
2277 rn = "VPEScheFBack";
2280 // gen_op_mtc0_vpeopt(); /* MT ASE */
2290 gen_op_mtc0_entrylo0();
2294 // gen_op_mtc0_tcstatus(); /* MT ASE */
2298 // gen_op_mtc0_tcbind(); /* MT ASE */
2302 // gen_op_mtc0_tcrestart(); /* MT ASE */
2306 // gen_op_mtc0_tchalt(); /* MT ASE */
2310 // gen_op_mtc0_tccontext(); /* MT ASE */
2314 // gen_op_mtc0_tcschedule(); /* MT ASE */
2318 // gen_op_mtc0_tcschefback(); /* MT ASE */
2328 gen_op_mtc0_entrylo1();
2338 gen_op_mtc0_context();
2342 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2343 rn = "ContextConfig";
2352 gen_op_mtc0_pagemask();
2356 gen_op_mtc0_pagegrain();
2366 gen_op_mtc0_wired();
2370 // gen_op_mtc0_srsconf0(); /* shadow registers */
2374 // gen_op_mtc0_srsconf1(); /* shadow registers */
2378 // gen_op_mtc0_srsconf2(); /* shadow registers */
2382 // gen_op_mtc0_srsconf3(); /* shadow registers */
2386 // gen_op_mtc0_srsconf4(); /* shadow registers */
2396 gen_op_mtc0_hwrena();
2410 gen_op_mtc0_count();
2413 /* 6,7 are implementation dependent */
2417 /* Stop translation as we may have switched the execution mode */
2418 ctx->bstate = BS_STOP;
2423 gen_op_mtc0_entryhi();
2433 gen_op_mtc0_compare();
2436 /* 6,7 are implementation dependent */
2440 /* Stop translation as we may have switched the execution mode */
2441 ctx->bstate = BS_STOP;
2446 gen_op_mtc0_status();
2450 gen_op_mtc0_intctl();
2454 gen_op_mtc0_srsctl();
2458 // gen_op_mtc0_srsmap(); /* shadow registers */
2464 /* Stop translation as we may have switched the execution mode */
2465 ctx->bstate = BS_STOP;
2470 gen_op_mtc0_cause();
2476 /* Stop translation as we may have switched the execution mode */
2477 ctx->bstate = BS_STOP;
2496 gen_op_mtc0_ebase();
2506 gen_op_mtc0_config0();
2514 gen_op_mtc0_config2();
2521 /* 6,7 are implementation dependent */
2523 rn = "Invalid config selector";
2526 /* Stop translation as we may have switched the execution mode */
2527 ctx->bstate = BS_STOP;
2542 gen_op_mtc0_watchlo0();
2546 // gen_op_mtc0_watchlo1();
2550 // gen_op_mtc0_watchlo2();
2554 // gen_op_mtc0_watchlo3();
2558 // gen_op_mtc0_watchlo4();
2562 // gen_op_mtc0_watchlo5();
2566 // gen_op_mtc0_watchlo6();
2570 // gen_op_mtc0_watchlo7();
2580 gen_op_mtc0_watchhi0();
2584 // gen_op_mtc0_watchhi1();
2588 // gen_op_mtc0_watchhi2();
2592 // gen_op_mtc0_watchhi3();
2596 // gen_op_mtc0_watchhi4();
2600 // gen_op_mtc0_watchhi5();
2604 // gen_op_mtc0_watchhi6();
2608 // gen_op_mtc0_watchhi7();
2618 /* 64 bit MMU only */
2619 gen_op_mtc0_xcontext();
2627 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2630 gen_op_mtc0_framemask();
2639 rn = "Diagnostic"; /* implementation dependent */
2644 gen_op_mtc0_debug(); /* EJTAG support */
2648 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
2649 rn = "TraceControl";
2652 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2653 rn = "TraceControl2";
2656 // gen_op_mtc0_usertracedata(); /* PDtrace support */
2657 rn = "UserTraceData";
2660 // gen_op_mtc0_debug(); /* PDtrace support */
2666 /* Stop translation as we may have switched the execution mode */
2667 ctx->bstate = BS_STOP;
2672 gen_op_mtc0_depc(); /* EJTAG support */
2682 gen_op_mtc0_performance0();
2683 rn = "Performance0";
2686 // gen_op_mtc0_performance1();
2687 rn = "Performance1";
2690 // gen_op_mtc0_performance2();
2691 rn = "Performance2";
2694 // gen_op_mtc0_performance3();
2695 rn = "Performance3";
2698 // gen_op_mtc0_performance4();
2699 rn = "Performance4";
2702 // gen_op_mtc0_performance5();
2703 rn = "Performance5";
2706 // gen_op_mtc0_performance6();
2707 rn = "Performance6";
2710 // gen_op_mtc0_performance7();
2711 rn = "Performance7";
2737 gen_op_mtc0_taglo();
2744 gen_op_mtc0_datalo();
2757 gen_op_mtc0_taghi();
2764 gen_op_mtc0_datahi();
2775 gen_op_mtc0_errorepc();
2785 gen_op_mtc0_desave(); /* EJTAG support */
2791 /* Stop translation as we may have switched the execution mode */
2792 ctx->bstate = BS_STOP;
2797 #if defined MIPS_DEBUG_DISAS
2798 if (loglevel & CPU_LOG_TB_IN_ASM) {
2799 fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
2806 #if defined MIPS_DEBUG_DISAS
2807 if (loglevel & CPU_LOG_TB_IN_ASM) {
2808 fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
2812 generate_exception(ctx, EXCP_RI);
2815 static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
2817 const char *opn = "unk";
2819 if (!(ctx->CP0_Status & (1 << CP0St_CU0)) &&
2820 (ctx->hflags & MIPS_HFLAG_UM) &&
2821 !(ctx->hflags & MIPS_HFLAG_ERL) &&
2822 !(ctx->hflags & MIPS_HFLAG_EXL)) {
2823 if (loglevel & CPU_LOG_TB_IN_ASM) {
2824 fprintf(logfile, "CP0 is not usable\n");
2826 generate_exception (ctx, EXCP_CpU);
2836 gen_mfc0(ctx, rd, ctx->opcode & 0x7);
2837 gen_op_store_T0_gpr(rt);
2841 /* If we get an exception, we want to restart at next instruction */
2842 /* XXX: breaks for mtc in delay slot */
2844 save_cpu_state(ctx, 1);
2846 GEN_LOAD_REG_TN(T0, rt);
2847 gen_mtc0(ctx, rd, ctx->opcode & 0x7);
2850 #if defined(MIPS_USES_R4K_TLB)
2870 save_cpu_state(ctx, 0);
2872 ctx->bstate = BS_EXCP;
2876 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
2877 generate_exception(ctx, EXCP_RI);
2879 save_cpu_state(ctx, 0);
2881 ctx->bstate = BS_EXCP;
2886 /* If we get an exception, we want to restart at next instruction */
2888 save_cpu_state(ctx, 1);
2891 ctx->bstate = BS_EXCP;
2894 if (loglevel & CPU_LOG_TB_IN_ASM) {
2895 fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
2896 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
2897 ((ctx->opcode >> 16) & 0x1F));
2899 generate_exception(ctx, EXCP_RI);
2902 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
2905 /* CP1 Branches (before delay slot) */
2906 static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
2909 target_ulong btarget;
2911 btarget = ctx->pc + 4 + offset;
2916 MIPS_DEBUG("bc1f %08x", btarget);
2920 MIPS_DEBUG("bc1fl %08x", btarget);
2924 MIPS_DEBUG("bc1t %08x", btarget);
2926 ctx->hflags |= MIPS_HFLAG_BC;
2930 MIPS_DEBUG("bc1tl %08x", btarget);
2932 ctx->hflags |= MIPS_HFLAG_BL;
2935 MIPS_INVAL("cp1 branch/jump");
2936 generate_exception_err (ctx, EXCP_RI, 1);
2941 MIPS_DEBUG("enter ds: cond %02x target %08x",
2942 ctx->hflags, btarget);
2943 ctx->btarget = btarget;
2948 /* Coprocessor 1 (FPU) */
2949 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
2951 const char *opn = "unk";
2955 GEN_LOAD_FREG_FTN(WT0, fs);
2957 GEN_STORE_TN_REG(rt, T0);
2961 GEN_LOAD_REG_TN(T0, rt);
2963 GEN_STORE_FTN_FREG(fs, WT0);
2967 if (fs != 0 && fs != 31) {
2968 MIPS_INVAL("cfc1 freg");
2969 generate_exception_err (ctx, EXCP_RI, 1);
2972 GEN_LOAD_IMM_TN(T1, fs);
2974 GEN_STORE_TN_REG(rt, T0);
2978 if (fs != 0 && fs != 31) {
2979 MIPS_INVAL("ctc1 freg");
2980 generate_exception_err (ctx, EXCP_RI, 1);
2983 GEN_LOAD_IMM_TN(T1, fs);
2984 GEN_LOAD_REG_TN(T0, rt);
2989 if (loglevel & CPU_LOG_TB_IN_ASM) {
2990 fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
2991 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
2992 ((ctx->opcode >> 16) & 0x1F));
2994 generate_exception_err (ctx, EXCP_RI, 1);
2997 MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
3000 /* verify if floating point register is valid; an operation is not defined
3001 * if bit 0 of any register specification is set and the FR bit in the
3002 * Status register equals zero, since the register numbers specify an
3003 * even-odd pair of adjacent coprocessor general registers. When the FR bit
3004 * in the Status register equals one, both even and odd register numbers
3007 * Multiple float registers can be checked by calling
3008 * CHECK_FR(ctx, freg1 | freg2 | ... | fregN);
3010 #define CHECK_FR(ctx, freg) do { \
3011 if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \
3012 generate_exception_err (ctx, EXCP_RI, 1); \
3017 #define FOP(func, fmt) (((fmt) << 21) | (func))
3019 static void gen_farith (DisasContext *ctx, uint32_t op1, int ft, int fs, int fd)
3021 const char *opn = "unk";
3022 const char *condnames[] = {
3041 uint32_t func = ctx->opcode & 0x3f;
3043 switch (ctx->opcode & FOP(0x3f, 0x1f)) {
3045 CHECK_FR(ctx, fs | ft | fd);
3046 GEN_LOAD_FREG_FTN(DT0, fs);
3047 GEN_LOAD_FREG_FTN(DT1, ft);
3048 gen_op_float_add_d();
3049 GEN_STORE_FTN_FREG(fd, DT2);
3054 CHECK_FR(ctx, fs | ft | fd);
3055 GEN_LOAD_FREG_FTN(DT0, fs);
3056 GEN_LOAD_FREG_FTN(DT1, ft);
3057 gen_op_float_sub_d();
3058 GEN_STORE_FTN_FREG(fd, DT2);
3063 CHECK_FR(ctx, fs | ft | fd);
3064 GEN_LOAD_FREG_FTN(DT0, fs);
3065 GEN_LOAD_FREG_FTN(DT1, ft);
3066 gen_op_float_mul_d();
3067 GEN_STORE_FTN_FREG(fd, DT2);
3072 CHECK_FR(ctx, fs | ft | fd);
3073 GEN_LOAD_FREG_FTN(DT0, fs);
3074 GEN_LOAD_FREG_FTN(DT1, ft);
3075 gen_op_float_div_d();
3076 GEN_STORE_FTN_FREG(fd, DT2);
3081 CHECK_FR(ctx, fs | fd);
3082 GEN_LOAD_FREG_FTN(DT0, fs);
3083 gen_op_float_sqrt_d();
3084 GEN_STORE_FTN_FREG(fd, DT2);
3088 CHECK_FR(ctx, fs | fd);
3089 GEN_LOAD_FREG_FTN(DT0, fs);
3090 gen_op_float_abs_d();
3091 GEN_STORE_FTN_FREG(fd, DT2);
3095 CHECK_FR(ctx, fs | fd);
3096 GEN_LOAD_FREG_FTN(DT0, fs);
3097 gen_op_float_mov_d();
3098 GEN_STORE_FTN_FREG(fd, DT2);
3102 CHECK_FR(ctx, fs | fd);
3103 GEN_LOAD_FREG_FTN(DT0, fs);
3104 gen_op_float_chs_d();
3105 GEN_STORE_FTN_FREG(fd, DT2);
3113 CHECK_FR(ctx, fs | fd);
3114 GEN_LOAD_FREG_FTN(DT0, fs);
3115 gen_op_float_roundw_d();
3116 GEN_STORE_FTN_FREG(fd, WT2);
3120 CHECK_FR(ctx, fs | fd);
3121 GEN_LOAD_FREG_FTN(DT0, fs);
3122 gen_op_float_truncw_d();
3123 GEN_STORE_FTN_FREG(fd, WT2);
3127 CHECK_FR(ctx, fs | fd);
3128 GEN_LOAD_FREG_FTN(DT0, fs);
3129 gen_op_float_ceilw_d();
3130 GEN_STORE_FTN_FREG(fd, WT2);
3134 CHECK_FR(ctx, fs | fd);
3135 GEN_LOAD_FREG_FTN(DT0, fs);
3136 gen_op_float_floorw_d();
3137 GEN_STORE_FTN_FREG(fd, WT2);
3140 case FOP(33, 16): /* cvt.d.s */
3141 CHECK_FR(ctx, fs | fd);
3142 GEN_LOAD_FREG_FTN(WT0, fs);
3143 gen_op_float_cvtd_s();
3144 GEN_STORE_FTN_FREG(fd, DT2);
3147 case FOP(33, 20): /* cvt.d.w */
3148 CHECK_FR(ctx, fs | fd);
3149 GEN_LOAD_FREG_FTN(WT0, fs);
3150 gen_op_float_cvtd_w();
3151 GEN_STORE_FTN_FREG(fd, DT2);
3170 CHECK_FR(ctx, fs | ft);
3171 GEN_LOAD_FREG_FTN(DT0, fs);
3172 GEN_LOAD_FREG_FTN(DT1, ft);
3174 opn = condnames[func-48];
3177 CHECK_FR(ctx, fs | ft | fd);
3178 GEN_LOAD_FREG_FTN(WT0, fs);
3179 GEN_LOAD_FREG_FTN(WT1, ft);
3180 gen_op_float_add_s();
3181 GEN_STORE_FTN_FREG(fd, WT2);
3186 CHECK_FR(ctx, fs | ft | fd);
3187 GEN_LOAD_FREG_FTN(WT0, fs);
3188 GEN_LOAD_FREG_FTN(WT1, ft);
3189 gen_op_float_sub_s();
3190 GEN_STORE_FTN_FREG(fd, WT2);
3195 CHECK_FR(ctx, fs | ft | fd);
3196 GEN_LOAD_FREG_FTN(WT0, fs);
3197 GEN_LOAD_FREG_FTN(WT1, ft);
3198 gen_op_float_mul_s();
3199 GEN_STORE_FTN_FREG(fd, WT2);
3204 CHECK_FR(ctx, fs | ft | fd);
3205 GEN_LOAD_FREG_FTN(WT0, fs);
3206 GEN_LOAD_FREG_FTN(WT1, ft);
3207 gen_op_float_div_s();
3208 GEN_STORE_FTN_FREG(fd, WT2);
3213 CHECK_FR(ctx, fs | fd);
3214 GEN_LOAD_FREG_FTN(WT0, fs);
3215 gen_op_float_sqrt_s();
3216 GEN_STORE_FTN_FREG(fd, WT2);
3220 CHECK_FR(ctx, fs | fd);
3221 GEN_LOAD_FREG_FTN(WT0, fs);
3222 gen_op_float_abs_s();
3223 GEN_STORE_FTN_FREG(fd, WT2);
3227 CHECK_FR(ctx, fs | fd);
3228 GEN_LOAD_FREG_FTN(WT0, fs);
3229 gen_op_float_mov_s();
3230 GEN_STORE_FTN_FREG(fd, WT2);
3234 CHECK_FR(ctx, fs | fd);
3235 GEN_LOAD_FREG_FTN(WT0, fs);
3236 gen_op_float_chs_s();
3237 GEN_STORE_FTN_FREG(fd, WT2);
3241 CHECK_FR(ctx, fs | fd);
3242 GEN_LOAD_FREG_FTN(WT0, fs);
3243 gen_op_float_roundw_s();
3244 GEN_STORE_FTN_FREG(fd, WT2);
3248 CHECK_FR(ctx, fs | fd);
3249 GEN_LOAD_FREG_FTN(WT0, fs);
3250 gen_op_float_truncw_s();
3251 GEN_STORE_FTN_FREG(fd, WT2);
3254 case FOP(32, 17): /* cvt.s.d */
3255 CHECK_FR(ctx, fs | fd);
3256 GEN_LOAD_FREG_FTN(DT0, fs);
3257 gen_op_float_cvts_d();
3258 GEN_STORE_FTN_FREG(fd, WT2);
3261 case FOP(32, 20): /* cvt.s.w */
3262 CHECK_FR(ctx, fs | fd);
3263 GEN_LOAD_FREG_FTN(WT0, fs);
3264 gen_op_float_cvts_w();
3265 GEN_STORE_FTN_FREG(fd, WT2);
3268 case FOP(36, 16): /* cvt.w.s */
3269 CHECK_FR(ctx, fs | fd);
3270 GEN_LOAD_FREG_FTN(WT0, fs);
3271 gen_op_float_cvtw_s();
3272 GEN_STORE_FTN_FREG(fd, WT2);
3275 case FOP(36, 17): /* cvt.w.d */
3276 CHECK_FR(ctx, fs | fd);
3277 GEN_LOAD_FREG_FTN(DT0, fs);
3278 gen_op_float_cvtw_d();
3279 GEN_STORE_FTN_FREG(fd, WT2);
3298 CHECK_FR(ctx, fs | ft);
3299 GEN_LOAD_FREG_FTN(WT0, fs);
3300 GEN_LOAD_FREG_FTN(WT1, ft);
3302 opn = condnames[func-48];
3305 if (loglevel & CPU_LOG_TB_IN_ASM) {
3306 fprintf(logfile, "Invalid FP arith function: %08x %03x %03x %03x\n",
3307 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
3308 ((ctx->opcode >> 16) & 0x1F));
3310 generate_exception_err (ctx, EXCP_RI, 1);
3314 MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
3316 MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]);
3319 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
3324 ccbit = 1 << (24 + cc);
3328 gen_op_movf(ccbit, rd, rs);
3330 gen_op_movt(ccbit, rd, rs);
3333 /* ISA extensions (ASEs) */
3334 /* MIPS16 extension to MIPS32 */
3335 /* SmartMIPS extension to MIPS32 */
3337 #ifdef MIPS_HAS_MIPS64
3338 static void gen_arith64 (DisasContext *ctx, uint32_t opc)
3340 if (func == 0x02 && rd == 0) {
3344 if (rs == 0 || rt == 0) {
3348 gen_op_load_gpr_T0(rs);
3349 gen_op_load_gpr_T1(rt);
3362 /* Coprocessor 3 (FPU) */
3364 /* MDMX extension to MIPS64 */
3365 /* MIPS-3D extension to MIPS64 */
3369 static void gen_blikely(DisasContext *ctx)
3372 l1 = gen_new_label();
3374 gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
3375 gen_goto_tb(ctx, 1, ctx->pc + 4);
3379 static void decode_opc (DisasContext *ctx)
3383 uint32_t op, op1, op2;
3386 /* make sure instructions are on a word boundary */
3387 if (ctx->pc & 0x3) {
3388 generate_exception(ctx, EXCP_AdEL);
3392 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
3393 /* Handle blikely not taken case */
3394 MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
3397 op = MASK_OP_MAJOR(ctx->opcode);
3398 rs = (ctx->opcode >> 21) & 0x1f;
3399 rt = (ctx->opcode >> 16) & 0x1f;
3400 rd = (ctx->opcode >> 11) & 0x1f;
3401 sa = (ctx->opcode >> 6) & 0x1f;
3402 imm = (int16_t)ctx->opcode;
3405 op1 = MASK_SPECIAL(ctx->opcode);
3407 case OPC_SLL: /* Arithmetic with immediate */
3408 case OPC_SRL ... OPC_SRA:
3409 gen_arith_imm(ctx, op1, rd, rt, sa);
3411 case OPC_SLLV: /* Arithmetic */
3412 case OPC_SRLV ... OPC_SRAV:
3413 case OPC_MOVZ ... OPC_MOVN:
3414 case OPC_ADD ... OPC_NOR:
3415 case OPC_SLT ... OPC_SLTU:
3416 gen_arith(ctx, op1, rd, rs, rt);
3418 case OPC_MULT ... OPC_DIVU:
3419 gen_muldiv(ctx, op1, rs, rt);
3421 case OPC_JR ... OPC_JALR:
3422 gen_compute_branch(ctx, op1, rs, rd, sa);
3424 case OPC_TGE ... OPC_TEQ: /* Traps */
3426 gen_trap(ctx, op1, rs, rt, -1);
3428 case OPC_MFHI: /* Move from HI/LO */
3430 gen_HILO(ctx, op1, rd);
3433 case OPC_MTLO: /* Move to HI/LO */
3434 gen_HILO(ctx, op1, rs);
3436 case OPC_PMON: /* Pmon entry point */
3440 generate_exception(ctx, EXCP_SYSCALL);
3441 ctx->bstate = BS_EXCP;
3444 generate_exception(ctx, EXCP_BREAK);
3446 case OPC_SPIM: /* SPIM ? */
3447 /* Implemented as RI exception for now. */
3448 MIPS_INVAL("spim (unofficial)");
3449 generate_exception(ctx, EXCP_RI);
3452 /* Treat as a noop. */
3456 gen_op_cp1_enabled();
3457 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
3458 (ctx->opcode >> 16) & 1);
3461 #ifdef MIPS_HAS_MIPS64
3462 /* MIPS64 specific opcodes */
3464 case OPC_DSRL ... OPC_DSRA:
3466 case OPC_DSRL32 ... OPC_DSRA32:
3467 gen_arith_imm(ctx, op1, rd, rt, sa);
3470 case OPC_DSRLV ... OPC_DSRAV:
3471 case OPC_DADD ... OPC_DSUBU:
3472 gen_arith(ctx, op1, rd, rs, rt);
3474 case OPC_DMULT ... OPC_DDIVU:
3475 gen_muldiv(ctx, op1, rs, rt);
3478 default: /* Invalid */
3479 MIPS_INVAL("special");
3480 generate_exception(ctx, EXCP_RI);
3485 op1 = MASK_SPECIAL2(ctx->opcode);
3487 case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
3488 case OPC_MSUB ... OPC_MSUBU:
3489 gen_muldiv(ctx, op1, rs, rt);
3492 gen_arith(ctx, op1, rd, rs, rt);
3494 case OPC_CLZ ... OPC_CLO:
3495 gen_cl(ctx, op1, rd, rs);
3498 /* XXX: not clear which exception should be raised
3499 * when in debug mode...
3501 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
3502 generate_exception(ctx, EXCP_DBp);
3504 generate_exception(ctx, EXCP_DBp);
3506 /* Treat as a noop */
3508 #ifdef MIPS_HAS_MIPS64
3509 case OPC_DCLZ ... OPC_DCLO:
3510 gen_cl(ctx, op1, rd, rs);
3513 default: /* Invalid */
3514 MIPS_INVAL("special2");
3515 generate_exception(ctx, EXCP_RI);
3520 op1 = MASK_SPECIAL3(ctx->opcode);
3524 gen_bitops(ctx, op1, rt, rs, sa, rd);
3527 op2 = MASK_BSHFL(ctx->opcode);
3530 GEN_LOAD_REG_TN(T1, rt);
3534 GEN_LOAD_REG_TN(T1, rt);
3538 GEN_LOAD_REG_TN(T1, rt);
3541 default: /* Invalid */
3542 MIPS_INVAL("bshfl");
3543 generate_exception(ctx, EXCP_RI);
3546 GEN_STORE_TN_REG(rd, T0);
3551 gen_op_rdhwr_cpunum();
3554 gen_op_rdhwr_synci_step();
3560 gen_op_rdhwr_ccres();
3562 default: /* Invalid */
3563 MIPS_INVAL("rdhwr");
3564 generate_exception(ctx, EXCP_RI);
3567 GEN_STORE_TN_REG(rt, T0);
3569 #ifdef MIPS_HAS_MIPS64
3570 case OPC_DEXTM ... OPC_DEXT:
3571 case OPC_DINSM ... OPC_DINS:
3572 gen_bitops(ctx, op1, rt, rs, sa, rd);
3575 op2 = MASK_DBSHFL(ctx->opcode);
3578 GEN_LOAD_REG_TN(T1, rt);
3582 GEN_LOAD_REG_TN(T1, rt);
3585 default: /* Invalid */
3586 MIPS_INVAL("dbshfl");
3587 generate_exception(ctx, EXCP_RI);
3590 GEN_STORE_TN_REG(rd, T0);
3592 default: /* Invalid */
3593 MIPS_INVAL("special3");
3594 generate_exception(ctx, EXCP_RI);
3599 op1 = MASK_REGIMM(ctx->opcode);
3601 case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
3602 case OPC_BLTZAL ... OPC_BGEZALL:
3603 gen_compute_branch(ctx, op1, rs, -1, imm << 2);
3605 case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
3607 gen_trap(ctx, op1, rs, -1, imm);
3612 default: /* Invalid */
3613 MIPS_INVAL("REGIMM");
3614 generate_exception(ctx, EXCP_RI);
3619 op1 = MASK_CP0(ctx->opcode);
3623 #ifdef MIPS_HAS_MIPS64
3627 gen_cp0(ctx, op1, rt, rd);
3629 case OPC_C0_FIRST ... OPC_C0_LAST:
3630 gen_cp0(ctx, MASK_C0(ctx->opcode), rt, rd);
3633 op2 = MASK_MFMC0(ctx->opcode);
3637 /* Stop translation as we may have switched the execution mode */
3638 ctx->bstate = BS_STOP;
3642 /* Stop translation as we may have switched the execution mode */
3643 ctx->bstate = BS_STOP;
3645 default: /* Invalid */
3646 MIPS_INVAL("MFMC0");
3647 generate_exception(ctx, EXCP_RI);
3650 GEN_STORE_TN_REG(rt, T0);
3652 /* Shadow registers (not implemented). */
3656 generate_exception(ctx, EXCP_RI);
3660 case OPC_ADDI ... OPC_LUI: /* Arithmetic with immediate opcode */
3661 gen_arith_imm(ctx, op, rt, rs, imm);
3663 case OPC_J ... OPC_JAL: /* Jump */
3664 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
3665 gen_compute_branch(ctx, op, rs, rt, offset);
3667 case OPC_BEQ ... OPC_BGTZ: /* Branch */
3668 case OPC_BEQL ... OPC_BGTZL:
3669 gen_compute_branch(ctx, op, rs, rt, imm << 2);
3671 case OPC_LB ... OPC_LWR: /* Load and stores */
3672 case OPC_SB ... OPC_SW:
3676 gen_ldst(ctx, op, rt, rs, imm);
3679 /* Treat as a noop */
3682 /* Treat as a noop */
3685 /* Floating point. */
3690 #if defined(MIPS_USES_FPU)
3691 save_cpu_state(ctx, 1);
3692 gen_op_cp1_enabled();
3693 gen_flt_ldst(ctx, op, rt, rs, imm);
3695 generate_exception_err(ctx, EXCP_CpU, 1);
3700 #if defined(MIPS_USES_FPU)
3701 save_cpu_state(ctx, 1);
3702 gen_op_cp1_enabled();
3703 op1 = MASK_CP1(ctx->opcode);
3709 gen_cp1(ctx, op1, rt, rd);
3712 gen_compute_branch1(ctx, MASK_CP1_BCOND(ctx->opcode), imm << 2);
3718 gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
3721 generate_exception_err(ctx, EXCP_RI, 1);
3725 generate_exception_err(ctx, EXCP_CpU, 1);
3735 /* COP2: Not implemented. */
3736 generate_exception_err(ctx, EXCP_CpU, 2);
3740 gen_op_cp1_enabled();
3741 op1 = MASK_CP3(ctx->opcode);
3743 /* Not implemented */
3745 generate_exception_err(ctx, EXCP_RI, 1);
3750 #ifdef MIPS_HAS_MIPS64
3751 /* MIPS64 opcodes */
3753 case OPC_LDL ... OPC_LDR:
3754 case OPC_SDL ... OPC_SDR:
3759 gen_ldst(ctx, op, rt, rs, imm);
3761 case OPC_DADDI ... OPC_DADDIU:
3762 gen_arith_imm(ctx, op, rt, rs, imm);
3765 #ifdef MIPS_HAS_MIPS16
3767 /* MIPS16: Not implemented. */
3769 #ifdef MIPS_HAS_MDMX
3771 /* MDMX: Not implemented. */
3773 default: /* Invalid */
3775 generate_exception(ctx, EXCP_RI);
3778 if (ctx->hflags & MIPS_HFLAG_BMASK) {
3779 int hflags = ctx->hflags;
3780 /* Branches completion */
3781 ctx->hflags &= ~MIPS_HFLAG_BMASK;
3782 ctx->bstate = BS_BRANCH;
3783 save_cpu_state(ctx, 0);
3784 switch (hflags & MIPS_HFLAG_BMASK) {
3786 /* unconditional branch */
3787 MIPS_DEBUG("unconditional branch");
3788 gen_goto_tb(ctx, 0, ctx->btarget);
3791 /* blikely taken case */
3792 MIPS_DEBUG("blikely branch taken");
3793 gen_goto_tb(ctx, 0, ctx->btarget);
3796 /* Conditional branch */
3797 MIPS_DEBUG("conditional branch");
3800 l1 = gen_new_label();
3802 gen_goto_tb(ctx, 1, ctx->pc + 4);
3804 gen_goto_tb(ctx, 0, ctx->btarget);
3808 /* unconditional branch to register */
3809 MIPS_DEBUG("branch to register");
3813 MIPS_DEBUG("unknown branch");
3819 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3822 DisasContext ctx, *ctxp = &ctx;
3823 target_ulong pc_start;
3824 uint16_t *gen_opc_end;
3827 if (search_pc && loglevel)
3828 fprintf (logfile, "search pc %d\n", search_pc);
3831 gen_opc_ptr = gen_opc_buf;
3832 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3833 gen_opparam_ptr = gen_opparam_buf;
3838 ctx.bstate = BS_NONE;
3839 /* Restore delay slot state from the tb context. */
3840 ctx.hflags = tb->flags;
3841 ctx.saved_hflags = ctx.hflags;
3842 if (ctx.hflags & MIPS_HFLAG_BR) {
3843 gen_op_restore_breg_target();
3844 } else if (ctx.hflags & MIPS_HFLAG_B) {
3845 ctx.btarget = env->btarget;
3846 } else if (ctx.hflags & MIPS_HFLAG_BMASK) {
3847 /* If we are in the delay slot of a conditional branch,
3848 * restore the branch condition from env->bcond to T2
3850 ctx.btarget = env->btarget;
3851 gen_op_restore_bcond();
3853 #if defined(CONFIG_USER_ONLY)
3856 ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
3858 ctx.CP0_Status = env->CP0_Status;
3860 if (loglevel & CPU_LOG_TB_CPU) {
3861 fprintf(logfile, "------------------------------------------------\n");
3862 /* FIXME: This may print out stale hflags from env... */
3863 cpu_dump_state(env, logfile, fprintf, 0);
3866 #if defined MIPS_DEBUG_DISAS
3867 if (loglevel & CPU_LOG_TB_IN_ASM)
3868 fprintf(logfile, "\ntb %p super %d cond %04x\n",
3869 tb, ctx.mem_idx, ctx.hflags);
3871 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
3872 if (env->nb_breakpoints > 0) {
3873 for(j = 0; j < env->nb_breakpoints; j++) {
3874 if (env->breakpoints[j] == ctx.pc) {
3875 save_cpu_state(ctxp, 1);
3876 ctx.bstate = BS_BRANCH;
3878 goto done_generating;
3884 j = gen_opc_ptr - gen_opc_buf;
3888 gen_opc_instr_start[lj++] = 0;
3890 gen_opc_pc[lj] = ctx.pc;
3891 gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
3892 gen_opc_instr_start[lj] = 1;
3894 ctx.opcode = ldl_code(ctx.pc);
3898 if (env->singlestep_enabled)
3901 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
3904 #if defined (MIPS_SINGLE_STEP)
3908 if (env->singlestep_enabled) {
3909 save_cpu_state(ctxp, ctx.bstate == BS_NONE);
3911 goto done_generating;
3913 else if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
3914 save_cpu_state(ctxp, 0);
3915 gen_goto_tb(&ctx, 0, ctx.pc);
3918 /* Generate the return instruction */
3921 *gen_opc_ptr = INDEX_op_end;
3923 j = gen_opc_ptr - gen_opc_buf;
3926 gen_opc_instr_start[lj++] = 0;
3929 tb->size = ctx.pc - pc_start;
3932 #if defined MIPS_DEBUG_DISAS
3933 if (loglevel & CPU_LOG_TB_IN_ASM)
3934 fprintf(logfile, "\n");
3936 if (loglevel & CPU_LOG_TB_IN_ASM) {
3937 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3938 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
3939 fprintf(logfile, "\n");
3941 if (loglevel & CPU_LOG_TB_OP) {
3942 fprintf(logfile, "OP:\n");
3943 dump_ops(gen_opc_buf, gen_opparam_buf);
3944 fprintf(logfile, "\n");
3946 if (loglevel & CPU_LOG_TB_CPU) {
3947 fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
3954 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3956 return gen_intermediate_code_internal(env, tb, 0);
3959 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3961 return gen_intermediate_code_internal(env, tb, 1);
3964 void fpu_dump_state(CPUState *env, FILE *f,
3965 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
3970 # define printfpr(fp) do { \
3971 fpu_fprintf(f, "w:%08x d:%08lx%08lx fd:%g fs:%g\n", \
3972 (fp)->w[FP_ENDIAN_IDX], (fp)->w[0], (fp)->w[1], (fp)->fd, (fp)->fs[FP_ENDIAN_IDX]); \
3975 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d\n",
3976 env->fcr0, env->fcr31,
3977 (env->CP0_Status & (1 << CP0St_FR)) != 0);
3978 fpu_fprintf(f, "FT0: "); printfpr(&env->ft0);
3979 fpu_fprintf(f, "FT1: "); printfpr(&env->ft1);
3980 fpu_fprintf(f, "FT2: "); printfpr(&env->ft2);
3981 for(i = 0; i < 32; i += 2) {
3982 fpu_fprintf(f, "%s: ", fregnames[i]);
3983 printfpr(FPR(env, i));
3989 void dump_fpu (CPUState *env)
3992 fprintf(logfile, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
3993 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
3994 fpu_dump_state(env, logfile, fprintf, 0);
3998 void cpu_dump_state (CPUState *env, FILE *f,
3999 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
4005 cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
4006 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
4007 for (i = 0; i < 32; i++) {
4009 cpu_fprintf(f, "GPR%02d:", i);
4010 cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]);
4012 cpu_fprintf(f, "\n");
4015 c0_status = env->CP0_Status;
4016 if (env->hflags & MIPS_HFLAG_UM)
4017 c0_status |= (1 << CP0St_UM);
4018 if (env->hflags & MIPS_HFLAG_ERL)
4019 c0_status |= (1 << CP0St_ERL);
4020 if (env->hflags & MIPS_HFLAG_EXL)
4021 c0_status |= (1 << CP0St_EXL);
4023 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
4024 c0_status, env->CP0_Cause, env->CP0_EPC);
4025 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
4026 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
4027 if (c0_status & (1 << CP0St_CU1))
4028 fpu_dump_state(env, f, cpu_fprintf, flags);
4031 CPUMIPSState *cpu_mips_init (void)
4035 env = qemu_mallocz(sizeof(CPUMIPSState));
4043 void cpu_reset (CPUMIPSState *env)
4045 memset(env, 0, offsetof(CPUMIPSState, breakpoints));
4050 env->PC = 0xBFC00000;
4051 #if defined (MIPS_USES_R4K_TLB)
4052 env->CP0_random = MIPS_TLB_NB - 1;
4053 env->tlb_in_use = MIPS_TLB_NB;
4056 /* SMP not implemented */
4057 env->CP0_EBase = 0x80000000;
4058 env->CP0_Config0 = MIPS_CONFIG0;
4059 env->CP0_Config1 = MIPS_CONFIG1;
4060 env->CP0_Config2 = MIPS_CONFIG2;
4061 env->CP0_Config3 = MIPS_CONFIG3;
4062 env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
4063 env->CP0_WatchLo = 0;
4064 env->hflags = MIPS_HFLAG_ERL;
4065 /* Count register increments in debug mode, EJTAG version 1 */
4066 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
4067 env->CP0_PRid = MIPS_CPU;
4068 env->exception_index = EXCP_NONE;
4069 #if defined(CONFIG_USER_ONLY)
4070 env->hflags |= MIPS_HFLAG_UM;
4072 #ifdef MIPS_USES_FPU
4073 env->fcr0 = MIPS_FCR0;
4075 /* XXX some guesswork here, values are CPU specific */
4076 env->SYNCI_Step = 16;